TPS2597 [TI]
TPS2597xx 2.7 Vâ23 V, 7-A, 9.8-mΩ eFuse With Accurate Current Monitor and Transient Overcurrent Blanking;
| 型号： | TPS2597 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | TPS2597xx 2.7 Vâ23 V, 7-A, 9.8-mΩ eFuse With Accurate Current Monitor and Transient Overcurrent Blanking |
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TPS2597
SLVSGG5A – NOVEMBER 2021 – REVISED DECEMBER 2021
TPS2597xx 2.7 V–23 V, 7-A, 9.8-mΩ eFuse With Accurate Current Monitor and
Transient Overcurrent Blanking
1 Features
3 Description
•
•
•
Wide operating input voltage range: 2.7 V to 23 V
– 28-V absolute maximum
Integrated FET with low on-resistance: RON = 9.8
mΩ (typ.)
The TPS2597xx family of eFuses is a highly
integrated circuit protection and power management
solution in
a
small package. The devices
provide multiple protection modes using very few
external components and are a robust defense
against overloads, short-circuits, voltage surges and
excessive inrush current.
Fast overvoltage protection
– Overvoltage clamp (OVC) with pin-selectable
threshold (3.89 V, 5.76 V, 13.88 V) and 5-μs
(typical) response time or
– Adjustable overvoltage lockout (OVLO) with
1.2-μs (typical) response time
Overcurrent protection with load current monitor
output (ILM)
– Active current limit or circuit-breaker options
– Adjustable threshold (ILIM) 0.87 A–7.7 A
Output slew rate and inrush current can be adjusted
using a single external capacitor. Loads are protected
from input overvoltage conditions either by clamping
the output to a safe fixed maximum voltage (pin
selectable), or by cutting off the output if the input
exceeds an adjustable overvoltage threshold. The
devices respond to output overload by actively limiting
the current or breaking the circuit. The output current
limit threshold as well as the transient overcurrent
blanking timer are user adjustable. The current limit
control pin also functions as an analog load current
monitor.
•
•
±10% accuracy for ILIM > 1.74 A
– Adjustable transient blanking timer (ITIMER) to
allow peak currents up to 2 × ILIM
– Output load current monitor accuracy: ±8%
(max)
•
•
Fast-trip response for short-circuit protection
– 550-ns (typical) response time
– Adjustable (2 × ILIM) and fixed thresholds
Active high enable input with adjustable
undervoltage lockout threshold (UVLO)
Adjustable output slew rate control (dVdt)
Overtemperature protection
The devices are available in a 2-mm × 2-mm, 10-
pin HotRod™ QFN package for improved thermal
performance and reduced system footprint.
The devices are characterized for operation over a
junction temperature range of –40°C to +125°C.
•
•
•
Device Information
Digital outputs
PART NUMBER
PACKAGE(1)
BODY SIZE (NOM)
– Fault indication (FLT) or
– Power Good indication (PG) with adjustable
threshold (PGTH)
TPS2597xxRPW
QFN (10)
2 mm × 2 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
•
•
•
UL 2367 recognition (pending)
IEC 62368 CB certification (pending)
Small footprint: QFN 2 mm × 2 mm, 0.45-mm pitch
VIN = 2.7 to 23 V
VOUT
IN
OUT
COUT
2 Applications
VLOGIC
EN/UVLO
•
•
•
•
•
•
Server, PC motherboard, and add-in cards
Enterprise storage – RAID/HBA/SAN/eSSD
Patient monitors
Appliances and power tools
Retail point-of-sale terminals
Smartphones and tablets
TPS25970x
OVLO
FLT
ITIMER dVdt
ILM
GND
CITIMER
CDVDT
RILM
Simplified Schematic
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS2597
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SLVSGG5A – NOVEMBER 2021 – REVISED DECEMBER 2021
Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Device Comparison Table...............................................3
6 Pin Configuration and Functions...................................4
7 Specifications.................................................................. 5
7.1 Absolute Maximum Ratings........................................ 5
7.2 ESD Ratings............................................................... 5
7.3 Recommended Operating Conditions.........................5
7.4 Electrical Characteristics.............................................6
7.5 Timing Requirements..................................................7
7.6 Switching Characteristics............................................8
7.7 Typical Characteristics................................................9
8 Detailed Description......................................................17
8.1 Overview...................................................................17
8.2 Functional Block Diagram.........................................18
8.3 Feature Description...................................................21
8.4 Device Functional Modes..........................................32
9 Application and Implementation..................................33
9.1 Application Information............................................. 33
9.2 Typical Application.................................................... 34
9.3 Parallel Operation..................................................... 37
10 Power Supply Recommendations..............................40
10.1 Transient Protection................................................40
10.2 Output Short-Circuit Measurements....................... 41
11 Layout...........................................................................42
11.1 Layout Guidelines................................................... 42
11.2 Layout Example...................................................... 43
12 Device and Documentation Support..........................44
12.1 Device Support....................................................... 44
12.2 Documentation Support.......................................... 44
12.3 Receiving Notification of Documentation Updates..44
12.4 Support Resources................................................. 44
12.5 Trademarks.............................................................44
12.6 Electrostatic Discharge Caution..............................44
12.7 Glossary..................................................................44
13 Mechanical, Packaging, and Orderable
Information.................................................................... 45
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision * (November 2021) to Revision A (December 2021)
Page
•
Changed status from "Advance Information" to "Production Data".....................................................................1
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SLVSGG5A – NOVEMBER 2021 – REVISED DECEMBER 2021
5 Device Comparison Table
PG
and PGTH
OVERCURRENT
RESPONSE
RESPONSE TO
FAULT
PART NUMBER
OVERVOLTAGE RESPONSE
FLT
TPS25970ARPW
TPS25970LRPW
TPS25972ARPW
TPS25972LRPW
TPS25974ARPW
TPS25974LRPW
Auto-Retry
Latch-Off
Auto-Retry
Latch-Off
Auto-Retry
Latch-Off
Adjustable OVLO
N
Y
Y
Active Current Limit
Circuit Breaker
Pin Selectable OVC
(3.89 V/5.76 V/13.88 V)
N
Adjustable OVLO
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SLVSGG5A – NOVEMBER 2021 – REVISED DECEMBER 2021
6 Pin Configuration and Functions
IN
OUT
1
EN/UVLO
10
ITIMER
OVLO/
ILM
9
2
OVCSEL
5
6
PG/
GND
8
3
DNC
PGTH/
FLT
DVDT
7
4
Figure 6-1. TPS2597xx RPW Package 10-Pin QFN (Top View)
Table 6-1. Pin Functions
PIN
TYPE
DESCRIPTION
NAME
NO.
Active high enable for the device. A resistor divider on this pin from input supply to GND can be used
to adjust the undervoltage lockout threshold. Do not leave floating. Refer to Undervoltage Lockout
(UVLO and UVP) for details.
EN/UVLO
1
Analog Input
TPS25970x and TPS25974x: A resistor divider on this pin from supply to GND can be used to adjust
the overvoltage lockout threshold. This pin can also be used as an active low enable for the device. Do
not leave floating. Refer to Overvoltage Lockout (OVLO) for details.
OVLO
OVCSEL
PG
Analog Input
Analog Input
Digital Output
2
TPS25972x: Overvoltage clamp threshold select pin. Refer to Overvoltage Clamp (OVC) for details.
TPS25972x and TPS25974x: Power-good indication. This is an open-drain signal, which is asserted
high when the internal powerpath is fully turned ON and the PGTH input exceeds a certain threshold.
Refer to Power Good Indication (PG) for more details.
3
4
DNC
FLT
Digital Output
Digital Output
TPS25970x: Can be left floating
TPS25970x: Active low fault event indicator. This pin is an open-drain signal that is pulled low when a
fault is detected. Refer to Fault Response and Indication (FLT) for more details.
TPS25972x and TPS25974x: Power-good threshold. Refer to Power Good Indication (PG) for more
details.
PGTH
Analog Input
IN
5
6
Power
Power
Power input
OUT
Power output
A capacitor from this pin to GND sets the output turn on slew rate. Leave this pin floating for the fastest
turn on slew rate. Refer to Slew Rate (dVdt) and Inrush Current Control for details.
DVDT
GND
7
8
Analog Output
Ground
This pin is the ground reference for all internal circuits and must be connected to system GND.
This pin is a dual function pin used to limit and monitor the output current. An external resistor from
this pin to GND sets the output current limit threshold during start-up as well as steady state. The pin
voltage can also be used as analog output load current monitor signal. Do not leave floating. Refer to
Circuit-Breaker or Active Current Limiting for more details.
ILM
9
Analog Output
Analog Output
A capacitor from this pin to GND sets the overcurrent blanking interval during which the output
current can temporarily exceed set current limit (but lower than fast-trip threshold) before the device
overcurrent response takes action. Leave this pin open for the fastest response to overcurrent events.
Refer to Circuit-Breaker or Active Current Limiting for more details.
ITIMER
10
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
Parameter
Pin
MIN
–0.3
–0.3
–0.8
–0.3
–0.3
MAX
28
UNIT
VIN
Maximum input voltage range, –40 ℃ ≤ TJ ≤ 125 ℃
Maximum output voltage range, –40 ℃ ≤ TJ ≤ 125 ℃
Minimum output voltage pulse (< 1 µs)
Maximum Enable pin voltage range
Maximum OVCSEL/OVLO pin voltage range
Maximum dVdT pin voltage range
Maximum ITIMER pin voltage range
Maximum PGTH pin voltage range
Maximum PG pin voltage range
IN
V
VOUT
VOUT,PLS
VEN/UVLO
VOV
OUT
OUT
VIN + 0.3
EN/UVLO
OVCSEL/OVLO
dVdt
6.5
6.5
V
V
VdVdT
VITIMER
VPGTH
VPG
Internally limited
Internally limited
–0.3
V
ITIMER
PGTH
V
6.5
6.5
6.5
V
PG
–0.3
V
VFLTB
VILM
Maximum FLT pin voltage range
Maximum ILM pin voltage range
Maximum continuous switch current
Junction temperature
FLT
–0.3
V
ILM
Internally limited
Internally limited
Internally limited
V
IMAX
IN to OUT
A
TJ
°C
°C
°C
TLEAD
Tstg
Maximum lead temperature
300
150
Storage temperature
–65
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.
If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
7.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC
JS-001(1)
±2000
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per ANSI/ESDA/JEDEC
JS-002(2)
±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
Parameter
Pin
MIN
MAX
23(1)
VIN
UNIT
V
VIN
Input voltage range
Output voltage range
IN
2.7
VOUT
VEN/UVLO
VOV
OUT
V
EN/UVLO pin voltage range
EN/UVLO
OVLO
dVdt
5(2)
V
OVLO pin voltage range (TPS25970x and TPS25974x variants only)
dVdT pin capacitor voltage rating
PGTH pin voltage range
0.5
1.5
V
VdVdT
VPGTH
VFLTB
VPG
VIN + 5 V
V
PGTH
FLT
5
5
5
V
FLT pin voltage range
V
PG pin voltage range
PG
V
VITIMER
RILM
ITIMER pin capacitor voltage rating
ILM pin resistance to GND
ITIMER
ILM
4
V
715
6650
7
Ω
IMAX
Continuous switch current, TJ ≤ 125 ℃
Junction temperature
IN to OUT
A
TJ
–40
125
°C
(1) For TPS25972x OVC variants, the input operating voltage must be limited to the selected Output Voltage Clamp Option as listed in the
Electrical Characteristics section.
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(2) For supply voltages below 5 V, it is okay to pull up the EN pin to IN directly. For supply voltages greater than 5 V, TI recommends
to use a resistor divider with minimum pullup resistor value of 350 kΩ.
7.4 Electrical Characteristics
(Test conditions unless otherwise noted) –40°C ≤ TJ ≤ 125°C, VIN = 12 V, OUT = Open, VEN/UVLO = 2 V, VOVLO = 0 V
for TPS25970x/4x, OVCSEL = 390 kΩ to GND for TPS25972x, RILM = 715 Ω , dVdT = Open, ITIMER = Open, FLT = Open
for TPS25970x, PGTH = Open for TPS25972x/4x, PG = Open for TPS25972x/4x. All voltages referenced to GND.
Test
Parameter
Description
MIN
TYP
MAX
UNITS
INPUT SUPPLY (IN)
IN supply quiescent current (TPS25970x)
IN supply quiescent current (TPS25972x)
IN supply quiescent current (TPS25974x)
IN supply quiescent current during OVC (TPS25972x)
413
407
413
429
67
650
650
650
650
131
25
µA
µA
µA
µA
µA
µA
V
IQ(ON)
IQ(OFF)
ISD
VUVP(R)
VUVP(F)
IN supply OFF state current (VSD(F) < VEN < VUVLO(F))
IN supply shutdown current (VEN < VSD(F)
)
2.3
IN supply UVP rising threshold
2.44
2.35
2.54
2.45
2.64
2.55
IN supply UVP falling threshold
V
OUTPUT VOLTAGE CLAMP (OUT) - TPS25972x
Overvoltage Clamp threshold, OVCSEL = Shorted to GND
Overvoltage Clamp threshold, OVCSEL = Open
3.65
5.25
13.2
3.89
5.76
4.1
6.2
V
V
V
VOVC
Overvoltage Clamp threshold, OVCSEL = 390 kΩ to GND
13.88
14.5
Output voltage during clamping, OVCSEL = Shorted to GND,
IOUT = 10 mA
3.2
5
3.82
5.68
4.2
6.12
14.6
V
V
V
Output voltage during clamping, OVCSEL = Open, IOUT = 10
mA
VCLAMP
Output voltage during clamping, OVCSEL = 390 kΩ to GND,
IOUT = 10 mA
13
13.79
OUTPUT LOAD CURRENT MONITOR (ILM)
Analog load current monitor gain (IMON : IOUT), 1 A ≤ IOUT
7.7 A, IOUT < ILIM
OVERCURRENT PROTECTION (OUT)
Overcurrent threshold, RILM = 6.65 KΩ
≤
GIMON
98
105.5
114
µA/A
0.745
1.55
3.2
0.87
1.73
3.48
7.67
0.97
1.905
3.715
8.15
A
A
A
A
A
Overcurrent threshold, RILM = 3.32 KΩ
Overcurrent threshold, RILM = 1.65 KΩ
Overcurrent threshold, RILM = 750 Ω
ILIM
7.03
ISPFLT
ISPFLT
Circuit-Breaker threshold, ILM pin open (Single point failure)
0.1
Circuit-Breaker threshold, ILM pin shorted to GND (Single
point failure)
2
3.1
A
ISCGain
VFB
Scalable fast-trip threshold (ISC) : ILIM ratio
VOUT threshold to exit current limit foldback
170
201
240
%
V
1.55
1.88
2.23
ON RESISTANCE (IN - OUT)
2.7 ≤ VIN ≤ 4 V, IOUT = 3 A, TJ = 25 ℃
4 < VIN ≤ 23 V, IOUT = 3 A, TJ = 25 ℃
ENABLE/UNDERVOLTAGE LOCKOUT (EN/UVLO)
10
18.3
18.3
mΩ
mΩ
RON
9.8
VUVLO(R)
VUVLO(F)
VSD(F)
EN/UVLO rising threshold
1.183
1.076
0.45
1.2
1.1
1.228
1.12
0.95
0.1
V
V
EN/UVLO falling threshold
EN/UVLO falling threshold for lowest shutdown current
EN/UVLO pin leakage current
0.75
V
IENLKG
-0.1
µA
OVERVOLTAGE LOCKOUT (OVLO) - TPS25970x/4x
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7.4 Electrical Characteristics (continued)
(Test conditions unless otherwise noted) –40°C ≤ TJ ≤ 125°C, VIN = 12 V, OUT = Open, VEN/UVLO = 2 V, VOVLO = 0 V
for TPS25970x/4x, OVCSEL = 390 kΩ to GND for TPS25972x, RILM = 715 Ω , dVdT = Open, ITIMER = Open, FLT = Open
for TPS25970x, PGTH = Open for TPS25972x/4x, PG = Open for TPS25972x/4x. All voltages referenced to GND.
Test
Description
MIN
TYP
MAX
UNITS
Parameter
VOV(R)
VOV(F)
IOVLKG
OVERCURRENT FAULT TIMER (ITIMER)
OVLO rising threshold
OVLO falling threshold
1.183
1.076
-0.1
1.2
1.1
1.228
1.12
0.1
V
V
OVLO pin leakage current (0.5 V < VOVLO < 1.5 V)
µA
IITIMER
ITIMER pin internal discharge current, IOUT > ILIM
1.5
2
13.8
2.57
1.05
1.52
2.72
35
µA
kΩ
V
RITIMER
VINT
VITIMER(F)
ΔVITIMER
ITIMER pin internal pull-up resistance
ITIMER pin internal pull-up voltage
2.1
0.609
1.286
2.74
1.37
1.741
ITIMER comparator threshold, IOUT > ILIM
ITIMER discharge differential voltage threshold, IOUT > ILIM
V
V
POWER GOOD INDICATION (PG) - TPS25972x/4x
PG pin voltage while de-asserted. VIN < VUVP(F), VEN
<
<
663
1000
1000
mV
mV
VSD(F), Weak pull-up (IPG = 26 μA)
VPGD
PG pin voltage while de-asserted. VIN < VUVP(F), VEN
VSD(F), Strong pull-up (IPG = 242 μA)
782
0
PG pin voltage while de-asserted, VIN > VUVP(R)
PG pin leakage current, PG asserted
600
3
mV
µA
IPGLKG
POWERGOOD THRESHOLD (PGTH)
VPGTH(R)
VPGTH(F)
IPGTHLKG
PGTH rising threshold
PGTH falling threshold
PGTH pin leakage current
1.178
1.071
-1
1.2
1.1
1.23
1.13
1
V
V
µA
FAULT INDICATION (FLTB) - TPS25970x
IFLTLKG
RFLTB
FLT pin leakage current
-1
1
µA
Ω
FLT pin internal pull-down resistance
12.4
OVERTEMPERATURE PROTECTION (OTP)
TSD
Thermal Shutdown rising threshold, TJ↑
Thermal Shutdown hysteresis, TJ↓
154
10
°C
°C
TSDHYS
DVDT
IdVdt
dVdt pin internal charging current
1.4
3.4
5.7
µA
7.5 Timing Requirements
PARAMETER
TEST CONDITIONS
MIN TYP MAX
UNIT
TPS25970x and TPS25974x, VOVLO > VOV(R)
to VOUT
tOVLO
Overvoltage lock-out response time
1.2
µs
↓
tOVC
tCB
Overvoltage clamp response time
Circuit-Breaker response time
TPS25972x, VIN > VOVC to VOUT
↓
5
2
µs
µs
TPS25974x, IOUT > ILIM + 30% to VOUT
↓
TPS25970x and TPS25972x, IOUT > ILIM
30% to IOUT settling to within 5% of ILIM
+
tLIM
Current limit response time
465
µs
tSC
Short-circuit response time
IOUT > 3x ILIM to output current cut off
550
550
110
14
ns
ns
ms
µs
µs
tFT
Fixed fast-trip response time
Thermal Shutdown auto-retry Interval
PG assertion de-glitch time
IOUT > IFT to IOUT↓
tTSD,RST
tPGA
tPGD
Device enabled and TJ < TSD - TSDHYS
VPGTH > VPGTH(R) to PG↑
PG de-assertion de-glitch time
VPGTH < VPGTH(F) to PG↓
14
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7.6 Switching Characteristics
The output rising slew rate is internally controlled and constant across the entire operating voltage range to ensure the
turn on timing is not affected by the load conditions. The rising slew rate can be adjusted by adding capacitance from
the dVdt pin to ground. As CdVdt is increased it will slow the rising slew rate (SR). See Slew Rate and Inrush Current
Control (dVdt) section for more details. The Turn-Off Delay and Fall Time, however, are dependent on the RC time constant
of the load capacitance (COUT) and Load Resistance (RL). The Switching Characteristics are only valid for the power-up
sequence where the supply is available in steady state condition and the load voltage is completely discharged before the
device is enabled. Typical values are taken at TJ = 25°C unless specifically noted otherwise. RL = 100 Ω, COUT = 1 µF.
CdVdt
3300 pF
=
PARAMETER
VIN
CdVdt = Open CdVdt = 1800 pF
UNITS
2.7 V
12 V
23 V
2.7 V
12 V
23 V
2.7 V
12 V
23 V
2.7 V
12 V
23 V
2.7 V
12 V
23 V
8.922
21.45
34.16
0.138
0.145
0.15
1.218
1.562
1.761
0.505
0.979
1.478
1.771
6.131
10.43
2.277
7.11
0.72
SRON
tD,ON
tR
Output rising slew rate
0.901
1.003
0.79
V/ms
Turn on delay
Rise time
1.659
2.562
2.993
10.63
18.31
3.783
12.29
20.87
22.1
ms
ms
ms
µs
0.242
0.446
0.538
0.379
0.582
0.668
22.1
tON
Turn on time
Turn off delay
11.91
22.1
tD,OFF
18.9
18.9
18.9
16.5
16.5
16.5
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7.7 Typical Characteristics
14.5
500
480
460
440
420
400
380
360
340
320
300
VIN (V)
2.7
14
13.5
13
12.5
12
11.5
11
10.5
10
9.5
9
8.5
8
7.5
-40
3.3
4
5
12
23
TA (C)
-40
25
85
125
-20
0
20
40
TA (C)
60
80
100 120 140
2.5
5
7.5
10 12.5 15 17.5 20 22.5 25
VIN (V)
Figure 7-1. ON-Resistance vs Supply Voltage
Figure 7-2. IN Quiescent Current vs Temperature (TPS25970x,
TPS25974x Variants)
500
450
400
350
300
100
90
80
70
60
50
TA (C)
TA (C)
40
30
20
-40
25
85
-40
25
85
125
125
3
4
5
6
7
8
9
10
11
12
2
4
6
8
10 12 14 16 18 20 22 24
VIN (V)
VIN (V)
Figure 7-3. IN Quiescent Current vs Temperature (TPS25972x
Variant)
Figure 7-4. IN OFF State (UVLO) Current vs Temperature
2.55
8
TA (C)
-40
25
85
125
6
4
2
0
2.5
Rising
Falling
2.45
2.4
-40
-20
0
20
40
TA (C)
60
80
100 120 140
2
4
6
8
10 12 14 16 18 20 22 24
VIN (V)
Figure 7-6. IN Undervoltage Threshold vs Temperature
Figure 7-5. IN Shutdown Current vs Temperature
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7.7 Typical Characteristics (continued)
1.208
1.1005
1.1
VIN (V)
VIN (V)
2.7
1.2075
2.7
5
12
23
5
12
23
1.0995
1.099
1.0985
1.098
1.0975
1.097
1.0965
1.096
1.0955
1.095
1.207
1.2065
1.206
1.2055
1.205
1.2045
1.204
1.2035
1.203
-40
-20
0
20
40
60
80
100 120 140
-40
-20
0
20
40
60
80
100 120 140
TA (C)
TA (C)
Figure 7-7. EN/UVLO Rising Threshold vs Temperature
Figure 7-8. EN/UVLO Falling Threshold vs Temperature
1.21
VIN (V)
1.209
2.7
5
12
1.208
23
1.207
1.206
1.205
1.204
1.203
1.202
1.201
1.2
-40
-20
0
20
40
60
80
100 120 140
TA (C)
Figure 7-9. EN/UVLO Shutdown Falling Threshold vs
Temperature
Figure 7-10. OVLO Rising Threshold vs Temperature
(TPS25970x, TPS25974x Variants)
1.1005
8000
7500
7000
6500
6000
5500
5000
4500
4000
3500
3000
2500
2000
1500
1000
500
VIN (V)
1.1
2.7
5
12
23
1.0995
1.099
1.0985
1.098
1.0975
1.097
1.0965
1.096
1.0955
1.095
-40
-20
0
20
40
60
80
100 120 140
0.5
1
1.5
2
2.5
3
3.5
RILM (k)
4
4.5
5
5.5
6
6.5
7
TA (C)
Figure 7-11. OVLO Falling Threshold vs Temperature
(TPS25970x, TPS25974x Variants)
Figure 7-12. Overcurrent Threshold vs ILM Resistor
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7.7 Typical Characteristics (continued)
16
14
12
10
8
10
8
Min
Max
Min
Max
6
4
6
4
2
2
0
0
-2
-4
-6
-8
-10
-12
-14
-16
-2
-4
-6
-8
-10
1
1.5
2
2.5
3
3.5
4
4.5
5 5.5 6 6.5 7 7.5 8
0.5
1.5
2.5
3.5
4.5
ILIM (A)
5.5
6.5
7.5
IOUT (A)
Figure 7-14. Analog Current Monitor Gain Accuracy
Figure 7-13. Overcurrent Threshold Accuracy (Across Process,
Voltage and Temperature)
14
201.95
201.85
201.75
201.65
201.55
13
12
11
10
9
OVCSEL
Shorted to GND
OPEN
390 k to GND
8
201.45
7
VIN (V)
2.7
5
12
23
201.35
201.25
201.15
6
5
4
-40
-20
0
20
40
TA (C)
60
80
100 120 140
3
-40
-20
0
20
40
60
80
100 120 140
TA (C)
Figure 7-15. Scalable Fast-Trip Threshold: Current Limit
Threshold (ILIM) Ratio vs Temperature
Figure 7-16. OVC Threshold vs Temperature (TPS25972x
Variant)
14
5.88
5.85
5.82
13.95
IOUT (mA)
IOUT (mA)
1
10
100
5.79
5.76
13.9
1
10
100
13.85
5.73
5.7
5.67
5.64
5.61
5.58
5.55
13.8
13.75
13.7
13.65
-40
-20
0
20
40
TA (C)
60
80
100 120 140
-40
-20
0
20
40
60
80
100 120 140
TA (C)
Figure 7-17. OVC Clamping Voltage (OVCSEL = 390 kΩ to GND)
vs Load Current (TPS25972x Variant)
Figure 7-18. OVC Clamping Voltage (OVCSEL = OPEN) vs Load
Current (TPS25972x Variant)
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7.7 Typical Characteristics (continued)
4.02
3.99
3.96
1.53
1.528
1.526
1.524
1.522
1.52
VIN (V)
2.7
5
12
23
IOUT (mA)
1
10
100
3.93
3.9
3.87
3.84
3.81
3.78
3.75
3.72
3.69
1.518
1.516
1.514
1.512
1.51
-40
-20
0
20
40
60
80
100 120 140
-40
-20
0
20
40
60
80
100 120 140
TA (C)
TA (C)
Figure 7-20. ITIMER Discharge Differential Voltage Threshold vs
Temperature
Figure 7-19. OVC Clamping Voltage (OVCSEL = GND) vs Load
Current (TPS25972x Variant)
18.5
VIN (V)
18
2.7
5
12
23
17.5
17
16.5
16
15.5
15
14.5
14
13.5
13
-40
-20
0
20
40
60
80
100 120 140
TA (C)
Figure 7-21. ITIMER Discharge Current vs Temperature
Figure 7-22. ITIMER Internal Pullup Resistance vs Temperature
2.8
4
VIN (V)
2.7
2.7
2.6
2.5
3.8
3.6
3.4
3.2
3
5
12
23
2.4
VIN (V)
2.7
5
12
23
2.3
2.2
2.8
-40
-20
0
20
40
60
80
100 120 140
-40
-20
0
20
40
60
80
100 120 140
TA (C)
TA (C)
Figure 7-23. ITIMER internal Pullup Voltage vs Temperature
Figure 7-24. DVDT Charging Current vs Temperature
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7.7 Typical Characteristics (continued)
1.206
1.1005
1.1
VIN (V)
VIN (V)
2.7
5
2.7
5
12
23
1.2055
1.205
1.0995
1.099
1.0985
1.098
1.0975
1.097
1.0965
1.096
1.0955
1.095
12
23
1.2045
1.204
1.2035
1.203
1.2025
1.202
-40
-20
0
20
40
60
80
100 120 140
-40
-20
0
20
40
60
80
100 120 140
TA (C)
TA (C)
Figure 7-25. PGTH Threshold (Rising) vs Temperature
(TPS25972x, TPS25974x Variants)
Figure 7-26. PGTH Threshold (Falling) vs Temperature
(TPS25972x, TPS25974x Variants)
19
10000
5000
VIN (V)
18
2.7
12
23
2000
1000
500
17
16
200
100
50
15
14
13
12
11
10
9
20
10
5
2
1
0.5
0.2
0.1
0
20
40
60
80
PD (W)
100
120
140
-40
-20
0
20
40
TA (C)
60
80
100 120 140
Figure 7-28. Time to Thermal Shut-Down During Inrush State
Figure 7-27. FLT Pin Pulldown Resistance vs Temperature
1000
TA (C)
-40
500
200
100
50
25
85
125
20
10
5
2
1
0.5
0.2
0.1
VIN = 12 V, COUT = 22 μF, CdVdt = Open, VEN/UVLO ramped
from 0 V → 1.4 V → 0 V
1
2
3
4
5 6 7 8 10
PD (W)
20
30 40 5060
Figure 7-29. Time to Thermal Shut-Down During Steady State
Figure 7-30. Power Up and Down With EN/UVLO Control
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7.7 Typical Characteristics (continued)
VEN/UVLO = 2 V, COUT = 22 μF, CdVdt = Open, VIN ramped from
0 V → 12 V → 0 V
COUT = 22 μF, CdVdt = Open, EN/UVLO connected to IN
through resistor ladder, 12 V hot-plugged to IN
Figure 7-31. Power Up and Down With Input Supply
Figure 7-32. Input Hot-Plug
VIN = 12 V, COUT = 470 μF, CdVdt = Open, VEN/UVLO stepped
up to 3.3 V
VIN = 12 V, COUT = 470 μF, CdVdt = 5100 pF, VEN/UVLO stepped
up to 3.3 V
Figure 7-33. Inrush Current Without Slew Rate Control –
Capacitive Load
Figure 7-34. Inrush Current With Slew Rate Control – Capacitive
Load
VIN = 12 V, COUT = 470 μF, ROUT = 10 Ω, CdVdt = 5100 pF,
VEN/UVLO stepped up to 3.3 V
OV threshold set to 16.7 V, VIN ramped up from 12 V to 17 V
Figure 7-36. Overvoltage Lockout Response – TPS25970x and
TPS25974x
Figure 7-35. Inrush Current With Slew Rate Control – Resistive
and Capacitive Load
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7.7 Typical Characteristics (continued)
ROVCSEL = Open, COUT = 220 μF, IOUT = 200 mA, VIN ramped
up from 5 V to 7.5 V
ROVCSEL = GND, COUT = 220 μF, IOUT = 200 mA, VIN ramped
up from 3.3 V to 5.8 V
Figure 7-38. Overvoltage Clamp Response – TPS25972x
Figure 7-37. Overvoltage Clamp Response – TPS25972x
ROVCSEL = 390 kΩ, COUT = 220 μF, IOUT = 200 mA, VIN
ramped up from 12 V to 16.5 V
VIN = 12 V, CITIMER = 1.3 nF, COUT = 220 μF, RILM = 715 Ω,
IOUT stepped from 0 A → 11 A
Figure 7-39. Overvoltage Clamp Response – TPS25972x
Figure 7-40. Active Current Limit Response – TPS25970x
VIN = 12 V, CITIMER = 120 pF, COUT = 470 μF, RILM = 715 Ω,
IOUT ramped from 0 A → 8 A→ 4 A within 100 μs
VIN = 12 V, CITIMER = 1.3 nF, COUT = 220 μF, RILM = 715 Ω,
IOUT stepped from 0 A → 11 A
Figure 7-42. Transient Overcurrent Blanking Timer Response
Figure 7-41. Active Current Limit Response Followed by TSD –
TPS25970x
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7.7 Typical Characteristics (continued)
VIN = 12 V, CITIMER = 1.3 nF, COUT = 470 μF, RILM = 715 Ω,
IOUT stepped from 0 A → 11 A
VIN = 12 V, RILM = 715 Ω, OUT stepped from Open → Short-
circuit to GND
Figure 7-43. Circuit-Breaker Response TPS25974x
Figure 7-44. Output Short-Circuit During Steady State
VIN = 12 V, RILM = 715 Ω, OUT stepped from Open → Short-
circuit to GND
VIN = 12 V, COUT = Open, OUT short-circuit to GND, RILM
715 Ω, VEN/UVLO stepped from 0 V to 3.3 V
=
Figure 7-45. Output Short-Circuit During Steady State (Zoomed
In)
Figure 7-46. Power Up into Short-Circuit
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8 Detailed Description
8.1 Overview
The TPS2597xx is an eFuse with an integrated power path that is used to ensure safe power delivery in a
system. The device starts its operation by monitoring the IN bus. When the input supply voltage (VIN) exceeds
the undervoltage protection threshold (VUVP), the device samples the EN/UVLO pin. A high level (> VUVLO) on
this pin enables the internal power path (HFET) to start conducting and allow current to flow from IN to OUT.
When EN/UVLO is held low (< VUVLO), the internal power path is turned off.
After a successful start-up sequence, the device now actively monitors its load current and input voltage, and
controls the internal HFET to ensure that the user adjustable overcurrent limit threshold (ILIM) is not exceeded
and overvoltage spikes are either safely clamped to the selected threshold voltage (VOVC) or cut-off after they
cross the user-adjustable overvoltage lockout threshold (VOVLO). The device also provides fast protection against
severe overcurrent during short-circuit events. This feature keeps the system safe from harmful levels of voltage
and current. At the same time, a user-adjustable overcurrent blanking timer allows the system to pass moderate
transient peaks in the load current profile without tripping the eFuse. This action ensures a robust protection
solution against real faults which is also immune to transients, thereby ensuring maximum system uptime.
The device also has a built-in thermal sensor based shutdown mechanism to protect itself in case the device
temperature (TJ) exceeds the recommended operating conditions.
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8.2 Functional Block Diagram
FFT
TPS25970x
354 mV
Temp Sense and
Overtemperature
protection
TSD
IN
5
OUT
6
7
INRUSH_DONE
HFET
DVDT
CP
2.8 V
3.4 ꢀA
+
UVPb
2.54 V9
2.45 V;
-
GHI
FFT
GHI
105.5 ꢀA/A
-
2x
1x
-
SC
OC
2
OVLO
OVLOb
UVLOb
HFET Control
1.2 V9
1.1 V;
+
-
+
Current Limit Amplifier
+
1
EN/UVLO
+
ILM
9
1.2 V9
1.1 V;
-
SWEN
Short
Detect
-
SD
ILM Pin Short
+
0.75 V;
RETRY#
1.05 V; 2.57 V
SD
UVPb
R
S
/Q
Q
RETRY#
110 ms
TIMER#
+
ITIMER_EXPIRED
TSD
FLT
10
ITIMER
-
ILM Pin Short
OC
ITIMER_EXPIRED
2 ꢀA
GND
8
4
FLT
# Not applicable to Latch-off variants (TPS25970L)
3
DNC
Figure 8-1. TPS25970x Block Diagram
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FFT
TPS25972x
354 mV
Temp Sense and
Overtemperature
TSD
protection
6
7
OUT
5
IN
INRUSH_DONE
HFET
DVDT
CP
+
2.8 V
3.4 ꢀA
UVPb
2.54 V9
2.45 V;
-
+
GHI
105.5 ꢀA/A
FFT
GHI
-
OVC
OVC Threshold
Select
-
2x
1x
OVCSEL
EN/UVLO
2
SC
OC
HFET Control
Current Limit Amplifier
+
-
+
1
UVLOb
+
ILM
9
1.2 V9
-
1.1 V;
SWEN
Short
Detect
-
SD
ILM Pin Short
+
0.75 V;
2.57 V
1.05 V;
PG_int
OVC
INRUSH_DONE
+
-
SD
UVPb
R
ITIMER_EXPIRED
/Q
Q
RETRY#
ITIMER
10
PG_int
TSD
SD
OC
FLT
S
PG_int
UVPb
ILM Pin Short
2 ꢀA
8
GND
R
Q
S
110 ms
TIMER#
RETRY#
/Q
1.2 V9
1.1 V;
4
3
PG
PGTH
# Not applicable to Latch-off variants (TPS25972L)
Figure 8-2. TPS25972x Block Diagram
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FFT
TPS25974x
354 mV
Temp Sense and
Overtemperature
protection
TSD
OUT
5
6
7
IN
INRUSH_DONE
HFET
DVDT
CP
2.8 V
3.4 ꢀA
+
UVPb
2.54 V9
2.45 V;
-
GHI
105.5 ꢀA/A
FFT
GHI
-
2x
1x
-
SC
OC
OVLO
2
1
OVLOb
UVLOb
HFET Control
Current Limit Amplifier
1.2 V9
+
+
-
1.1 V;
+
EN/UVLO
+
ILM
9
1.2 V9
1.1 V;
-
SWEN
Short
Detect
INRUSH_DONE
-
SD
ILM Pin Short
+
0.75 V;
PG_int
1.05 V; 2.57 V
INRUSH_DONE
+
SD
UVPb
R
S
/Q
Q
ITIMER_EXPIRED
PG_int
RETRY#
OVLOb
PG_int
10 ITIMER
-
TSD
ILM Pin Short
SD
FLT
OC
UVPb
ITIMER_EXPIRED
2 ꢀA
8
GND
R
Q
S
110 ms
TIMER#
RETRY#
/Q
1.2 V9
1.1 V;
3
4
PGTH
# Not applicable to Latch-off variants (TPS25974L)
Figure 8-3. TPS25974x Block Diagram
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8.3 Feature Description
The TPS2597xx eFuse is a compact, feature-rich power management device that provides detection, protection,
and indication in the event of system faults.
8.3.1 Undervoltage Lockout (UVLO and UVP)
The TPS2597xx implements undervoltage protection on IN in case the applied voltage becomes too low for the
system or device to properly operate. The undervoltage protection has a default lockout threshold of VUVP which
is fixed internally. Also, the UVLO comparator on the EN/UVLO pin allows the undervoltage protection threshold
to be externally adjusted to a user-defined value. Figure 8-4 and Equation 1 show how a resistor divider can be
used to set the UVLO set point for a given voltage supply.
Power
Supply
IN
R1
EN/UVLO
R2
GND
Figure 8-4. Adjustable Undervoltage Protection
VUVLO × (R1 + R2)
VIN(UV) =
(1)
R2
8.3.2 Overvoltage Lockout (OVLO)
The TPS25970x and TPS25974x variants allow the user to implement overvoltage lockout to protect the load
from input overvoltage conditions. The OVLO comparator on the OVLO pin allows the overvoltage protection
threshold to be adjusted to a user-defined value. After the voltage at the OVLO pin crosses the OVLO rising
threshold, VOV(R), the device turns off the power to the output. Thereafter, the devices wait for the voltage at the
OVLO pin to fall below the OVLO falling threshold, VOV(F) before the output power is turned ON again. The rising
and falling thresholds are slightly different to provide hysteresis. Figure 8-5 and Equation 2 show how a resistor
divider can be used to set the OVLO set point for a given voltage supply.
Power
Supply
IN
R1
OVLO
R2
GND
Figure 8-5. Adjustable Overvoltage Protection
VOV × (R1 + R2)
VIN(OV) =
(2)
R2
While recovering from a OVLO event, the TPS25970x variants start up with inrush control (dVdt).
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Input Overvoltage Event
Input Overvoltage Removed
IN
0
VOV(R)
OVLO
VOV(F)
tOVLO
0
OUT
dVdt Limited Start-up
0
VFLT
FLT
0
Time
Figure 8-6. TPS25970x Overvoltage Lockout and Recovery
While recovering from an OVLO event, the TPS25974x variants start up with inrush control (dVdt).
Input Overvoltage Event
Input Overvoltage Removed
IN
0
VOV(R)
VOV(F)
OVLO
tOVLO
0
OUT
dVdt Limited Start-up
0
VPG
0
tPGA
tPGD
PG
Time
Figure 8-7. TPS25974x Overvoltage Lockout and Recovery
8.3.3 Overvoltage Clamp (OVC)
The TPS25972x variants implement a voltage clamp on the output to protect the system in the event of input
overvoltage. When the device detects the input has exceeded the overvoltage clamp threshold (VOVC), it quickly
responds within tOVC and stops the output from rising further. the device then regulates the HFET linearly to
clamp the output voltage below VCLAMP as long as an overvoltage condition is present on the input.
If the part stays in clamping state for an extended period of time, there is higher power dissipation inside the
part which can eventually lead to thermal shutdown (TSD). After the part shuts down due to TSD fault, it either
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stays latched off (TPS25972L variant) or restart automatically after a fixed delay (TPS25972A variant). See
Overtemperature Protection (OTP) for more details on device response to overtemperature.
Input Overvoltage Event
Input Overvoltage Removed
VOVC
IN
Thermal
Shutdown
Retry Timer Expired (1)
0
tOVC
tRST
VCLAMP
OUT
PG
TJ
dVdt Limited Start-up
0
tPGD
tPGA
VPG
0
TSD
TSDHYS
Time
(1) Applicable only for TPS25972A (Auto-retry variant)
Figure 8-8. TPS25972x Overvoltage Response (Auto-Retry)
There are three available overvoltage clamp threshold options, which can be configured using the OVCSEL pin.
Table 8-1. TPS25972x Overvoltage Clamp Threshold Selection
OVCSEL PIN CONNECTION
OVERVOLTAGE CLAMP THRESHOLD
Shorted to GND
Open
3.89 V
5.76 V
13.88 V
Connected to GND through a 390-kΩ resistor
8.3.4 Inrush Current, Overcurrent, and Short Circuit Protection
TPS2597xx incorporates four levels of protection against overcurrent:
1. Adjustable slew rate (dVdt) for inrush current control
2. Adjustable threshold (ILIM) for overcurrent protection during start-up or steady-state
3. Adjustable threshold (ISC) for fast-trip response to severe overcurrent during start-up or steady-state
4. Fixed threshold (IFT) for fast-trip response to quickly protect against hard output short-circuits during steady-
state
8.3.4.1 Slew Rate (dVdt) and Inrush Current Control
During hot-plug events or while trying to charge a large output capacitance at start-up, there can be a large
inrush current. If the inrush current is not managed properly, it can damage the input connectors or cause
the system power supply to droop leading to unexpected restarts elsewhere in the system or both. The inrush
current during turn on is directly proportional to the load capacitance and rising slew rate. Use Equation 3 to find
the slew rate (SR) required to limit the inrush current (IINRUSH) for a given load capacitance (COUT):
IINRUSH mA
COUT µF
SR (V/ms) =
(3)
A capacitor can be connected to the dVdt pin to control the rising slew rate and lower the inrush current during
turn on. Use Equation 4 to calulate the required CdVdt capacitance to produce a given slew rate.
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3300
CdVdt pF =
SR V/ms
(4)
The fastest output slew rate is achieved by leaving the dVdt pin open.
Note
For CdVdt > 10 nF, TI recommends to add a 100-Ω resistor in series with the capacitor on the dVdt pin.
8.3.4.2 Circuit-Breaker
The circuit-breaker variants (TPS25974x) respond to output overcurrent conditions by turning off the output after
a user-adjustable transient fault blanking interval. When the load current exceeds the set overcurrent threshold
(ILIM) set by the ILM pin resistor (RILM), but stays lower than the fast-trip threshold (2 × ILIM), the device starts
discharging the ITIMER pin capacitor using an internal 2-μA pulldown current. If the load current drops below
ILIM before the ITIMER pin capacitor (CITIMER) discharges by ΔVITIMER, the ITIMER is reset by pulling it up to
VINT internally and the circuit breaker action is not engaged. This action allows short load transient pulses to
pass through the device without tripping the circuit. If the overcurrent condition persists, the CITIMER continues to
discharge and after it discharges by ΔVITIMER, the circuit breaker action turns off the HFET immediately. At the
same time, the CITIMER is charged up to VINT again so that it is at its default state before the next overcurrent
event. This action ensures the full blanking timer interval is provided for every overcurrent event. Use Equation 5
to calculate the RILM value for an overcurrent threshold.
5747
ILIM A
RILM Ω =
(5)
Note
1. Leaving the ILM pin Open sets the current limit to nearly zero and results in the part breaking the
circuit with the slightest amount of loading at the output.
2. Shorting the ILM pin to ground at any point during normal operation is detected as a fault and the
part shuts down. There is a minimum current (IFLT) which the part allows in this condition before
the pin short condition is detected.
The duration for which transients are allowed can be adjusted using an appropriate capacitor value from ITIMER
pin to ground. Use Equation 6 to calculate the CITIMER value needed to set the desired transient overcurrent
blanking interval.
∆ VITIMER (V) × CITIMER (nF)
tITIMER (ms) =
(6)
IITIMER (µA)
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Transient Overcurrent
Persistent Output Overload
ITIMER expired
2 x ILIM
Circuit-Breaker
operation
IOUT
ILIM
0
tITIMER
VINT
∆VITIMER
ITIMER
0
VIN
OUT
0
VPGTH
PGTH
0
tPGD
VPG
PG
0
TSD
TSDHYS
TJ
TJ
Time
Figure 8-9. TPS25974x Overcurrent Response
Note
1. Leave the ITIMER pin open to allow the part to break the circuit with the minimum possible delay.
2. Shorting the ITIMER pin to ground results in minimum overcurrent response delay (similar to
ITIMER pin open condition), but increases the device current consumption. This action is not a
recommended mode of operation.
3. Increasing the ITIMER cap value extends the overcurrent blanking interval, but it also extends
the time needed for the ITIMER cap to recharge up to VINT. If the next overcurrent event occurs
before the ITIMER cap is recharged fully, it takes less time to discharge to the ITIMER expiry
threshold, thereby providing a shorter blanking interval than intended.
After the part shuts down due to a circuit-breaker fault, it either stays latched off (TPS25974L variant) or restart
automatically after a fixed delay (TPS25974A variant).
8.3.4.3 Active Current Limiting
The active current limit variants (TPS25970x and TPS25972x) respond to output overcurrent conditions by
actively limiting the current after a user adjustable transient fault blanking interval. When the load current
exceeds the set overcurrent threshold (ILIM) set by the ILM pin resistor (RILM), but stays lower than the
short-circuit threshold (2 × ILIM), the device starts discharging the ITIMER pin capacitor using an internal 2-μA
pulldown current. If the load current drops below the overcurrent threshold before the ITIMER capacitor (CITIMER
)
discharges by ΔVITIMER, the ITIMER is reset by pulling it up to VINT internally and the current limit action is not
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engaged. This event allows short load transient pulses to pass through the device without getting current limited.
If the overcurrent condition persists, the CITIMER continues to discharge and after it discharges by ΔVITIMER, the
current limit starts regulating the HFET to actively limit the current to the set overcurrent threshold (ILIM). At the
same time, the CITIMER is charged up to VINT again so that it is at its default state before the next overcurrent
event. This event ensures the full blanking timer interval is provided for every overcurrent event. Use Equation 7
to calculate the RILM value for a desired overcurrent threshold.
5747
ILIM A
RILM Ω =
(7)
Note
1. Leaving the ILM pin open sets the current limit to nearly zero and results in the part entering
current limit with the slightest amount of loading at the output.
2. The current limit circuit employs a foldback mechanism. The current limit threshold in the foldback
region (0 V < VOUT < VFB) is lower than the steady state current limit threshold (ILIM).
3. Shorting the ILM pin to ground at any point during normal operation is detected as a fault and the
part shuts down. There’s a minimum current (IFLT) which the part allows in this condition before
the pin short condition is detected.
The duration for which transients are allowed can be adjusted using an appropriate capacitor value from ITIMER
pin to ground. Use Equation 8 to calculate the CITIMER value needed to set the desired transient overcurrent
blanking interval.
∆ VITIMER (V) × CITIMER (nF)
tITIMER (ms) =
(8)
IITIMER (µA)
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Overload Removed
Persistent Output Overload
Transient Overcurrent
Persistent Output Overload
ITIMER expired
ITIMER expired
Thermal shutdown
2 x ILIM
tLIM
tLIM
IOUT
ILIM
Current limiting
operation
Current limiting
operation
0
tITIMER
tITIMER
VINT
∆VITIMER
ITIMER
0
VIN
OUT
0
1.2 V
PGTH(1)
tPGD
tPGD
tPGA
0
VPG
PG(1)
0
VFLT
FLT(2)
0
TSD
TSDHYS
TJ
TJ
Time
(1) Applicable only to TPS25972x and TPS25974x variants
(2) Applicable only to TPS25970x variants
Figure 8-10. TPS25970x and TPS25972x Active Current Limit Response
Note
1. Leave the ITIMER pin open to allow the part to limit the current with the minimum possible delay.
2. Shorting the ITIMER pin to ground results in minimum overcurrent response delay (similar to
ITIMER pin open condition), but increases the device current consumption. This action is not a
recommended mode of operation.
3. Active current limiting based on RILM is active during start-up for TPS25970x, TPS25972x (active
current limit) as well as TPS25974x (circuit-breaker) variants. In case the start-up current exceeds
ILIM, the device regulates the current to the set limit. However, during start-up the current limit is
engaged without waiting for the ITIMER delay.
4. For the TPS25972x variants, during overvoltage clamp condition, if an overcurrent event occurs,
the current limit is engaged without waiting for the ITIMER delay.
5. Increasing the CITIMER value extends the overcurrent blanking interval, but it also extends the time
needed for the CITIMER to recharge up to VINT. If the next overcurrent event occurs before the
CITIMER is recharged fully, it takes lesser time to discharge to the ITIMER expiry threshold, thereby
providing a shorter blanking interval than intended.
During active current limit, the output voltage drops, resulting in increased device power dissipation across the
HFET. If the device internal temperature (TJ) exceeds the thermal shutdown threshold (TSD), the HFET is turned
off. After the part shuts down due to TSD fault, it either stays latched off (TPS2597xL variants) or restarts
automatically after a fixed delay (TPS2597xA variants). See Overtemperature Protection (OTP) for more details
on device response to overtemperature.
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8.3.4.4 Short-Circuit Protection
During an output short-circuit event, the current through the device increases very rapidly. When a severe
overcurrent condition is detected, the device triggers a fast-trip response to limit the current to a safe level. The
internal fast-trip comparator employs a scalable threshold (ISC) which is equal to 2 × ILIM. This action enables
the user to adjust the fast-trip threshold rather than using a fixed threshold which can be too high for some low
current systems. The device also employs a fixed fast-trip threshold (IFT) to protect fast protection against hard
short-circuits during steady state. The fixed fast-trip threshold is higher than the maximum recommended user
adjustable scalable fast-trip threshold. After the current exceeds ISC or IFT, the HFET is turned off completely
within tFT. Thereafter, the devices tries to turn the HFET back on after a short de-glitch interval (30 μs) in a
current limited manner instead of a dVdt limited manner. This action ensures that the HFET has a faster recovery
after a transient overcurrent event and minimizes the output voltage droop. However, if the fault is persistent, the
device stays in current limit causing the junction temperature to rise and eventually enter thermal shutdown. For
details on the device response to overtemperature, see Overtemperature Protection (OTP).
Persistent Severe Overcurrent
Thermal Shutdown
Overcurrent Removed
Retry Timer Elapsed (3)
Transient Severe Overcurrent
Output Hard Short-circuit to ground
Thermal Shutdown
Short-circuit Removed
Retry Timer Elapsed (3)
VIN
IN
0
tFT
tSC
tSC
IFT
2 x ILIM
IOUT
ILIM
0
VIN
OUT
Current Limited
Start-up
0
dVdt Limited
Start-up
dVdt Limited
Start-up
tPGD
tPGD
tPGD
VPG
tPGA
tPGA
tPGA
(1)
PG
0
VFLT
(2)
FLT
0
tRST
tRST
TSD
TSDHYS
TJ
Time
(1)
Applicable only to TPS25972x and TPS25974x variants
Applicable only to TPS25970x variants
Applicable only to TPS2597xA variants
(2)
(3)
Figure 8-11. TPS2597xx Short-Circuit Response
8.3.5 Analog Load Current Monitor
The device allows the system to accurately monitor the output load current by providing an analog current sense
output on the ILM pin, which is proportional to the current through the FET. The user can sense the voltage
(VILM) across the RILM to get a measure of the output load current.
VILM (µV)
RILM (Ω) × GIMON (µA/A)
IOUT (A) =
(9)
The waveform below shows the ILM signal response to a load step at the output.
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VIN = 12 V, RILM = 715 Ω, IOUT varied dynamically between 0 A and 5.5 A
Figure 8-12. Analog Load Current Monitor Response
Note
The ILM pin is sensitive to capacitive loading. Careful design and layout is needed to ensure the
parasitic capacitive loading on the ILM pin is < 50 pF for stable operation.
8.3.6 Overtemperature Protection (OTP)
The device monitors the internal die temperature (TJ) at all times and shuts down the part as soon as the
temperature exceeds a safe operating level (TSD), thereby protecting the device from damage. The device does
not turn back on until the junction cools down sufficiently, that is the die temperature falls below (TSD – TSDHYS).
When the TPS2597xL (latch-off variant) detects thermal overload, it shuts down and remains latched-off until
the device is power cycled or re-enabled. When the TPS2597xA (auto-retry variant) detects thermal overload, it
remains off until it has cooled down by TSDHYS. Thereafter, the device remains off for an additional delay of tRST
after which it automatically retries to turn on if it is still enabled.
Table 8-2. Thermal Shutdown
DEVICE
ENTER TSD
EXIT TSD
TJ < TSD – TSDHYS
VIN cycled to 0 V and then above VUVP(R) OR
EN/UVLO toggled below VSD(F)
TPS2597xL (Latch-Off)
TJ ≥ TSD
TJ ≥ TSD
TJ < TSD – TSDHYS
VIN cycled to 0 V and then above VUVP(R) or
TPS2597xA (Auto-Retry)
EN/UVLO toggled below VSD(F) or tRST timer
expired
8.3.7 Fault Response and Indication (FLT)
Table 8-3 summarizes the device response to various fault conditions. Additionally, an active low external fault
indication (FLT) pin is available on the TPS25970x variants.
Table 8-3. Fault Summary
PROTECTION
RESPONSE
FAULT LATCHED
INTERNALLY
FLT ASSERTION
DELAY(1)
EVENT
FLT PIN STATUS (1)
Overtemperature
Shutdown
Shutdown
Y
N
L
Undervoltage (UVP or
UVLO)
H
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Table 8-3. Fault Summary (continued)
PROTECTION
RESPONSE
FAULT LATCHED
INTERNALLY
FLT ASSERTION
DELAY(1)
EVENT
FLT PIN STATUS (1)
Shutdown(1) (2)
N
N
H
Input Overvoltage
Voltage Clamp(2)
N/A
Transient Overcurrent (ILIM
None
N
N
< IOUT < 2 × ILIM
)
Persistent Overcurrent
Persistent Overcurrent
Circuit Breaker(3)
Current Limit(4)
Y
N
N/A
L
tITIMER
Output Short-Circuit to
GND
Circuit Breaker followed by
Current Limit
N
H
ILM Pin Open
(During Steady State)
Shutdown
Shutdown
N
Y
L
L
tITIMER
tITIMER
ILM Pin Shorted to GND
(1) Applicable to TPS25970x variants only.
(2) Applicable to TPS25972x variants only.
(3) Applicable to TPS25974x variants only.
(4) Applicable to TPS25970x and TPS25972x variants only.
Faults which are latched internally can be cleared either by power cycling the part (pulling VIN to 0 V) or by
pulling the EN/UVLO pin voltage below VSD. This action also releases the FLT pin for the TPS25970x variants
and resets the tRST timer for the TPS2597xA (auto-retry) variants.
During a latched fault, pulling the EN/UVLO just below the UVLO threshold has no impact on the device. This
fact is true for both TPS2597xL (latch-off) and TPS2597xA (auto-retry) variants.
For TPS2597xA (auto-retry) variants, on expiry of the tRST timer after a fault, the device restarts automatically
and the FLT pin is de-asserted (TPS25970A variant).
8.3.8 Power-Good Indication (PG)
The TPS25972x and TPS25974x variants provide an active high digital output (PG) which serves as a power-
good indication signal and is asserted high depending on the voltage at the PGTH pin along with the device
state information. The PG is an open-drain pin and must be pulled up to an external supply.
After power up, PG is pulled low initially. The device initiates a inrush sequence in which the HFET is turned
on in a controlled manner. When the HFET gate voltage reaches the full overdrive indicating that the inrush
sequence is complete and the voltage at PGTH is above VPGTH(R), the PG is asserted after a de-glitch time
(tPGA).
PG is de-asserted if at any time during normal operation, the voltage at PGTH falls below VPGTH(F), or the device
detects a fault (except overcurrent). The PG de-assertion de-glitch time is tPGD
.
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Overload Event
Overcurrent blanking timer expired
Overload Removed
Device Enabled
VUVLO(R)
0
EN/UVLO
IN
Slew rate (dVdt) controlled
startup/Inrush current limiting
0
Active Current
limiting (1)
VIN
OUT
0
VPGTH(R)
VPGTH(F)
(2)
PGTH
0
VPG
(2)
tPGA
tPGD
PG
tPGA
0
VIN
dVdt
0
VOUT + 2.8V
VHGate
0
tITIMER
ILIM
IINRUSH
IOUT
0
Time
(1)
(2)
Not applicable to TPS25974x
Not applicable to TPS25970x
Figure 8-13. TPS25972x, TPS25974x PG Timing Diagram
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Table 8-4. TPS25972x and TPS25974x PG Indication Summary
EVENT
DEVICE STATUS
PG PIN STATUS
PG PIN TOGGLE DELAY
Undervoltage (UVP or UVLO)
OFF
L
H (If PGTH pin voltage >
VPGTH(R)
L (If PGTH pin voltage <
VPGTH(F)
Overvoltage
)
tPGA
tPGD
ON (Clamping)
(TPS25972x only)
)
Overvoltage
OFF
ON
L
tPGD
(TPS25974x only)
H (If PGTH pin voltage >
VPGTH(R)
L (If PGTH pin voltage <
VPGTH(F)
)
tPGA
tPGD
Steady state
)
H (If PGTH pin voltage >
VPGTH(R)
L (If PGTH pin voltage <
VPGTH(F)
)
tPGA
tPGD
Transient overcurrent
ON
)
H (If PGTH pin voltage >
VPGTH(R)
L (If PGTH pin voltage <
VPGTH(F)
Persistent overload (TPS25972x
only)
)
tPGA
tPGD
ON (Current Limiting)
)
Persistent overload (TPS25974x
only)
OFF (Circuit-Breaker)
L
tPGD
H (If PGTH pin voltage >
VPGTH(R)
)
tPGA
tPGD
Output short-circuit to GND
Fast-trip followed by Current Limit
L (If PGTH pin voltage <
VPGTH(F)
)
ILM pin open
OFF
OFF
OFF
L (If PGTH < 1.1 V)
tPGD + tITIMER
tPGD
ILM pin shorted to GND
Overtemperature
L
L
tPGD
When there is no supply to the device, the PG pin is expected to stay low. However, there is no active pulldown
in this condition to drive this pin all the way down to 0 V. If the PG pin is pulled up to an independent supply
which is present even if the device is unpowered, there can be a small voltage seen on this pin depending on the
pin sink current, which is a function of the pullup supply voltage and resistor. Minimize the sink current to keep
this pin voltage low enough not to be detected as a logic HIGH by associated external circuits in this condition.
8.4 Device Functional Modes
The TPS25970x and TPS25974x variants have only one functional mode that applies when operated within the
recommended operating conditions.
The TPS25972x variants have three different functional modes depending on the OVCSEL pin connection.
Table 8-5. TPS25972x Overvoltage Clamp Threshold Selection
OVCSEL PIN CONNECTION
OVERVOLTAGE CLAMP THRESHOLD
Shorted to GND
3.89 V
5.76 V
13.88 V
Open
Connected to GND through a 390-kΩ resistor
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
The TPS2597xx is a 2.7-V to 23-V, 7-A eFuse that is typically used for power rail protection applications.
The device operates from 2.7 V to 23 V with adjustable overvoltage and undervoltage protection. The device
provides ability to control inrush current and protection against overcurrent conditions. The device can be used
in a variety of systems such as adapter input protection, server, PC motherboard, add-on cards, enterprise
storage – RAID/HBA/SAN/eSSD, retail point-of-sale terminals, smartphones, and tablets. The design procedure
explained in the subsequent sections can be used to select the supporting component values based on the
application requirement. Additionally, a spreadsheet design tool, TPS2597xx Design Calculator, is available in
the web product folder.
9.1.1 Single Device, Self-Controlled
VOUT
VIN = 2.7 to 23
V
VOUT
VIN = 2.7 to 23 V
IN
OUT
IN
OUT
COUT
COUT
VLOGIC
VLOGIC
PGTH
EN/UVLO
EN/UVLO
TPS25972x
TPS25970x
OVLO
OVCSEL
PG
FLT
ITIMER dVdt
ITIMER dVdt
GND
ILM
ILM
GND
VOUT
IN
OUT
VIN = 2.7 to 23
V
COUT
VLOGIC
PGTH
EN/UVLO
TPS25974x
OVLO
PG
ITIMER dVdt
GND
ILM
Figure 9-1. Single Device, Self-Controlled
Other variations:
In a Host MCU controlled system, EN/UVLO or OVLO can also be driven from the host GPIO to control the
device.
ILM pin can be connected to the MCU ADC input for current monitoring purpose.
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Note
TI recommends to keep parasitic capacitance on ILM pin below 50 pF to ensure stable operation.
For the TPS25972x and TPS25974x variants, either VIN or VOUT can be used to drive the PGTH resistor divider
depending on which supply must be monitored for Power Good indication.
9.2 Typical Application
TPS2597xx can be used for server add-on card input power protection. During overcurrent or short-circuit event
at load side, TPS2597xx can quickly respond to this fault event by turning off the device and thus protect the
load from damage as well as prevent input supply from drooping. The ITIMER feature allows short duration peak
currents to pass through without tripping the eFuse, thereby meeting the transient load current profile of these
cards.
VOUT
VIN = 12 V
IN
OUT
R4
COUT
R1
D2*
47 kꢁ
470 kꢁ
470 ꢀF
PGTH
EN/UVLO
3.3 V
TPS25974L
R5
R2
5.6 kꢁ
11 kꢁ
CIN
D1*
47 kꢁ
0.1 ꢀF
OVLO
PG
ITIMER dVdt
ILM
GND
R3
RILM
750 ꢁ
CITIMER
1.3 nF
CdVdt
47 kꢁ
5600 pF
* Optional circuit components needed for transient protection depending on input and output inductance.
Please refer to Transient Protection section for details.
Figure 9-2. Server Add-on Card Input Power Protection
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9.2.1 Design Requirements
Table 9-1. Design Parameters
PARAMETER
VALUE
12 V
Input supply voltage (VIN)
Undervoltage threshold (VIN(UV)
)
10.8 V
13.2 V
11.4 V
Overvoltage threshold (VIN(OV)
)
Output Power Good threshold (VPG
Maximum continuous current
)
7 A
1 ms
Load transient blanking interval (tITIMER
)
Output capacitance (COUT
Output rise time (tR)
)
470 μF
20 ms
Overcurrent threshold (ILIM
Overcurrent response
Fault response
)
7.7 A
Circuit breaker
Latch-off
9.2.2 Detailed Design Procedure
9.2.2.1 Device Selection
Because the application requires circuit-breaker response to overcurrent with latch-off response after a fault, the
TPS25974L variant is selected after referring to the Device Comparison Table.
9.2.2.2 Setting Undervoltage and Overvoltage Thresholds
The supply undervoltage and overvoltage thresholds are set using the resistors R1, R2, and R3, whose values
can be calculated using Equation 10 and Equation 11:
VUVLO(R) × (R1 + R2 + R3)
VIN(UV) =
VIN(OV) =
(10)
(11)
R2 + R3
VOV(R) × (R1 + R2 + R3)
R3
Where VUVLO(R) is the UVLO rising threshold and VOV(R) is the OVLO rising threshold. Because R1, R2, and R3
leak the current from input supply VIN, these resistors must be selected based on the acceptable leakage current
from input power supply VIN. The current drawn by R1, R2, and R3 from the power supply is IR123 = VIN / (R1 +
R2 + R3). However, leakage currents due to external active components connected to the resistor string can add
error to these calculations. So, the resistor string current, IR123 must be chosen to be 20 times greater than the
leakage current expected on the EN/UVLO and OVLO pins.
From the device electrical specifications, both the EN/UVLO and OVLO leakage currents are 0.1 μA (maximum),
VOV(R) = 1.2 V and VUVLO(R) = 1.2 V. From design requirements, VIN(OV) = 13.2 V and VIN(UV) = 10.8 V. To solve
the equation, first choose the value of R1 = 470 kΩ and use the above equations to solve for R2 = 10.7 kΩ and
R3 = 48 kΩ.
Using the closest standard 1% resistor values, we get R1 = 470 kΩ, R2 = 11 kΩ, and R3 = 47 kΩ.
9.2.2.3 Setting Output Voltage Rise Time (tR)
For a successful design, the junction temperature of the device must be kept below the absolute maximum
rating during both dynamic (start-up) and steady-state conditions. Dynamic power stresses often are an order
of magnitude greater than the static stresses, so it is important to determine the right start-up time and inrush
current limit required with system capacitance to avoid thermal shutdown during start-up.
The slew rate (SR) needed to achieve the desired output rise time can be calculated as:
VIN V
tR ms
12 V
SR (V/ms) =
=
= 0.6 V/ms
20 ms
(12)
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The CdVdt needed to achieve this slew rate can be calculated as:
3300
SR V/ms
3300
= 5500 pF
0.6
CdVdt pF =
=
(13)
Choose the nearest standard capacitor value as 5600 pF.
For this slew rate, the inrush current can be calculated as:
IINRUSH mA = SR (V/ms) × COUT µF = 0.6 × 470 = 282 mA
(14)
(15)
The average power dissipation inside the part during inrush can be calculated as:
IINRUSH A × VIN V
2
0.282 × 12
= 1.69 W
2
PDINRUSH W =
=
For the given power dissipation, the thermal shutdown time of the device must be greater than the ramp-up time
tR to avoid start-up failure. Figure 9-3 shows the thermal shutdown limit. For 1.69 W of power, the shutdown time
is more than 10 s, which is very large as compared to tR = 20 ms. Therefore, it is safe to use 20 ms as the
start-up time for this application.
10000
5000
2000
1000
500
200
100
50
20
10
5
2
1
0.5
0.2
0.1
0
20
40
60
80
100
120
140
PD (W)
Figure 9-3. Thermal Shut-Down Plot During Inrush
Note
In some systems, there can be active load circuits (for example, DC-DC converters) with low turn-
on threshold voltages which can start drawing power before the eFuse has completed the inrush
sequence. This action can cause additional power dissipation inside the eFuse during start-up and
can lead to thermal shutdown. TI recommends to use the Power Good (PG) pin of the eFuse to
enable and disable the load circuit. This action ensures that the load is turned on only when the
eFuse has completed its start-up and is ready to deliver full power without the risk of hitting thermal
shutdown.
9.2.2.4 Setting Power-Good Assertion Threshold
The Power Good assertion threshold can be set using the resistors R4 and R5 connected to the PGTH pin,
whose values can be calculated as:
VPGTH(R) × (R4 + R5)
VPG =
(16)
R5
Because R4 and R5 leak the current from the output rail VOUT, these resistors must be selected to minimize
the leakage current. The current drawn by R4 and R5 from the power supply is IR45 = VOUT / (R4 + R5).
However, leakage currents due to external active components connected to the resistor string can add error to
these calculations. So, the resistor string current, IR123 must be chosen to be 20 times greater than the PGTH
leakage current expected.
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From the device electrical specifications, PGTH leakage current is 1 μA (maximum), VPGTH(R) = 1.2 V and from
design requirements, VPG = 11.4 V. To solve the equation, first choose the value of R4 = 47 kΩ and calculate R5
= 5.52 kΩ. Choose the nearest 1% standard resistor value as R5 = 5.6 kΩ.
9.2.2.5 Setting Overcurrent Threshold (ILIM
)
The overcurrent protection (Circuit Breaker) threshold can be set using the RILM resistor whose value can be
calculated as:
5747
ILIM A
5747
= 746.4 Ω
7.7 A
RILM Ω =
=
(17)
Choose nearest 1% standard resistor value as 715 Ω.
9.2.2.6 Setting Overcurrent Blanking Interval (tITIMER
)
The overcurrent blanking timer interval can be set using the CITIMER capacitor whose value can be calculated as:
tITIMER (ms) × IITIMER (µA)
1 × 2
= 1.32 nF
1.52
CITIMER (nF) =
=
(18)
∆ VITIMER (V)
Choose nearest standard capacitor value as 1.3 nF.
9.2.3 Application Curves
Figure 9-4. Power Up
Figure 9-5. Transient Overload
Figure 9-6. Circuit Breaker Response
9.3 Parallel Operation
Applications that need higher steady current can use two TPS25974x devices connected in parallel as shown
in Figure 9-7. In this configuration, the first device turns on initially to provide the inrush current control. The
second device is held in an OFF state by driving its EN/UVLO pin low using the PG signal of the first device.
After the inrush sequence is complete, the first device asserts its PG pin high and turns on the second device.
The second device asserts its PG signal to indicate when it has turned on fully, thereby indicating to the system
that the parallel combination is ready to deliver the full steady state current.
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After in steady state, both devices share current nearly equally. There can be a slight skew in the currents
depending on the part-to-part variation in the RON as well as the PCB trace resistance mismatch.
IN
OUT
VLOGIC
EN/UVLO
PGTH
TPS25974x
PG
OVLO
ITIMER
dVdt
ILM
GND
VOUT
VIN = 2.7 to 23 V
COUT
IN
OUT
EN/UVLO
TPS25974x
PGTH
OVLO
To downstream
enable
PG
ITIMER dVdt
ILM
GND
Figure 9-7. Two Devices Connected in Parallel for Higher Steady State Current Capability
The waveforms below illustrate the behavior of the parallel configuration during start-up as well as during steady
state.
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Figure 9-8. Parallel Devices Sequencing During Start-Up
Figure 9-9. Parallel Devices Load Current During Steady State and Overload
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10 Power Supply Recommendations
The TPS2597xx devices are designed for a supply voltage range of 2.7 V ≤ VIN ≤ 23 V. TI recommends an
input ceramic bypass capacitor higher than 0.1 μF if the input supply is located more than a few inches from
the device. The power supply must be rated higher than the set current limit to avoid voltage droops during
overcurrent and short-circuit conditions.
10.1 Transient Protection
In the case of a short-circuit and overload current limit when the device interrupts current flow, the input
inductance generates a positive voltage spike on the input, and the output inductance generates a negative
voltage spike on the output. The peak amplitude of voltage spikes (transients) is dependent on the value of
inductance in series to the input or output of the device. Such transients can exceed the absolute maximum
ratings of the device if steps are not taken to address the issue. Typical methods for addressing transients
include:
•
•
•
•
•
Minimize lead length and inductance into and out of the device.
Use a large PCB GND plane.
Connect a Schottky diode from the OUT pin ground to absorb negative spikes.
Connect a low ESR capacitor larger than 1 μF at the OUT pin very close to the device.
Use a low-value ceramic capacitor CIN = 1 μF to absorb the energy and dampen the transients. The capacitor
voltage rating must be at least twice the input supply voltage to be able to withstand the positive voltage
excursion during inductive ringing.
Use Equation 19 to estimate the approximate value of input capacitance:
LIN
CIN
VSPIKE(Absolute) = VIN + ILOAD ×
(19)
where
– VIN is the nominal supply voltage.
– ILOAD is the load current.
– LIN equals the effective inductance seen looking into the source.
– CIN is the capacitance present at the input.
•
Some applications can require the addition of a Transient Voltage Suppressor (TVS) to prevent transients
from exceeding the absolute maximum ratings of the device. In some cases, even if the maximum amplitude
of the transients is below the absolute maximum rating of the device, a TVS can help to absorb the excessive
energy dump and prevent it from creating very fast transient voltages on the input supply pin of the IC, which
can couple to the internal control circuits and cause unexpected behavior.
Figure 10-1 shows the circuit implementation with optional protection components.
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VOUT
VIN = 2.7 to 23 V
IN
OUT
R1
CLOAD
D2
COUT
EN/UVLO
TPS25970x
R2
CIN
D1
OVLO
FLT
ITIMER dVdt
GND
ILM
R3
CITIMER
CDVDT
RILM
Figure 10-1. Circuit Implementation With Optional Protection Components
10.2 Output Short-Circuit Measurements
It is difficult to obtain repeatable and similar short-circuit testing results. The following contribute to variation in
results:
•
•
•
•
•
•
•
Source bypassing
Input leads
Circuit layout
Component selection
Output shorting method
Relative location of the short
Instrumentation
The actual short exhibits a certain degree of randomness because it microscopically bounces and arcs. Ensure
that configuration and methods are used to obtain realistic results. Do not expect to see waveforms exactly like
those in this data sheet because every setup is different.
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11 Layout
11.1 Layout Guidelines
•
For all applications, TI recommends a ceramic decoupling capacitor of 0.1 μF or greater between the IN
terminal and GND terminal.
•
The optimal placement of the decoupling capacitor is closest to the IN and GND terminals of the device. Care
must be taken to minimize the loop area formed by the bypass-capacitor connection, the IN terminal, and the
GND terminal of the IC.
•
•
High current-carrying power-path connections must be as short as possible and must be sized to carry at
least twice the full-load current.
The GND terminal must be tied to the PCB ground plane at the terminal of the IC with the shortest possible
trace. The PCB ground must be a copper plane or island on the board. TI recommends to have a separate
ground plane island for the eFuse. This plane does not carry any high currents and serves as a quiet ground
reference for all the critical analog signals of the eFuse. The device ground plane must be connected to the
system power ground plane using a star connection.
•
•
The IN and OUT pins are used for heat dissipation. Connect to as much copper area on top and bottom
PCB layers using as possible with thermal vias. The vias under the device also help to minimize the voltage
gradient across the IN and OUT pads and distribute current uniformly through the device, which is essential
to achieve the best on-resistance and current sense accuracy.
Locate the following support components close to their connection pins:
– RILM
– CdVdT
– CITIMER
– Resistors for the EN/UVLO, OVLO/OVCSEL, and PGTH pins
•
Connect the other end of the component to the GND pin of the device with shortest trace length. The trace
routing for the RILM, CITIMER and CdVdt components to the device must be as short as possible to reduce
parasitic effects on the current limit, overcurrent blanking interval and soft start timing. It's recommended to
keep parasitic capacitance on ILM pin below 50 pF to ensure stable operation. These traces must not have
any coupling to switching signals on the board.
•
•
Because the bias current on ILM pin directly controls the overcurrent protection behavior of the device, the
PCB routing of this node must be kept away from any noisy (switching) signals.
Protection devices such as TVS, snubbers, capacitors, or diodes must be placed physically close to the
device they are intended to protect. These protection devices must be routed with short traces to reduce
inductance. For example, TI recommends a protection Schottky diode to address negative transients due to
switching of inductive loads. TI also recommends to add a ceramic decoupling capacitor of 1 μF or greater
between OUT and GND. These components must be physically close to the OUT pins. Care must be taken
to minimize the loop area formed by the Schottky diode/bypass-capacitor connection, the OUT pin, and the
GND terminal of the IC.
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11.2 Layout Example
Inner GND layer
Top Power layer
Bottom Power layer
6
OUT
IN
OUT
5
IN
Figure 11-1. Layout Example - Single TPS25974x With PGTH Referred to OUT
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12 Device and Documentation Support
TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,
generate code, and develop solutions are listed below.
12.1 Device Support
12.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
12.2 Documentation Support
12.2.1 Related Documentation
For related documentation see the following:
•
•
Texas Instruments, TPS2597EVM eFuse Evaluation Board user's guide
Texas Instruments, TPS2597xx Design Calculator
12.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.5 Trademarks
HotRod™ and TI E2E™ are trademarks of Texas Instruments.
All trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.7 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
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13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
28-Dec-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
PTPS25970ARPWR
PTPS25972ARPWR
PTPS25974LRPWR
TPS25970ARPWR
TPS25972LRPWR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
VQFN-HR
VQFN-HR
VQFN-HR
VQFN-HR
VQFN-HR
RPW
RPW
RPW
RPW
RPW
10
10
10
10
10
3000
3000
3000
TBD
TBD
TBD
Call TI
Call TI
Call TI
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
Call TI
Call TI
Call TI
3000 RoHS & Green
3000 RoHS & Green
NIPDAU
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
2KNH
2KQH
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
28-Dec-2021
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
29-Dec-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS25970ARPWR
TPS25972LRPWR
VQFN-
HR
RPW
RPW
10
10
3000
3000
180.0
8.4
2.3
2.3
1.15
4.0
8.0
Q2
VQFN-
HR
180.0
8.4
2.3
2.3
1.15
4.0
8.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
29-Dec-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS25970ARPWR
TPS25972LRPWR
VQFN-HR
VQFN-HR
RPW
RPW
10
10
3000
3000
210.0
210.0
185.0
185.0
35.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
VQFN-HR - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
RPW0010A
2.1
1.9
A
B
2.1
1.9
PIN 1 IDENTIFICATION
(0.1) TYP
1 MAX
C
SEATING PLANE
0.08 C
0.05
0.00
2X 1.45
PKG
4X
SQ (0.15) TYP
4X 0.475
4
2X 0.25
6
5
7
0.35
4X
4X 0.475
0.25
0.1
C A B
C
0.05
2.1
1.9
2X
2X 0.45
PKG
4X
0.3
0.2
0.1
0.05
C A B
C
1
10
0.3
0.2
PIN 1 ID
(OPTIONAL)
4X
0.5
0.3
0.35
0.25
8X
2X
0.1
C A B
C
0.1
C A B
0.05
0.05
C
4225183/A 08/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
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EXAMPLE BOARD LAYOUT
VQFN-HR - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
RPW0010A
(1.8)
(1.45)
4X (0.475)
2X (0.25)
1
10
4X (0.25)
4X
(0.225)
PKG
2X
2X
(1.75)
(2.4)
4X (0.3)
4X (0.475)
7
4
4X
(0.65)
(R0.05) TYP
6
5
2X (0.3)
4X (0.25)
PKG
8X (0.6)
LAND PATTERN EXAMPLE
SCALE: 30X
SOLDER MASK
OPENING
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
METAL
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
SOLDER MASK
DEFINED
NON- SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
4225183/A 08/2019
NOTES: (continued)
3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).
4. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
VQFN-HR - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
RPW0010A
(1.8)
(1.425)
4X (0.4625)
2X (0.25)
METAL TYP
1
10
4X (0.25)
4X
(0.63)
PKG
2X
(1.75)
4X (0.225)
4X (0.275)
4X
4X (0.4625)
(1.06)
7
4
4X
(0.65)
(R0.05)
TYP
6
5
4X (0.28)
4X (0.225)
PKG
8X (0.6)
SOLDER PASTE EXAMPLE
BASED ON 0.100 mm THICK STENCIL
PADS 1, 4,7 & 10: 93%; PADS 5 & 6: 82%
SCALE: 30X
4225183/A 08/2019
NOTES: (continued)
5.
Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
resources.
TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with
such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for
TI products.
TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2021, Texas Instruments Incorporated
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TI
TPS25972LRPW
TPS2597xx 2.7 Vâ23 V, 7-A, 9.8-mΩ eFuse With Accurate Current Monitor and Transient Overcurrent BlankingWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TI
TPS25972LRPWR
TPS2597xx 2.7 Vâ23 V, 7-A, 9.8-mΩ eFuse With Accurate Current Monitor and Transient Overcurrent BlankingWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TI
TPS25974ARPW
TPS2597xx 2.7 Vâ23 V, 7-A, 9.8-mΩ eFuse With Accurate Current Monitor and Transient Overcurrent BlankingWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TI
TPS25974ARPWR
具有精确电流监视器和瞬态过流消隐功能的 2.7V 至 23V、7A、9.8mΩ 电子保险丝 | RPW | 10 | -40 to 125Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TI
TPS25974LRPW
TPS2597xx 2.7 Vâ23 V, 7-A, 9.8-mΩ eFuse With Accurate Current Monitor and Transient Overcurrent BlankingWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TPS25974LRPWR
具有精确电流监视器和瞬态过流消隐功能的 2.7V 至 23V、7A、9.8mΩ 电子保险丝 | RPW | 10 | -40 to 125Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TI
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