TPS259802O_技术文档

TPS25980

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TPS25980: 2.7- 24 V, 8 A, 3 mΩ Smart eFuse - Integrated Hot-swap Protection With

Adjustable Transient Fault Management

1 Features

3 Description

•

Wide input voltage range: 2.7 V to 24 V

– 30-V Absolute maximum

Low On-Resistance: R_ON= 3-mΩ typical

Circuit Breaker Response

Adjustable current limit threshold

– Range: 2 A to 8 A

– Accuracy: ± 8% (typical for I_LIM> 5 A)

Adjustable over-current blanking timer

– Handles load transients without tripping

Accurate current monitor output

– ± 3% (typical at 25 °C for I_OUT> 3 A)

User configurable fault response

– Latch-off or auto-retry

– Number of retries (Finite or indefinite)

– Delay between retries

Robust short-circuit protection

– Fast-trip response time < 400-ns typical

– Tested against 1 million power-into-short events

– Immune to line transients - no nuisance tripping

Adjustable output slew rate (dVdt) control

Adjustable undervoltage lockout

Overvoltage lockout (Fixed 3.7-V, 7.6-V, 16.9-V

and no-OVLO options)

Integrated overtemperature protection

Power good indication

Adjustable load detect and handshake timer

UL 2367 Recognition

The TPS25980x family of eFuses is a highly

integrated circuit protection and power management

solution in a small package. The devices are

operational over a wide input voltage range. A single

part caters to low-voltage systems needing minimal

I*R voltage drop as well as higher voltage, high

current systems needing low power dissipation. They

are a robust defense against overloads, short-circuits,

voltage surges and excessive inrush current.

•

Overvoltage events are limited by internal cutoff

circuits, with multiple device options to choose the

overvoltage threshold.

The device provides a circuit-breaker response to

overcurrent conditions. The overcurrent limit (circuit-

breaker threshold) and fast-trip (short-circuit)

threshold can be set with a single external resistor.

The devices intelligently manage the overcurrent

response by distinguishing between transient events

and actual faults, thereby allowing the system to

function uninterrupted during line and load transients

without compromising on the robustness of the

protection against faults. The device can be

configured to stay latched off or retry automatically

after a fault shutdown. The number of auto-retries as

well as the retry delay are configurable with

capacitors. This enables remote systems to

automatically recover from temporary faults while

ensuring that power supplies are not stressed

indefinitely due to a persistent fault.

•

– File no. E339631

– R_ILIM≥ 182 Ω

IEC 62368 CB Certification

Small footprint: 4-mm × 4-mm QFN package

The TPS25980x devices are available in a small 4

mm × 4 mm QFN package. The devices are

characterized for operation over a junction

temperature range of –40°C to 125°C.

•

Device Information ⁽¹⁾

2 Applications

PART NUMBER

PACKAGE

BODY SIZE (NOM)

•

Hot-Swap, hot-plug

Server standby rail, PCIe riser, add-on card and

fan module protection

TPS25980x

QFN (24)

4.0 mm × 4.0 mm

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

•

Routers and switches optical module protection

Industrial PC

Digital TV

TPS25980

Power

Supply

IN

OUT

V_PG

R_PG

LDSTRT

R_VL1

EN/UVLO

NRETRY

PG

IMON

C_L

R_L

C_IN

RETRY_DLY

dVdt

*

C_NRETRY

C_LDSTRT

R_VL2

ILIM

R_ILIM

GND ITIMER

C_dVdt

*

C_{RETRY_DLY}

R_IMON

*

C_ITIMER

*

Optional components for extended functionality

Simplified Schematics

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

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Table of Contents

1 Features............................................................................1

2 Applications.....................................................................1

3 Description.......................................................................1

4 Revision History.............................................................. 2

5 Device Comparison Table...............................................3

6 Pin Configuration and Functions...................................4

7 Specifications.................................................................. 6

7.1 Absolute Maximum Ratings........................................ 6

7.2 ESD Ratings............................................................... 6

7.3 Recommended Operating Conditions.........................7

7.4 Thermal Information....................................................7

7.5 Electrical Characteristics.............................................8

7.6 Timing Requirements..................................................9

7.7 Switching Characteristics..........................................10

7.8 Typical Characteristics.............................................. 11

8 Detailed Description......................................................17

8.1 Overview...................................................................17

8.2 Functional Block Diagram.........................................17

8.3 Feature Description...................................................17

8.4 Fault Response.........................................................25

8.5 Device Functional Modes..........................................28

9 Application and Implementation..................................29

9.1 Application Information............................................. 29

9.2 Typical Application: Patient Monitoring System in

Medical Applications....................................................29

9.3 System Examples..................................................... 36

10 Power Supply Recommendations..............................41

10.1 Transient Protection................................................41

10.2 Output Short-Circuit Measurements....................... 42

11 Layout...........................................................................43

11.1 Layout Guidelines................................................... 43

11.2 Layout Example...................................................... 44

12 Device and Documentation Support..........................45

12.1 Documentation Support.......................................... 45

12.2 Receiving Notification of Documentation Updates..45

12.3 Support Resources................................................. 45

12.4 Trademarks.............................................................45

12.5 Electrostatic Discharge Caution..............................45

12.6 Glossary..................................................................45

13 Mechanical, Packaging, and Orderable

Information.................................................................... 46

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

DATE

REVISION

NOTES

August 2020

*

Initial release.

2

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5 Device Comparison Table

OVERVOLTAGE LOCKOUT

THRESHOLD

PART NUMBER

OVERCURRENT RESPONSE

TYPICAL (V)

3.7

TPS259802ONRGE

TPS259803ONRGE

TPS259804ONRGE

TPS259807ONRGE

Circuit Breaker

7.6

16.9

No OVLO

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6 Pin Configuration and Functions

18

17

OUT

IN

1

2

IN

Thermal Pad 1

16

15

14

13

3

4

5

6

dVdt

GND

Thermal Pad 2

EN/UVLO

PG

Figure 6-1. RGE 24-Pin QFN Top View

Pin Functions

TYPE

DESCRIPTION

NAME

NO.

17, 18, 19,

20, 21, 22,

23, 24

OUT

Power

Power Output.

1, 2, 3, 16,

Pad 1

Thermal /

Power

Power Input. The exposed pad must be soldered to input power plane uniformly to ensure

proper heat dissipation and to maintain optimal current distribution through the device.

IN

4, 5, 14,

Pad 2

GND

Ground

Connect to System Ground.

Active High Enable for the device. A resistor divider on this pin from input supply to GND can

be used to adjust the Undervoltage Lockout threshold. Do not leave floating.

EN/UVLO

6

Analog Input

A capacitor from this pin to GND sets the overcurrent blanking interval during which the

output current can temporarily exceed set current limit (but lower than fast-trip threshold)

before the device overcurrent response takes action. Leave this pin open for fastest

response to overcurrent events. Refer to ITIMER Functional Mode Summary for more

details.

Analog

Output

ITIMER

7

Analog

Output

An external resistor from this pin to GND sets the output current limit threshold and fast trip

threshold. Do not leave floating.

ILIM

8

9

Analog output load current monitor. This pin sources a current proportional to the load

current. This can be converted to a voltage signal by connecting an appropriate resistor from

this pin to GND.

Analog

Output

IMON

A capacitor from this pin to GND sets the time period that has to elapse after a fault

shutdown before the device attempts to restart automatically. Connect this pin to GND for

latch-off operation (no auto-retries) after a fault. Refer to Fault Response section for more

details.

Analog

Output

RETRY_DLY

NRETRY

10

11

A capacitor from this pin to GND sets the number of times the part attempts to restart

automatically after shutdown due to fault. Connect this pin to GND if the part should retry

indefinitely. Refer to Fault Response section for more details.

Analog

Output

4

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Pin Functions (continued)

TYPE

DESCRIPTION

NAME

NO.

Load Detect/Handshake Signal. A capacitor from this pin to GND sets the time period after

PG assertion within which the pin has to be pulled low for the device to remain ON. Connect

to GND if the load detect/handshake feature is not used. Refer to Load Detect/Handshake

(LDSTRT) section for more details. Do not leave floating.

LDSTRT

12

Analog Input

Active High Power Good Indication. This pin is asserted when the FET is fully enhanced and

PG

13

15

Digital Output output has reached maximum voltage. It is an open drain output that requires an external

pull-up resistor to an external supply. This pin remains logic low when V_IN< V_UVP

.

Analog

Output

A capacitor from this pin to GND sets the output turn on slew rate. Leave this pin floating for

the fastest slew rate during start up.

dVdt

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7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

Parameter

MIN

–0.3

–0.8

–0.3

MAX UNIT

V_IN

Maximum Input Voltage Range

Maximum Output Voltage Range

Maximum Enable Pin Voltage Range

Maximum LDSTRT Pin Voltage Range

Maximum dVdt Pin Voltage Range

Maximum PG Pin Voltage Range

Maximum ITIMER Pin Voltage Range

Maximum NRETRY Pin Voltage Range

IN

30

V

A

°C

V_OUT

OUT

min (30V, V_IN+ 0.3)

V_EN/UVLO

V_LDSTRT

V_dVdt

EN/UVLO

LDSTRT

dVdt

7

Internally Limited

–0.3

V_PG

PG

7

V_ITIMER

V_NRETRY

V_{RETRY_DLY}

I_MAX

ITIMER

NRETRY

Internally Limited

Maximum RETRY_DLY Pin Voltage Range RETRY_DLY

Maximum Continuous Switch Current

Junction temperature

IN to OUT

T_J

T_LEAD

T_stg

Maximum Soldering Temperature

Storage temperature

300 °C

150 °C

–65

(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under

Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device

reliability.

7.2 ESD Ratings

VALUE

UNIT

Human body model (HBM), per ANSI/ESDA/

JEDEC JS-001, all pins⁽¹⁾

± 2000

V_(ESD)

Electrostatic discharge

V

Charged device model (CDM), per JEDEC

specificationJESD22-C101, all pins⁽²⁾

± 1000

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6

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7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

Parameter

MIN

MAX

24

UNIT

V

V_IN

Input Voltage Range

IN

2.7

V_OUT

Output Voltage Range

OUT

V_IN+ 0.3

6⁽¹⁾

V

V_EN/UVLO

V_LDSTRT

V_dVdT

V_PG

Enable Pin Voltage Range

EN/UVLO

LDSTRT

dVdt

V

LDSTRT Pin Capacitor Voltage Rating

dVdT Pin Capacitor Voltage Rating

PG Pin Voltage Range

4

V

V_IN+ 4

V

PG

6⁽²⁾

V

V_ITIMER

V_NRETRY

V_{RETRY_DLY}

R_ILIM

ITIMER Pin Capacitor Voltage Rating

NRETRY Pin Capacitor Voltage Rating

RETRY_DLY Pin Capacitor Voltage Rating

ILIM Pin Resistor

ITIMER

NRETRY

4

V

RETRY_DLY

ILIM

4

V

182

1650

8

Ω

A

I_MAX

Continuous Switch Current

Junction temperature

IN to OUT

T_J

–40

125

°C

(1) For supply voltages below 6V, it is okay to pull up the EN pin to IN directly. For supply voltages greater than 6V, it is recommended

to use an appropriate resistor divider between IN, EN and GND to ensure the voltage at the EN pin is within the specified limits.

(2) For supply voltages below 6V, it is okay to pull up the PG pin to IN/OUT through a resistor. For supply voltages greater than 6V, it is

recommended to use a stepped down power supply to ensure the voltage at the PG pin is within the specified limits.

7.4 Thermal Information

TPS25980X

THERMAL METRIC^{(1) (2)}

RGE (QFN)

24 PINS

34.6

UNIT

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

R_θJC(top)

R_θJB

36.7

11.2

Ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

3

Ψ_JB

11.2

R_θJC(bot)

1.6

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

(2) Based on simulations conducted with the device mounted on a JEDEC 4-layer PCB (2s2p) with minimum recommended pad size (2 oz

Cu) and 3x2 via array.

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7.5 Electrical Characteristics

(Test conditions unless otherwise noted) –40°C ≤ T_J≤ 125°C, V_IN= 12 V for TPS259804x/7x, 5 V for

TPS259803x, 3.3 V for TPS259802x, V_EN/UVLO= 2 V, R_ILIM= 1650 Ω , C_dVdT= Open, OUT = Open. All

voltages referenced to GND.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

INPUT SUPPLY (IN)

V_IN

I_Q

Input Voltage Range

IN Quiescent Current

2.7

24

1200

300

20

V

µA

V

V_EN≥ V_UVLO(R)

800

204

V_SD< V_EN< V_UVLO

V_EN< V_SD

I_SD

IN Shutdown Current

3.67

2.53

2.42

V_INRising

2.46

2.35

2.6

IN Undervoltage Protection

Threshold

V_UVP

V_INFalling

2.49

V

OVERVOLTAGE PROTECTION (IN)

TPS259802x, V_INRising

TPS259803x, V_INRising

TPS259804x, V_INRising

TPS259802x, V_INFalling

TPS259803x, V_INFalling

TPS259804x, V_INFalling

3.62

7.39

3.7

7.6

3.76

7.76

V

V_OVP(R)

16.32

3.52

16.9

3.6

17.31

3.66

Overvoltage Protection Threshold

V_OVP(F)

7.22

7.4

7.55

15.80

16.4

16.81

OUTPUT CURRENT MONITOR (IMON)

G_IMON

Current Monitor Gain (I_IMON:I_OUT

)

3 A ≤ I_OUT≤ min(8 A, I_LIM

)

228.78

246

263.22

µA/A

OUTPUT CURRENT LIMIT (ILIM)

R_ILIM= 773 Ω, T_J= 25 ℃

R_ILIM= 773 Ω, T_J= -40 to 125 ℃

R_ILIM= 300 Ω, T_J= 25 ℃

R_ILIM= 300 Ω, T_J= -40 to 125 ℃

R_ILIM= 182 Ω, T_J= 25 ℃

R_ILIM= 182 Ω, T_J= -40 to 125 ℃

R_ILIM= Open

1.76

1.53

4.75

4.36

7.77

7.23

2

2.17

2.43

5.23

5.66

8.54

9.07

A

4.98

8.13

0

I_LIM

I_OUTCurrent Limit Threshold

I_OUTCircuit Breaker Threshold

During ILIM pin Short to GND

Condition (Single point failure)

I_CB

I_SC

R_ILIM= Short to GND, T_J= 25 ℃

20

A

Short-circuit Fast Trip Threshold

210

3

% I_LIM

ON-RESISTANCE (IN - OUT)

T_J= 25 ℃, I_OUT= 2 A

mΩ

R_ONON State Resistance

T_J= -40 to 125 ℃, I_OUT= 2 A

5

ENABLE / UNDERVOLTAGE LOCKOUT (EN/UVLO)

V_UVLO(R)

V_ENRising

V_ENFalling

1.18

1.08

1.2

1.1

1.23

1.13

V

EN/UVLO Pin Voltage Threshold

V_UVLO(F)

EN/UVLO Pin Voltage Threshold for

Lowest Shutdown Current

V_SD

V_ENFalling

0.59

0.8

V

I_ENLKG

EN/UVLO Pin Leakage Current

0.1

µA

POWER GOOD INDICATION (PG)

V_IN< V_UVP, V_EN< V_SD,I_PG= 26 µA

V_IN= 3.3V, I_PG≤ 5 mA

651

320

100

786

mV

PG Pin Low Voltage (PG de-

asserted)

V_PGD

V_IN≥ 5V, I_PG≤ 5 mA

PG Pin Leakage Current (PG

asserted)

I_PGLKG

PG pulled up to 5 V through 10 kΩ

1.7

µA

R_ON(PGA)

R_ONWhen PG is asserted

4.2

mΩ

8

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7.5 Electrical Characteristics (continued)

(Test conditions unless otherwise noted) –40°C ≤ T_J≤ 125°C, V_IN= 12 V for TPS259804x/7x, 5 V for

TPS259803x, 3.3 V for TPS259802x, V_EN/UVLO= 2 V, R_ILIM= 1650 Ω , C_dVdT= Open, OUT = Open. All

voltages referenced to GND.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

V_IN- V_OUTThreshold when PG is de-

asserted

V_PGTHD

0.224

0.326

0.450

V

AUTO-RETRY DELAY INTERVAL (RETRY_DLY)

V_{RETRY_DLY(R)}

V_{RETRY_DLY(F)}

1.1

0.35

0.75

2.05

V

RETRY_DLY Oscillator Comparator

Threshold

V_{RETRY_DLY_HYS}RETRY_DLY Oscillator Hysteresis

I_{RETRY_DLY}RETRY_DLY Pin Bias Current

NUMBER OF AUTO-RETRIES (NRETRY)

0.65

1.7

0.85

2.5

V

µA

V_NRETRY(R)

V_NRETRY(F)

V_{NRETRY_HYS}

I_NRETRY

1.1

0.35

0.75

2.05

V

NRETRY Oscillator Comparator

Threshold

NRETRY Oscillator Hysteresis

NRETRY Pin Bias Current

0.65

1.7

0.85

2.5

V

µA

CURRENT FAULT TIMER (ITIMER)

I_ITIMER

R_ITIMER

V_INT

ITIMER Discharge Current

I_SC> I_OUT> I_LIM

1.4

2.1

23

2.8

µA

kΩ

V

ITIMER Internal Pull-up Resistance I_OUT< I_LIM

ITIMER Pin Default Voltage

I_OUT< I_LIM

2.5

ITIMER Comparator Falling

Threshold

V_ITIMER

I_SC> I_OUT> I_LIM,ITIMER Voltage Rising

1.53

0.98

V

ITIMER Comparator Voltage

Threshold Delta

ΔV_ITIMER

I_SC> I_OUT> I_LIM,ITIMER Voltage Falling

0.7

1.3

LDSTRT

V_LDSTRT

I_LDSTRT

LDSTRT Rising Threshold

LDSTRT Charging Current

LDSTRT voltage rising

PG asserted

1.1

1.7

1.21

2.05

1.3

2.4

V

µA

LDSTRT Internal Pull-down

Resistance

R_LDSTRT

RQOD

31

Ω

IN connected to EN, OUT connected to

QOD, EN! to 1V

QOD effective resistance

73.2

mA

OVERTEMPERATURE PROTECTION

TSD

Thermal Shutdown Threshold

T_JRising

T_JFalling

150

10

°C

TSDHys

dVdt

I_dVdt

Thermal Shutdown Hysteresis

dVdt Pin Charging Current

2

4.6

6.33

µA

7.6 Timing Requirements

PARAMETER

TEST CONDITIONS

V_IN> V_OVLO(R)to V_OUT↓, TPS259802x

V_IN> V_OVLO(R)to V_OUT↓, TPS259803x

V_IN> V_OVLO(R)to V_OUT↓, TPS259804x

I_OUT> 3 x I_LIMto V_OUTturned OFF

MIN TYP MAX

UNIT

µs

1.5

5

t_OVP

Overvoltage Protection Response Time ⁽¹⁾

µs

5

µs

t_SC

Short Circuit Response Time

400

ns

V_G> (V_IN+ 3.6V) to PG↑ or (V_IN- V_OUT)>

V_PGTHDto PG↓

t_PGD

PG Assertion/De-assertion De-glitch ⁽²⁾

120

µs

(1) Please refer to Fig. 8-2

(2) Please refer to Fig. 8-5

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7.7 Switching Characteristics

The output rising slew rate is internally controlled and constant across the entire operating voltage range to

ensure the turn on timing is not affected by the load conditions. The rising slew rate can be adjusted by adding

capacitance from the dVdt pin to ground. As C_dVdtis increased it will slow the rising slew rate (SR). See Slew

Rate and Inrush Current Control (dVdt) section for more details. The Turn-Off Delay and Fall Time, however, are

dependent on the RC time constant of the load capacitance (C_OUT) and Load Resistance (R_L). The Switching

Characteristics are only valid for the power-up sequence where the supply is available in steady state condition

and the load voltage is completely discharged before the device is enabled.Typical Values are taken at T_J=

25°C unless specifically noted otherwise. R_L= 3.6 Ω, C_OUT= 1 mF

C_dVdt

6800pF

=

PARAMETER

V_IN

C_dVdt= Open C_dVdt= 3300pF

UNIT

2.7 V

12 V

24 V

2.7 V

12 V

24 V

2.7 V

12 V

24 V

2.7 V

12 V

24 V

2.7 V

12 V

24 V

6.26

1.39

1.4

0.68

SR_ON

t_D,ON

t_R

Output Rising slew rate

7.35

7.4

0.68

1.7

V/ms

1.4

1.3

1.49

2.1

Turn on delay

Rise time

1.24

1.2

3.01

4.74

3.35

14.41

28.41

5.05

17.42

33.15

152

ms

µs

2.91

1.63

6.99

13.77

3.12

9.09

16.68

152

0.67

1.35

2.66

1.97

2.59

3.86

151

212

262

t_ON

Turn on time

Turn off delay

t_D,OFF

212

262

10

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7.8 Typical Characteristics

3.7

3.68

3.66

3.64

3.62

3.6

2.56

2.54

2.52

2.5

Rising

Falling

2.48

2.46

2.44

2.42

2.4

Rising

Falling

3.58

-40

-20

0

20

40

T_J(èC)

60

80

100 120 140

D001

TPS259802x Variants

-40

-20

0

20

40

T_J(èC)

60

80

100 120 140

D007

Figure 7-1. Supply UVP Threshold vs Temperature

Figure 7-2. Supply OVP Threshold vs Temperature

7.625

16.9

16.85

16.8

7.6

7.575

16.75

16.7

Rising

Falling

Rising

Falling

7.55

7.525

7.5

16.65

16.6

16.55

16.5

7.475

7.45

7.425

7.4

16.45

16.4

16.35

16.3

7.375

-40

-20

0

20

40

60

80

100 120 140

-40

-20

0

20

40

60

80

100 120 140

T_J(èC)

D003

D009

TPS259803x Variants

TPS259804x Variants

Figure 7-3. Supply OVP Threshold vs Temperature Figure 7-4. Supply OVP Threshold vs Temperature

900

1.21

V_IN

875

1.2

1.19

1.18

1.17

1.16

1.15

1.14

1.13

1.12

1.11

1.1

2.7 V

12 V

24 V

850

825

800

775

750

725

700

675

650

Rising

Falling

-40

-20

0

20

40

60

80

100 120 140

T_J(èC)

D002

V_ENUVLO= 2 V, OUT = Open

-40

-20

0

20

40

T_J(èC)

60

80

100 120 140

D008

Figure 7-5. EN/UVLO Threshold vs Temperature

Figure 7-6. Quiescent Current vs Temperature

240

0.875

0.85

V_IN

2.7 V

12 V

24 V

235

230

225

220

215

210

205

200

195

190

185

180

175

170

165

160

0.825

V_IN

0.8

3.3 V

12 V

24 V

0.775

0.75

0.725

0.7

0.675

0.65

-40

-20

0

20

40

60

80

100 120 140

T_J(èC)

D004

0.625

V_ENUVLO= 1 V, OUT = Open

-40

-20

0

20

40

T_J(èC)

60

80

100 120 140

D014

Figure 7-7. EN/UVLO Falling Threshold for Lowest

Current Consumption

Figure 7-8. Shut-Down Current vs Temperature

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12

9

8

7

6

5

4

3

2

1

0

V_IN

2.7 V

12 V

24 V

10

8

6

4

2

0

-40

-20

0

20

40

T_J(èC)

60

80

100 120 140

D005

V_ENUVLO= 0 V, OUT = Open

180 360 540 720 900 1080 1260 1440 1620 1800

R_ILIM(W)

D010

Figure 7-10. Output Current Limit (I_LIM) vs R_ILIM

Figure 7-9. Deep Shut-Down Current vs

Temperature

25

900

MIN

MAX

I_PG

26uA

242uA

20

850

800

750

700

650

600

550

500

15

10

5

0

-5

-10

-15

-20

-25

2

3

4

5

I_LIM(A)

6

7

8

-40

-20

0

20

40

T_J(èC)

60

80

100 120 140

D011

D015

Across Process, Voltage, Temperature Corners

V_IN= 0 V

Figure 7-11. Output Current Limit (I_LIM) Accuracy

Figure 7-12. Power Good Output Voltage (De-

asserted State) vs Temperature

1.0025

1

2.2

2.18

2.16

2.14

2.12

2.1

0.9975

0.995

0.9925

0.99

0.9875

0.985

2.08

2.06

0.9825

2.04

V_IN

0.98

0.9775

0.975

2.02

2

2.7 V

12 V

24 V

2.7 V

12 V

24 V

1.98

-40

-20

0

20

40

60

80

100 120 140

-40

-20

0

20

40

60

80

100 120 140

T_J(èC)

D016

D019

Figure 7-13. ITIMER Voltage Threshold Delta vs

Temperature

Figure 7-14. ITIMER Discharge Current vs

Temperature

2.16

2.14

2.12

2.1

1.215

V_IN

2.7 V

12 V

24 V

1.213

1.211

2.08

2.06

2.04

1.209

1.207

1.205

V_IN

2.02

2.7 V

12 V

24 V

2

1.98

-40

-20

0

20

40

60

80

100 120 140

-40

-20

0

20

40

60

80

100 120 140

T_J(èC)

D020

D021

Figure 7-15. LDSTRT Charging Current vs

Temperature

Figure 7-16. LDSTRT Threshold Voltage vs

Temperature

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5

4.8

4.6

4.4

4.2

4

2.16

2.14

2.12

2.1

V_IN

2.7 V

12 V

24 V

2.08

2.06

2.04

2.02

2

V_IN

2.7 V

12 V

24 V

1.98

-40

-20

0

20

40

T_J(èC)

60

80

100 120 140

-40

-20

0

20

40

T_J(èC)

60

80

100 120 140

D024

D022

Figure 7-17. DVDT Charging Current vs

Temperature

Figure 7-18. RETRY_DLY Bias Current vs

Temperature

0.76

2.14

2.12

2.1

V_IN

2.7 V

12 V

0.758

0.756

24 V

0.754

2.08

2.06

2.04

2.02

0.752

0.75

0.748

0.746

0.744

0.742

0.74

V_IN

2

2.7 V

12 V

24 V

1.98

1.96

-40

-20

0

20

40

60

80

100 120 140

-40

-20

0

20

40

60

80

100 120 140

T_J(èC)

D025

D027

Figure 7-19. RETRY_DLY Oscillator Hysteresis vs Figure 7-20. NRETRY Bias Current vs Temperature

Temperature

0.76

0.755

0.75

1000

V_IN

3.3 V

12 V

24 V

T_A

500

-40 èC

27 èC

85 èC

125 èC

300

200

100

50

0.745

0.74

30

20

0.735

0.73

10

5

3

2

0.725

0.72

1

-40

-20

0

20

40

T_J(èC)

60

80

100 120 140

0

4

8

12

16

Power Dissipation (W)

20

24

28

32

36

40

D026

D023

Figure 7-21. NRETRY Oscillator Hysteresis vs

Temperature

Figure 7-22. Thermal Shutdown Plot - Steady State

200

100

50

TPS259807x

TPS259802x/03x/04x

30

20

10

5

3

2

1

0.5

2

3

4

5

6 7 8 10 20

Power Dissipation (W)

30 40 50 70 100

D002

Figure 7-23. Thermal Shutdown Plot - Inrush/Overload

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C_IN= 1 μF

C_OUT= 220 μF

C_dVdt= 3.3 nF

C_OUT= 220 μF

C_dVdt= 10 nF

R_OUT= Open

Figure 7-24. Hotplug

Figure 7-25. Startup With EN - dVdt Limited

C_OUT= 220 μF

C_dVdt= 3.3 nF

R_OUT= 6 Ω

TPS259804x (16.7-V OVP

variant)

Figure 7-26. Startup With EN Into Resistive Load -

dVdt Limited

Figure 7-27. Overvoltage Protection

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A.

R_ILIM= 182 Ω

C_ITIMER= 4.7 nF

R_ILIM= 182 Ω

C_ITIMER= 4.7 nF C_{RETRY_DLY}= 2.2 nF,

C_NRETRY= 2.2 nF

Figure 7-28. Circuit Breaker With Transient

Overcurrent Blanking

Figure 7-29. Circuit Breaker - Auto-Retry

R_ILIM= 182 Ω

Figure 7-30. Power Up Into Output Short-Circuit

Figure 7-31. Output Hard Short-Circuit While ON

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R_ILIM= 182 Ω

R_ILIM= 332 Ω

Figure 7-32. Output Hard Short-Circuit While ON

(Zoomed In)

Figure 7-33. Supply Line Transient Immunity -

Input Voltage Step

R_ILIM= 511 Ω

Figure 7-34. Supply Line Transient Immunity - Adjacent Load Hot Unplug

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8 Detailed Description

8.1 Overview

The TPS25980x device is a smart eFuse with integrated power switch that is used to manage load voltage and

load current. The device starts its operation by monitoring the IN bus. When V_INis above the Undervoltage

Protection threshold (V_UVP) and below the Overvoltage Protection threshold (V_OVP), the device samples the EN/

UVLO pin. A high level on this pin enables the internal MOSFET to start conducting and allow current to flow

from IN to OUT. When EN/UVLO is held low, the internal MOSFET is turned off. After a successful start-up

sequence, the device now actively monitors its load current, input voltage and protects the load from harmful

overcurrent and overvoltage conditions. The device also relies on a built-in thermal sense circuit to shut down

and protect itself in case the device internal temperature (T_J) exceeds the safe operating conditions.

8.2 Functional Block Diagram

8.3 Feature Description

The TPS25980x eFuse is a compact, feature rich power management device that provides detection, protection

and indication in the event of system faults.

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8.3.1 Undervoltage Protection (UVLO and UVP)

The TPS25980x implements Undervoltage Protection on IN to turn off the output in case the applied voltage

becomes too low for the downstream load or the device to operate correctly. The Undervoltage Protection has a

default internal threshold of V_UVP. If needed, it is also possible to set a user defined Undervoltage Protection

threshold higher than V_UVPusing the UVLO comparator on the EN/UVLO pin. Figure 8-1 and Equation 1 show

how a resistor divider from supply to GND can be used to set the UVLO set point for a given voltage supply

level.

Power

Supply

IN

R_VL1

EN/UVLO

R_VL2

GND

Figure 8-1. Adjustable Supply UVLO Threshold

V^UVLO(R)x (R^VL1+ R^VL2)

R^VL2

VIN^UVLO=

(1)

The resistors must be sized large enough to minimize the constant leakage from supply to ground through the

resistor divider network. At the same time, keep the current through the resistor network sufficiently larger (20x)

than the leakage current on the EN/UVLO pin to minimize the error in the resistor divider ratio.

8.3.2 Overvoltage Protection (OVP)

The TPS25980x implements Overvoltage Lock-Out (OVLO) on IN to protect the output load in the event of input

overvoltage. When the input exceeds the Overvoltage Protection threshold (V_OVP(R)) the device turns off the

output within t_OVP. As long as an overvoltage condition is present on the input, the device stays disabled and the

output will be turned off. Once the input voltage returns to the normal operating range, the device attempts to

start up normally.

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Input Overvoltage Event

Input Overvoltage Removed

V_OVP(R)

V_OVP(F)

IN

0

t_OVP

OUT

PG

dVdt Limited

0

V_PG

0

Time

Figure 8-2. Overvoltage Response

There are multiple device options with different fixed overvoltage thresholds to choose from, including one

without internal overvoltage protection. See the Device Comparison Table for a list of available options.

8.3.3 Inrush Current, Overcurrent, and Short-Circuit Protection

TPS25980x devices incorporate three levels of protection against overcurrent:

•

Adjustable slew rate (dVdt) for inrush current control

Adjustable overcurrent protection (with adjustable blanking timer) - Circuit Breaker to protect against soft

overload conditions

•

Adjustable fast-trip response to quickly protect against severe overcurrent (short-circuit) faults

8.3.3.1 Slew Rate and Inrush Current Control (dVdt)

During hot-plug events or while trying to charge a large output capacitance, there can be a large inrush current.

If the inrush current is not controlled, it can damage the input connectors and/or cause the system power supply

to droop leading to unexpected restarts elsewhere in the system. The TPS25980x provides integrated output

slew rate (dVdt) control to manage the inrush current during start-up. The inrush current is directly proportional to

the load capacitance and rising slew rate. The following equation can be used to calculate the slew rate (SR)

required to limit the inrush current (I_INRUSH) for a given load capacitance (C_OUT):

IINRUSH

(

mA

)

SR V / ms =

(

)

COUT

(

mF

)

(2)

An external capacitance can be connected to the dVdt pin to control the rising slew rate and lower the inrush

current during turn on. The required C_dVdtcapacitance to produce a given slew rate can be calculated using the

following formula:

4600

CdVdt pF =

(

)

SR V / ms

(

)

(3)

The fastest output slew rate is achieved by leaving the dVdt pin open.

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8.3.3.2 Circuit Breaker

The TPS25980x responds to output overcurrent conditions by turning off the output after a user adjustable

transient fault blanking interval. When the load current exceeds the programmed current limit threshold (I_LIMset

by the ILIM pin resistor R_ILIM), but lower than the fast-trip threshold (2.1 x I_LIM), the device starts discharging the

ITIMER pin capacitor using an internal pull-down current (I_ITIMER). If the load current drops below the current limit

threshold before the ITIMER capacitor drops by ΔV_ITIMER, the circuit breaker action is not engaged and the

ITIMER is reset by pulling it up to V_INTinternally. This allows short transient overcurrent pulses to pass through

the device without tripping the circuit. If the overcurrent condition persists, the ITIMER capacitor continues to

discharge and once it falls by ΔV_ITIMER, the circuit breaker action turns off the FET immediately. The following

equation can be used to calculate the R_ILIMvalue for a desired current limit threshold.

1460

RILIM W =

(

)

ILIM

( )

A - 0.11

(4)

Note

Leaving the ILIM pin Open sets the current limit to zero and causes the FET to shut off as soon as any

load current is detected. Shorting the ILIM pin to ground at any point during normal operation is

detected as a fault and the part shuts down. The ILIM pin Short to GND fault detection circuit requires

a minimum amount of load current (I_CB) to flow through the device. This ensures robust eFuse

behavior even under single point failure conditions. Refer to the Fault Response section for details on

the device behavior after a fault.

Transient Output Overload

Overload Removed

Persistent Output Overload

ITIMER expired

2.1 x I_LIM

I_OUT

I_LIM

Circuit Breaker

operation

0

V_INT

t_ITIMER

4V_ITIMER

ITIMER

OUT

0

V_IN

0

V_PG

PG

T_J

0

TSD

TSD_HYS

T_J

Time

Figure 8-3. Circuit Breaker Response

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The duration for which load transients are allowed can be adjusted using an appropriate capacitor value from

ITIMER pin to ground. The transient overcurrent blanking interval can be calculated using Equation 5.

CITIMER (nF) ì DVITIMER (V)

tITIMER (ms) =

IITIMER (mA)

(5)

Leave the ITIMER pin open to allow the part to break the circuit with the minimum possible delay.

Table 8-1. Device ITIMER Functional Mode Summary

ITIMER Pin Connection

Timer Delay before Overcurrent response

OPEN

0 s

Capacitor to ground

Short to GND

As per Equation 5

ITIMER Pin Fault - Part Shuts Off

Note

1. Shorting the ITIMER pin to ground is detected as a fault and the part shuts down. This ensures

robust eFuse behavior even in case of single point failure conditions. Refer to the Fault Response

section for details on the device behavior after a fault.

2. Larger ITIMER capacitors take longer to charge during start-up and may lead to incorrect fault

assertion if the ITIMER voltage is still below the pin short detection threshold after the device has

reached steady state. To avoid this, it is recommended to limit the maximum ITIMER capacitor to the

value suggested by the equation below.

tGHI

CITIMER <

53000

VIN + 3.6V

≈

’

tGHI = tD,ON + C^dvdtì

∆

«

÷

◊

Idvdt

Where

•

t_GHIis the time taken by the device to reach steady state

t_D,ONis the device turn-on delay

C_dvdtis the dVdt capacitance

I_dvdtis the dVdt charging current

It is possible to avoid incorrect ITIMER pin fault assertion and achieve higher ITIMER intervals if

needed by increasing the dVdt capacitor value accordingly, but at the expense of higher start-up time.

Once the part shuts down due to a Circuit Breaker fault, it can be configured to either stay latched off or restart

automatically. Refer to the Fault Response section for details.

8.3.3.3 Short-Circuit Protection

During an output short-circuit event, the current through the device increases very rapidly. When an output short-

circuit is detected, the internal fast-trip comparator turns off the output within the t_SC. The comparator employs a

scalable threshold which is equal to 2.1 × I_LIM. This enables the user to adjust the fast-trip threshold as per

system needs rather than using a fixed threshold which may not be suitable for all systems. After a fast trip

event, the device restarts in a current limited mode to try and restore power to the load quickly in case the fast

trip was triggered by a transient event. However, if the fault is persistent, the device will stay in current limit

causing the junction temperature to rise and eventually enter thermal shutdown. See Overtemperature

Protection (OTP) section for details on the device response to overtemperature.

In some of the systems, for example servers or telecom equipment which house multiple hot-pluggable cards

connected to a common supply backplane, there can be transients on the supply due to switching of large

currents through the inductive backplane. This can result in current spikes on adjacent cards which could be

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potentially large enough to inadvertently trigger the fast-trip comparator of the eFuse. The TPS25980x uses a

proprietary algorithm to avoid nuisance tripping in such cases thereby facilitating un-interrupted system

operation.

Input Line

Transient

Persistent Output Short-Circuit

Thermal Shutdown

Output Short-Circuit Removed

Temporary Output

Short-Circuit

Retry Timer Elapsed

IN

0

t_SC

2.1 x I_LIM

I_OUT

I_LIM

0

No Fast-trip

Fast-trip

V_IN

OUT

dVdt Limited

Start-up

Current Limited

Start-up

0

V_PG

PG

t_{RETRY_DLY}

0

TSD

TSD_HYS

T_J

Time

Figure 8-4. Input Line Transient and Output Short-Circuit Response

Note

To prevent the circuit breaker loop from interfering with the input line transient detection logic, TI

recommends to set the ITIMER interval higher than 100 μs. Refer to Table 8-1 for more details on

ITIMER.

8.3.4 Overtemperature Protection (OTP)

The device monitors the internal die temperature (T_J) at all times and shuts down the part as soon as the

temperature exceeds a safe operating level (TSD) thereby protecting the device from damage. The device will

not turn back on until the die cools down sufficiently, that is the die temperature falls below (TSD - TSDHys).

Thereafter, the part can be configured to either remain latched off or restart automatically. Refer to the Fault

Response section for details.

8.3.5 Analog Load Current Monitor (IMON)

The device allows the system to monitor the output load current accurately by providing an analog current on the

IMON pin which is proportional to the current through the FET. The user can connect a resistor from IMON to

ground to convert this signal to a voltage which can be fed to the input of an Analog-to-Digital Converter. The

internal amplifier on the IMON employs chopper based offset cancellation techniques to provide accurate

measurement even at lower currents over time and temperature.

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V_IMONV = G

( )

mA / A ìI

A ìR

( )

W

( )

(

)

IMON

OUT

IMON

(6)

It is recommended to limit the maximum IMON voltage to the values mentioned in VIMON(Max) Recommended

Values . This is to ensure the IMON pin internal amplifier has sufficient headroom to operate linearly.

Table 8-2. V_IMON(MAX)Recommended Values

V_IN

Recommended V_IMON(MAX)

2.7 V

3.3 V

> 5 V

1 V

1.8 V

3.3 V

It is recommended to add a RC low pass filter on the IMON output to filter out any glitches and get a smooth

average current measurement. TI recommends a series resistance of 10 kΩ or higher.

8.3.6 Power Good (PG)

PG is an active high open drain output which indicates whether the FET is fully turned ON and the output voltage

has reached the maximum value. After power-up, PG is pulled low initially. The gate driver circuit starts charging

the gate capacitance from the internal charge pump. When the FET gate voltage reaches (V_IN+ 3.6V), PG is

asserted after a de-glitch time (t_PGD). During normal operation, if at any time V_OUTfalls below (V_IN- V_PGTHD), PG

is de-asserted after a de-glitch time (t_PGD).

Overcurrent Removed

Device Enabled

Overcurrent Event

V_UVLO(R)

0

EN/UVLO

IN

Slew rate (dVdt) controlled

startup/Inrush current limiting

0

V_IN

Current limiting

operation

V_PGTHD

OUT

PG

0

V_PG

0

120 µs

V_IN

dVdT

0

V_IN+ 3.6V

V_Gate

t_ITIMER

0

I_LIM

I_INRUSH

0

I_OUT

Time

Figure 8-5. Power Good Assertion and De-assertion

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Note

1. When there is no supply to the device, the PG pin is expected to stay low. However, there is no

active pull-down in this condition to drive this pin all the way down to 0 V. If the PG pin is pulled up to

an independent supply which is present even if the TPS25980x is unpowered, there can be a small

voltage seen on this pin depending on the pin sink current, which in turn is a function of the pull-up

supply voltage and resistor. Minimize the sink current to keep this pin voltage low enough not to be

detected as a logic HIGH by associated external circuits in this condition.

2. The PG pin provides a mechanism to detect a possible failed MOSFET condition during start-up. If

the PG does not get asserted for an extended period of time after the device is powered up and

enabled, it might be an indication of internal MOSFET failure.

8.3.7 Load Detect/Handshake (LDSTRT)

The LDSTRT pin provides a mechanism for the downstream load circuit to indicate to the TPS25980x that the

load is present and has powered up successfully. This allows the system to have additional control over the

conditions in which power is presented to the load and disconnect the power when the load is not present or

unable to provide a valid handshake signal after an expected boot-up time.

Once the TPS25980x completes the startup sequence and the output reaches the full voltage, it asserts the PG

signal. At the same time, it also starts charging the capacitor on the LDSTRT pin (C_LDSTRT) with an internal

current source (I_LDSTRT). If the LDSTRT pin voltage rises above V_LDSTRTbefore the load circuit pulls it low, the

TPS25980x detects the condition as a LDSTRT fault and turns off the FET to power down the load. The time to

trigger the LDSTRT fault can be calculated from the following equation:

CLDSTRT (nF) ì VLDSTRT (V)

tLDSTRT (ms) =

ILDSTRT (mA)

(7)

During normal operation, if at any time the load circuit releases the active pull-down on the LDSTRT pin, the

capacitor C_LDSTRTwould start charging up again and eventually trigger a shutdown due to LDSTRT fault once

the capacitor charges up to V_LDSTRT

.

Once the TPS25980x turns off due to LDSTRT fault, it can be turned ON again in 3 ways:

•

LDSTRT pin is driven low

Input supply voltage is driven low (< V_UVP(F)) and then driven high (> V_UVP(R)

EN/UVLO voltage is driven low (< V_SD) and then driven high (> V_UVLO(R)

)

Tie the LDSTRT pin to ground if this functionality is not needed.

IN

0

EN/UVLO

OUT

0

V_IN

OUT

0

V_PG

PG

0

t_LDSTRT

1.2 V

2.5 V

LDSTRT

1.2 V

LDSTRT pulled low by MCU

No Handshake Signal from System MCU

0

Time

Figure 8-6. Successful LDSTRT Handshake

Figure 8-7. Unsuccessful LDSTRT Handshake

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The LDSTRT pin can also be used to implement a load or module detect function wherein the output power is

presented only when the load or module is plugged in. A typical use case for this function is on optical module

power supply rails in Switches/Routers or similar networking end equipment. The LDSTRT pin should be tied to

a corresponding pin on the module connector which gets pulled low by the module when it is plugged in. An

example of such a signal is ModPrsL on QSFP-DD modules.

In this scheme, initially when the TPS25980x is powered up or enabled, the output charges up and PG is

asserted. If the module is not plugged in, there is no external pull-down on the LDSTRT pin and the pin voltage

starts rising due to internal pull-up . Once the LDSTRT pin voltage exceeds V_LDSTRT, the TPS25980x turns off

the output power. If the module is plugged in later, the LDSTRT pin is pulled low by the module and the

TPS25980x turns on the output power.

IN

0

EN/UVLO

0

V_IN

OUT

dVdt limited

0

V_PG

PG

0

2.5 V

LDSTRT

1.2 V

Optical module not present

Optical module plugged in

0

Time

Figure 8-8. Optical Module Plug-In Detection Using LDSTRT

8.4 Fault Response

The following events trigger an internal fault which causes the device to shut down:

•

Overtemperature Protection

Circuit Breaker Operation

ITIMER pin Short to GND

ILIM pin Short to GND

Once the device shuts down due to a fault, even if the associated external fault is subsequently cleared, the fault

stays latched internally and the output cannot turn on again until the latch is reset. The fault latch can be

externally reset by one of the following methods:

•

Input supply voltage is driven low (< V_UVP(F)

)

EN/UVLO voltage is driven low (< V_SD

)

The fault latch can also be reset by an internal auto-retry logic. The user can either disable the auto-retry

behavior completely (latch-off behavior) or configure the device to auto-retry indefinitely or for a limited number

of times before latching off. The auto-retry behavior is controlled by the connections on the RETRY_DLY and

NRETRY pins.

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Table 8-3. Pin Configurable Fault Response

EN/UVLO

RETRY_DLY

NRETRY

DEVICE STATE

Disabled

L

X

H

Short to GND

No auto-retry (Latch-off)

Auto-retry 4 times with minimum delay between retries and

then latch-off

H

Open

H

Open

Short to GND

Auto-retry indefinitely with minimum delay between retries

Auto-retry delay and count as per Equation 8 and Equation 9

Capacitor to GND

Auto-retry 4 times with finite delay between retries as per

Equation 8 and then latch-off

H

Capacitor to GND

Open

Auto-retry indefinitely with finite delay between retries as per

Equation 8

Short to GND

To configure the part for a finite number of auto-retries with a finite auto-retry delay, first choose the capacitor

value on RETRY_DLY pin using the following equation.

128ì CRETRY_DLY (pF) + 4 pF ì VRETRY_DLY_HYS (V)

(

)

tRETRY_DLY (ms) =

IRETRY_DLY (mA)

(8)

(9)

Next, choose the capacitor value on the NRETRY pin using the following equation.

4ìIRETRY_DLY (mA)ìCNRETRY (pF)

NRETRY =

INRETRY (mA)ì CRETRY_DLY (pF) + 4 pF

(

)

The number of auto-retries is quantized to certain discrete levels as shown in Table 8-4 .

Table 8-4. NRETRY Quantization Levels

NRETRY Calculated From Equation 9

NRETRY Actual

0 < N < 4

4

16

4 < N < 16

16 < N < 64

64

64 < N < 256

256

1024

256 < N < 1024

Table 8-5. NRETRY and RETRY_DLY Combination Examples

Auto Retry Delay

915 ms

416 ms

91.7 ms

9.3 ms

3 ms

RETRY_DLY Capacitor

22 nF

10 nF

2.2 nF

220 pF

68 pF

No. of Auto Retries

NRETRY Capacitor

Open

4

16

47 nF

0.22 μF

1 μF

22 nF

0.1 μF

0.47 μF

1.5 μF

4.7 nF

1 nF

2.2 nF

10 nF

33 nF

220 pF

1 nF

64

22 nF

256

0.1 μF

4.7 nF

10 nF

1024

Infinite

3.3 μF

0.47 μF

Short to GND

A spreadsheet design tool TPS25980xx Design Calculator is also available for simplified calculations.

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Output overload followed by Thermal Shutdown

Retry Timer starts once device cools down

1^stRetry

N^thRetry

IN

0

t_{RETRY_DLY}

Thermal Shutdown

I_OUT

I_LIM

0

V_IN

OUT

Programmed number of retries over,

Device Latches Off

0

TSD

TSD_HYS

T_J

Time

Figure 8-9. Auto-Retry After Fault

The auto-retry logic has a mechanism to reset the count to zero if two consecutive faults occur far apart in time.

This ensures that the auto-retry response to any later fault is handled as a fresh sequence and not as a

continuation of the previous fault. If the fault which triggered the shutdown and subsequent auto-retry cycle is

cleared eventually and does not occur again for a duration equal to 7 retry delay timer periods starting from the

last fault, the auto-retry logic resets the internal auto-retry count to zero.

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8.5 Device Functional Modes

The TPS25980x can be pin strapped to support various configurable functional modes.

Table 8-6. LDSTRT Handshake Functional Modes

EN/UVLO

LDSTRT

DEVICE STATE

L

H

X

L

Disabled

ON

H

OFF

Refer to Load Detect/Handshake (LDSTRT) section for more details.

Table 8-7. Fault Response Functional Modes

EN/UVLO

RETRY_DLY

NRETRY

DEVICE STATE

L

X

Disabled

H

Short to GND

No auto-retry (Latch-off)

Auto-retry 4 times with minimum delay between retries and

then latch-off

H

Open

H

Open

Short to GND

Auto-retry indefinitely with minimum delay between retries

Auto-retry delay and count as per Equation 8 and Equation 9

Capacitor to GND

Auto-retry 4 times with finite delay between retries as per

Equation 8 and then latch-off

H

Capacitor to GND

Open

Auto-retry indefinitely with finite delay between retries as per

Equation 8

Short to GND

Refer to Fault Response section for more details.

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9 Application and Implementation

Note

Information in the following applications sections is not part of the TI component specification, and TI

does not warrant its accuracy or completeness. TI’s customers are responsible for determining

suitability of components for their purposes. Customers should validate and test their design

implementation to confirm system functionality.

9.1 Application Information

The TPS25980x device is an integrated 8-A eFuse that is typically used for hot-swap and power rail protection

applications. It operates from 2.7 V to 24 V with adjustable overcurrent and undervoltage protection. It also

provides optional overvoltage with various fixed internal thresholds. The device aids in controlling the inrush

current and has the flexibility to configure the number of auto-retries and retry delay. The adjustable overcurrent

blanking timer provides the functionality to allow transient overcurrent pulses without limiting or tripping. These

devices protect source, load and internal MOSFET from potentially damaging events in systems such as PCIe

cards, SSDs, HDDs, Optical Modules, Routers, Switches, Industrial PCs, Retail ePOS (Point-of-sale) terminals

and Patient Monitoring Systems.

The following design procedure can be used to select the supporting component values based on the application

requirement. Additionally, a spreadsheet design tool TPS25980xx Design Calculator is available in the web

product folder.

9.2 Typical Application: Patient Monitoring System in Medical Applications

TPS259804O

V_OUT

V_IN

IN

OUT

3.3V

LDSTRT

R_VL1

1MΩ

R_PG

100KΩ

EN/UVLO

NRETRY

PG

IMON

C_NRETRY

2.2nF

B520C-

13-F

R_L(SU)

10Ω

C_OUT

1.4mF

C_IN

RETRY_DLY

dVdt

SMCJ12A

0.1µF

C_LDSTRT

0.1µF

R_VL2

GND ITIMER

ILIM

125KΩ

R_IMON

C_dVdt

1.62KΩ

C_{RETRY_DLY}

2.2nF

10nF

R_ILIM

182Ω

C_ITIMER

4.7nF

Figure 9-1. Typical Application Schematic - Input Protection for Patient Monitoring System

9.2.1 Design Requirements

Table 9-1 shows the design parameters for this application example.

Table 9-1. Design Parameters

DESIGN PARAMETER

EXAMPLE VALUE

12 V

Input voltage, V_IN

Undervoltage lockout set point, VIN_UVLO

Maximum load current, I_OUT

Current limit, I_LIM

10.8 V

6.5 A

8 A

Transient overcurrent blanking interval (t_ITIMER

)

2 ms

Load capacitance, C_OUT

1.4 mF

10 Ω

Load at start-up, R_L(SU)

Output voltage ramp time, T_dVdt

Maximum ambient temperature, T_A

20 ms

70 °C

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Table 9-1. Design Parameters (continued)

DESIGN PARAMETER

EXAMPLE VALUE

Retry delay, t_{RETRY_DLY}

No. of retries, N_RETRY

100 ms

4

9.2.2 Detailed Design Procedure

9.2.2.1 Device Selection

This design example considers a 12-V system operating voltage with a tolerance of ±10 %. The rated load

current is 6.5 A. If the current exceeds 8 A, then the device must allow overload current for 2-ms interval before

breaking the circuit and then restart. Accordingly, the TPS259804O variant is chosen. (Refer to Device

Comparison Table for device options.) Ambient temperatures may range from 20 °C to 70 °C. The load has a

minimum input capacitance of 1.4 mF and start-up resistive load of 10 Ω. The downstream load is turned on only

after the PG signal is asserted.

9.2.2.2 Setting the Current Limit Threshold: R_ILIMSelection

The R_ILIMresistor at the ILIM pin sets the overload current limit, whose value can be calculated using Equation

10.

1460

RILIM W =

(

)

ILIM

( )

A - 0.11

(10)

For I_LIM= 8 A, R_ILIMvalue is calculated to be 185.04 Ω. Choose the closest available standard value: 182 Ω, 1%.

Refering to the Electrical Characteristics table, it can be verified that the minimum current limit across

temperature for R_ILIMvalue of 182 Ω is 7.23 A, which is higher than the nominal rated load current (6.5 A),

thereby ensuring stable operation under normal conditions.

9.2.2.3 Setting the Undervoltage Lockout Set Point

The undervoltage lockout (UVLO) trip point is adjusted using the external voltage divider network of R_VL1and

R_VL2connected between IN, EN/UVLO and GND pins of the device. The resistor values required for setting the

undervoltage are calculated using Equation 11.

V^UVLO(R)x (R^VL1+ R^VL2)

R^VL2

VIN^UVLO=

(11)

For minimizing the input current drawn from the power supply, TI recommends to use higher values of resistance

for R_VL1and R_VL2. However, leakage currents due to external active components connected to the resistor string

can add error to these calculations. So, the resistor string current, I_RVL12must be 20 times greater than the

leakage current (I_ENLKG).

From the device electrical specifications, UVLO rising threshold V_UVLO(R)= 1.2 V. From design requirements,

VIN_UVLO= 10.8 V. First choose the value of R_VL1= 1 MΩ and use Equation 11 to calculate R_VL2= 125 kΩ.

Use the closest standard 1% resistor values: R_VL1= 1 MΩ, and R_VL2= 125 kΩ

9.2.2.4 Choosing the Current Monitoring Resistor: R_IMON

Voltage at IMON pin V_IMONis proportional to the output load current. This can be connected to an ADC of the

downstream system for monitoring the operating condition and health of the system. The R_IMONmust be

selected based on the maximum load current and the maximum IMON pin voltage at full-scale load current. The

maximum IMON pin voltage must be selected based on the input voltage range of the ADC used or the value

suggested in VIMON(Max) Recommended Values, whichever is lower. R_IMONis set using Equation 12.

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VIMONmax(V)

RIMON(W) =

-6

IOUTmax(A)ì 246 ì10

(12)

For I_LIM= 8 A and considering the operating range of ADC to be 0 V to 3.3 V, R_IMONcan be calculated as

3.3

RIMON=

= 1697 ꢀ

-6

8ì 243 ì10

(13)

Selecting R_IMONvalue less than shown in Equation 13 ensures that ADC limits are not exceeded for maximum

value of load current. Choose closest available standard value: 1620 Ω, 1 %.

9.2.2.5 Setting the Output Voltage Ramp Time (T_dVdt

)

For a successful design, the junction temperature of device must be kept below the absolute maximum rating

during both dynamic (start-up) and steady state conditions. Dynamic power stresses often are an order of

magnitude greater than the static stresses, so it is important to determine the right start-up time and in-rush

current limit required with system capacitance to avoid thermal shutdown during start-up with and without load.

The required ramp-up capacitor C_dVdtis calculated considering the two possible cases (see Case 1: Start-Up

Without Load: Only Output Capacitance C_OUTDraws Current and Case 2: Start-Up With Load:Output

Capacitance C_OUTand Load Draw Current)

9.2.2.5.1 Case 1: Start-Up Without Load: Only Output Capacitance C_OUTDraws Current

During start-up, as the output capacitor charges, the voltage drop as well as the power dissipated across the

internal FET decreases. The average power dissipated in the device during start-up is calculated using equation

14

P

D(INRUSH) = 0.5 x VIN x IINRUSH

(14)

(15)

Where I_INRUSHis the inrush current and is determined by Equation 15

VIN

I

^INRUSH= C^OUT

ì

T

dVdt

Equation 14 assumes that the load does not draw any current (apart from the capacitor charging current) until

the output voltage has reached its final value.

9.2.2.5.2 Case 2: Start-Up With Load: Output Capacitance C_OUTand Load Draw Current

When the load draws current during the turn-on sequence, there is additional power dissipated. Considering a

resistive load during start-up R_L(SU), load current ramps up proportionally with increase in output voltage during

T_dVdttime. Equation 16 shows the average power dissipation in the internal FET during charging time due to

resistive load.

2

1

V

IN

≈ ’

P_D(LOAD)

=

×

∆ ÷

6

R

L(SU)

« ◊

(16)

Equation 17 gives the total power dissipated in the device during start-up

P_D(STARTUP)= P_D(INRUSH)+ P_D(LOAD)

(17)

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The power dissipation, with and without load, for selected start-up time must not exceed the start-up thermal

shutdown limits as shown in Thermal Shutdown Plot During Start-up

200

TPS259807x

TPS259802x/03x/04x

100

50

30

20

10

5

3

2

1

0.5

2

3

4

5

6 7 8 10 20

Power Dissipation (W)

30 40 50 70 100

D002

Figure 9-2. Thermal Shutdown Plot During Start-up

For the design example under discussion, the output voltage has to be ramped up in 20 ms, which mandates a

slew-rate of 0.6 V/ms for a 12 V rail.

The required C_dVdtcapacitance on dVdt pin to set 0.6 V/ms slew rate can be calculated using Equation 18

4600

CdVdt pF =

= 7666 pF

(

)

SR V / ms

(

)

(18)

The dVdt capacitor is subjected to typically V_IN+ 4 V during startup. The high voltage bias leads to a drop in the

effective capacitor value. So, it is suggested to choose 20% higher than the calculated value, which gives 9.2 nF.

Choose closest 10% standard value: 10 nF

The 10 nF C_dVdtcapacitance sets a slew-rate of 0.46 V/ms and output ramp time T_dVdtof 26 ms.

The inrush current drawn by the load capacitance C_OUTduring ramp-up can be calculated using Equation 19

12 V

I

INRUSH = 1.4 mFì

= 0.65 A

26 ms

(19)

The inrush power dissipation can be calculated using Equation 20

PD(INRUSH) = 0.5 x 12 x 0.65 = 3.9 W

(20)

For 3.9 W of power loss, the thermal shutdown time of the device must be greater than the ramp-up time T_dVdtto

ensure a successful start-up. Figure 9-2 shows the start-up thermal shutdown limit. For 3.9 W of power, the

shutdown time is approximately 100 ms. So it is safe to use 26 ms as the start-up time without any load on the

output.

The additional power dissipation when a 10-Ω load is present during start-up is calculated using Equation 21

1

12²

10

≈ ’

P_D(LOAD)

=

ì

= 2.4W

∆ ÷

6

« ◊

(21)

(22)

The total device power dissipation during start-up can be calculated using Equation 22

P_D(STARTUP)= 3.9 + 2.4 = 6.3 W

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From Thermal Shutdown Plot During Start-up, the thermal shutdown time for 6.3 W is approximately 40 ms. It is

safe to have 30% margin to allow for variation of system parameters such as load, component tolerance, and

input voltage. So it is well within acceptable limits to use the 10 nF for C_dVdtcapacitor with start-up load of 10 Ω.

When C_OUTis large, there is a need to decrease the power dissipation during start-up. This can be done by

increasing the value of the C_dVdtcapacitor. A spreadsheet tool TPS25980xx Design Calculator available on the

web can be used for iterative calculations.

9.2.2.6 Setting the Load Handshake (LDSTRT) Delay

To indicate a successful start-up, the load circuit must provide a handshake signal to TPS25980x by pulling

down the LDSTRT pin within the time set by the capacitor C_LDSTRTon the LDSTRT pin. Once the PG asserts,

the device sources 2-μA current into C_LDSTRT. For a successful handshake, the load circuit must pull-down the

LDSTRT pin before C_LDSTRTcharges up to 1.2 V.

For the design requirement of 60-ms handshake delay, use Equation 23 to calculate C_LDSTRT

tLDSTRT

60ms

1.2V

CLDSTRT = ILDSTRT ì

= 2mA ì

= 0.1mF

VLDSTRT

(23)

Choose closest available standard value: 0.1 µF, 10 %.

9.2.2.7 Setting the Transient Overcurrent Blanking Interval (t_ITIMER

)

For the design example under discussion, overcurrent transients are allowed for 2-ms duration. This blanking

interval can be set by selecting appropriate capacitor C_ITIMERfrom ITIMER pin to ground. The value of C_ITIMERto

set 2 ms for t_ITIMERcan be calculated using Equation 24.

tITIMER (ms)

CITIMER (nF) =

= 4.255 nF

0.47

(24)

Choose closest available standard value: 4.7 nF, 10 %.

9.2.2.8 Setting the Auto-Retry Delay and Number of Retries

The time delay between retries can be programmed by selecting capacitor C_{RETRY_DLY}on RETRY_DLY pin. The

value of C_{RETRY_DLY}to set a 100-ms auto-retry delay can be calculated using Equation 25.

tRETRY_DLY (ms)

46.83

CRETRY_DLY (pF) =

- 4 pF = 2131.38 pF

(25)

Choose closest available standard value: 2.2 nF, 10 %.

The number of auto-retry attempts can be set by a capacitor C_NRETRYon the NRETRY pin using Equation 26

4ìCNRETRY (pF)

CRETRY_DLY (pF) + 4 pF

NRETRY =

(26)

For this design example, the requirement is to retry 4 times after the device shuts down due to a fault. Since, the

number of auto-retries can be adjusted in discrete steps as explained in Fault Response, choose C_NRETRYsuch

that N_RETRYis less than 4. Use Equation 27 to calculate C_NRETRY

.

NRETRY ì CRETRY_DLY (pF) + 4 pF

(

)

< 2204 pF

CNRETRY (pF) <

4

(27)

Choose closest available standard value: 2.2 nF, 10 %.

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9.2.3 Application Curves

A.

C_OUT= 1.4 mF

C_dVdt= 10 nF

R_L(SU)= Open

C_OUT= 1.4 mF

C_dVdt= 10 nF

R_L(SU)= 10 Ω

Figure 9-3. Hot-Plug Start-Up Without Load on

Output - dVdt Limited

Figure 9-4. Hot-Plug Start-Up With Load on Output

- dVdt Limited

A.

R_ILIM= TBD Ω

R_ILIM= 182 Ω

C_ITIMER= 4.7 nF

C_ITIMER= 4.7 nF C_{RETRY_DLY}= 2.2 nF,

C_NRETRY= 2.2 nF

Figure 9-5. Circuit Breaker With Transient

Overcurrent Blanking Interval of 2 ms

Figure 9-6. Circuit Breaker - Auto-Retry 4 Times

With Retry Delay of 100 ms

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A.

R_ILIM= 182 Ω

Figure 9-7. Output Hard Short-Circuit While ON

Figure 9-8. Output Hard Short-Circuit While ON

(Zoomed In)

A.

R_ILIM= 182 Ω

Figure 9-9. Power-Up With Short-Circuit on Output

Figure 9-10. Power-Up With Short-Circuit on

Output - Auto-Retry 4 Times With Retry Delay of

100 ms

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A.

C_LDSTRT= 0.1 μF

Figure 9-11. Successful Load Handshake (LDSTRT)

Figure 9-12. Unsuccessful Load Handshake

(LDSTRT)

9.3 System Examples

9.3.1 Optical Module Power Rail Path Protection

Optical modules are commonly used in high-bandwidth data communication systems such as Optical Networking

equipment, Enterprise/Data-Center Switches and Routers. Several variants of optical modules are available in

the market, which differ in the form-factor and the data speed support (Gbit/s). Of these, the popular variant

Double Dense Quad Small Form-factor Pluggable (QSFP-DD) module supports speeds up to 400 Gbit/s. In

addition to the system protection during hot-plug events, the other key requirement for optical module is the tight

voltage regulation. The optical module uses 3.3 V supply and requires voltage regulation within ±5 % for proper

operation.

A typical power tree of such system is shown in Figure 9-13. The optical line card consists of DC-DC converter,

protection device (eFuse) and power supply filters. The DC-DC converter steps-down the 12 V to 3.3 V and

maintains the 3.3 V rail within ±2 %. The power supply filtering network uses ‘LC’ components to reduce high

frequency noise injection into the optical module. The DC resistance of the inductor ‘L’ causes voltage drop of

around 1.5 % which leaves us with a voltage drop budget of just 1.5 % (3.3 V * 1.5% = 50 mV) across the

protection device. Considering a maximum load current of 5.5 A per module, the maximum ON-resistance of the

protection device should be less than 9 mΩ. TPS25980x eFuse offers ultra-low ON-resistance of 2.7 mΩ

(typical) and 4.5 mΩ (maximum, across temperature), thereby meeting the target specification with additional

margin to spare and simplifying the overall system design.

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V_IN

12V

3.3V

V_OUT

IN

OUT

VccTx

VccRx

DC-DC

eFuse

LDSTRT

QSFP

Module

Hot Plug / Unplug

Vcc

GND

ModPrsL

Optical Line Card

Figure 9-13. Power Tree Block Diagram of a Typical Optical Line Card

As shown in Figure 9-13, ModPrsL signal acts as a handshake signal between the line card and the optical

module. ModPrsL is always pulled to ground inside the module. When the module is hot-plugged into the host

“Optical Line Card” connector, the ModPrsL signal pulls down the LDSTRT pin and enables the TPS25980x

eFuse to power the module. This ensures that power is applied on the port only when a module is plugged in

and disconnected when there is no module present.

TPS259802O

V_OUT

V_IN

IN

OUT

3.3V

ModPrsL

LDSTRT

R_PG

100KΩ

EN/UVLO

NRETRY

PG

IMON

C_NRETRY

OPEN

C_IN

0.1µF

C_L

10µF

R_L

RETRY_DLY

dVdt

B520C-13-F

GND ITIMER

ILIM

0.1µF

R_IMON

C_dVdt

1910Ω

C_{RETRY_DLY}

OPEN

3.3nF

R_ILIM

210Ω

C_ITIMER

15nF

Figure 9-14. TPS259802O Configured for a 3.3-V Power Rail Path Protection in Optical Module

9.3.1.1 Design Requirements

Table 9-2 shows the design parameters for this example.

Table 9-2. Design Parameters

DESIGN PARAMETER

Input voltage, V_IN

EXAMPLE VALUE

3.3 V

3.7 V

± 5 %

5.5 A

7 A

Overvoltage lockout, V_OVP

Maximum voltage drop in the path

Maximum load current, I_OUT

Current limit, I_LIM

Transient overcurrent blanking interval (t_ITIMER

)

6 ms

10 µF

85 °C

Yes

Load capacitance, C_OUT

Maximum ambient temperature, T_A

Module present detection, ModPrsL

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Table 9-2. Design Parameters (continued)

Retry delay, t_{RETRY_DLY}

200 µs

4

No. of retries, N_RETRY

9.3.1.2 Device Selection

Optical modules are very sensitive to supply voltage variations and thus require input overvoltage protection.

TPS259802O variant from TPS25980x family is selected to set overvoltage protection at 3.7 V. TPS259802O

allows overcurrents for a user specified blanking interval t_ITIMERbefore breaking the circuit path. In this use case,

t_ITIMERis set for 6 ms interval.

9.3.1.3 External Component Settings

By following similar design procedure as outlined in Detailed Design Procedure, the external component values

are calculated as below

•

R_ILIM= 210 Ω to set 7-A current limit

C_ITIMER= 15 nF to set fault blanking time of 6 ms

R_IMON= 1910 Ω to set maximum IMON pin voltage V_IMONwithin ADC range of 3.3 V

C_dVdtcapacitance is chosen as 3.3 nF

Leave RETRY_DLY and NRETRY pins OPEN to set minimum auto-retry delay of 200 μs and number of

retries to 4

9.3.1.4 Voltage Drop

Table 9-3 shows the power path voltage drop (%) due to the eFuse in QSFP modules of different power classes.

Table 9-3. Voltage Drop across TPS25980x on QSFP Module Power Rail

POWER CLASS

MAXIMUM POWER

CONSUMPTION PER MODULE

(W)

MAXIMUM LOAD CURRENT (A) TYPICAL VOLTAGE DROP (%)

1

2

3

4

5

6

7

8

1.5

3.5

7

0.454

1.06

2.12

2.42

3.03

3.63

4.24

5.45

0.037

0.087

0.174

0.2

8

10

12

14

18

0.248

0.3

0.347

0.446

38

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9.3.1.5 Application Curves

Figure 9-15. Output Voltage Profile When Optical

Module is Inserted

Figure 9-16. Output Voltage Profile When Optical

Module is Plugged Out

Figure 9-17. Circuit Breaker With Transient

Overcurrent Blanking Interval of 6 ms; Device

Restarts in Current Limit Mode

Figure 9-18. Overload Response and Recovery

Figure 9-19. Overvoltage Cut-off at 3.7 V with

TPS259802O Device

Figure 9-20. Overvoltage Protection Response and

Recovery with TPS259802O Device

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9.3.2 Input Protection for 12-V Rail Applications: PCIe Cards, Storage Interfaces and DC Fans

TPS25980x eFuse provides inrush current management and also protects the system from most common faults

such as undervoltage, overvoltage and overcurrents. The combination of high current support along with low

ON-resistance makes TPS25980x eFuse an ideal protection solution for PCIe cards, Storage Interfaces and DC

Fan loads. The external component values can be calculated by following the design procedure outlined in

Detailed Design Procedure. Alternatively, a spreadsheet design tool TPS25980xx Design Calculator is available

for simplified design efforts.

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10 Power Supply Recommendations

The TPS25980x devices are designed for a supply voltage range of 2.7 V ≤ VIN ≤ 24 V. TI recommends an input

ceramic bypass capacitor higher than 0.1 μF if the input supply is located more than a few inches from the

device. The power supply must be rated higher than the set current limit to avoid voltage droops during

overcurrent and short-circuit conditions.

10.1 Transient Protection

In the case of a short circuit and overload current limit when the device interrupts current flow, the input

inductance generates a positive voltage spike on the input, and the output inductance generates a negative

voltage spike on the output. The peak amplitude of voltage spikes (transients) is dependent on the value of

inductance in series to the input or output of the device. Such transients can exceed the absolute maximum

ratings of the device if steps are not taken to address the issue. Typical methods for addressing transients

include:

•

Minimize lead length and inductance into and out of the device.

Use a large PCB GND plane.

Use a Schottky diode across the output to absorb negative spikes.

Use a low value ceramic capacitor C_IN= 0.001 μF to 0.1 μF to absorb the energy and dampen the transients.

The approximate value of input capacitance can be estimated using Equation 28.

LIN

V^{SPIKE(Absolute)}= V^IN+ I^LOADx

CIN

(28)

where

•

V_INis the nominal supply voltage

I_LOADis the load current

L_INequals the effective inductance seen looking into the source

C_INis the capacitance present at the input

Some of the applications may require the addition of a Transient Voltage Suppressor (TVS) to prevent transients

from exceeding the absolute maximum ratings of the device. A typical circuit implementation with optional

protection components (a ceramic capacitor, TVS and Schottky diode) is shown in Figure 10-1.

TPS25980

IN

OUT

12V

3.3V

LDSTRT

1MO

100kO

100O

EN/UVLO

NRETRY

PG

IMON

220uF

0.1uF

RETRY_DLY

dVdt

1uF

56pF

137kO

GND ITIMER

ILIM

511O

3.3nF

4.7nF

182O

Figure 10-1. Typical Circuit Implementation With Optional Protection Components

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10.2 Output Short-Circuit Measurements

It is difficult to obtain repeatable and similar short-circuit testing results. The following contribute to variation in

results:

•

Source bypassing

Input leads

Board layout

Component selection

Output shorting method

Relative location of the short

Instrumentation

The actual short exhibits a certain degree of randomness because it microscopically bounces and arcs. Ensure

that configuration and methods are used to obtain realistic results.

Note

Do not expect to see waveforms exactly like the waveforms in this data sheet because every setup is

different.

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11 Layout

11.1 Layout Guidelines

•

The IN Exposed Thermal Pad is used for Heat Dissipation. Connect to as much copper area as possible

using an array of thermal vias. The via array also helps to minimize the voltage gradient across the VIN pad

and facilitates uniform current distribution through the internal FET, which improves the current sensing and

monitoring accuracy.

•

For all applications, TI recommends a ceramic decoupling capacitor of 0.01 μF or greater between IN and

GND terminals. For hot-plug applications, where input power-path inductance is negligible, this capacitor can

be eliminated or minimized.

The optimal placement of the decoupling capacitor is closest to the IN and GND terminals of the device. Care

must be taken to minimize the loop area formed by the bypass-capacitor connection, the IN terminal, and the

GND terminal of the IC.

High current carrying power path connections must be as short as possible and must be sized to carry at

least twice the full-load current. It is recommended to use a minimum trace width of 50 mil for the OUT power

connection.

The GND terminal is the reference for all internal signals and must be isolated from any bounce due to large

switching currents in the system power ground plane. It is recommended to connect the device GND to a

signal ground island on the board, which in turn is connected to the system power GND plane at one point.

Locate the support components for the following signals close to their respective connection pins - ILIM,

IMON, ITIMER, RETRY_DLY, NRETRY and dVdT with the shortest possible trace routing to reduce parasitic

effects on the respective associated functions. These traces must not have any coupling to switching signals

on the board.

•

The ILIM pin is highly sensitive to capacitance and TI recommends to pay special attention to the layout to

maintain the parasitic capacitance below 30 pF for stable operation.

Use short traces on the RETRY_DLY and NRETRY pins to ensure the auto-retry timer delay and number of

auto-retries is not altered by the additional parasitic capacitance on these pins.

Protection devices such as TVS, snubbers, capacitors, or diodes must be placed physically close to the

device they are intended to protect. These protection devices must be routed with short traces to reduce

inductance. For example, TI recommends a protection Schottky diode to address negative transients due to

switching of inductive loads, and it must be physically close to the OUT pins.

•

Use proper layout and thermal management techniques to ensure there is no significant steady state thermal

gradient between the two thermal pads on the IC. This is necessary for proper functioning of the device

overtemperature protection mechanism and successful startup under all conditions.

Obtaining acceptable performance with alternate layout schemes is possible; the Layout Example is intended

as a guideline and shown to produce good results from electrical and thermal standpoint.

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11.2 Layout Example

PCB via to Bottom Layer

VIN Plane (Top Layer)

Blind PCB via to Inner Layer

VOUT Plane (Top Layer)

> 50 mils

*

Signal GND (Top Layer)

Power GND Plane (Top Layer)

* Optional components for suppressing transients induced while

switching current through inductive elements at input/output

Figure 11-1. TPS25980 Example PCB Layout

44

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12 Device and Documentation Support

12.1 Documentation Support

12.1.1 Related Documentation

For related documentation see the following:

•

TPS259804OEVM eFuse Evaluation Board

TPS25980xx Design Calculator

12.1.1.1 Related Links

The table below lists quick access links. Categories include technical documents, support and community

resources, tools and software, and quick access to order now.

Table 12-1. Related Links

TECHNICAL

DOCUMENTS

TOOLS &

SOFTWARE

SUPPORT &

COMMUNITY

PARTS

PRODUCT FOLDER

ORDER NOW

TPS259802O

TPS259803O

TPS259804O

TPS259807O

Click here

12.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper

right corner, click on Alert me to register and receive a weekly digest of any product information that has

changed. For change details, review the revision history included in any revised document.

12.3 Support Resources

TI E2E^™support forums are an engineer's go-to source for fast, verified answers and design help — straight

from the experts. Search existing answers or ask your own question to get the quick design help you need.

Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do

not necessarily reflect TI's views; see TI's Terms of Use.

12.4 Trademarks

TI E2E^™is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

12.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

12.6 Glossary

TI Glossary

This glossary lists and explains terms, acronyms, and definitions.

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13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGE MATERIALS INFORMATION

www.ti.com

16-Aug-2020

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TPS259802ONRGER

TPS259803ONRGER

TPS259804ONRGER

TPS259807ONRGER

VQFN

RGE

24

3000

330.0

12.4

4.35

1.1

8.0

12.0

Q2

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

16-Aug-2020

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

TPS259802ONRGER

TPS259803ONRGER

TPS259804ONRGER

TPS259807ONRGER

VQFN

RGE

24

3000

338.0

355.0

50.0

Pack Materials-Page 2

GENERIC PACKAGE VIEW

RGE 24

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

Images above are just a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4204104/H

PACKAGE OUTLINE

RGE0024M

VQFN - 1 mm max height

S

C

A

L

E

3

.

0

PLASTIC QUAD FLATPACK - NO LEAD

4.1

3.9

B

A

0.475

0.275

PIN 1 INDEX AREA

4.1

3.9

0.29

0.19

DETAIL

OPTIONAL TERMINAL

TYPICAL

1.0

0.8

C

SEATING PLANE

0.08 C

0.05

0.00

2X 2.7 0.1

4X 2.5

(0.2) TYP

7

12

SEE TERMINAL

DETAIL

EXPOSED

THERMAL PAD

6

13

26

25

0.85 0.1

(0.925)

SYMM

(0.625)

1.45 0.1

1

18

0.29

0.19

24X

24

19

0.1

0.05

C A B

SYMM

PIN 1 ID

(OPTIONAL)

0.475

0.275

24X

2X 0.5

4223975/B 03/2018

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT

RGE0024M

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(2.7)

SYMM

24

19

24X (0.575)

24X (0.24)

1

18

(0.625)

(1.45)

25

26

(1.1)

TYP

(R0.05)

TYP

SYMM

(3.825)

(0.925)

TYP

(0.15)

TYP

20X (0.5)

(0.85)

13

6

(

0.2) TYP

VIA

7

12

6X (1.1)

(3.825)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:15X

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

SOLDER MASK

OPENING

METAL

EXPOSED

METAL

EXPOSED

METAL

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4223975/B 03/2018

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

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EXAMPLE STENCIL DESIGN

RGE0024M

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

4X (1.188)

4X (0.694)

19

24

24X (0.575)

1

25

18

24X (0.24)

2X

(1.3)

(R0.05) TYP

2X

(0.625)

SYMM

(3.825)

26

2X

(0.925)

2X

(0.76)

20X (0.5)

13

6

METAL

TYP

7

12

SYMM

(3.825)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD 25

78% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

SCALE:20X

4223975/B 03/2018

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

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IMPORTANT NOTICE AND DISCLAIMER

TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE

DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”

AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY

IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

PARTY INTELLECTUAL PROPERTY RIGHTS.

These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable

standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you

permission to use these resources only for development of an application that uses the TI products described in the resource. Other

reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third

party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims,

damages, costs, losses, and liabilities arising out of your use of these resources.

TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on

ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable

warranties or warranty disclaimers for TI products.

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	TPS259802O
厂家：	TEXAS INSTRUMENTS
描述：	TPS25980: 2.7- 24 V, 8 A, 3 mÎ© Smart eFuse - Integrated Hot-swap Protection With Adjustable Transient Fault Management
文件：	总55页 (文件大小：6258K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TPS259802O [TI]

相关型号：

TPS259802ONRGE

TPS259802ONRGER

TPS259803O

TPS259803ONRGE

TPS259803ONRGER

TPS259804O

TPS259804ONRGE

TPS259804ONRGER

TPS259807O

TPS259807ONRGE

TPS259807ONRGER

TPS25980X