TPS259814ARPWR [TI]
具有瞬态过流消隐计时器的 2.7V 至 16V、10A、6mΩ 电子保险丝 | RPW | 10 | -40 to 125;
| 型号： | TPS259814ARPWR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有瞬态过流消隐计时器的 2.7V 至 16V、10A、6mΩ 电子保险丝 | RPW | 10 | -40 to 125 电子 |
| 文件： | 总52页 (文件大小：5167K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS25981
SLVSGG6B – APRIL 2022 – REVISED JUNE 2023
TPS25981x 2.7 V – 16 V, 10-A, 6-mΩ eFuse with Transient Overcurrent Blanking Timer
1 Features
3 Description
•
•
•
Wide operating input voltage range: 2.7 V to 16 V
– 20-V absolute maximum
Integrated FET with low on-resistance: RON = 6
mΩ (typ.)
Fast overvoltage protection
– Adjustable overvoltage lockout (OVLO) with
1.2-μs (typ.) response time
The TPS25981xx family of eFuses is a highly
integrated circuit protection and power management
solution in a small package. The devices provide
multiple protection modes using very few external
components and are a robust defense against
overloads, short circuits, voltage surges and
excessive inrush current.
•
Overcurrent protection with load current monitor
output (ILM)
– Circuit-breaker response
Output slew rate and inrush current can be
adjusted using a single external capacitor. Loads
are protected from input overvoltage conditions by
cutting off the output if input exceeds an adjustable
overvoltage threshold. The devices respond to output
overload by actively limiting the current (during start-
up) or breaking the circuit (during steady-state).
The overcurrent protection threshold as well as
the transient overcurrent blanking timer are user-
adjustable. The current limit control pin also functions
as an analog load current monitor.
– Adjustable threshold (ILIM) 1.5 A – 11 A
•
±10% accuracy for ILIM > 5 A
– Adjustable transient blanking timer (ITIMER) to
allow peak currents up to 2 × ILIM
– Output load current monitor accuracy: ±10%
(IOUT ≥ 3 A)
Fast-trip response for short-circuit protection
– 640-ns (typ.) response time
•
– Adjustable (2 × ILIM) and fixed thresholds
Active high enable input with adjustable
undervoltage lockout threshold (UVLO)
Active low enable input with adjustable
undervoltage lockout threshold (OVLO)
Adjustable output slew rate control (dVdt)
Option to drive external FET for reverse current
blocking in disabled/OFF state
Overtemperature protection
Quick Output Discharge
Digital outputs
– Power Good (PG) and fault indication (FLT)
UL 2367 recognition (pending)
The devices are available in a 2-mm × 2-mm, 10-
pin HotRod™ QFN package for improved thermal
performance and reduced system footprint.
•
•
The devices are characterized for operation over a
junction temperature range of –40°C to +125°C.
•
•
Device Information
PART NUMBER
PACKAGE(1)
BODY SIZE (NOM)
•
•
•
TPS25981
RPW (VQFN-HR, 10) 2.00 mm × 2.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
•
•
•
VOUT
VIN = 2.7 to 16 V
IN
OUT
IEC 62368 CB certification (pending)
Small footprint: QFN 2-mm × 2-mm, 0.45-mm pitch
VLOGIC
COUT
2 Applications
EN/UVLO
TPS25981x
•
•
•
•
•
Optical modules
PG
Server/PC motherboard/add-on cards
Enterprise routers/data center switches
Industrial PC
EN/OVLO
ITIMER dVdt
FLT
ILM
GND
RILM
CITIMER
CDVDT
UHDTV
Simplified Schematic
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS25981
SLVSGG6B – APRIL 2022 – REVISED JUNE 2023
www.ti.com
Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Device Comparison Table...............................................3
6 Pin Configuration and Functions...................................4
7 Specifications.................................................................. 6
7.1 Absolute Maximum Ratings........................................ 6
7.2 ESD Ratings............................................................... 6
7.3 Recommended Operating Conditions.........................6
7.4 Thermal Information....................................................7
7.5 Electrical Characteristics.............................................8
7.6 Timing Requirements..................................................9
7.7 Switching Characteristics..........................................10
7.8 Typical Characteristics.............................................. 11
8 Detailed Description......................................................18
8.1 Overview...................................................................18
8.2 Functional Block Diagram.........................................19
8.3 Feature Description...................................................20
8.4 Device Functional Modes..........................................30
9 Application and Implementation..................................31
9.1 Application Information............................................. 31
9.2 Typical Application.................................................... 34
10 Power Supply Recommendations..............................39
10.1 Transient Protection................................................39
10.2 Output Short-Circuit Measurements....................... 40
11 Layout...........................................................................41
11.1 Layout Guidelines................................................... 41
11.2 Layout Example...................................................... 42
12 Device and Documentation Support..........................43
12.1 Documentation Support.......................................... 43
12.2 Receiving Notification of Documentation Updates..43
12.3 Support Resources................................................. 43
12.4 Trademarks.............................................................43
12.5 Electrostatic Discharge Caution..............................43
12.6 Glossary..................................................................43
13 Mechanical, Packaging, and Orderable
Information.................................................................... 44
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (July 2022) to Revision B (June 2023)
Page
•
•
•
•
•
•
•
Added "Option to drive external FET for reverse current".................................................................................. 1
Added variants TPS259813ARPW and TPS259813LRPW................................................................................3
Updated the description of the DVDT pin........................................................................................................... 4
Updated image formatting.................................................................................................................................11
Updated image................................................................................................................................................. 19
Updated Figure 8-7 ..........................................................................................................................................27
Added Section 8.3.9 ........................................................................................................................................ 29
Changes from Revision * (April 2022) to Revision A (July 2022)
Page
•
Changed status from "Advance Information" to "Production Data".................................................................... 1
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5 Device Comparison Table
Reverse Current
Part Number
Overvoltage Response
Overcurrent Response
Response to Fault
Blocking FET driver
TPS259814ARPW
Auto-Retry
No
TPS259814LRPW
TPS259813ARPW
TPS259813LRPW
Latch-Off
Auto-Retry
Latch-Off
Adjustable OVLO
Circuit-Breaker
Yes
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6 Pin Configuration and Functions
IN
OUT
1
EN/UVLO
10
ITIMER
ILM
EN/OVLO
9
2
5
6
PG
GND
8
3
DVDT
FLT
7
4
Figure 6-1. TPS25981xx RPW Package 10-Pin QFN Top View
Table 6-1. Pin Functions
PIN
TYPE
DESCRIPTION
NAME
NO.
Active high enable for the device. A resistor divider on this pin from input supply to GND
can be used to adjust the undervoltage lockout threshold. Do not leave floating. Refer to
Undervoltage Lockout (UVLO and UVP) for details.
Analog
Input
EN/UVLO
1
A resistor divider on this pin from supply to GND can be used to adjust the overvoltage lockout
threshold. This pin can also be used as an Active low enable for the device. Do not leave
floating. Refer to Overvoltage Lockout (OVLO) for details.
Analog
Input
EN/OVLO
2
Power Good indication.
This pin is an open-drain signal which is asserted high when the power FET has fully turned
ON and is ready to deliver power. Refer to Power Good (PG) for more details.
Digital
Output
PG
3
4
Digital Active low fault event indicator. This pin is an open-drain signal which is pulled low when a
Output fault is detected. Refer to Fault Response and Indication (FLT) for more details.
FLT
IN
5
6
Power Power input
Power Power output
OUT
A capacitor from this pin to GND sets the output turn on slew rate. Leave this pin floating for
the fastest turn-on slew rate. Refer to Slew Rate (dVdt) and Inrush Current Control for details.
Only for TPS259813x variants, this pin can also be used to drive an external FET to
Analog
Output
DVDT
7
implement reverse current blocking. Please refer to Reverse Current Blocking FET Driver
for more details.
GND
ILM
8
9
Ground This pin is the ground reference for all internal circuits and must be connected to system GND.
This pin is a dual function pin used to limit and monitor the output current. An external resistor
from this pin to GND sets the overcurrent protection threshold during start-up as well as
steady-state. The pin voltage can also be used as analog output load current monitor signal.
Analog
Output
Do not leave floating. Refer to Circuit-Breaker During Steady-state or Active Current Limiting
During Start-up for more details.
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Table 6-1. Pin Functions (continued)
PIN
TYPE
DESCRIPTION
NAME
NO.
A capacitor from this pin to GND sets the overcurrent blanking interval during which the output
current can temporarily exceed set current limit (but lower than fast-trip threshold) during
steady-state before the device overcurrent response takes action. Leave this pin open for
fastest response to overcurrent events. Refer to Circuit-Breaker During Steady-state for more
details.
Analog
Output
ITIMER
10
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
Parameter
Pin
MIN
–0.3
–0.3
–0.8
–0.3
–0.3
MAX
20
UNIT
VIN
Maximum input voltage range, –40℃ ≤ TJ ≤ 125℃
Maximum output voltage range, –40℃ ≤ TJ ≤ 125℃
Minimum output voltage pulse (< 1 µs)
Maximum Enable pin voltage range
Maximum EN/OVLO pin voltage range
Maximum dVdT pin voltage range
Maximum ITIMER pin voltage range
Maximum PG pin voltage range
Maximum FLT pin voltage range
Maximum ILM pin voltage range
Maximum continuous switch current
Junction temperature
IN
V
VOUT
VOUT,PLS
VEN/UVLO
VOV
OUT
OUT
VIN + 0.3
EN/UVLO
EN/OVLO
dVdt
6.5
6.5
V
V
VdVdT
VITIMER
VPG
Internally limited
Internally limited
–0.3
V
ITIMER
PG
V
6.5
6.5
V
VFLTB
VILM
FLT
–0.3
V
ILM
Internally limited
Internally limited
Internally limited
V
IMAX
IN to OUT
A
TJ
°C
°C
°C
TLEAD
Tstg
Maximum lead temperature
300
150
Storage temperature
–65
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.
If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
7.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC
JS-001(1)
±2000
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per ANSI/ESDA/JEDEC
JS-002(2)
±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
Parameter
Pin
MIN
MAX
16
UNIT
V
VIN
Input voltage range
IN
2.7
VOUT
VEN/UVLO
VOV
Output voltage range
OUT
VIN
5(1)
1.5
V
EN/UVLO pin voltage range
EN/OVLO pin voltage range
dVdT pin capacitor voltage rating
FLT pin voltage range
EN/UVLO
EN/OVLO
dVdt
V
0.5
V
VdVdT
VFLTB
VPG
VIN + 5 V
V
FLT
5
5
V
PG pin voltage range
PG
V
VITIMER
RILM
ITIMER pin capacitor voltage rating
ILM pin resistance to GND
Continuous switch current, TJ ≤ 125℃
ITIMER
ILM
4
V
600
4400
10
Ω
IMAX
IN to OUT
A
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7.3 Recommended Operating Conditions (continued)
over operating free-air temperature range (unless otherwise noted)
Parameter
Pin
MIN
MAX
UNIT
TJ
Junction temperature
–40
125
°C
(1) For supply voltages below 5V, it is okay to pull up the EN pin to IN directly. For supply voltages greater than 5V , it is recommended
to use a resistor divider with minimum pull-up resistor value of 350 kΩ.
7.4 Thermal Information
TPS25981xx
THERMAL METRIC (1)
RPW (QFN)
10 PINS
49.7(2)
71.8(3)
15.7
UNIT
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJA
RθJB
ΨJT
Junction-to-ambient thermal resistance
Junction-to-board thermal resistance
Junction-to-top characterization parameter
Junction-to-top characterization parameter
2.1(2)
1.3(3)
23 (2)
ΨJB
Junction-to-board characterization parameter
14.5 (3)
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
(2) Based on simulations conducted with the device mounted on a custom 4-layer PCB (2s2p) with 8 thermal vias under device
(3) Based on simulations conducted with the device mounted on a JEDEC 4-layer PCB (2s2p) with no thermal vias under device
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7.5 Electrical Characteristics
(Test conditions unless otherwise noted) –40°C ≤ TJ ≤ 125°C, VIN = 12 V, OUT = Open, VEN/UVLO = 2 V, VOVLO = 0 V, RILM
611 Ω , dVdT = Open, ITIMER = Open, FLT = Open, PG = Open. All voltages referenced to GND.
=
Test
Parameter
Description
MIN
TYP
MAX
UNITS
INPUT SUPPLY (IN)
IQ(ON)
IQ(OFF)
ISD
IN supply quiescent current
417
68
610
90
µA
µA
µA
V
IN supply OFF state current (VSD(F) < VEN < VUVLO(F)
)
IN supply shutdown current (VEN < VSD(F)
)
3
25
VUVP(R)
VUVP(F)
IN supply UVP rising threshold
2.44
2.35
2.53
2.42
2.64
2.55
IN supply UVP falling threshold
V
OUTPUT LOAD CURRENT MONITOR (ILM)
Analog load current monitor gain (IMON : IOUT), IOUT = 1.5 A,
IOUT < ILIM
82.9
87
95.3
95.3
95.3
95.3
95.3
107.6
104.5
103.1
102.6
102.4
µA/A
µA/A
µA/A
µA/A
µA/A
Analog load current monitor gain (IMON : IOUT), IOUT = 3 A,
IOUT < ILIM
Analog load current monitor gain (IMON : IOUT), IOUT = 4.5 A,
IOUT < ILIM
GIMON
87.6
87.7
87.8
Analog load current monitor gain (IMON : IOUT), IOUT = 8 A,
IOUT < ILIM
Analog load current monitor gain (IMON : IOUT), IOUT = 10 A,
IOUT < ILIM
OVERCURRENT PROTECTION (OUT)
Overcurrent threshold, RILM = 3320 Ω
1.72
2.64
5.43
7.95
9.8
1.99
2.98
2.26
3.32
6.52
9.52
11.73
0.1
A
A
A
A
A
A
Overcurrent threshold, RILM = 2212 Ω
ILIM
Overcurrent threshold, RILM = 1102 kΩ
Overcurrent threshold, RILM = 750 Ω
5.98
8.73
Overcurrent threshold, RILM = 611 Ω
10.76
ISPFLT
ISPFLT
Circuit-Breaker threshold, ILM pin open (Single point failure)
Circuit-Breaker threshold, ILM pin shorted to GND (Single
point failure)
2.24
3.3
A
IFT
Fixed fast-trip current threshold
39.5
193
A
%
V
ISCGain
VFB
Scalable fast-trip threshold (ISC) : ILIM ratio
VOUT threshold to exit current limit foldback
170
242
1.55
1.91
2.23
ON RESISTANCE (IN - OUT)
2.7 ≤ VIN ≤ 4 V, IOUT = 3 A, TJ = 25℃
6.07
5.81
mΩ
mΩ
mΩ
RON
4 < VIN ≤ 16 V, IOUT = 3 A, TJ = 25℃
2.7 ≤ VIN ≤ 16 V, IOUT = 3 A, –40℃ ≤ TJ ≤ 125℃
8.4
ENABLE/UNDERVOLTAGE LOCKOUT (EN/UVLO)
VUVLO(R)
VUVLO(F)
VSD(F)
EN/UVLO rising threshold
1.176
1.073
0.45
1.20
1.09
0.75
1.224
1.116
V
V
EN/UVLO falling threshold
EN/UVLO falling threshold for lowest shutdown current
EN/UVLO pin leakage current
V
IENLKG
–0.1
0.1
µA
OVERVOLTAGE LOCKOUT (EN/OVLO)
VOV(R)
VOV(F)
IOVLKG
OVLO rising threshold
1.176
1.074
–0.1
1.20
1.09
1.224
1.116
0.1
V
V
OVLO falling threshold
OVLO pin leakage current (0.5 V < VOVLO < 1.5 V)
µA
OVERCURRENT FAULT TIMER (ITIMER)
IITIMER ITIMER pin internal discharge current, IOUT > ILIM
1.25
2
2.72
µA
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7.5 Electrical Characteristics (continued)
(Test conditions unless otherwise noted) –40°C ≤ TJ ≤ 125°C, VIN = 12 V, OUT = Open, VEN/UVLO = 2 V, VOVLO = 0 V, RILM
=
611 Ω , dVdT = Open, ITIMER = Open, FLT = Open, PG = Open. All voltages referenced to GND.
Test
Parameter
Description
MIN
TYP
MAX
UNITS
RITIMER
ITIMER pin internal pullup resistance
15.4
2.57
1.06
1.51
kΩ
V
VINT
ITIMER pin internal pullup voltage
2.1
0.6
2.74
1.37
1.74
VITIMER(F)
ΔVITIMER
ITIMER comparator threshold, IOUT > ILIM
ITIMER discharge differential voltage threshold, IOUT > ILIM
V
1.28
V
POWER GOOD INDICATION (PG)
PG pin voltage while de-asserted. VIN < VUVP(F), VEN
<
<
0.66
0.80
0.90
V
V
VSD(F), Weak pullup (IPG = 26 μA)
VPGD
PG pin voltage while de-asserted. VIN < VUVP(F), VEN
VSD(F), Strong pullup (IPG = 242 μA)
0.78
0
PG pin voltage while de-asserted, VIN > VUVP(R)
PG pin leakage current, PG asserted
FLT pin internal pulldown resistance
0.60
3
V
µA
Ω
IPGLKG
RFLTB
12.57
FAULT INDICATION (FLT)
IFLTLKG
FLT pin leakage current
–1
1
µA
OVERTEMPERATURE PROTECTION (OTP)
TSD
Thermal Shutdown rising threshold, TJ↑
Thermal Shutdown hysteresis, TJ↓
154
10
°C
°C
TSDHYS
DVDT
IdVdt
dVdt pin internal charging current
1.4
3.45
488
5.7
µA
Ω
QUICK OUTPUT DISCHARGE (OUT)
RQOD
Quick Output Discharge Resistance, VEN < VUVLO(F)
455
530
7.6 Timing Requirements
PARAMETER
TEST CONDITIONS
MIN TYP MAX
UNIT
µs
tOVLO
tCB
Overvoltage lock-out response time
VOVLO > VOV(R) to VOUT
↓
1.2
1.8
640
640
105
14
Circuit-Breaker response time
Short-circuit response time
ITIMER = Open, IOUT > ILIM + 30% to VOUT
IOUT > 3 × ILIM to output current cut off
↓
µs
tSC
ns
tFT
Fixed fast-trip response time
Thermal Shutdown auto-retry Interval
PG assertion de-glitch time
IOUT > IFT to IOUT
↓
ns
tTSD,RST
tPGA
tPGD
Device enabled and TJ < TSD – TSDHYS
ms
µs
PG de-assertion de-glitch time
14
µs
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7.7 Switching Characteristics
The output rising slew rate is internally controlled and constant across the entire operating voltage range to ensure the turn
on timing is not affected by the load conditions. The rising slew rate can be adjusted by adding capacitance from the dVdt pin
to ground. As CdVdt is increased it slows the rising slew rate (SR). See Slew Rate and Inrush Current Control (dVdt) section
for more details. The Turn-Off Delay and Fall Time, however, are dependent on the RC time constant of the load capacitance
(COUT) and Load Resistance (RL). The Switching Characteristics are only valid for the power-up sequence where the supply
is available in steady-state condition and the load voltage is completely discharged before the device is enabled. Typical
values are taken at TJ = 25°C unless specifically noted otherwise. RL = 100 Ω, COUT = 1 µF.
CdVdt
3300 pF
=
PARAMETER
VIN
CdVdt = Open CdVdt = 1800 pF
8.19 0.78
UNITS
2.7 V
5 V
1.30
1.42
1.68
0.46
0.60
0.93
1.66
2.82
5.74
2.11
3.42
6.67
24.90
21.10
18.80
SRON
tD,ON
tR
Output rising slew rate
11.28
19.71
0.14
0.14
0.14
0.26
0.36
0.49
0.40
0.50
0.63
24.90
21.10
18.80
0.84
0.98
0.70
0.96
1.57
2.77
4.78
9.84
3.47
5.74
11.41
24.90
21.10
18.80
V/ms
12 V
2.7 V
5 V
Turn-on delay
Rise time
ms
ms
ms
µs
12 V
2.7 V
5 V
12 V
2.7 V
5 V
tON
Turn-on time
Turn-off delay
12 V
2.7 V
5 V
tD,OFF
12 V
VEN/UVLO
EN/UVLO
VUVLO(R)
VUVLO(F)
0
tON
SRON
tD,OFF
90%
VIN
OUT
10%
0V
tR
tF
tD,ON
Time
Figure 7-1. TPS25981xx Switching Times
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7.8 Typical Characteristics
6.1
6.05
6
8
7.5
7
IOUT(A)
1.5
VIN(V)
2.7
3
4.5
6
3.3
4
5
12
16
5.95
5.9
6.5
6
5.85
5.8
5.5
5
5.75
5.7
4.5
-40
2
4
6
8
10
VIN (V)
12
14
16
-20
0
20
40
60
80
100 120 140
TA (C)
Figure 7-2. ON-Resistance vs Supply Voltage (TA = 25°C)
Figure 7-3. ON-Resistance vs Temperature (IOUT = 3 A)
440
77.5
VIN(V)
75
2.7
420
5
12
72.5
16
70
67.5
65
400
VIN(V)
2.7
5
12
16
380
360
340
320
62.5
60
57.5
55
52.5
-40
-20
0
20
40
60
80
100 120 140
-40
-20
0
20
40
60
80
100 120 140
TA(C)
TA(C)
Figure 7-5. IN OFF State (UVLO) Current vs Temperature
Figure 7-4. IN Quiescent Current vs Temperature
3.9
3.6
3.3
3
2.54
2.52
2.5
2.7
2.4
2.1
1.8
1.5
1.2
0.9
0.6
VIN(V)
2.7
2.48
Rising
Falling
5
12
16
2.46
2.44
2.42
2.4
-40
-20
0
20
40
TA (C)
60
80
100 120 140
-40
-20
0
20
40
TA(C)
60
80
100 120 140
Figure 7-7. IN Undervoltage Threshold vs Temperature
Figure 7-6. IN Shutdown Current vs Temperature
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7.8 Typical Characteristics (continued)
1.20195
1.2019
1.20185
1.2018
1.20175
1.2017
1.20165
1.2016
1.20155
1.2015
1.20145
1.2014
1.20135
1.2013
1.09465
1.0946
1.09455
1.0945
1.09445
1.0944
1.09435
1.0943
1.09425
1.0942
1.09415
1.0941
1.09405
VIN(V)
2.7
VIN(V)
2.7
5
5
12
16
12
16
-40
-20
0
20
40
60
80
100 120 140
-40
-20
0
20
40
60
80
100 120 140
TA (C)
TA (C)
Figure 7-8. EN/UVLO Rising Threshold vs Temperature
Figure 7-9. EN/UVLO Falling Threshold vs Temperature
1.20205
1.202
0.8
VIN(V)
0.78
2.7
5
12
16
1.20195
1.2019
1.20185
1.2018
1.20175
1.2017
1.20165
0.76
0.74
0.72
0.7
0.68
0.66
0.64
0.62
0.6
VIN(V)
1.2016
2.7
5
12
16
1.20155
1.2015
1.20145
1.2014
0.58
-40
-20
0
20
40
TA (C)
60
80
100 120 140
-40
-20
0
20
40
60
80
100 120 140
TA (C)
Figure 7-11. OVLO Rising Threshold vs Temperature
Figure 7-10. EN/UVLO Shutdown Falling Threshold vs
Temperature
1.09525
1.0952
1.09515
1.0951
1.09505
1.095
1.09495
1.0949
1.09485
1.0948
1.09475
10.5
9.5
8.5
7.5
6.5
5.5
4.5
3.5
2.5
VIN(V)
1.0947
2.7
5
12
16
1.09465
1.0946
1.09455
1.0945
1.5
-40
-20
0
20
40
60
80
100 120 140
600 900 1200 1500 1800 2100 2400 2700 3000 3300 3600
TA (C)
RILM ()
Figure 7-12. OVLO Falling Threshold vs Temperature
Figure 7-13. Overcurrent Threshold vs ILM Resistor
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7.8 Typical Characteristics (continued)
193.9
193.8
193.7
193.6
193.5
193.4
193.3
193.2
193.1
193
20
15
10
5
Min
Typ
Max
0
-5
VIN(V)
2.7
5
-10
-15
-20
12
16
192.9
-40
-20
0
20
40
TA (C)
60
80
100 120 140
2
3
4
5
6
7
8
9
10
11
ILIM (A)
Figure 7-15. Scalable Fast-Trip Threshold: Current Limit
Threshold (ILIM) Ratio vs Temperature
Figure 7-14. Overcurrent Threshold Accuracy (Across Process,
Voltage and Temperature)
44
18
VIN(V)
2.7
5
Min
Typ
Max
15
12
9
12
16
41
38
35
32
6
3
0
-3
-6
-9
-12
-15
-18
-40
-20
0
20
40
60
80
100 120 140
1
2
3
4
5
6
7
8
9
10
11
TA(C)
IOUT (A)
Figure 7-16. Fixed Fast-Trip Threshold vs Temperature
Figure 7-17. Analog Current Monitor Gain Accuracy
1.522
1.521
2.004
VIN(V)
2.7
2.001
1.998
1.995
1.992
1.989
1.986
1.983
1.98
5
12
16
1.52
1.519
1.518
1.517
1.516
1.515
1.514
1.513
1.512
VIN(V)
2.7
5
12
16
1.977
1.974
-40
-20
0
20
40
60
80
100 120 140
-40
-20
0
20
40
60
80
100 120 140
TA (C)
TA (C)
Figure 7-18. ITIMER Discharge Differential Voltage Threshold vs
Temperature
Figure 7-19. ITIMER Discharge Current vs Temperature
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7.8 Typical Characteristics (continued)
2.64
2.61
2.58
2.55
2.52
2.49
2.46
2.43
2.4
3.8
3.75
3.7
3.65
3.6
3.55
3.5
3.45
3.4
3.35
3.3
3.25
3.2
3.15
3.1
VIN(V)
2.7
5
12
16
VIN(V)
2.7
5
12
16
2.37
-40
-20
0
20
40
60
80
100 120 140
-40
-20
0
20
40
60
80
100 120 140
TA (C)
TA (C)
Figure 7-20. ITIMER Internal Pullup Voltage vs Temperature
Figure 7-21. DVDT Charging Current vs Temperature
0.84
17
IPG(A)
VIN(V)
2.7
16.5
16
15.5
15
14.5
14
13.5
13
12.5
12
11.5
11
10.5
10
0.81
26
242
12
16
0.78
0.75
0.72
0.69
0.66
0.63
0.6
0.57
0.54
-40
-20
0
20
40
60
80
100 120 140
-40
-20
0
20
40
60
80
100 120 140
TA (C)
TA (C)
Figure 7-22. PG Pin Voltage vs Temperature (VIN = 0 V)
Figure 7-23. FLT Pin Pulldown Resistance vs Temperature
0.06
502
500
498
496
494
492
490
VIN(V)
0.055
2.7
12
16
0.05
0.045
0.04
0.035
0.03
0.025
0.02
0.015
0.01
0.005
0
488
486
484
482
VIN(V)
2.7
5
12
16
-40
-20
0
20
40
TA (C)
60
80
100 120 140
-40
-20
0
20
40
60
80
100 120 140
TA (C)
Figure 7-24. FLT Pin Leakage Current vs Temperature
Figure 7-25. Quick Output Discharge Resistance vs
Temperature
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7.8 Typical Characteristics (continued)
10000
5000
2000
1000
500
200
100
50
20
10
5
2
1
0.5
0.2
0.1
0
20
40
60
80
100
120
140
PD (W)
Figure 7-26. Time to Thermal Shutdown During Inrush State
Figure 7-27. Time to Thermal Shutdown During Steady-State
VEN/UVLO = 3.3 V, COUT = 10 μF, CdVdt = Open, VIN ramped up
to 12 V
VIN = 12 V, COUT = 10 μF, CdVdt = Open, VEN/UVLO stepped up
to 3.3 V
Figure 7-29. Start-Up with Supply
Figure 7-28. Start-Up with Enable
VIN = 12 V, COUT = 220 μF, CdVdt = 3300 pF, VEN/UVLO stepped
up to 1.4 V
COUT = 220 μF, CdVdt = 15 nF, EN/UVLO connected to IN
through resistor ladder, 12 V hot-plugged to IN
Figure 7-31. Inrush Current with Capacitive Load
Figure 7-30. Input Hot-Plug
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7.8 Typical Characteristics (continued)
VIN = 12 V, COUT = 220 μF, ROUT = 5 Ω, CdVdt = 3300 pF,
VEN/UVLO stepped up to 1.4 V
VIN Overvoltage threshold set to 13.6 V using resistor ladder
connected to OVLO pin, VIN ramped up from 12 V to 16 V
Figure 7-32. Inrush Current with Resistive and Capacitive Load
Figure 7-33. Overvoltage Lockout Response
VIN = 12 V, CITIMER = 1.5 nF, RILM = 649 Ω, IOUT ramped from
8 A → 14 A→ 8 A within 1 ms
VIN = 12 V, CITIMER = 1.5 nF, RILM = 649 Ω, IOUT ramped from
4 A → 13 A
Figure 7-34. Transient Overcurrent Blanking Timer Response
Figure 7-35. Circuit-Breaker Response
VIN = 12 V, RILM = 649 Ω, OUT stepped from Open → Short-
circuit to GND
VIN = 12 V, RILM = 649 Ω, OUT stepped from Open → Short-
circuit to GND
Figure 7-36. Output Short-Circuit During Steady-State
Figure 7-37. Output Short-Circuit During Steady-State (Zoomed
In)
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7.8 Typical Characteristics (continued)
VIN = 12 V, OUT short-circuit to GND, RILM = 649 Ω, VEN/UVLO stepped from 0 V to 3.3 V
Figure 7-38. Power Up into Short Circuit
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8 Detailed Description
8.1 Overview
The TPS25981xx is an eFuse with integrated power path that is used to ensure safe power delivery in a system.
The device starts its operation by monitoring the IN bus. When the input supply voltage (VIN) exceeds the
Undervoltage Protection threshold (VUVP), the device samples the EN/UVLO pin. A high level (> VUVLO) on this
pin enables the internal power path to start conducting and allow current to flow from IN to OUT. When EN/UVLO
is held low (< VUVLO), the internal power path is turned off.
After a successful start-up sequence, the device now actively monitors its load current and input voltage,
and controls the internal FET to ensure that the user adjustable overcurrent protection threshold (ILIM) is not
exceeded and overvoltage spikes are cut-off after they cross the user adjustable overvoltage lockout threshold
(VOVLO). The device also provides fast protection against severe overcurrent during short-circuit events. This
feature keeps the system safe from harmful levels of voltage and current. At the same time, a user adjustable
overcurrent blanking timer allows the system to pass moderate transient peaks in the load current profile without
tripping the eFuse. This feature ensures a robust protection solution against real faults which is also immune to
transients, thereby ensuring maximum system uptime.
The device also has a built-in thermal sensor based shutdown mechanism to protect itself in case the device
temperature (TJ) exceeds the recommended operating conditions.
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8.2 Functional Block Diagram
FFT
TPS25981xx
229 mV
Temp Sense and
Overtemperature
protection
TSD
5
IN
6
7
OUT
*
INRUSH_DONE
DVDT
CP
3.4
A
2.8 V
UVLOb
+
UVPb
2.53 V
2.42 V
-
95.3 A/A
FFT
GHI
GHI
-
2x
1x
-
SC
OC
2
EN/OVLO
EN/UVLO
OVLOb
UVLOb
HFET Control
Current Limit Amplifier
1.20 V
1.09 V
+
-
+
+
1
+
9
ILM
1.20 V
1.09 V
-
SWEN
Short
Detect
-
SD
ILM Pin Short
+
0.75 V
RETRY#
2.57 V
1.06 V
+
SD
UVPb
R
S
/Q
Q
RETRY#
105 ms
TIMER#
GHI
ITIMER_EXPIRED
TSD
FLT
10
ITIMER
-
ILM Pin Short
ITIMER_EXPIRED
OC
GHI
2
A
8
GND
4
3
PG
FLT
# Not applicable to TPS25981xL (Latch-off) variants
* Not applicable for TPS259813x variants
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8.3 Feature Description
The TPS25981xx eFuse is a compact, feature rich power management device that provides detection, protection
and indication in the event of system faults.
8.3.1 Undervoltage Lockout (UVLO and UVP)
The TPS25981xx implements undervoltage protection on IN in case the applied voltage becomes too low for the
system or device to properly operate. The undervoltage protection has a default lockout threshold of VUVP which
is fixed internally. Also, the UVLO comparator on the EN/UVLO pin allows the undervoltage protection threshold
to be externally adjusted to a user defined value. Figure 8-1 and Equation 1 show how a resistor divider can be
used to set the UVLO set point for a given voltage supply.
Power
Supply
IN
R1
EN/UVLO
R2
GND
Figure 8-1. Adjustable Undervoltage Protection
V
× R + R
1 2
UVLO
V
=
(1)
IN UV
R
2
8.3.2 Overvoltage Lockout (OVLO)
The TPS259814x devices allow the user to implement overvoltage lockout to protect the load from input
overvoltage conditions. The OVLO comparator on the EN/OVLO pin allows the overvoltage protection threshold
to be adjusted to a user defined value. After the voltage at the EN/OVLO pin crosses the OVLO rising threshold
VOV(R), the device turns off the power to the output. Thereafter, the devices wait for the voltage at the EN/OVLO
pin to fall below the OVLO falling threshold VOV(F) before the output power is turned ON again. The rising and
falling thresholds are slightly different to provide hysteresis. Figure 8-2 and Equation 2 show how a resistor
divider can be used to set the OVLO set point for a given voltage supply.
Power
Supply
IN
R1
EN/OVLO
R2
GND
Figure 8-2. Adjustable Overvoltage Protection
V
× R + R
1 2
OV
V
=
(2)
IN OV
R
2
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Input Overvoltage Event
Input Overvoltage Removed
IN
0
VOV(R)
VOV(F)
EN/OVLO
tOVLO
0
OUT
FLT
PG
dVdt Limited Start-up
0
VFLT
0
VPG
0
Time
Figure 8-3. TPS259814x Overvoltage Lockout and Recovery
While recovering from a OVLO event, the TPS259814x variants start up with inrush control (dVdt).
8.3.3 Inrush Current, Overcurrent, and Short-Circuit Protection
TPS25981xx incorporates four levels of protection against overcurrent:
1. Adjustable slew rate (dVdt) for inrush current control
2. Adjustable threshold (ILIM) for overcurrent protection during start-up or steady-state
3. Adjustable threshold (ISC) for fast-trip response to severe overcurrent during start-up or steady-state
4. Fixed threshold (IFT) for fast-trip response to quickly protect against hard output short circuits during steady-
state
8.3.3.1 Slew Rate (dVdt) and Inrush Current Control
During hot-plug events or while trying to charge a large output capacitance at start-up, there can be a large
inrush current. If the inrush current is not managed properly, it can damage the input connectors and cause the
system power supply to droop leading to unexpected restarts elsewhere in the system. The inrush current during
turn-on is directly proportional to the load capacitance and rising slew rate. Equation 3 can be used to find the
slew rate (SR) required to limit the inrush current (IINRUSH) for a given load capacitance (COUT):
I
mA
V
ms
INRUSH
SR
=
(3)
C
µF
OUT
A capacitor can be connected to the dVdt pin to control the rising slew rate and lower the inrush current during
turn on. Use Equation 4 to calculate the required CdVdt capacitance to produce a given slew rate.
3300
C
pF =
(4)
dVdt
V
SR
ms
The fastest output slew rate is achieved by leaving the dVdt pin open.
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Note
For CdVdt > 10 nF, TI recommends to add a 100-Ω resistor in series with the capacitor on the dVdt pin.
8.3.3.2 Circuit-Breaker During Steady-State
The TPS259814x (circuit-breaker) variants respond to output overcurrent conditions by turning off the output
after a user adjustable transient fault blanking interval. When the load current exceeds the set overcurrent
threshold (ILIM) set by the ILM pin resistor (RILM), but stays lower than the fast-trip threshold (2 × ILIM), the device
starts discharging the ITIMER pin capacitor using an internal 2-μA pulldown current. If the load current drops
below ILIM before the ITIMER pin capacitor (CITIMER) discharges by ΔVITIMER, the ITIMER is reset by pulling it up
to VINT internally and the circuit-breaker action is not engaged. This action allows short load transient pulses to
pass through the device without tripping the circuit. If the overcurrent condition persists, the CITIMER continues
to discharge and after it discharges by ΔVITIMER, the circuit-breaker action turns off the FET immediately. At the
same time, the CITIMER is charged up to VINT again so that it is at its default state before the next overcurrent
event. This action ensures the full blanking timer interval is provided for every overcurrent event. Equation 5 can
be used to calculate the RILM value for a overcurrent threshold.
6585
R
Ω =
(5)
ILM
I
A
LIM
Note
1. Leaving the ILM pin open sets the current limit to nearly zero and results in the part breaking the
circuit with the slightest amount of loading at the output.
2. Shorting the ILM pin to ground at any point during normal operation is detected as a fault and the
part shuts down. There is a minimum current (IFLT) which the part allows in this condition before
the pin short condition is detected.
The duration for which transients are allowed can be adjusted using an appropriate capacitor value from ITIMER
pin to ground. Use Equation 6 to calculate the CITIMER value needed to set the desired transient overcurrent
blanking interval.
t
ms × I
µA
ITIMER
ITIMER
V
C
nF =
(6)
ITIMER
ΔV
ITIMER
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Transient Overcurrent
Persistent Output Overload
ITIMER expired
2 × ILIM
Circuit-Breaker
operation
IOUT
ILIM
0
tITIMER
VINT
∆VITIMER
ITIMER
0
VIN
OUT
0
VFLT
FLT
PG
TJ
0
tPGD
VPG
0
TSD
TSDHYS
TJ
Time
Figure 8-4. TPS259814x Overcurrent Response
Note
1. Leave the ITIMER pin open to allow the part to break the circuit with the minimum possible delay.
2. Shorting the ITIMER pin to ground results in minimum overcurrent response delay (similar to
ITIMER pin open condition), but increases the device current consumption. This action is not a
recommended mode of operation.
3. Increasing the ITIMER cap value extends the overcurrent blanking interval, but it also extends the
time needed for the CITIMER to recharge up to VINT. If the next overcurrent event occurs before the
CITIMER is recharged fully, it takes lesser time to discharge to the ITIMER expiry threshold, thereby
providing a shorter blanking interval than intended.
4. In low voltage applications, TI recommends adding a 30 kΩ resistor between the ITIMER pin and
CITIMER for improved immunity to supply noise or fluctuations.
After the part shuts down due to a circuit-breaker fault, it either stays latched off (TPS259814L variant) or
restarts automatically after a fixed delay (TPS259814A variant).
8.3.3.3 Active Current Limiting During Start-Up
The TPS259814x devices respond to output overcurrent conditions during start-up by actively limiting the
current. If the load current exceeds the set overcurrent threshold (ILIM) set by the ILM pin resistor (RILM), but
stays lower than the short-circuit threshold (2 × ILIM), the current limit loop starts regulating the FET to actively
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limit the current to the set overcurrent threshold (ILIM). Equation 7 can be used to calculate the RILM value for a
desired overcurrent threshold.
6585
R
Ω =
(7)
ILM
I
A
LIM
Note
1. Leaving the ILM pin open sets the current limit to nearly zero and results in the part entering
current limit with the slightest amount of loading at the output.
2. The current limit circuit employs a foldback mechanism. The current limit threshold in the foldback
region (0 V < VOUT < VFB) is lower than the target steady-state overcurrent threshold (ILIM).
During active current limit, the output voltage drops, resulting in increased device power dissipation across
the FET. If the device internal temperature (TJ) exceeds the thermal shutdown threshold (TSD), the FET
is turned off. After the part shuts down due to TSD fault, it either stays latched off (TPS25981xL variants)
or restarts automatically after a fixed delay (TPS25981xA variants). For more details on device response to
overtemperature, see Overtemperature Protection (OTP).
8.3.3.4 Short-Circuit Protection
During an output short-circuit event, the current through the device increases very rapidly. When a severe
overcurrent condition is detected, the device triggers a fast-trip response to limit the current to a safe level. The
internal fast-trip comparator employs a scalable threshold (ISC) which is equal to 2 × ILIM. This action enables
the user to adjust the fast-trip threshold rather than using a fixed threshold which can be too high for some
low current systems. The device also employs a fixed fast-trip threshold (IFT) to protect fast protection against
hard short circuits during steady-state. The fixed fast-trip threshold is higher than the maximum recommended
user adjustable scalable fast-trip threshold. After the current exceeds ISC or IFT, the FET is turned off completely
within tFT. Thereafter, the devices tries to turn the FET back on after a short de-glitch interval (30 μs) in a current
limited manner instead of a dVdt limited manner. This action ensures that the FET has a faster recovery after a
transient overcurrent event and minimizes the output voltage droop. However, if the fault is persistent, the device
stays in current limit causing the junction temperature to rise and eventually enter thermal shutdown. For details
on the device response to overtemperature, see Overtemperature Protection (OTP).
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Persistent Severe Overcurrent
Thermal Shutdown
Overcurrent Removed
Retry Timer Elapsed (1)
Transient Severe Overcurrent
Output Hard Short-circuit to ground
Thermal Shutdown
Short-circuit Removed
Retry Timer Elapsed (1)
VIN
IN
0
tFT
tSC
tSC
IFT
2 × ILIM
IOUT
ILIM
0
VIN
OUT
dVdt Limited
Start-up
dVdt Limited
Start-up
Current Limited
Start-up
0
VPG
PG
0
VFLT
FLT
0
tRST
tRST
TSD
TSDHYS
TJ
Time
(1) Applicable only to TPS259814A (Auto-retry variant)
Figure 8-5. TPS25981xx Short-Circuit Response
8.3.4 Analog Load Current Monitor
The device allows the system to accurately monitor the output load current by providing an analog current sense
output on the ILM pin which is proportional to the current through the FET. The user can sense the voltage (VILM
across the RILM to get a measure of the output load current.
)
V
µV
ILM
µA/A × R
I
A =
(8)
LOAD
G
Ω
ILM
IMON
The waveform below shows the ILM signal response to a load step at the output.
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VIN = 12 V, RILM = 649 Ω, IOUT varied dynamically between 8 A and 14 A
Figure 8-6. Analog Load Current Monitor Response
Note
The ILM pin is sensitive to capacitive loading. Careful design and layout is needed to ensure the
parasitic capacitive loading on the ILM pin is < 50 pF for stable operation.
8.3.5 Overtemperature Protection (OTP)
The device monitors the internal die temperature (TJ) at all times and shuts down the part as soon as the
temperature exceeds a safe operating level (TSD) thereby protecting the device from damage. The device does
turn back on until the junction cools down sufficiently, that is the die temperature falls below (TSD – TSDHYS).
When the TPS25981xL (latch-off variant) detects thermal overload, it is shut down and remains latched-off until
the device is power cycled or re-enabled. When the TPS25981xA (auto-retry variant) detects thermal overload, it
remains off until it has cooled down by TSDHYS. Thereafter, the device remains off for an additional delay of tRST
after which it automatically retries to turn on if it is still enabled.
Table 8-1. Thermal Shutdown
Device
Enter TSD
Exit TSD
TJ < TSD – TSDHYS
VIN cycled to 0 V and then above VUVP(R) or
TPS25981xL (latch-off)
TJ ≥ TSD
TJ ≥ TSD
EN/UVLO toggled below VSD(F)
TJ < TSD – TSDHYS
VIN cycled to 0 V and then above VUVP(R) or
TPS25981xA (auto-retry)
EN/UVLO toggled below VSD(F) or tRST timer
expired
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8.3.6 Fault Response and Indication (FLT)
The following table summarizes the device response to various fault conditions. Additionally, an active low
external fault indication (FLT) pin is available.
Table 8-2. Fault Summary
Event
Protection Response
Fault Latched Internally
FLT Pin Status
FLT Assertion Delay
Overtemperature
Shutdown
Y
L
Undervoltage (UVP or
UVLO)
Shutdown
Shutdown
None
N
N
N
Y
N
H
H
Input overvoltage
Transient overcurrent (ILIM
N
< IOUT < 2 × ILIM
)
Persistent overcurrent
Circuit-breaker
N/A
H
Output short circuit to
GND
Circuit-breaker followed by
current limit
ILM pin open
(during steady-state)
Shutdown
Shutdown
N
Y
L
L
tITIMER
tITIMER
ILM pin shorted to GND
Faults which are latched internally can be cleared either by power cycling the part (pulling VIN to 0 V) or by
pulling the EN/UVLO pin voltage below VSD. This action also releases the FLT pin and resets the tRST timer for
the TPS25981xA (auto-retry) variants.
During a latched fault, pulling the EN/UVLO just below the UVLO threshold has no impact on the device. This
fact is true for both TPS25981xL (latch-off) and TPS25981xA (auto-retry) variants.
For TPS25981xA (auto-retry) variants, on expiry of the tRSTtimer after a fault, the device restarts automatically
and the FLT pin is de-asserted.
8.3.7 Power Good Indication (PG)
The TPS259814x provides an active high digital output (PG) which serves as a power good indication signal and
is asserted high when the device is in steady-state and ready to deliver power. The PG is an open-drain pin and
must be pulled up to an external supply.
After power up, PG is pulled low initially. The device initiates a inrush sequence in which the FET is turned on in
a controlled manner. When the FET gate voltage reaches the full overdrive indicating that the inrush sequence is
complete, the PG is asserted after a de-glitch time (tPGA).
PG is de-asserted if at any time the FET is turned off. The PG de-assertion de-glitch time is tPGD
.
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Device Enabled
VUVLO(R)
0
EN/UVLO
IN
Slew rate (dVdt) controlled
startup/Inrush current limiting
0
VIN
OUT
0
VPG
0
PG
tPGA
VIN
dVdt (1)
0
VIN
dVdt (2)
0
VOUT + 2.8 V
VHGate
0
ILIM
IINRUSH
IOUT
0
Time
(1) Applicable only for TPS259814x variants
(2) Applicable only for TPS259813x variants
Figure 8-7. TPS25981xx PG Timing Diagram
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Table 8-3. TPS25981xx PG Indication Summary
Event
Protection Response
PG Pin
PG Delay
Undervoltage (UVP or UVLO)
Overvoltage (OVLO)
Steady-state
Shutdown
L
L
H
H
L
L
L
L
L
Shutdown
tPGD
tPGA
NA
Transient overcurrent
Persistent overload
Output short-circuit to GND
ILM pin open
NA
Circuit-breaker
Fast-trip followed by current limit
Shutdown
tITIMER + tPGD
tPGD
tITIMER + tPGD
tPGD
ILM pin shorted to GND
Overtemperature
Shutdown
Shutdown
tPGD
When there is no supply to the device, the PG pin is expected to stay low. However, there is no active pulldown
in this condition to drive this pin all the way down to 0 V. If the PG pin is pulled up to an independent supply
which is present even if the device is unpowered, there can be a small voltage seen on this pin depending on the
pin sink current, which is a function of the pullup supply voltage and resistor. Minimize the sink current to keep
this pin voltage low enough not to be detected as a logic HIGH by associated external circuits in this condition.
8.3.8 Quick Output Discharge (QOD)
The TPS25981xx has an integrated output discharge function which can be helpful in quickly removing residual
charge left on the large output capacitors and avoids bus floating at some undefined voltage. The internal QOD
pulldown FET on the OUT pin is activated when the EN/UVLO is held low (VEN < VUVLO(F)). The output discharge
function can result in excess power dissipation inside the device leading to increase in junction temperature. The
output discharge is disabled if the junction temperature (TJ) crosses the thermal shutdown threshold (TSD) to
avoid long term degradation of the part.
8.3.9 Reverse Current Blocking FET Driver
The TPS259813x variants provide an option to drive an external N-FET for implementing reverse current
blocking function. The N-FET is connected in series with the eFuse in a common source configuration as shown
in Figure 8-8. The gate of the blocking FET is controlled by the DVDT pin of the eFuse. When the eFuse is
turned ON and operating in steady-state, the DVDT pin is driven high which turns the external FET fully ON to
provide a low impedance power path from input to output. When the eFuse turns OFF under any condition, the
DVDT pin is pulled low and the blocking FET is turned OFF. This ensures there's no current path from the output
to input in the OFF state.
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VIN = 2.7 to 16 V
VOUT
IN
OUT
COUT
PG
EN/UVLO
TPS259813x
FLT
EN/OVLO
dVdt
ITIMER
GND
ILM
CITIMER
CDVDT
RILM
Figure 8-8. Reverse Current Blocking Using External FET
8.4 Device Functional Modes
The device has one mode of operation that applies when operated within the Recommended Operating
Conditions.
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
The TPS25981xx is a 2.7-V to 16-V, 10-A eFuse that is typically used for power rail protection applications.
The device operates from 2.7 V to 16 V with adjustable overvoltage and undervoltage protection. The device
provides ability to control inrush current. The device can be used in a variety of systems such as server
motherboard/add-on cards/NIC, optical modules, enterprise switches/routers, Industrial PC, UHDTV. The design
procedure explained in the subsequent sections can be used to select the supporting component values based
on the application requirement. Additionally, a spreadsheet design tool, TPS25981xx Design Calculator, is
available in the web product folder.
9.1.1 Single Device, Self-Controlled
VOUT
VIN = 2.7 to 16 V
IN
OUT
VLOGIC
COUT
EN/UVLO
TPS259814x
PG
EN/OVLO
ITIMER dVdt
FLT
ILM
GND
RILM
CITIMER
CDVDT
Figure 9-1. Single Device, Self-Controlled
Other variations:
In a Host MCU controlled system, EN/UVLO or OVLO can also be driven from the host GPIO to control the
device.
ILM pin can be connected to the MCU ADC input for current monitoring purpose.
Note
TI recommends to keep parasitic capacitance on the ILM pin below 50 pF to ensure stable operation.
9.1.2 Parallel Operation
Applications which need higher steady current can use two TPS25981xx devices connected in parallel as shown
in Figure 9-2 below. In this configuration, the first device turns on initially to provide the inrush current limiting.
The second device is held in an OFF state by driving its EN/UVLO pin low using the PG signal of the first device.
After the inrush sequence is complete, the first device asserts its PG pin high and turns on the second device.
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The second device asserts its PG signal to indicate when it has turned on fully, thereby indicating to the system
that the parallel combination is ready to deliver the full steady-state current.
Once in steady-state, both devices share current nearly equally. There can be a slight skew in the currents
depending on the part-to-part variation in the RON as well as the PCB trace resistance mismatch.
IN
OUT
VLOGIC
EN/UVLO
EN/OVLO
TPS259814x
PG
FLT
ITIMER dVdt
GND
ILM
VOUT
VIN = 2.7 to 16 V
COUT
IN
OUT
To
downstream
enable
EN/UVLO
EN/OVLO
PG
TPS259814x
dVdt
FLT
ITIMER
ILM
GND
Figure 9-2. Two TPS259814x Devices Connected in Parallel for Higher Steady-State Current Capability
The waveforms below illustrate the behavior of the parallel configuration during start-up as well as during
steady-state.
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Figure 9-3. Parallel Devices Sequencing During Start-Up
Figure 9-4. Parallel Devices Load Current During Steady-State
Figure 9-5. Parallel Devices Overcurrent Response
Another way to increase current handling capability of the eFuse in steady-state is by connecting a TPS25981xx
eFuse in parallel with a TPS22811x load switch as shown in Figure 9-6.
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IN
OUT
VLOGIC
EN/UVLO
TPS259814x
PG
EN/OVLO
ITIMER dVdt
To system MCU
FLT
GND
ILM
VOUT
VIN = 2.7 to 16 V
RILM
COUT
IN
OUT
IMON
PGTH
EN/UVLO
TPS22811x
To downstream enable
EN/OVLO
PG
GND
Figure 9-6. TPS259814x and TPS22811x Connected in Parallel for Higher Steady-State Current Capability
9.2 Typical Application
TPS259814x can be used for optical module power rail protection. Optical modules are commonly used in high-
bandwidth data communication systems such as optical networking equipment, enterprise/data-center switches
and routers. Several variants of optical modules are available in the market, which differ in the form-factor and
the data speed support (Gbit/s). Of these, the popular variant double dense quad small form-factor pluggable
(QSFP-DD) module supports speeds up to 400 Gbit/s. In addition to the system protection during hot-plug
events, the other key requirement for optical module is the tight voltage regulation. The optical module uses
3.3-V supply and requires voltage regulation within ±5% for proper operation.
A typical power tree of such system is shown in Figure 9-7. The optical line card consists of DC-DC converter,
protection device (eFuse) and power supply filters. The DC-DC converter steps-down the 12 V to 3.3 V and
maintains the 3.3-V rail within ±2 %. The power supply filtering network uses ‘LC’ components to reduce high
frequency noise injection into the optical module. The DC resistance of the inductor ‘L’ causes voltage drop
of around 1.5% which leaves us with a voltage drop budget of just 1.5% (3.3 V × 1.5% = 50 mV) across the
protection device. Considering a maximum load current of 5.5 A per module, the maximum ON-resistance of
the protection device must be less than 9 mΩ. TPS259814x eFuse offers a very low ON-resistance of 6 mΩ
(typical), thereby meeting the target specification with additional margin to spare and simplifying the overall
system design.
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VIN
12V
3.3V
VOUT
IN
OUT
VccTx
VccRx
DC-DC
eFuse
OVLO
QSFP
Hot Plug / Unplug
Module
Vcc
GND
ModPrsL
Optical Line Card
Figure 9-7. Power Tree Block Diagram of a Typical Optical Line Card
As shown in Figure 9-7, ModPrsL signal acts as a handshake signal between the line card and the optical
module. ModPrsL is always pulled to ground inside the module. When the module is hot-plugged into the host
“Optical Line Card” connector, the ModPrsL signal pulls down the OVLO pin and enables the TPS259814x
eFuse to power the module. This action ensures that power is applied on the port only when a module is plugged
in and disconnected when there is no module present.
VOUT
VIN = 3.3 V
IN
OUT
47 kꢁ
10 ꢀF
1 ꢀF
D2*
EN
EN/UVLO
PG
TPS259814x
3.3 V
CIN
47 kꢁ
1 ꢀF
47 kꢁ
FLT
ModPrsL
EN/OVLO
ILM
ITIMER dVdt
GND
RILM
CITIMER
6.8 nF
CdVdt
1 kꢁ
2200 pF
* Optional circuit components needed for transient protection depending on input and output inductance. Please
refer to Transient Protection section for details.
Figure 9-8. Optical Module Port Protection
9.2.1 Design Requirements
Table 9-1. Design Parameters
PARAMETER
VALUE
Input supply voltage (VIN)
3.3 V
± 5%
5.5 A
Maximum voltage drop in the path
Maximum continuous current
Load transient blanking interval (tITIMER
)
5 ms
Output capacitance (COUT
)
10 μF
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Table 9-1. Design Parameters (continued)
PARAMETER
VALUE
Output rise time (tR)
Overcurrent threshold (ILIM
Fault response
2.2 ms
)
6.5 A
Auto-retry
9.2.2 Detailed Design Procedure
9.2.2.1 Device Selection
Because the application requires retry response after a fault, the TPS259814A variant is selected after referring
to the Device Comparison Table.
9.2.2.2 Setting Output Voltage Rise Time (tR)
For a successful design, the junction temperature of device must be kept below the absolute maximum rating
during both dynamic (start-up) and steady-state conditions. Dynamic power stresses often are an order of
magnitude greater than the static stresses, so it is important to determine the right start-up time and inrush
current limit required with system capacitance to avoid thermal shutdown during start-up.
The slew rate (SR) needed to achieve the desired output rise time can be calculated as:
V
t
V
V
ms
IN
3.3 V
2.2 ms
V
ms
SR
=
=
= 1.5
(9)
ms
R
The CdVdt needed to achieve this slew rate can be calculated as:
3300
3300
C
pF =
=
= 2200 pF
(10)
dVdt
V
V
SR
1.5
ms
ms
Choose the nearest standard capacitor value as 2200 pF.
For this slew rate, the inrush current can be calculated as:
V
ms
V
ms
I
mA = C
µF × SR
= 10 µF × 1.5
= 15 mA
(11)
(12)
INRUSH
OUT
The average power dissipation inside the part during inrush can be calculated as:
PD
mW = 0.5 × V
V
× I
mA = 0.5 × 3.3 V × 15 mA = 25 mW
INRUSH
IN
INRUSH
For the given power dissipation, the thermal shutdown time of the device must be greater than the ramp-up time
tR to avoid start-up failure. Figure 9-9 shows the thermal shutdown limit, for 0.025 W of power, the shutdown time
is more than 10 s which is very large as compared to tR = 2.2 ms. Therefore, it is safe to use 2.2 ms as the
start-up time for this application.
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20000
10000
1000
100
10
1
0.1
0
20
40
60
80
100
120
140
Power Dissipation (W)
Figure 9-9. Thermal Shutdown Plot During Inrush
9.2.2.3 Setting Overcurrent Threshold (ILIM
)
The overcurrent protection (circuit-breaker) threshold can be set using the RILM resistor whose value can be
calculated as:
6585
6585
R
Ω =
=
= 1013 Ω
6.5 A
(13)
ILM
I
A
LIM
Choose the nearest 1% standard resistor value as 1 kΩ.
9.2.2.4 Setting Overcurrent Blanking Interval (tITIMER
The overcurrent blanking timer interval can be set using the CITIMER capacitor whose value can be calculated as:
)
t
ms × I
µA
5 ms × 2 µA
= 6.62 nF
1.51 V
ITIMER
ITIMER
V
C
nF =
=
(14)
ITIMER
ΔV
ITIMER
Choose the nearest standard capacitor value as 6.8 nF.
9.2.2.5 Voltage Drop
Table 9-2 shows the power path voltage drop (%) due to the eFuse in QSFP modules of different power classes.
Table 9-2. Voltage Drop Across TPS25981 on QSFP Module Power Rail
MAXIMUM POWER
POWER CLASS
CONSUMPTION PER MODULE MAXIMUM LOAD CURRENT (A) TYPICAL VOLTAGE DROP (%)
(W)
1
2
3
4
5
6
7
8
1.5
3.5
7
0.454
1.06
2.12
2.42
3.03
3.63
4.24
5.45
0.082
0.192
0.385
0.440
0.551
0.660
0.771
0.991
8
10
12
14
18
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9.2.3 Application Curves
Figure 9-10. Output Voltage Profile When Optical
Module is Inserted
Figure 9-11. Output Voltage Profile When Optical
Module is Plugged Out
Figure 9-12. Circuit-Breaker with Transient
Overcurrent Blanking Interval of 5 ms; Device
Restarts in Current Limit Mode
Figure 9-13. Overload Response and Recovery
Figure 9-14. Output Hard Short Circuit While ON
Figure 9-15. Power Up with Short Circuit on Output
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10 Power Supply Recommendations
The TPS25981xx devices are designed for a supply voltage range of 2.7 V ≤ VIN ≤ 16 V. TI recommends an
input ceramic bypass capacitor higher than 0.1 μF if the input supply is located more than a few inches from
the device. The power supply must be rated higher than the set current limit to avoid voltage droops during
overcurrent and short-circuit conditions.
10.1 Transient Protection
In the case of a short-circuit and overload current limit when the device interrupts current flow, the input
inductance generates a positive voltage spike on the input, and the output inductance generates a negative
voltage spike on the output. The peak amplitude of voltage spikes (transients) is dependent on the value of
inductance in series to the input or output of the device. Such transients can exceed the absolute maximum
ratings of the device if steps are not taken to address the issue. Typical methods for addressing transients
include:
•
•
•
•
•
Minimize lead length and inductance into and out of the device.
Use a large PCB GND plane.
Connect a Schottky diode from the OUT pin ground to absorb negative spikes.
Connect a low ESR capacitor larger than 1 μF at the OUT pin very close to the device.
Use a low-value ceramic capacitor CIN = 1 μF to absorb the energy and dampen the transients. The capacitor
voltage rating must be at least twice the input supply voltage to be able to withstand the positive voltage
excursion during inductive ringing.
Use Equation 15 to estimate the approximate value of input capacitance:
L
IN
V
= V + I
×
(15)
SPIKE Absolute
IN
LOAD
C
IN
where
– VIN is the nominal supply voltage.
– ILOAD is the load current.
– LIN equals the effective inductance seen looking into the source.
– CIN is the capacitance present at the input.
•
Some applications can require the addition of a Transient Voltage Suppressor (TVS) to prevent transients
from exceeding the absolute maximum ratings of the device. In some cases, even if the maximum amplitude
of the transients is below the absolute maximum rating of the device, a TVS can help to absorb the excessive
energy dump and prevent it from creating very fast transient voltages on the input supply pin of the IC, which
can couple to the internal control circuits and cause unexpected behavior.
Figure 10-1 shows the circuit implementation with optional protection components.
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VOUT
VIN = 2.7 to 16 V
IN
OUT
R1
COUT
CLOAD
D2
EN/UVLO
TPS25981x
R2
CIN
PG
D1
EN/OVLO
ITIMER
FLT
dVdt
GND
ILM
R3
RILM
CITIMER
CDVDT
Figure 10-1. Circuit Implementation with Optional Protection Components
10.2 Output Short-Circuit Measurements
It is difficult to obtain repeatable and similar short-circuit testing results. The following contribute to variation in
results:
•
•
•
•
•
•
•
Source bypassing
Input leads
Circuit layout
Component selection
Output shorting method
Relative location of the short
Instrumentation
The actual short exhibits a certain degree of randomness because it microscopically bounces and arcs. Ensure
that configuration and methods are used to obtain realistic results. Do not expect to see waveforms exactly like
those in this data sheet because every setup is different.
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11 Layout
11.1 Layout Guidelines
•
For all applications, TI recommends a ceramic decoupling capacitor of 0.1 μF or greater between the IN
terminal and GND terminal.
•
The optimal placement of the decoupling capacitor is closest to the IN and GND terminals of the device. Care
must be taken to minimize the loop area formed by the bypass-capacitor connection, the IN terminal, and the
GND terminal of the IC.
•
•
High current-carrying power-path connections must be as short as possible and must be sized to carry at
least twice the full-load current.
The GND terminal must be tied to the PCB ground plane at the terminal of the IC with the shortest possible
trace. The PCB ground must be a copper plane or island on the board. TI recommends to have a separate
ground plane island for the eFuse. This plane does not carry any high currents and serves as a quiet ground
reference for all the critical analog signals of the eFuse. The device ground plane must be connected to the
system power ground plane using a star connection.
•
•
The IN and OUT pins are used for heat dissipation. Connect to as much copper area on top and bottom
PCB layers using as possible with thermal vias. The vias under the device also help to minimize the voltage
gradient across the IN and OUT pads and distribute current uniformly through the device, which is essential
to achieve the best on-resistance and current sense accuracy.
Locate the following support components close to their connection pins:
– RILM
– CdVdT
– CITIMER
– Resistors for the EN/UVLO, EN/OVLO pins
•
Connect the other end of the component to the GND pin of the device with shortest trace length. The trace
routing for the RILM, CITIMER and CdVdt components to the device must be as short as possible to reduce
parasitic effects on the current limit , overcurrent blanking interval and soft start timing. TI recommends to
keep parasitic capacitance on ILM pin below 50 pF to ensure stable operation. These traces must not have
any coupling to switching signals on the board.
•
•
Because the bias current on ILM pin directly controls the overcurrent protection behavior of the device, the
PCB routing of this node must be kept away from any noisy (switching) signals.
Protection devices such as TVS, snubbers, capacitors, or diodes must be placed physically close to the
device they are intended to protect. These protection devices must be routed with short traces to reduce
inductance. For example, TI recommends a protection Schottky diode to address negative transients due to
switching of inductive loads. TI also recommends to add a ceramic decoupling capacitor of 1 μF or greater
between OUT and GND. These components must be physically close to the OUT pins. Care must be taken
to minimize the loop area formed by the Schottky diode, bypass-capacitor connection, the OUT pin, and the
GND terminal of the IC.
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11.2 Layout Example
Inner GND layer
Top Power layer
Bottom Power layer
6
5
OUT
IN
OUT
IN
Figure 11-1. Layout Example
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TPS25981
SLVSGG6B – APRIL 2022 – REVISED JUNE 2023
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12 Device and Documentation Support
TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,
generate code, and develop solutions are listed below.
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
•
•
Texas Instruments, TPS25981EVM eFuse Evaluation Board
Texas Instruments, TPS25981xx Design Calculator
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 Trademarks
HotRod™ and TI E2E™ are trademarks of Texas Instruments.
All trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
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13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
25-Jun-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS259813ARPWR
TPS259813LRPWR
TPS259814ARPWR
TPS259814LRPWR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
-40 to 125
-40 to 125
34NH
34OH
Samples
Samples
Samples
Samples
NIPDAU
NIPDAU
NIPDAU
VQFN-HR
VQFN-HR
RPW
RPW
10
10
2KWH
2KXH
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
25-Jun-2023
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
6-Jun-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS259814ARPWR
TPS259814LRPWR
VQFN-
HR
RPW
RPW
10
10
3000
3000
180.0
8.4
2.3
2.3
1.15
4.0
8.0
Q2
VQFN-
HR
180.0
8.4
2.3
2.3
1.15
4.0
8.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
6-Jun-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS259814ARPWR
TPS259814LRPWR
VQFN-HR
VQFN-HR
RPW
RPW
10
10
3000
3000
210.0
210.0
185.0
185.0
35.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
VQFN-HR - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
RPW0010A
2.1
1.9
A
B
2.1
1.9
PIN 1 IDENTIFICATION
(0.1) TYP
1 MAX
C
SEATING PLANE
0.08 C
0.05
0.00
2X 1.45
PKG
4X
SQ (0.15) TYP
4X 0.475
4
2X 0.25
6
5
7
0.35
4X
4X 0.475
0.25
0.1
C A B
C
0.05
2.1
1.9
2X
2X 0.45
PKG
4X
0.3
0.2
0.1
0.05
C A B
C
1
10
0.3
0.2
PIN 1 ID
(OPTIONAL)
4X
0.5
0.3
0.35
0.25
8X
2X
0.1
C A B
C
0.1
C A B
0.05
0.05
C
4225183/A 08/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
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EXAMPLE BOARD LAYOUT
VQFN-HR - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
RPW0010A
(1.8)
(1.45)
4X (0.475)
2X (0.25)
1
10
4X (0.25)
4X
(0.225)
PKG
2X
2X
(1.75)
(2.4)
4X (0.3)
4X (0.475)
7
4
4X
(0.65)
(R0.05) TYP
6
5
2X (0.3)
4X (0.25)
PKG
8X (0.6)
LAND PATTERN EXAMPLE
SCALE: 30X
SOLDER MASK
OPENING
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
METAL
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
SOLDER MASK
DEFINED
NON- SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
4225183/A 08/2019
NOTES: (continued)
3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).
4. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
VQFN-HR - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
RPW0010A
(1.8)
(1.425)
4X (0.4625)
2X (0.25)
METAL TYP
1
10
4X (0.25)
4X
(0.63)
PKG
2X
(1.75)
4X (0.225)
4X (0.275)
4X
4X (0.4625)
(1.06)
7
4
4X
(0.65)
(R0.05)
TYP
6
5
4X (0.28)
4X (0.225)
PKG
8X (0.6)
SOLDER PASTE EXAMPLE
BASED ON 0.100 mm THICK STENCIL
PADS 1, 4,7 & 10: 93%; PADS 5 & 6: 82%
SCALE: 30X
4225183/A 08/2019
NOTES: (continued)
5.
Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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