TPS26622DRCT [TI]
具有集成输入和输出反极性保护功能的 4.5V 至 60V、478mΩ、0.025A 至 0.88A 电子保险丝
| DRC | 10 | -40 to 125;
| 型号： | TPS26622DRCT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有集成输入和输出反极性保护功能的 4.5V 至 60V、478mΩ、0.025A 至 0.88A 电子保险丝 | DRC | 10 | -40 to 125 电子 光电二极管 |
| 文件： | 总46页 (文件大小：4453K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS2662
ZHCSI22F –OCTOBER 2017 –REVISED DECEMBER 2021
TPS2662x 具有集成输入和输出反极性保护功能的60V 800mA 工业电子保险丝
1 特性
3 说明
• 工作电压为4.5V 至60V，
绝对最大值为62V
• 集成反向输入极性保护，低至
–60V
• 集成反向输出极性保护，低至
–(60 –VIN)（仅限TPS26624 和TPS26625）
• 总RON 为478mΩ的集成背对背MOSFET
• 25mA 至880mA 可调节电流限制
（880mA 时精度为±5%）
TPS2662x 系列高电压电子保险丝设计紧凑，功能丰
富，且具有一整套保护功能。4.5V 至 60V 的宽电源输
入范围可实现对众多常用直流总线电压的控制。该器件
可以承受并保护由高达±60V 的正负电源供电的负载。
TPS26624 和 TPS26625 器件支持输入和输出反极性
保护功能。集成的背对背 FET 可提供反向电流阻断功
能，因此该器件适用于在电源故障和欠压条件下要求保
持输出电压的系统。负载、电源和器件保护具有许多可
调特性，包括过流、输出压摆率和过压、欠压阈值。
TPS2662x 系列内部可靠的保护控制模块以及高额定电
压有助于简化针对浪涌保护的系统设计。
• 使用最少的外部组件在浪涌期间提供负载保护(IEC
61000-4-5)
• 符合IEC 61000-4-4 标准的电气快速瞬变抗扰度
• 快速反向电流阻断响应(0.3µs)
• 可调节UVLO、OVP 切断、
输出压摆率控制，用于浪涌电流限制
• 38V 固定过压钳位
（仅限TPS26622 和TPS26623）
• 低静态电流（工作时为340µA，
关断时为12µA）
TPS26620、TPS26622 和TPS26624 具有闭锁功能，
TPS26621、TPS26623 和TPS26625 具有自动重试功
能，用于应对过热和过流故障事件。
这些器件采用 3mm × 3mm 10 引脚 SON 封装，额定
工作温度范围为–40°C 至+125°C。
器件信息(1)
封装尺寸（标称值）
器件型号
TPS26620
封装
• 小尺寸- 10L (3mm × 3mm) VSON
• 通过UL 2367 认证
TPS26621
TPS26622
TPS26623
TPS26624
TPS26625
– 文件编号169910
– RILIM ≥7.5kΩ（最大电流为0.91A）
• 通过IEC 62368-1 认证
SON (10)
3.00mm × 3.00mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
2 应用
• PLC I/O 模块
• 交流和伺服驱动器
• 传感器和控制
• 恒温器
• PoE 高侧保护
VIN
VIN: 4.5 V - 60 V
OUT
VOUT
IN
COUT
CIN
478 mΩ
R1
R4
Health
UVLO
OVP
VOUT
FLT
Monitor
TPS2662x
R2
ON/OFF
Control
SHDN
MODE
dVdT
RTN
IIN
ILIM
R3
CdVdT
GND
RILIM
–60V 电源时的反向输入极性保护
简化版原理图
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLVSDT4
TPS2662
www.ti.com.cn
ZHCSI22F –OCTOBER 2017 –REVISED DECEMBER 2021
Table of Contents
10 Application and Implementation................................25
10.1 Application Information........................................... 25
10.2 Typical Application.................................................. 25
10.3 System Examples................................................... 31
10.4 Do's and Don'ts.......................................................32
11 Power Supply Recommendations..............................33
11.1 Transient Protection................................................ 33
12 Layout...........................................................................35
12.1 Layout Guidelines................................................... 35
12.2 Layout Example...................................................... 36
13 Device and Documentation Support..........................37
13.1 Documentation Support.......................................... 37
13.2 接收文档更新通知................................................... 37
13.3 支持资源..................................................................37
13.4 Trademarks.............................................................37
13.5 Electrostatic Discharge Caution..............................37
13.6 术语表..................................................................... 37
14 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Device Comparison Table...............................................4
6 Pin Configuration and Functions...................................4
7 Specifications.................................................................. 5
7.1 Absolute Maximum Ratings........................................ 5
7.2 ESD Ratings............................................................... 5
7.3 Recommended Operating Conditions.........................5
7.4 Thermal Information....................................................6
7.5 Electrical Characteristics.............................................6
7.6 Timing Requirements..................................................8
7.7 Typical Characteristics................................................9
8 Parameter Measurement Information..........................14
9 Detailed Description......................................................15
9.1 Overview...................................................................15
9.2 Functional Block Diagram.........................................16
9.3 Feature Description...................................................16
9.4 Device Functional Modes..........................................24
Information.................................................................... 37
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision E (August 2019) to Revision F (December 2021)
Page
• 更新了整个文档中的表格、图和交叉参考的编号格式.........................................................................................1
• Moved ISHDN from Source Current to Sink Current row in the Absolute Maximum Ratings table.......................5
• Changed External Capacitance min from 0.1 to 0.01 in Recommended Operating Conditions table................ 5
• Deleted OVPMAX row in Electrical Characteristics table..................................................................................... 6
• Changed I(FLT) test condition in Electrical Characteristics table..........................................................................6
• Deleted UVLO_tREC row in Timing Requirements table..................................................................................... 8
• Updated the Parameter Measurement Information section..............................................................................14
• Added tCL_Dly description to Overvoltage Protection (OVP) section................................................................. 17
• Changed device mention to TPS2662x to include all variants in Input Side Reverse Polarity Protection section
..........................................................................................................................................................................19
• Added UVLO back to the Overload Protection section.....................................................................................20
• Added more description and clarification for the tCL(dly) parameter in the Overload Protection section............20
• Added minimum voltage to FAULT Response section......................................................................................23
Changes from Revision D (February 2019) to Revision E (August 2019)
Page
• 将特性部分中的“UL 2367 认证正在处理中”更改为“通过UL 2367 认证”和“通过IEC 62368-1 认证”.... 1
• Replaced TPS26623 with TPS26624 for Pin No. 4 SHDN in the Pin Functions table........................................4
• Added UVLO Recovery Time in the Timing Requirements table in the Specifications section.......................... 5
• Changed Input voltage range MAX from 60 V to 62 V in tne Absolute Maximum Ratings table in the
Specifications section......................................................................................................................................... 5
• Changed Input voltage MAX from 57 V to 60 V in the Recommended Operating Conditions table in the
Specifications section......................................................................................................................................... 5
• Updated the Parameter Measurement Information graph to explain the UVLO_tREC ..................................... 14
• Updated the Feature Description Undervoltage Lockout (UVLO) section to explain the UVLO_tREC timer..... 16
• Updated the Feature Description Undervoltage Lockout (UVLO) section ....................................................... 16
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ZHCSI22F –OCTOBER 2017 –REVISED DECEMBER 2021
• Removed UVLO from the Overload Protection section ................................................................................... 20
Changes from Revision C (July 2018) to Revision D (February 2019) Page
• Changed SHDN pin voltage MAX from 4 V to 6 V in the Recommended Operating Conditions table in the
Specifications section ........................................................................................................................................ 5
Changes from Revision B (April 2018) to Revision C (July 2018)
Page
• 将状态从“预告信息”更改为“量产数据”....................................................................................................... 1
Changes from Revision A (March 2018) to Revision B (April 2018)
Page
• Changed Repinse to Response in the Device Comparison table header ..........................................................4
Changes from Revision * (October 2017) to Revision A (March 2018)
Page
• 将一页更改为整个数据表.................................................................................................................................... 1
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5 Device Comparison Table
OVERLOAD and THERMAL FAULT
RESPONSE
PART NUMBER
OVERVOLTAGE PROTECTION
REVERSE POLARITY PROTECTION
TPS26620
TPS26621
TPS26622
TPS26623
TPS26624
TPS26625
Overvoltage cut-off, adjustable
Overvoltage cut-off, adjustable
Overvoltage clamp, fixed (38 V)
Overvoltage clamp, fixed (38 V)
Overvoltage cut-off, adjustable
Overvoltage cut-off, adjustable
Latch Off
Auto-Retry
Latch Off
Input side
Input side
Input side
Auto-Retry
Latch Off
Input side
Input and Output side
Input and Output side
Auto-Retry
6 Pin Configuration and Functions
10
9
OUT
FLT
1
2
IN
UVLO
3
4
5
8
dVdT
OVP
PowerPad TM
SHDN
7
6
ILIM
RTN
GND
图6-1. DRC Package 10-Pin VSON Top View
表6-1. Pin Functions
PIN
TYPE
DESCRIPTION
NO.
NAME
1
IN
Power
Input supply voltage
Resistor programmable undervoltage lockout threshold setting input. An undervoltage event
opens the internal FET. If the Undervoltage Lock Out function is not needed, the UVLO terminal
must be connected to the IN terminal with at least a 1-MΩ resistor. UVLO pin is 5-V rated and
this resistor limits the UVLO pin current to < 60 µA.
2
UVLO
I
Resistor programmable overvoltage protection threshold. An overvoltage event opens internal
FET. In TPS26620, TPS26621, TPS26624, TPS26625 devices, if overvoltage protection feature
is not to be used then connect OVP terminal to RTN. For overvoltage clamp response
(TPS26622 and TPS26623 only) connect OVP to RTN externally.
3
4
OVP
I
I
Shutdown pin. Pulling the pin low makes the device to enter into low power shutdown mode.
Cycling SHDN low and then back high resets the device that has latched off (TPS26620,
TPS26622, TPS26624 only) due to a fault condition.
SHDN
5
6
RTN
GND
Reference ground for all internal voltages
System ground
–
–
A resistor from this pin to RTN sets the overload and short-circuit current limit. See the Overload
and Short Circuit Protection section.
7
8
ILIM
I/O
I/O
A capacitor from this pin to RTN sets output voltage slew rate. See the Hot Plug-In and In-Rush
Current Control section.
dVdT
9
FLT
O
Fault event indicator. This pin is an open drain output. If unused, leave floating.
Output voltage
10
OUT
Power
Connect PowerPAD to RTN plane for heat sinking. Do not use PowerPAD as the only electrical
connection to RTN.
PowerPAD™
–
–
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ZHCSI22F –OCTOBER 2017 –REVISED DECEMBER 2021
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range, all voltages referred to GND (unless otherwise noted)(1)
MIN
MAX
UNIT
62
62
70
62
5
IN, IN–OUT
–60
OUT (TPS26624 and TPS26625 Only)
–(60–VIN)
–70
IN, IN–OUT (10 ms transient), TA = 25 ℃
[IN, OUT, FLT, SHDN] to RTN
[UVLO, OVP, dVdT, ILIM] to RTN
RTN
Input voltage range
V
–0.3
–0.3
0.3
10
–60
Sink current
IFLT, IdVdT
mA
°C
Source current
IdVdT, IILIM, ISHDN
Internally limited
Operating junction
temperature
150
–40
TJ
Transient junction
temperature
T(TSD)
150
°C
°C
–65
–65
Storage temperature
Tstg
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
7.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC
JS-001, all pins(1)
±1500
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC specification
JESD22-C101, all pins(2)
±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
4.5
0
NOM
MAX
60
UNIT
V
IN
Input voltage
Input voltage
OUT, FLT
60
V
UVLO, OVP,
dVdT, ILIM
Input voltage
0
4
V
SHDN
ILIM
Input voltage
Resistance
0
7.5
6
V
267
kΩ
µF
nF
°C
IN, OUT
dVdT
Tj
0.01
6.8
External capacitance
Operating junction temperature
25
125
–40
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ZHCSI22F –OCTOBER 2017 –REVISED DECEMBER 2021
7.4 Thermal Information
TPS2662
DRC (VSON)
10 PINS
44.8
THERMAL METRIC(1)
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
39.5
20.7
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.5
ΨJT
20.7
ΨJB
RθJC(bot)
3.4
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Electrical Characteristics
–40°C ≤TA = TJ ≤+125°C, V(IN) = 24 V, V( SHDN) = 2 V, R(ILIM) = 267 kΩ, FLT = OPEN, C(OUT) = 1 µF, C(dVdT) = OPEN. (All
voltages referenced to GND, (unless otherwise noted))
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
SUPPLY VOLTAGE
V(IN)
Operating input voltage
Internal POR threshold, rising
Internal POR hysteresis
4.5
60
V
V
V(PORR)
V(PORHys)
IQ(ON)
IQ(OFF)
I(VINR)
3.54
3.73
110
343
11.5
50
4.2
mV
µA
µA
µA
Enabled: V( SHDN) = 2 V
482
25
Supply current
V( SHDN) = 0 V
Reverse Input supply current
Over voltage clamp
130
V(IN) = –24 V, V(OUT) = 0 V
V(IN) > 40 V, ILOAD = 10 mA,TPS26622,
TPS26623 Only
V(OVC)
36
37.5
40
V
UNDERVOLTAGE LOCKOUT (UVLO) INPUT
V(UVLOR)
V(UVLOF)
I(UVLO)
UVLO threshold voltage, rising
UVLO threshold, Falling
1.18
1.09
1.2
1.1
0
1.23
1.135
100
V
V
UVLO Input Leakage Current
UVLO Input Leakage Current
nA
µA
0 V ≤V(UVLO) ≤3.5 V
–100
I(UVLO)
V(UVLO) = 5 V
18.8
38
OVER VOLTAGE PROTECTION (OVP) INPUT
V(OVPR)
V(OVPF)
I(OVP)
Overvoltage threshold voltage, rising
Overvoltage threshold, falling
OVP Input Leakage Current
1.18
1.09
1.2
1.12
0
1.23
1.135
100
V
V
nA
0 V ≤V(OVP) ≤5 V
–100
LOW IQ SHUTDOWN ( SHDN) INPUT
V( SHDN)
V(SHUTF)
Output voltage
I( SHDN) = 0.1 µA
2.39
0.9
2.781
3.1
1.8
V
V
SHDN Threshold Voltage for Low
IQ Shutdown, Falling
V(SHUTR)
I( SHDN)
SHDN Threshold, rising
Input current
V
V( SHDN) = 0.4 V
V(dVdT) = 0V
µA
–10
–2.4
OUTPUT RAMP CONTROL (dVdT)
I(dVdT)
dVdT Charging Current
1.68
1.98
13.1
2.33
22
µA
V( SHDN) = 0 V, with I(dVdT) = 10mA
sinking
R(dVdT)
dVdT Discharging Resistance
Ω
V(dVdTmax)
GAIN(dVdT)
dVdT Max Capacitor Voltage
dVdT to OUT Gain
4
4.34
24.6
4.75
25.2
V
V(OUT) /V(dVdT)
23.9
V/V
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7.5 Electrical Characteristics (continued)
–40°C ≤TA = TJ ≤+125°C, V(IN) = 24 V, V( SHDN) = 2 V, R(ILIM) = 267 kΩ, FLT = OPEN, C(OUT) = 1 µF, C(dVdT) = OPEN. (All
voltages referenced to GND, (unless otherwise noted))
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
CURRENT LIMIT PROGRAMMING (ILIM)
V(ILIM)
ILIM bias voltage
1
0.025
0.152
0.25
0.5
V
0.032
0.02
0.145
0.237
0.47
R(ILIM) = 267 kΩ, V(IN) –V(OUT) = 1 V
R(ILIM) = 44.2 kΩ, V(IN) –V(OUT) = 1 V
R(ILIM) = 26.7 kΩ, V(IN) –V(OUT) = 1 V
R(ILIM) = 13.3 kΩ, V(IN) –V(OUT) = 1 V
R(ILIM) = 8.25 kΩ, V(IN) –V(OUT) = 1 V
R(ILIM) = 7.5 kΩ, V(IN) –V(OUT)= 1 V
0.159
0.257
A
0.52
I(OL)
0.757
0.83
0.8
0.827
0.91
Overload Current Limit
0.88
R(ILIM)= OPEN, Open Resistor Current
Limit (single point failure test: UL60950)
I(OL_R-OPEN)
8
15.5
39.3
27
51
mA
mA
R(ILIM)= SHORT, Shorted Resistor
Current Limit (single point failure test:
UL60950)
I(OL_R-SHORT)
31
I(SCL)
Short-Circuit Current Limit
0.885
1.6
A
A
R(ILIM) = 7.5 kΩ, V(IN) –V(OUT)= 24 V
I(FAST-TRIP)
Fast-Trip Comparator Threshold
PASS FET OUTPUT (OUT)
0.025 A ≤I(OUT) ≤0.8 A, TJ = 25°C,
R(ILIM) = 7.5 kΩ
435
250
478
626
521
685
0.025 A ≤I(OUT) ≤0.8A, TJ = 85°C,
R(ILIM) = 7.5 kΩ
RON
mΩ
0.025 A ≤I(OUT) ≤0.8A, –40°C ≤TJ
≤125°C, R(ILIM) = 7.5 kΩ
478
4.38
7.27
800
12
V(IN) = 57 V, V( SHDN)= 0 V, V(OUT) = 0 V,
Sourcing
V(IN) = 0 V, V( SHDN)= 0 V, V(OUT) = 24 V,
Sinking
102
168
OUT Leakage Current in Off State
Ilkg(OUT)
µA
V(IN) = –57V, V( SHDN)= 0V, V(OUT)
=
0V, Sinking
OUT leakage current under output
reverse polarity condition
V(IN) = 24 V, V(OUT) = –24 V, V( SHDN)
2 V, TP26624, TPS26625 Only
=
450
–54
15
V
(IN) –V(OUT) threshold for reverse
V(REVTH)
V(FWDTH)
mV
mV
–71
–40
protection comparator, falling
V
(IN) –V(OUT) threshold for reverse
1.4
30
protection comparator, rising
FAULT FLAG ( FLT): ACTIVE LOW
R( FLT)
I( FLT)
FLT Pull-Down Resistance
FLT Input Leakage Current
V(OVP) = 2 V, I( FLT) = 5mA sinking
45
82.3
0
145
100
Ω
nA
0 V ≤V( FLT) ≤60 V
–100
THERMAL SHUT DOWN (TSD)
T(TSD)
TSD Threshold, rising
TSD Hysteresis
155
10
°C
°C
T(TSDhyst)
TPS26620, TPS26622, TPS26624
TPS26621, TPS26623, TPS26625
Latch
Thermal Fault (Latch or Auto-Retry)
Auto–
retry
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7.6 Timing Requirements
–40°C ≤TA = TJ ≤+125°C, V(IN) = 24 V, V( SHDN) = 2 V, R(ILIM) = 267 kΩ, FLT = OPEN, C(OUT) = 1 µF, C(dVdT) = OPEN. (All
voltages referenced to GND, (unless otherwise noted))
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX UNIT
IN and UVLO INPUT
UVLO ↑(100 mV above V(UVLOR)) to V(OUT) = 100
mV, C(dVdT) = Open
51
µs
UVLO_tON(dly)
UVLO_toff(dly)
UVLO Turnon Delay
UVLO Turnoff delay
51 +
27.4 x
C(dVdT)
UVLO↑(100 mV above V(UVLOR)) to V(OUT) = 100
mV, C(dVdT) > 4.7 nF, [C(dVdT) in nF]
µs
µs
6.14
UVLO↓(100 mV below V(UVLOF)) to FLT↓
SHDN↑to V(OUT) = 100 mV, C(dVdT) = Open
SHUTDOWN CONTROL INPUT ( SHDN)
156
µs
µs
µs
156 +
27.4 x
C(dVdT)
SHUTDOWN exit delay
tSD(dly)
SHDN↑to V(OUT) = 100 mV, C(dVdT) > 4.7 nF,
[C(dVdT) in nF]
SHUTDOWN entry delay
6.83
SHDN↓(below SHUTF) to FLT↓
OVER VOLTAGE PROTECTION INPUT (OVP)
OVP↓(20 mV below V(OVPF)) to V(OUT) = 100 mV,
TPS26620/21/24/25 Only
OVP Exit delay
77
µs
µs
tOVP(dly)
OVP↑(20mV above V(OVPR)) to FLT↓,
TPS26620/21/24/25 Only
OVP Disable delay
4.84
CURRENT LIMIT
tCL(dly)
Maximum duration in current limit
Fast-Trip Comparator Delay
512
1.5
ms
µs
I(ILIM) < I(OUT) < I(FAST-TRIP), V(IN) –V(OUT) < 2.6 V
I(OUT) > I(FAST-TRIP), V(IN) –V(OUT) = 2 V
I(OUT) > I(FAST-TRIP), 4.5 V < V(IN) ≤6 V, V(IN)
(OUT) ≥2.6 V
–
1.4
µs
ns
tFAST-TRIP(dly)
V
I(OUT) > I(FAST-TRIP), 6 V < V(IN) ≤57 V, V(IN)
(OUT) ≥2.6 V
–
220
V
REVERSE PROTECTION COMPARATOR
(V(IN) –V(OUT)) ↓(10 mV overdrive below
V(REVTH)) to internal FET turn OFF
15
3.71
0.31
45
(V(IN) –V(OUT)) ↓(1 V overdrive below V(REVTH)
to internal FET turn OFF
)
tREV(dly)
(V(IN) –V(OUT)) ≤–2.6 V to internal FET turn
OFF
Reverse Protection Comparator
µs
Delay
(V(IN) –V(OUT)) ↓(150 mV overdrive below
V(REVTH)) to FLT↓
(V(IN) –V(OUT)) ↑(100 mV overdrive above
V(FWDTH)) to FLT↑
tFWD(dly)
63
THERMAL SHUTDOWN
Retry Delay in
TSD
512
ms
ms
OUTPUT RAMP CONTROL (dVdT)
11
SHDN ↑to V(OUT) = 23.9 V, with C(dVdT) = 22 nF
SHDN ↑to V(OUT) = 23.9 V, with C(dVdT) = open
tdVdT
Output Ramp Time
0.664
FAULT FLAG ( FLT)
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7.6 Timing Requirements (continued)
–40°C ≤TA = TJ ≤+125°C, V(IN) = 24 V, V( SHDN) = 2 V, R(ILIM) = 267 kΩ, FLT = OPEN, C(OUT) = 1 µF, C(dVdT) = OPEN. (All
voltages referenced to GND, (unless otherwise noted))
PARAMETER
TEST CONDITIONS
MIN
NOM
875
1.4
MAX UNIT
tPGOODF
Falling edge
µs
Rising edge, C(dVdT) = Open
ms
PGOOD Delay
750 +
573 x
tPGOODR
Rising edge, C(dVdT) > 4.7 nF, [C(dVdT) in nF]
µs
C(dVdT)
7.7 Typical Characteristics
800
700
600
500
400
300
200
100
0
1.22
1.2
1.18
1.16
1.14
V(UVLOR)
V(UVLOF)
1.12
0.8 A
0.4 A
0.025 A
1.1
1.08
-50
0
50
Temperature (èC)
100
150
-50 -30 -10 10
30
50
70
90 110 130 150
Temperature (èC)
D001
D002
图7-1. On-Resistance vs Temperature Across Load Current
图7-2. UVLO Threshold Voltage vs Temperature
1.22
-50
-51
-52
-53
-54
-55
-56
-57
-58
-59
-60
1.2
1.18
1.16
V(OVPR)
V(OVPF)
1.14
1.12
1.1
-50
0
50
Temperature (èC)
100
150
-50
0
50
Temperature (èC)
100
150
D003
D005
图7-3. OVP Threshold Voltage vs Temperature
图7-4. Reverse Voltage Threshold vs Temperature
25
40
39.5
39
23
21
19
17
15
13
11
9
38.5
38
37.5
37
36.5
36
7
35.5
35
5
-50
0
50
Temperature (Cè)
100
150
-50
0
50
Temperature (èC)
100
150
D006
D023
图7-5. V(FWDTH) vs Temperature
图7-6. Overvoltage Clamp Threshold vs Temperature
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7.7 Typical Characteristics (continued)
4
20
15
10
5
V(PORR)
V(PORF)
3.95
3.9
3.85
3.8
3.75
3.7
3.65
3.6
125
85
25
-40
3.55
3.5
0
-50
0
50
Temperature (èC)
100
150
0
10
20
30 40
Input Voltage (V)
50
60
70
D008
D021
图7-7. Internal POR Threshold Voltage vs Temperature
图7-8. Input Supply Current vs Supply Voltage in Shutdown
500
450
400
350
300
250
200
5
-5
-15
-25
-35
150
100
50
-45
125
85
25
125
85
25
-40
-55
-40
0
-65
-70
0
5
10 15 20 25 30 35 40 45 50 55 60 65 70
Input Voltage (V)
-60
-50
-40
-30
Input Voltage (V)
-20
-10
0
10
D020
D027
图7-9. Input Supply Current vs Supply Voltage During Normal
V(OUT) = 0 V
Operation
图7-10. Input Supply Current vs Reverse Supply Voltage, –V(IN)
7
6
5
4
3
2
1
0
9
8
7
6
5
4
3
2
1
0
-50
0
50
Temperature (èC)
100
150
-50
0
50
Temperature (èC)
100
150
D022
D012
图7-11. OVP Disable Delay vs Temperature
图7-12. Shutdown Entry Delay vs Temperature
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7.7 Typical Characteristics (continued)
1.19
1.185
1.18
540
538
536
534
532
530
1.175
1.17
1.165
1.16
1.155
1.15
-50
0
50
Temperature (èC)
100
150
-50
0
50
Temperature (èC)
100
150
D013
D019
图7-13. Shutdown Threshold Voltage Shutdown vs Temperature 图7-14. Max Duration in Current Limiting t(CL) vs Temperature
2%
1.75%
1.5%
20%
15%
10%
5%
44.2 k
26.7 k
13.3 k
8.25 k
7.5 k
1.25%
1%
0.75%
0.5%
0.25%
0
-0.25%
-0.5%
-0.75%
-1%
0
-5%
-10%
-1.25%
-1.5%
267 k
150
-50
0
50
Temperature (èC)
100
150
-50
0
50
Temperature (èC)
100
D014
D015
图7-15. Current Limit (% Normalized) vs Temperature
图7-16. Current Limit (% Normalized) vs Temperature
1.2
0.05
0.045
0.04
267 kW
44.2 kW
26.7 kW
13.3 kW
8.25 kW
7.5 kW
1.1
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0.035
0.03
0.025
0.02
0.015
0.01
R(ILIM) = Open
R(ILIM) = Short
0.005
0
-50 -30 -10 10
30
50
70
90 110 130 150
-50
0
50
Temperature (èC)
100
150
Temperature (èC)
D009
D004
图7-17. Over Load Current Limit vs Temperature
图7-18. Current Limit for R(ILIM) = Open and Short vs
Temperature
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7.7 Typical Characteristics (continued)
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1
30
25
20
15
10
5
0
-50
0
50
Temperature (èC)
100
150
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
Current Limit (A)
1
D017
D024
图7-19. Fast-Trip Comparator Threshold I(FAST-TRIP) vs
图7-20. Current Limit Accuracy vs Current Limit, I(OL)
Temperature Threshold
7
6.8
6.6
6.4
6.2
6
100
10
1
0.1
-50
0
50
Temperature (èC)
100
150
1
10
100
Vrev_overdrive (mV)
1000
10000
D016
D026
图7-21. UVLO Turnoff Delay vs Temperature
图7-22. Reverse Current Blocking Response Time vs Reverse
Comparator Overdrive Voltage
100000
10000
1000
100
Temp = -40èC
Temp = 25èC
Temp = 85èC
Temp = 105èC
Temp = 125èC
VIN
VOUT
FLTb
IIN
10
1
0.2
1
10
Power Dissipation (W)
50
D025
RILIM = 7.5 kΩ
RFLTb = 100 kΩ
RLOAD = 80 Ω
Taken on 2-Layer board, 2 oz.(0.08-mm thick) with RTN plane
area: 0.8 cm2 (Top) and 4.5 cm2 (Bottom)
OVP setting at 33 V
图7-24. OVP Overvoltage Cut-Off Response
图7-23. Thermal Shutdown Time vs Power Dissipation
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7.7 Typical Characteristics (continued)
VIN
VOUT
FLTb
IIN
RILIM = 7.5 kΩ
RFLTb = 100 kΩ
RLOAD = 80 Ω
RILIM = 7.5 kΩ
RFLTb = 100 kΩ
图7-25. OV Clamp Response (TPS26602 Only)
图7-26. Hot-Short: Fast-Trip Response and Current Regulation
VIN
SHDNb
VOUT
VOUT
FLTb
IIN
IIN
RILIM = 7.5 kΩ
RILIM = 7.5 kΩ
RFLTb = 100 kΩ
RLOAD = 80 Ω
图7-27. Hot-Short: Fast-Trip Response (Zoomed)
图7-28. Turnon Control With SHDN
SHDNb
VOUT
FLTb
IIN
RILIM = 7.5 kΩ
RFLTb = 100 kΩ
图7-29. Turnoff Control With SHDN
RLOAD = 80 Ω
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8 Parameter Measurement Information
V(OUT)
VUVLO
V(UVLOF)-0.1 V
0.1 V
VUVLO
FLT
V(UVLOR)+0.1V
10%
time
0
time
0
UVLO_tON(dly)
UVLO_toff(dly)
-54 mV
15 mV
V(IN) -V(OUT)
V(IN) -V(OUT)
90%
FLT
FLT
10%
0
time
tREV(dly)
0
time
tFWD(dly)
I(FASTRIP)
V(OVPR)+0.1V
V(OVP)
I(SCL)
I(OUT)
FLT
10%
0
time
0
time
tOVP(dly)
tFASTRIP(dly)
图8-1. Timing Waveforms
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9 Detailed Description
9.1 Overview
The TPS2662x is a family of high voltage industrial eFuses with integrated back-to-back MOSFETs and
enhanced built-in protection circuitry. The device provides robust protection for all systems and applications
powered from 4.5 V to 60 V. The device can withstand ±60-V positive and negative supply voltages without
damage. The device features fully integrated reverse polarity protection and require zero additional power
components. For hot-pluggable boards, the device provides hot-swap power management with in-rush current
control. Load, source, and device protections are provided with many programmable features including
overcurrent, overvoltage, undervoltage. The precision overcurrent limit (±5% at 880 mA) helps to minimize over
design of the input power supply, while the fast response short-circuit protection 220 ns (typical) immediately
isolates the faulty load from the input supply when a short circuit is detected.
The internal robust protection control blocks of the TPS2662x along with its ±60-V rating helps to simplify the
system designs for the surge compliance ensuring complete protection of the load and the device. TPS2662x
devices are immune to noise tests like Electrical Fast Transients that are common in industrial applications and
simplifies the system design that require criterion-A performance during this test.
The device provides precise monitoring of voltage bus for brown-out and overvoltage conditions and asserts fault
signal for the downstream system. The TPS2662x monitor functions threshold accuracy of ±3% ensures tight
supervision of the supply bus, eliminating the need for a separate supply voltage supervisor chip.
The device monitors V(IN) and V(OUT) to provide true reverse current blocking when a reverse condition or input
power failure condition is detected.
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9.2 Functional Block Diagram
OUT
IN
478mΩ
-54mV
15mV
+
PORb
Charge
Pump
3.8V
3.7V
CP
+
UVLO
UVLOb
1.2V
1.1V
REVERSE
4.4V
SWEN
Gate Control Logic
Current Limit Amp
TSD
Thermal
Shutdown
* TPS26620/1/4/5 Only
+
OVP
Fast-Trip Comp
(I(FASTTRIP), VIN, VOUT)
OVP
1.2V
1.1V
* TPS26622/3 Only
1V
Over Voltage
Clamp detect
(38V)
SHDNb
ILIM
Short detect
Ramp Control
24.6x
SWEN
FLT
Avdd
I(LOAD) ≥ I(OL)
* TPS26620/2/4 Only
512msec
timer
SET
Timeout
82Ω
1.98µA
S
Q
dVdT
UVLOb
PORb
TSD
CLR
R
Q
1.4 msec
875 µs
13Ω
PORb
Fault Latch
RTN
SHDNb
Gate Enhanced (tPGOOD
)
Avdd
Reverse Polarity Protection
circuit
0.9V
GND
SHDNb
+
RTN
TPS2662x
SHDN
9.3 Feature Description
9.3.1 Undervoltage Lockout (UVLO)
When the voltage at UVLO pin falls below V(UVLOF) during input power fail or input undervoltage fault, the internal
FET quickly turns off and FLT is asserted. The UVLO comparator has a hysteresis of 100 mV. To set the input
UVLO threshold, connect a resistor divider network from IN supply to UVLO terminal to RTN as shown in 图9-1.
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V(IN)
IN
TPS26620/1/4/5
R1
UVLO
+
+
UVLOb
1.2 V
1.1 V
R2
OVP
RTN
OVP
1.2 V
1.1 V
R3
GND
图9-1. UVLO and OVP Thresholds Set by R1, R2 and R3
If the Undervoltage Lockout function is not needed, the UVLO terminal must be connected to the IN terminal with
a 1-MΩ resistor. UVLO pin is 5-V rated and this resistor limits the UVLO pin current to < 60 µA. The UVLO
terminal must not be left floating.
9.3.2 Overvoltage Protection (OVP)
The TPS2662x family incorporate circuitry to protect the system during overvoltage conditions. The TPS26620,
TPS26621, TPS26624 and TPS26625 feature overvoltage cut off functionality. A voltage more than V(OVPR) on
OVP pin turns off the internal FET and protects the downstream load. To program the OVP threshold externally,
connect a resistor divider from IN supply to OVP terminal to RTN as shown in 图9-1. If the overvoltage feature is
not to be used then connect OVP terminal to RTN directly and ensure VIN is not exceeded beyond OVPMAX
.
The TPS26622 and TPS26623 feature an internally fixed 38-V overvoltage clamp (VOVC) functionality. The OVP
terminal of these devices must be connected to the RTN terminal directly. These devices clamp the output
voltage to VOVC, when the input voltage exceeds 38 V. During the output voltage clamp operation, the power
dissipation in the internal MOSFET is PD = (VIN – VOVC) × IOUT. Excess power dissipation for prolonged period
can make the device to enter into thermal shutdown. If the device temperature does not reach T(TSD), the device
turns off the internal FETs after a delay of tCL_Dly. After the internal FETs are turned off, TPS26622 latches-off
and TPS26623 device auto-retries. 图7-25 illustrates the overvoltage clamp functionality.
9.3.3 Hot Plug-In and Inrush Current Control
The devices are designed to control the inrush current upon insertion of a card into a live backplane or other
hotpower source. This design limits the voltage sag on the backplane’s supply voltage and prevents
unintended resets of the system power. The controlled start-up also helps to eliminate conductive and radiative
interferences. An external capacitor connected from the dVdT pin to RTN defines the slew rate of the output
voltage at power-on as shown in 图9-2 and Figure 9-3.
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TPS2662x
4.34 V
1.98µA
dVdT
RTN
13 Ω
SWENb
C(dVdT)
GND
图9-2. Output Ramp Up Time tdVdT is Set by C(dVdT)
The dVdT pin can be left floating to obtain a predetermined slew rate (tdVdT) on the output. When the terminal is
left floating, the devices set an internal output voltage ramp rate of 24 V/660 µs. A capacitor can be connected
from dVdT pin to RTN to program the output voltage slew rate slower than 24 V/660 µs. Use 方程式 1 and 方程
式2 to calculate the external C(dVdT) capacitance.
方程式1 governs slew rate at start-up.
æ
ç
ö
÷
C dVdT
dV
OUT
æ
ö
÷
÷
ø
(
)
(
)
I(dVdT)
=
´ ç
ç
ç
è
÷
ø
Gain dVdT
dt
(
)
è
(1)
where
• I(dVdT) = 1.98 µA (typical)
dV
(
OUT
)
dt
•
= Desired output slew rate
• Gain(dVdT) = dVdT to VOUT gain = 24.6
The total ramp time (tdVdT) of V(OUT) for 0 to V(IN) can be calculated using 方程式2.
tdVdT = 20.5 × 103 × V(IN) × C(dVdT)
(2)
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VIN
VOUT
FLTb
IIN
CdVdT = 22 nF
COUT = 22 µF
RILIM = 7.5 kΩ
图9-3. Hot Plug-In and Inrush Current Control at 24-V Input
9.3.4 Reverse Polarity Protection
9.3.4.1 Input Side Reverse Polarity Protection
TPS2662x eFuses feature fully integrated input side reverse polarity protection. The internal FETs of the eFuse
turn OFF during the input reverse polarity event and protect the downstream loads from negative supply voltages
that can appear due to field mis-wiring on the input power terminals. Figure 9-4 illustrates the reverse input
polarity protection functionality.
VIN
VOUT
IIN
图9-4. Reverse Input Supply Protection at –60 V
9.3.4.2 Output Side Reverse Polarity Protection
TheTPS26624 and TPS26625 eFuses feature fully integrated input as well as output reverse polarity protection.
The internal FETs of the eFuse turn OFF during the output reverse polarity event and protects the upstream
circuits from negative voltage that can appear at the output of the eFuse due to field miswiring at the output side
with an external isolated power supplies. 图 9-5 illustrates the performance during output side reverse polarity
event with V(IN) un-powered and 图 9-6 illustrates the performance with V(IN) powered. 图 9-7 illustrates the
output recovery performance after the reverse polarity is removed.
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VIN
VOUT
IOUT
图9-5. Reverse Output Polarity Protection With –60 V at OUT and VIN = 0 V
VIN
VIN
VOUT
VOUT
IIN
IIN
图9-6. Reverse Output Polarity Protection With –
图9-7. Response During Coming Out of Output
24 V at OUT and 24 V at IN
Reverse Polarity Fault Condition
9.3.5 Overload and Short-Circuit Protection
The device monitors the load current by sensing the voltage across the internal sense resistor. The FET current
is monitored during start-up and normal operation.
9.3.5.1 Overload Protection
Connect a resistor across ILIM to RTN to program the over load current limit I(OL). During overload conditions,
the device regulates the current through it at I(OL) programmed by the R(ILIM) resistor as shown in 方程式 3 for a
maximum duration of tCL(dly)
.
6.636
=
IOL
RILIM
(3)
where
• I(OL) is the overload current limit in Ampere
• R(ILIM) is the current limit resistor in kΩ
During the current limit operation the output voltage droops and this can cause the device to hit the thermal
shutdown threshold T(TSD) before tCL(dly) time. After the thermal shutdown threshold is hit or tCL(dly) is elapsed,
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the internal FETs of TPS2662x turns OFF. FETs in TPS26620, TPS26622 and TPS26624 remain OFF and
latched. To reset the latch, cycle the SHDN or UVLO, or recycle the VIN. TPS26621, TPS26623 and TPS26625
commence an auto-retry cycle after a retry time of 512 msec. The internal FETs turn back on in dVdT mode after
this retry time. If the overload still exists, then the device regulates the current at programmed current limit, I(OL)
.
tCL(dly) is the maximum duration for current limiting and estimated as tCL(dly) = 512 ms + [3.3 × CdVdT / 2 μA]
(CdVdT in nF).
VIN
VIN
VOUT
VOUT
FLTb
FLTb
IIN
IIN
Load transition from
VIN = 24 V, RILIM
=
Load transition from
VIN = 24 V, RILIM =
120 Ω to 20 Ω
7.5 kΩ
20 Ω to 120 Ω
7.5 kΩ
图9-8. Auto-Retry Fault Behavior
图9-9. Response During Coming Out of Overload
Fault
9.3.5.2 Short-Circuit Protection
During a transient output short circuit event, the current through the device increases rapidly. As the current-limit
amplifier cannot respond quickly to this event due to its limited bandwidth, the device incorporates a fast-trip
comparator. The fast-trip comparator architecture is designed for fast turn OFF (tFAST-TRIP(dly) = 220 ns (typical))
of the internal FET during an output short circuit event. The fast-trip threshold is internally set to I(FAST-TRIP). The
fast-trip circuit holds the internal FET off for only a few microseconds, after which the device turns back on
slowly, allowing the current-limit loop to regulate the output current to I(OL). Then the device functions similar to
the overload condition. Figure 9-10 and Figure 9-11 illustrate the behavior of the system during output short-
circuit condition.
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VIN
VOUT
IIN
VIN = 24 V, RILIM = 7.5 kΩ
图9-11. Hot-Short: Fast-Trip Response (Zoomed)
图9-10. Output Hot Short Functionality at 24-V
Input
The fast-trip comparator architecture has a supply line noise immunity resulting in a robust performance in noisy
environments. This feature is achieved by controlling the turn OFF time of the internal FET based on the
differential voltage across V(IN) and V(OUT) after the current through the device exceeds I(FAST-TRIP). Higher the
voltage difference V(IN) –V(OUT), faster the turn OFF time, tFAST-TRIP(dly)
.
9.3.5.2.1 Start-Up With Short-Circuit On Output
When the device is started with short-circuit on the output, it limits the load current to the current limit, I(OL), and
functions similar to the overload condition. Figure 9-12 illustrates the function of the device in this condition. This
feature helps in quick isolation of the fault and ensures stability of the DC bus.
VIN
VOUT
FLTb
IIN
VIN = 24 V
RILIM = 7.5 kΩ
图9-12. Start-Up With Short on Output
9.3.6 Reverse Current Protection
The device monitors V(IN) and V(OUT) to provide true reverse current blocking when a reverse condition or input
power failure condition is detected. The reverse comparator turns OFF the internal FET within 310 ns (typical) as
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soon as V(IN) – V(OUT) falls below –2.6 V. The reverse comparator turns on within 63 µs (typical) after the
differential forward voltage V(IN)– V(OUT) exceeds 115 mV. 图 9-13 and 图 9-14 illustrate the behavior of the
system during input hot short circuit condition.
图9-13. Input Hot Short Functionality at 24-V
图9-14. Hot-Short: Fast-Trip Response (Zoomed)
Supply
The reverse comparator architecture has a supply line noise immunity resulting in a robust performance in noisy
environments. This feature is achieved by controlling the turn OFF time of the internal FET based on the over-
drive differential voltage V(IN) – V(OUT) over V(REVTH). Higher the over-drive, faster the turn OFF time, tREV(dly)
.
Figure 7-22 shows the reverse current blocking response time versus over-drive voltage.
9.3.7 FAULT Response
The FLT open-drain output asserts (active low) under the following conditions:
• Fault events such as undervoltage, overvoltage, over load, reverse current and thermal shutdown conditions
• The device enters low current shutdown mode when SHDN is pulled low
• During start-up when the internal FET GATE is not fully enhanced
The device is designed to eliminate false reporting by using an internal de-glitch circuit for fault conditions
without the need for an external circuitry.
The FLT signal can also be used as a Power Good indicator to the downstream loads like DC/DC converters. An
internal Power Good (PGOOD) signal is ORd with the fault logic. During start-up, when the device is operating in
dVdT mode, PGOOD and FLT it remains low and is de-asserted after the dVdT mode is completed and the
internal FET is fully enhanced. The PGOOD signal has deglitch time incorporated to ensure that internal FET is
fully enhanced before heavy load is applied by the downstream converters. Rising deglitch delay is determined
by tPGOOD(degl) = Maximum {(750 + 573× C(dVdT)), tPGOODR}, where C(dVdT) is in nF and tPGOOD(degl) is in µs. FLT
can be left open or connected to RTN when not used. V(IN) falling below 3.4 V resets FLT.
9.3.8 IN, OUT, RTN, and GND Pins
TI recommends a ceramic bypass capacitor close to the device from IN to GND to alleviate bus transients. The
recommended input operating voltage range is 4.5 to 60 V. V(OUT), in the ON condition, is calculated using 方程
式4.
V
(
OUT
)
= V
(
IN
)
- RON ì I
(
(
OUT
)
)
(4)
Where,
• RON is the total ON resistance of the internal FETs.
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GND pin must be connected to the system ground. RTN is the device ground reference for all the internal control
blocks. Connect the TPS2662x family support components: R(ILIM), C(dVdT) and resistors for UVLO and OVP with
respect to the RTN pin. Internally, the device has reverse input polarity protection block between RTN and the
GND terminal. Connecting RTN pin to GND pin disables the reverse polarity protection feature and the
TPS2662x gets permanently damaged when operated under this fault event.
9.3.9 Thermal Shutdown
The device has a built-in overtemperature shutdown circuitry designed to protect the internal FETs, if the junction
temperature exceeds T(TSD). After the thermal shutdown event, depending upon the mode of fault response, the
device either latches off or commences an auto-retry cycle 512 ms after TJ < (T(TSD) – 13.5°C). During the
thermal shutdown, the fault pin FLT pulls low to indicate a fault condition.
9.4 Device Functional Modes
9.4.1 Low Current Shutdown Control (SHDN)
The internal FETs and the load current can be switched off by pulling the SHDN pin below 0.9-V threshold with a
micro-controller GPIO pin or can be controlled remotely with an opto-isolator device as shown in 图 9-15 and 图
9-16. The device quiescent current reduces to 10 μA (typical) in SHUTDOWN state. To assert SHDN low, the
pull down must sink at least 10 µA at 400 mV. To enable the device, SHDN must be pulled up to at least 1.8 V.
After the device is enabled, the internal FETs turn on with dVdT mode.
ON OFF
TPS2662x
AVdd
Rpu
TPS2662x
AVdd
Rpu
SHDN
GND
SHDN
+
SHDNb
from µC GPIO
+
SHDNb
a
k
C
E
0.9V
0.9 V
œ
Opto Isolator
GND
OFF
ON
图9-15. Shutdown Control
图9-16. Opto-Isolator Shutdown Control
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10 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
10.1 Application Information
The TPS2662x family is an industrial eFuse, typically used for Hot-Swap and power rail protection applications.
The device operates from 4.5 V to 60 V with programmable current limit, overvoltage, undervoltage and reverse
polarity protections. The device aids in controlling inrush current and provides robust protection against reverse
current and field miss-wiring conditions for systems such as PLC I/O modules and sensor power supplies. The
device also provides robust protection for multiple faults on the system rail.
The Detailed Design Procedure section can be used to select component values for the device.
Alternatively, the WEBENCH® software can be used to generate a complete design. The WEBENCH® software
uses an iterative design procedure and accesses a comprehensive database of components when generating a
design. Additionally, a spreadsheet design tool, TPS2662 Design Calculator, is available in the web product
folder.
10.2 Typical Application
IN: 18 V-30 V
OUT
IN
OUT
COUT
22 µF
CIN
1 µF
R1
715 k
RFLTb
100 k
478 mꢀ
UVLO
OVP
Health Monitor
TPS2662x
R2
20 k
FLT
ON/OFF Control
SHDN
dVdT
RTN
ILIM
R3
30.1 k
CdVdT
GND
RILIM
13.3 k
10 nF
图10-1. 24-V, 500-mA eFuse Input Protection Circuit for PLC I/O Module
10.2.1 Design Requirements
表10-1 shows the design requirements for TPS2662x.
表10-1. Design Requirements
DESIGN PARAMETER
EXAMPLE VALUE
24 V
V(IN)
V(UV)
V(OV)
T(SU)
I(LIM)
C(OUT)
TA
Typical input voltage
Undervoltage lockout set point
Overvoltage cutoff set point
Load during start-up
18 V
30 V
96 Ω
Current limit
500 mA
22 µF
Load capacitance
Maximum ambient temperature
125°C
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10.2.2 Detailed Design Procedure
10.2.2.1 Step-by-Step Design Procedure
To begin the design process, the designer must know the following parameters:
• Input operating voltage range
• Maximum output capacitance
• Maximum current limit
• Load during start-up
• Maximum ambient temperature
This design procedure below seeks to control junction temperature of the device in both steady state and
start-up conditions by proper selection of the output ramp-up time and associated support components. The
designer can adjust this procedure to fit the application and design criteria.
10.2.2.2 Programming the Current Limit Threshold R(ILIM) Selection
The R(ILIM) resistor at the ILIM pin sets the over load current limit. the current limit can be set using 方程式5.
6.636
RILIM
=
= 13.27 kW
ILIM
(5)
where
• ILIM = 500 mA
Choose the closest standard 1% resistor value: R(ILIM) = 13.3 kΩ.
10.2.2.3 Undervoltage Lockout and Overvoltage Set Point
The undervoltage lockout (UVLO) and overvoltage trip point are adjusted using an external voltage divider
network of R1, R2 and R3 connected between IN, UVLO, OVP and RTN pins of the device. The values required
for setting the undervoltage and overvoltage are calculated by solving 方程式6 and 方程式7.
R3
V(OVPR) =
ì V(OV)
R1+ R2 + R3
(6)
R2 + R3
R1+ R2 + R3
V(UVLOR) =
ì V(UV)
(7)
For minimizing the input current drawn from the power supply {I(R123) = V(IN) / (R1+R2+R3)}, TI recommends to
use higher value resistance for R1, R2 and R3.
However, the leakage current due to external active components connected at resistor string can add error to
these calculations. So, the resistor string current, I(R123) must be chosen to be 20 times greater than the leakage
current of UVLO and OVP pins.
From the device electrical specifications, V(OVPR) = 1.19 V and V(UVLOR) = 1.19 V. From the design requirements,
V(OV) is 30 V and V(UV) is 18 V. To solve the equation, first choose the value of R3 = 30.1 kΩ and use 方程式 6 to
solve for (R1 + R2) = 728.7 kΩ. Use 方程式 7 and value of (R1 + R2) to solve for R2 = 20.05 kΩ and finally R1=
708.6 kΩ.
Choose the closest standard 1% resistor values: R1 = 715 kΩ, R2 = 20 kΩ, and R3 = 30.1 kΩ.
10.2.2.4 Setting Output Voltage Ramp Time—(tdVdT
)
For a successful design, the junction temperature of the device must be kept below the absolut -maximum rating
during dynamic (start-up) and steady state conditions. The dynamic power dissipation is often an order
magnitude greater than the steady state power dissipation. It is important to determine the right start-up time and
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the inrush current limit for the system to avoid thermal shutdown during start-up with and without load. The ramp-
up capacitor C(dVdT) is calculated considering the two possible cases:
10.2.2.4.1 Case 1: Start-Up Without Load—Only Output Capacitance C(OUT) Draws Current During Start-Up
During start-up, as the output capacitor charges, the voltage difference across the internal FET decreases, and
the power dissipation decreases. Typical ramp-up of the output voltage, inrush current and instantaneous power
dissipated in the device during start-up are shown in Figure 10-2. The average power dissipated in the device
during start-up is equal to the area of triangular plot (red curve in Figure 10-3) averaged over tdVdT
.
2
24
18
12
6
Input Current (A)
Power Dissipation (W)
Output Voltage (V)
1.5
1
0.5
0
0
0
20
40 60
Start-up Time, tdVdT (%)
80
100
D029
VIN = 24 V
CdVdT = 10 nF
COUT = 22 µF
VIN = 24 V
CdVdT = 10 nF
COUT = 22 µF
图10-3. PD(INRUSH) Due to Inrush Current
图10-2. Start-Up Without Load
The inrush current is determined as shown in 方程式8.
dV
dT
V(IN)
tdVdT
I = C ì
í I(INRUSH) = C(OUT) ì
(8)
(9)
Average power dissipated during start-up is given by 方程式9.
PD(INRUSH) = 0.5ì V(IN) ìI(INRUSH)
方程式9 assumes that the load does not draw any current until the output voltage reaches its final value.
10.2.2.4.2 Case 2: Start-Up With Load —Output Capacitance C(OUT) and Load Draws Current During Start-Up
When the load draws current during the turn-on sequence, additional power is dissipated in the device.
Considering a resistive load RL(SU) during start-up, typical ramp-up of output voltage, Figure 10-4 shows load
current and the instantaneous power dissipation in the device. Figure 10-5 plots Instantaneous power dissipation
with respect to time.
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5
4.5
4
30
Input Current (A)
Power Dissipation (W)
Output Voltage (V)
27
24
21
18
15
12
9
3.5
3
2.5
2
1.5
1
6
0.5
0
3
0
0
20
40 60
Start-up Time, tdVdT (%)
80
100
D030
VIN = 24 V
RL (SU) = 96 Ω
VIN = 24 V
CdVdT = 10 nF
RL (SU) = 96 Ω
CdVdT = 10 nF
COUT = 22 µF
COUT = 22 µF
图10-4. Start-Up With Load
图10-5. PD(INRUSH) Due to Inrush and Load Current
The additional power dissipation during start-up is calculated using 方程式10.
1
6
V(IN)2
PD(LOAD) =
ì
RL(SU)
(10)
(11)
(12)
Total power dissipated in the device during start-up is given by 方程式11.
PD(STARTUP) = PD(INRUSH) + PD(LOAD)
Total current during start-up is given by 方程式12.
I(STARTUP) = I(INRUSH) + IL(t)
For the design example under discussion,
Select the inrush current I(INRUSH) = 0.1 A and tdVdT calculated using 方程式8 is 5.28 ms.
For a given start-up time, CdVdT capacitance value calculated using 方程式 2 is 10.7 nF for tdVdT = 5.28 ms and
VIN = 24 V.
Choose the closest standard value: 10.0 nF and 16-V capacitor.
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The inrush power dissipation due to output capacitor alone is calculated using 方程式 9 and it is 1.2 W.
Considering the start-up with 96-Ω load, the additional power dissipation calculated using 方程式 10 is 1 W. The
total device power dissipation during start-up is 2.2 W
The power dissipation with or without load, for a selected start-up time must not exceed the thermal shutdown
limits as shown in 图10-6.
From the thermal shutdown limit graph, at TA = 125°C, thermal shutdown time for 2.2 W is close to 580 ms. It is
safe to have a minimum 30% margin to allow for variation of the system parameters such as load, component
tolerance, input voltage and layout. Selected 10-nF CdVdT capacitor and 5.28-ms start-up time (tdVdT) are well
within the limit for successful start-up with 96-Ω load.
Higher value C(dVdT) capacitor can be selected to further reduce the power dissipation during start-up.
100000
Temp = -40èC
Temp = 25èC
10000
Temp = 85èC
Temp = 105èC
Temp = 125èC
1000
100
10
1
0.2
1
10
Power Dissipation (W)
50
D025
图10-6. Thermal Shutdown Time vs Power Dissipation
10.2.2.4.3 Support Component Selections –RFLT and C(IN)
The RFLT Absolute Maximum Ratings serves as pull-up for the open-drain fault output. The current sink by this
pin must not exceed 10 mA (see the Absolute Maximum Ratings table). TI recommends typical resistance value
in the range of 10 kΩ to 100 kΩ for RFLT. The CIN is a local bypass capacitor to suppress noise at the input. TI
recommends typical capacitance value in the range of 0.1 µF to 1 µF for C(IN)
.
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10.2.3 Application Curves
VIN
VIN
VOUT
VOUT
FLTb
FLTb
IIN
IIN
图10-7. Hot Plug With VIN –No Load
图10-8. Hot-Plug With VIN –96-Ω Load
图10-9. Start-Up With Shutdown Pin –96-Ω Load
图10-10. Power Down With Shutdown Pin –96-Ω
Load
VIN
VIN
VOUT
VOUT
FLTb
FLTb
IIN
IIN
图10-11. Over Load Response –Load Stepped
From 136-Ω to 36-Ω Load
图10-12. Turn ON With Short Circuit on Output
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10.3 System Examples
10.3.1 Field Supply Protection in PLC, DCS I/O Modules
TPS26624 / TPS26625
24-V nominal (from field
SELV power supply)
IN
Power FET isolation during over
OUT
To Field Loads
(Sensors & Actuators)
Inrush Current
Control
voltage , Input Reverse Polarity,
Output Reverse Polarity and short
circuit faults
Fault Diagnostics
SHDN
FLT
FLT
ON/OFF
Control
Fault
DC/DC
MCU
Field side
PLC side
Digital Isolator
图10-13. Power Delivery Circuit Block Diagram in I/O Modules
The PLC or Distributed Control System (DCS) I/O modules are often connected to an external field power supply
to support higher power requirements of the field loads like sensors and actuators. Power-supply faults or
miswiring can damage the loads or cause the loads not to operate correctly. The TPS26624 and TPS26625 can
be used as a front end protection circuit to protect and provide stable supply to the field loads. Undervoltage,
overvoltage, and input and output side reverse polarity protection features of these devices prevent the loads to
experience voltages outside the operating range, which can permanently damage the loads.
Field power supply is often connected to multiple I/O modules that can deliver more current than a single I/O
module can handle. Overcurrent protection scheme of the TPS2662x family limits the current from the power
supply to the module so that the maximum current does not rise above what the board is designed for. Fast
short-circuit protection scheme isolates the faulty load from the field supply quickly and prevents the field supply
to dip and cause interrupts in the other I/O modules connected to the same field supply. High accurate (±5% at
0.88 A) current limit facilitates more I/O modules to be connected to field supply. Fault indication ( FLT) features
facilitate continuous load monitoring.
The TPS26624 and TPS26625 also acts as a smart diode with protection against reverse current during output
side miswiring. Reverse current can potentially damage the field power supply and cause the I/O modules to run
hot or can cause permanent damage.
If the field power supply is connected in reverse polarity on the input side (which is not unlikely as field power
supplies are usually connected with screw terminals), field loads can permanently get damaged due to the
reverse voltage. Also, during the installation the field power supply can be miswired on the output side instead of
on the input side which can damage the upstream power supply and electronics. The input and output reverse
polarity protection feature of the TPS26624 and TPS26625 prevents the reverse voltage to appear at the load
side as well as supply side offering complete system protection during field miswiring.
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10.3.2 Simple 24-V Power Supply Path Protection
With the TPS2662x, a simple 24-V power supply path protection can be realized using a minimum of four
external components as shown in the schematic diagram in 图 10-14. The external components required are: a
1Meg Ω R(1) resistor across IN and UVLO pins, a R(ILIM) resistor to program the current limit, C(IN) and C(OUT)
capacitors.
System Load
VOUT
COUT
OUT
IN
CIN
R1
1Meg
478 mΩ
Input from a 24V
power supply
UVLO
OVP
FLT
TPS2662x
SHDN
dVdT
RTN
ILIM
GND
RILIM
图10-14. TPS2662x Configured for a Simple 24-V Supply Path Protection
Protection features with this configuration include:
• Load and device protection from reverse input polarity fault down to –60 V
• Upstream supply and device protection from reverse output polarity fault down to –(60 –VIN) V with
TPS26624 and TPS26625 variants
• Protection from 60 V from the external SELV supply: overvoltage Clamp at 38 V with TPS26622 and
TPS26623 variants
• Inrush current control with 24 V and 660-µs output voltage slew rate
• Reverse Current Blocking
• Accurate current limiting with auto-retry with TPS26621, TPS26623, TPS26625 variants
• Accurate current limiting with latch-off with TPS26620, TPS26622, TPS26624 variants
10.3.3 Power Stealing in Smart Thermostat
The adjustable protection features of the TPS2662x eFuse, like the inrush current limiting, overvoltage and
overcurrent protection, simplifies the input power management design in smart thermostats. Refer to the TI
Design report, Power Stage Reference Design for Power Stealing Thermostat, for further information.
10.4 Do's and Don'ts
• Do not connect RTN to GND. Connecting RTN to GND disables the Reverse Polarity protection feature.
• Do connect the TPS2662x support components R(ILIM), C(dVdT), and UVLO, OVP resistors with respect to
RTN pin.
• Do connect device PowerPAD to the RTN plane for an enhanced thermal performance.
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11 Power Supply Recommendations
The TPS2662x eFuse is designed for the supply voltage range of 4.5 V ≤ VIN ≤ 60 V. If the input supply is
located more than a few inches from the device, TI recommends an input ceramic bypass capacitor higher than
0.1 μF. Power supply must be rated higher than the current limit set to avoid voltage droops during overcurrent
and shor-circuit conditions.
11.1 Transient Protection
In case of short circuit and over load current limit, when the device interrupts current flow, input inductance
generates a positive voltage spike on the input and output inductance generates a negative voltage spike on the
output. The peak amplitude of voltage spikes (transients) depends on the value of inductance in series to the
input or output of the device. These transients can exceed the Absolute Maximum Ratings of the device if steps
are not taken to address the issue.
Typical methods for addressing transients include:
• Minimizing lead length and inductance into and out of the device
• Using large PCB GND plane
• Use of a Schottky diode across the output and GND to absorb negative spikes in the designs with TPS26620,
TPS26621, TPS26622, TPS26623 devices and a TVS clamp in the designs withTPS26624 and TPS26625
devices
• A low value ceramic capacitor (C(IN) to approximately 0.1 μF) to absorb the energy and dampen the
transients.
The approximate value of input capacitance can be estimated with 方程式13.
L IN
( )
Vspike Absolute = V IN + I Load
( ) )
´
(
)
(
C IN
( )
(13)
where
• V(IN) is the nominal supply voltage
• I(LOAD) is the load current
• L(IN) equals the effective inductance seen looking into the source
• C(IN) is the capacitance present at the input
Some applications can require additional Transient Voltage Suppressor (TVS) to prevent transients from
exceeding the Absolute Maximum Ratings of the device. These transients can occur during positive and
negative surge tests on the supply lines. In such applications TI recommends to place at least 1 µF of input
capacitor to limit the falling slew rate of the input voltage within a maximum of 20 V/µs.
The circuit implementation with optional protection components (a ceramic capacitor, TVS and Schottky diode) is
shown in Figure 11-1 and Figure 11-2.
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INPUT
IN
OUT
OUTPUT
CIN
COUT
R4
R1
478 mꢀ
UVLO
OVP
FLT
*
*
SHDN
R2
TPS26620/1/2/3
dVdT
RTN
ILIM
GND
R3
RILIM
CdVdT
* Optional components needed for suppression of transients
图11-1. Circuit Implementation With Optional Protection Components for TPS26620, TPS26621,
TPS26622, and TPS26623
INPUT
IN
OUT
OUTPUT
CIN
COUT
R4
R1
R2
478 mꢀ
UVLO
OVP
FLT
*
*
TPS26624/5
SHDN
dVdT
RTN
ILIM
GND
R3
RILIM
CdVdT
* Optional components needed for suppression of transients
图11-2. Circuit Implementation With Optional Protection Components for TPS26624 and TPS26625
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12 Layout
12.1 Layout Guidelines
• For all the applications, TI recommends a 0.1 µF or higher value ceramic decoupling capacitor between IN
terminal and GND.
• The optimum placement of decoupling capacitor is closest to the IN and GND terminals of the device. Care
must be taken to minimize the loop area formed by the bypass-capacitor connection, the IN terminal, and the
GND terminal of the IC. See 图12-1 for a typical PCB layout example.
• High current carrying power path connections must be as short as possible and must be sized to carry at
least twice the full-load current.
• RTN, which is the reference ground for the device must be a copper plane or island.
• Locate all the TPS2662x family support components R(ILIM), C(dVdT), UVLO, OVP resistors close to their
connection pin. Connect the other end of the component to the RTN with shortest trace length.
• The trace routing for the RILIM component to the device must be as short as possible to reduce parasitic
effects on the current limit and current monitoring accuracy. These traces must not have any coupling to
switching signals on the board.
• Protection devices such as TVS, snubbers, capacitors, or diodes must be placed physically close to the
device they are intended to protect, and routed with short traces to reduce inductance. For example, TI
recommends a protection Schottky diode to address negative transients due to switching of inductive loads,
and it must be physically close to the OUT and GND pins.
• Thermal considerations: when properly mounted, the PowerPAD package provides significantly greater
cooling ability. To operate at rated power, the PowerPAD must be soldered directly to the board RTN plane
directly under the device. Other planes, such as the bottom side of the circuit board can be used to increase
heat sinking in higher current applications. Designs that do not need reverse input polarity protection can
have RTN, GND and PowerPAD connected together. PowerPAD in these designs can be connected to the
PCB ground plane.
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
35
Product Folder Links: TPS2662
TPS2662
www.ti.com.cn
ZHCSI22F –OCTOBER 2017 –REVISED DECEMBER 2021
12.2 Layout Example
Top Layer
Bottom layer GND plane
Top Layer RTN Plane
Bottom Layer RTN Plane
Via to Bottom Layer
Track in bottom layer
BOTTOM Layer GND Plane
Top Layer
Power GND Plane
High
Frequency
Bypass cap
VOUT PLANE
VIN PLANE
OUT
FLT
IN
UVLO
OVP
dVdT
SHDN
RTN
ILIM
GND
TOP Layer
RTN Plane
BOTTOM Layer RTN Plane
图12-1. Typical PCB Layout Example With a 2 Layer PCB
Copyright © 2022 Texas Instruments Incorporated
36
Submit Document Feedback
Product Folder Links: TPS2662
TPS2662
www.ti.com.cn
ZHCSI22F –OCTOBER 2017 –REVISED DECEMBER 2021
13 Device and Documentation Support
13.1 Documentation Support
13.1.1 Related Documentation
• Texas Instruments, Power Stage Reference Design for Power Stealing Thermostat design guide
13.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
13.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
13.4 Trademarks
PowerPAD™ and TI E2E™ are trademarks of Texas Instruments.
WEBENCH® is a registered trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
13.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
13.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
37
Product Folder Links: TPS2662
PACKAGE OPTION ADDENDUM
www.ti.com
12-Apr-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS26620DRCR
TPS26620DRCT
TPS26621DRCR
TPS26621DRCT
TPS26622DRCR
TPS26622DRCT
TPS26623DRCR
TPS26623DRCT
TPS26624DRCR
TPS26624DRCT
TPS26625DRCR
TPS26625DRCT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
VSON
VSON
VSON
VSON
VSON
VSON
VSON
VSON
VSON
VSON
VSON
VSON
DRC
DRC
DRC
DRC
DRC
DRC
DRC
DRC
DRC
DRC
DRC
DRC
10
10
10
10
10
10
10
10
10
10
10
10
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
ED00
ED00
ED01
ED01
ED02
ED02
ED03
ED03
ED04
ED04
ED05
ED05
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
12-Apr-2023
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS26620DRCR
TPS26620DRCT
TPS26621DRCR
TPS26621DRCT
TPS26622DRCR
TPS26622DRCT
TPS26623DRCR
TPS26623DRCT
TPS26624DRCR
TPS26624DRCT
TPS26625DRCR
TPS26625DRCT
VSON
VSON
VSON
VSON
VSON
VSON
VSON
VSON
VSON
VSON
VSON
VSON
DRC
DRC
DRC
DRC
DRC
DRC
DRC
DRC
DRC
DRC
DRC
DRC
10
10
10
10
10
10
10
10
10
10
10
10
3000
250
330.0
180.0
330.0
180.0
330.0
180.0
330.0
180.0
330.0
180.0
330.0
180.0
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.1
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
3000
250
3000
250
3000
250
3000
250
3000
250
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS26620DRCR
TPS26620DRCT
TPS26621DRCR
TPS26621DRCT
TPS26622DRCR
TPS26622DRCT
TPS26623DRCR
TPS26623DRCT
TPS26624DRCR
TPS26624DRCT
TPS26625DRCR
TPS26625DRCT
VSON
VSON
VSON
VSON
VSON
VSON
VSON
VSON
VSON
VSON
VSON
VSON
DRC
DRC
DRC
DRC
DRC
DRC
DRC
DRC
DRC
DRC
DRC
DRC
10
10
10
10
10
10
10
10
10
10
10
10
3000
250
367.0
210.0
367.0
210.0
367.0
210.0
367.0
210.0
367.0
210.0
367.0
210.0
367.0
185.0
367.0
185.0
367.0
185.0
367.0
185.0
367.0
185.0
367.0
185.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
3000
250
3000
250
3000
250
3000
250
3000
250
Pack Materials-Page 2
GENERIC PACKAGE VIEW
DRC 10
3 x 3, 0.5 mm pitch
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4226193/A
www.ti.com
PACKAGE OUTLINE
DRC0010J
VSON - 1 mm max height
SCALE 4.000
PLASTIC SMALL OUTLINE - NO LEAD
3.1
2.9
B
A
PIN 1 INDEX AREA
3.1
2.9
1.0
0.8
C
SEATING PLANE
0.08 C
0.05
0.00
1.65 0.1
2X (0.5)
(0.2) TYP
EXPOSED
THERMAL PAD
4X (0.25)
5
6
2X
2
11
SYMM
2.4 0.1
10
1
8X 0.5
0.30
0.18
10X
SYMM
PIN 1 ID
0.1
C A B
C
(OPTIONAL)
0.05
0.5
0.3
10X
4218878/B 07/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
DRC0010J
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(1.65)
(0.5)
10X (0.6)
1
10
10X (0.24)
11
(2.4)
(3.4)
SYMM
(0.95)
8X (0.5)
6
5
(R0.05) TYP
(
0.2) VIA
TYP
(0.25)
(0.575)
SYMM
(2.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
EXPOSED METAL
EXPOSED METAL
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
SOLDER MASK
DEFINED
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4218878/B 07/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
DRC0010J
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
2X (1.5)
(0.5)
SYMM
EXPOSED METAL
TYP
11
10X (0.6)
1
10
(1.53)
10X (0.24)
2X
(1.06)
SYMM
(0.63)
8X (0.5)
6
5
(R0.05) TYP
4X (0.34)
4X (0.25)
(2.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 11:
80% PRINTED SOLDER COVERAGE BY AREA
SCALE:25X
4218878/B 07/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
重要声明和免责声明
TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，
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保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。
您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成
本、损失和债务，TI 对此概不负责。
TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改
TI 针对 TI 产品发布的适用的担保或担保免责声明。
TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2023，德州仪器 (TI) 公司
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