TPS2814DR [TI]
DUAL HIGH-SPEED MOSFET DRIBERS; 双高速MOSFET DRIBERS
| 型号： | TPS2814DR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | DUAL HIGH-SPEED MOSFET DRIBERS |
| 文件： | 总38页 (文件大小：1475K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ꢀ ꢁꢂꢃ ꢄ ꢅꢅ ꢆ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢃ ꢆ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢇ ꢆ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢈ ꢆ ꢀꢁ ꢂ ꢃꢄ ꢅꢉ
ꢊꢋꢌ ꢍ ꢎꢏ ꢐꢎ ꢑꢂꢁꢒ ꢒꢊ ꢓ ꢔꢂ ꢕꢒ ꢀ ꢊ ꢖꢏ ꢗ ꢒꢖ ꢂ
SLVS132F − NOVEMBER 1995 − REVISED OCTOBER 2004
TPS2811, TPS2812, TPS2813 . . . D, P, AND PW
D
D
Industry-Standard Driver Replacement
25-ns Max Rise/Fall Times and 40-ns Max
PACKAGES
(TOP VIEW)
Propagation Delay − 1-nF Load, V
= 14 V
CC
REG_IN
1IN
REG_OUT
1OUT
1
2
3
4
8
7
6
5
D
D
D
2-A Peak Output Current, V
= 14 V
CC
5-µA Supply Current — Input High or Low
GND
2IN
V
CC
4-V to 14-V Supply-Voltage Range; Internal
Regulator Extends Range to 40 V (TPS2811,
TPS2812, TPS2813)
2OUT
TPS2814 . . . D, P, AND PW PACKAGES
D
−40°C to 125°C Ambient-Temperature
Operating Range
(TOP VIEW)
1IN1
1IN2
2IN1
2IN2
GND
1
2
3
4
8
7
6
5
description
1OUT
V
CC
The TPS28xx series of dual high-speed MOSFET
drivers are capable of delivering peak currents of 2 A
into highly capacitive loads. This performance is
achieved with a design that inherently minimizes
shoot-through current and consumes an order of
magnitude less supply current than competitive
products.
2OUT
TPS2815 . . . D, P, AND PW PACKAGES
(TOP VIEW)
1IN1
1IN2
2IN1
2IN2
GND
1
2
3
4
8
7
6
5
1OUT
The TPS2811, TPS2812, and TPS2813 drivers include
a regulator to allow operation with supply inputs
between 14 V and 40 V. The regulator output can power
other circuitry, provided power dissipation does
V
CC
2OUT
not exceed package limitations. When the regulator is not required, REG_IN and REG_OUT can be left disconnected
or both can be connected to V or GND.
CC
The TPS2814 and the TPS2815 have 2-input gates that give the user greater flexibility in controlling the MOSFET.
The TPS2814 has AND input gates with one inverting input. The TPS2815 has dual-input NAND gates.
TPS281x series drivers, available in 8-pin PDIP, SOIC, and TSSOP packages operate over a ambient temperature
range of −40°C to 125°C.
AVAILABLE OPTIONS
PACKAGED DEVICES
INTERNAL
REGULATOR
SMALL
OUTLINE
(D)
PLASTIC
DIP
T
A
LOGIC FUNCTION
TSSOP (PW)
(P)
Dual inverting drivers
Dual noninverting drivers
One inverting and one noninverting driver
TPS2811D TPS2811P TPS2811PW
TPS2812D TPS2812P TPS2812PW
TPS2813D TPS2813P TPS2813PW
Yes
No
−40°C
to
125°C
TPS2814D TPS2814P TPS2814PW
Dual 2-input AND drivers, one inverting input on each driver
Dual 2-input NAND drivers
TPS2815D TPS2815P TPS2815PW
The D package is available taped and reeled. Add R suffix to device type (e.g., TPS2811DR). The PW package is only available left-end
taped and reeled and is indicated by the R suffix on the device type (e.g., TPS2811PWR).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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Copyright 2002, Texas Instruments Incorporated
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SLVS132F − NOVEMBER 1995 − REVISED OCTOBER 2004
regulator diagram (TPS2811, TPS2812,
functional block diagram
TPS2813 only)
REG_IN
TPS2811
1
2
8
6
Regulator
REG_OUT
REG_IN
1IN
V
CC
7
5
1OUT
2OUT
4
3
2IN
GND
7.5 Ω
REG_OUT
TPS2812
Regulator
1
2
8
6
REG_OUT
REG_IN
1IN
V
CC
7
5
1OUT
2OUT
4
3
2IN
GND
input stage diagram
V
CC
TPS2813
Regulator
1
2
8
6
REG_OUT
REG_IN
1IN
V
CC
7
5
1OUT
2OUT
4
3
2IN
To Drive
Stage
IN
GND
TPS2814
6
7
V
CC
1
2
1IN1
1IN2
1OUT
2OUT
3
4
2IN1
2IN2
5
output stage diagram
V
CC
8
GND
Predrive
TPS2815
6
7
V
CC
1
2
1IN1
1IN2
1OUT
2OUT
3
4
8
OUT
2IN1
2IN2
GND
5
2
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ꢀ ꢁꢂꢃ ꢄ ꢅꢅ ꢆ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢃ ꢆ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢇ ꢆ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢈ ꢆ ꢀꢁ ꢂ ꢃꢄ ꢅꢉ
ꢊꢋꢌ ꢍ ꢎꢏ ꢐꢎ ꢑꢂꢁꢒ ꢒꢊ ꢓ ꢔꢂ ꢕꢒ ꢀ ꢊ ꢖꢏ ꢗ ꢒꢖ ꢂ
SLVS132F − NOVEMBER 1995 − REVISED OCTOBER 2004
TPS28xxY chip information
This chip, when properly assembled, displays characteristics similar to those of the TPS28xx. Thermal compression
or ultrasonic bonding may be used on the doped aluminum bonding pads. The chip may be mounted with conductive
epoxy or a gold-silicon preform.
BONDING PAD ASSIGNMENTS
(8)
(8)
(7)
REG_OUT
1OUT
(1)
(2)
(4)
REG_IN
1IN
TPS2811Y
TPS2812Y
TPS2813Y
(6)
(5)
(1)
V
CC
2IN
2OUT
(3)
(7)
GND
(1)
(2)
(2)
(7)
(6)
1IN1
1IN2
1OUT
V
CC
TPS2814Y
(3)
(4)
2IN1
2IN2
(5)
2OUT
(8)
57
(6)
GND
(1)
(2)
(7)
(6)
1IN1
1IN2
1OUT
(3)
TPS2815Y
V
CC
(3)
(4)
2IN1
2IN2
(5)
2OUT
(5)
(8)
GND
(4)
CHIP THICKNESS: 15 MILS TYPICAL
BONDING PADS: 4 × 4 MILS MINIMUM
47
T max OPERATING TEMPERATURE = 150°C
J
TOLERANCES ARE 10%.
ALL DIMENSIONS ARE IN MILS.
3
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ꢀ ꢁ ꢂ ꢃ ꢄꢅꢅ ꢆ ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢃ ꢆ ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢇ ꢆ ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢈ ꢆ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢉ
ꢊ ꢋꢌꢍ ꢎ ꢏ ꢐꢎꢑꢂ ꢁꢒꢒ ꢊ ꢓꢔ ꢂꢕ ꢒ ꢀ ꢊꢖ ꢏ ꢗꢒ ꢖꢂ
SLVS132F − NOVEMBER 1995 − REVISED OCTOBER 2004
Terminal Functions
TPS2811, TPS2812, TPS2813
TERMINAL NUMBERS
TPS2812
Dual Noninverting
Drivers
TERMINAL
NAME
TPS2811
Dual Inverting
Drivers
TPS2813
Complimentary
Drivers
DESCRIPTION
REG_IN
1
1
1
Regulator input
Input 1
1IN
2
2
2
GND
2IN
3
3
3
Ground
4
5 = 2IN
6
4
5 = 2IN
6
4
5 = 2IN
6
Input 2
2OUT
Output 2
V
CC
Supply voltage
Output 1
1OUT
7 = 1IN
8
7 = 1IN
8
7 = 1IN
8
REG_OUT
Regulator output
TPS2814, TPS2815
TERMINAL NUMBERS
TERMINAL
NAME
TPS2814
Dual AND Drivers with Single
Inverting Input
DESCRIPTION
TPS2815
Dual NAND Drivers
1IN1
1IN2
1IN2
2IN1
2IN2
2IN2
1
1
Noninverting input 1 of driver 1
Inverting input 2 of driver 1
Noninverting input 2 of driver 1
Noninverting input 1 of driver 2
Inverting input 2 of driver 2
Noninverting input 2 of driver 2
Output 2
2
-
-
2
3
3
4
-
-
4
2OUT
5 = 2IN1 • 2IN2
5 = 2IN1 • 2IN2
V
CC
6
6
Supply voltage
1OUT
GND
7 = 1IN1 • 1IN2
7 = 1IN1 • 1IN2
Output 1
8
8
Ground
DISSIPATION RATING TABLE
DERATING FACTOR
T
≤ 25°C
T
A
= 70°C
T = 85°C
A
A
PACKAGE
POWER RATING
ABOVE T = 25°C
POWER RATING POWER RATING
A
P
D
1090 mW
8.74 mW/°C
5.84 mW/°C
4.17 mW/°C
697 mW
467 mW
332 mW
566 mW
380 mW
270 mW
730 mW
PW
520 mW
4
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ꢀ ꢁꢂꢃ ꢄ ꢅꢅ ꢆ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢃ ꢆ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢇ ꢆ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢈ ꢆ ꢀꢁ ꢂ ꢃꢄ ꢅꢉ
ꢊꢋꢌ ꢍ ꢎꢏ ꢐꢎ ꢑꢂꢁꢒ ꢒꢊ ꢓ ꢔꢂ ꢕꢒ ꢀ ꢊ ꢖꢏ ꢗ ꢒꢖ ꢂ
SLVS132F − NOVEMBER 1995 − REVISED OCTOBER 2004
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 15 V
CC
Regulator input voltage range, REG_IN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
−0.3 V to 42 V
CC
Input voltage range, 1IN, 2IN, 1IN1, 1IN2, 1IN2, 2IN1, 2IN2, 2IN2 . . . . . . . . . . . . . . . . . −0.3 V to V
Output voltage range, 1OUT, 2OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 < V < V
+0.5 V
+0.5 V
CC
CC
Continuous regulator output current, REG_OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 mA
Continuous output current, 1OUT, 2OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Operating ambient temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 125°C
A
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
stg
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltages are with respect to device GND pin.
recommended operating conditions
MIN
8
MAX
40
UNIT
V
Regulator input voltage range
Supply voltage, V
CC
4
14
V
Input voltage, 1IN1, 1IN2, 1IN2, 2IN1, 2IN2, 2IN2, 1IN, 2IN
Continuous regulator output current, REG_OUT
Ambient temperature operating range
−0.3
0
V
V
CC
20
mA
°C
−40
125
TPS28xx electrical characteristics over recommended operating ambient temperature range,
= 10 V, REG_IN open for TPS2811/12/13, C = 1 nF (unless otherwise noted)
V
CC
L
inputs
†
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
4
UNIT
V
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 5 V
3.3
5.8
8.3
1.6
4.2
6.2
1.6
0.2
5
= 10 V
= 14 V
= 5 V
9
V
Positive-going input threshold voltage
Negative-going input threshold voltage
13
V
1
1
1
V
= 10 V
= 14 V
= 5 V
V
V
Input hysteresis
Input current
V
Inputs = 0 V or V
CC
−1
1
µA
pF
Input capacitance
10
†
Typicals are for T = 25°C unless otherwise noted.
A
outputs
†
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
UNIT
I
I
I
I
= −1 mA
= −100 mA
= 1 mA
9.75
8
9.9
9.1
0.18
1
O
O
O
O
High-level output voltage
Low-level output voltage
V
0.25
2
V
A
= 100 mA
Peak output current
†
V
= 10 V
2
CC
Typicals are for T = 25°C unless otherwise noted.
A
5
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ꢀ ꢁ ꢂ ꢃ ꢄꢅꢅ ꢆ ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢃ ꢆ ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢇ ꢆ ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢈ ꢆ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢉ
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SLVS132F − NOVEMBER 1995 − REVISED OCTOBER 2004
regulator (TPS2811/2812/2813 only)
PARAMETER
†
TEST CONDITIONS
14 ≤ REG_IN ≤ 40 V, 0 ≤ I ≤ 20 mA
MIN TYP
MAX
UNIT
V
Output voltage
10
9
11.5
9.6
13
O
Output voltage in dropout
†
I
O
= 10 mA,
REG_IN = 10 V
V
Typicals are for T = 25°C unless otherwise noted.
A
supply current
†
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
5
UNIT
µA
Supply current into V
CC
Inputs high or low
REG_IN = 20 V,
0.2
40
Supply current into REG_IN
REG_OUT open
100
µA
†
Typicals are for T = 25°C unless otherwise noted.
A
TPS28xxY electrical characteristics at T = 25°C, V
= 10 V, REG_IN open for TPS2811/12/13,
CC
A
C = 1 nF (unless otherwise noted)
L
inputs
PARAMETER
TEST CONDITIONS
MIN
TYP
3.3
5.8
8.2
1.6
3.3
4.2
1.2
0.2
5
MAX
UNIT
V
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 5 V
= 10 V
= 14 V
= 5 V
V
Positive-going input threshold voltage
Negative-going input threshold voltage
V
V
= 10 V
= 14 V
= 5 V
V
V
Input hysteresis
Input current
V
Inputs = 0 V or V
CC
µA
pF
Input capacitance
outputs
PARAMETER
TEST CONDITIONS
MIN
TYP
9.9
9.1
0.18
1
MAX
UNIT
I
O
I
O
I
O
I
O
= −1 mA
= −100 mA
= 1 mA
High-level output voltage
V
Low-level output voltage
Peak output current
V
A
= 100 mA
V
CC
= 10.5 V
2
regulator (TPS2811, 2812, 2813)
PARAMETER
TEST CONDITIONS
14 ≤ REG_IN ≤ 40 V, 0 ≤ I ≤ 20 mA
MIN
MIN
TYP
11.5
9.6
MAX
MAX
UNIT
V
Output voltage
O
Output voltage in dropout
I
O
= 10 mA,
REG_IN = 10 V
V
power supply current
PARAMETER
TEST CONDITIONS
TYP
0.2
40
UNIT
µA
Supply current into V
CC
Inputs high or low
REG_IN = 20 V,
Supply current into REG_IN
REG_OUT open
µA
6
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ꢀ ꢁꢂꢃ ꢄ ꢅꢅ ꢆ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢃ ꢆ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢇ ꢆ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢈ ꢆ ꢀꢁ ꢂ ꢃꢄ ꢅꢉ
ꢊꢋꢌ ꢍ ꢎꢏ ꢐꢎ ꢑꢂꢁꢒ ꢒꢊ ꢓ ꢔꢂ ꢕꢒ ꢀ ꢊ ꢖꢏ ꢗ ꢒꢖ ꢂ
SLVS132F − NOVEMBER 1995 − REVISED OCTOBER 2004
switching characteristics for all devices over recommended operating ambient temperature range,
REG_IN open for TPS2811/12/13, C = 1 nF (unless otherwise specified)
L
PARAMETER
TEST CONDITIONS
MIN
TYP
14
15
20
15
15
18
25
25
34
24
26
36
MAX
25
30
35
25
30
35
40
45
50
40
45
50
UNIT
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 14 V
= 10 V
= 5 V
t
t
t
t
Rise time
Fall time
ns
r
= 14 V
= 10 V
= 5 V
ns
ns
ns
f
= 14 V
= 10 V
= 5 V
Prop delay time high-to-low-level output
Prop delay time low-to-high-level output
PHL
PLH
= 14 V
= 10 V
= 5 V
PARAMETER MEASUREMENT INFORMATION
TPS2811
V
CC
+
1
8
Regulator
0.1 µF
4.7 µF
2
3
7
6
5
Input
Output
50 Ω
1 nF
4
NOTE A: Input rise and fall times should be ≤10 ns for accurate measurement of ac parameters.
Figure 1. Test Circuit For Measurement of Switching Characteristics
7
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ꢀ ꢁ ꢂ ꢃ ꢄꢅꢅ ꢆ ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢃ ꢆ ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢇ ꢆ ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢈ ꢆ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢉ
ꢊ ꢋꢌꢍ ꢎ ꢏ ꢐꢎꢑꢂ ꢁꢒꢒ ꢊ ꢓꢔ ꢂꢕ ꢒ ꢀ ꢊꢖ ꢏ ꢗꢒ ꢖꢂ
SLVS132F − NOVEMBER 1995 − REVISED OCTOBER 2004
PARAMETER MEASUREMENT INFORMATION
TPS2811
1
8
Regulator
2
3
7
6
5
0−10 V dc
xOUT
Current
Loop
V
CC
10 V
+
0.1 µF
4.7 µF
4
Figure 2. Shoot-through Current Test Setup
50%
50%
1IN
0 V
0 V
t
f
t
r
90%
90%
10%
50%
50%
1OUT
10%
t
t
PHL
PLH
Figure 3. Typical Timing Diagram (TPS2811)
TYPICAL CHARACTERISTICS
Tables of Characteristics Graphs and Application Information
typical characteristics
PARAMETER
vs PARAMETER 2
Supply voltage
FIGURE
PAGE
10
10
10
11
Rise time
4
5
Fall time
Supply voltage
Propagation delay time
Supply voltage
6, 7
8
Supply voltage
Supply current
Load capacitance
Ambient temperature
Supply voltage
9
11
10
11
11
Input threshold voltage
Regulator output voltage
Regulator quiescent current
Peak source current
11
Regulator input voltage
Regulator input voltage
Supply voltage
12, 13
14
15
16
17
18
12
12
12
13
13
13
Peak sink current
Supply voltage
Input voltage, high-to-low
Input voltage, low-to-high
Shoot-through current
8
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ꢀ ꢁꢂꢃ ꢄ ꢅꢅ ꢆ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢃ ꢆ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢇ ꢆ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢈ ꢆ ꢀꢁ ꢂ ꢃꢄ ꢅꢉ
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SLVS132F − NOVEMBER 1995 − REVISED OCTOBER 2004
TYPICAL CHARACTERISTICS
Tables of Characteristics Graphs and Application Information (Continued)
general applications
PARAMETER
vs PARAMETER 2
FIGURE
19, 20
PAGE
15
Switching test circuits and application information
Low-to-high
High-to-low
21, 23, 25
22, 24, 26
16, 17
16, 17
Voltage of 1OUT vs 2OUT
Time
circuit for measuring paralleled switching characteristics
PARAMETER
vs PARAMETER 2
FIGURE
27
PAGE
17
Switching test circuits and application information
Low-to-high
High-to-low
28, 30
29, 31
18
Input voltage vs output voltage
Time
18
Hex-1 to Hex-4 application information
PARAMETER
vs PARAMETER 2
FIGURE
32
PAGE
19
20
20
21
22
23
20
21
21
22
23
20
21
22
22
23
Driving test circuit and application information
Hex-1 size
33
Hex-2 size
36
Hex-3 size
39
Drain-source voltage vs drain current
Time
Time
Time
Hex-4 size
41
Hex-4 size parallel drive
Hex-1 size
45
34
Hex-2 size
37
Hex-3 size
40
Drain-source voltage vs gate-source voltage at turn-on
Drain-source voltage vs gate-source voltage at turn-off
Hex-4 size
43
Hex-4 size parallel drive
Hex-1 size
46
35
Hex-2 size
38
Hex-3 size
42
Hex-4 size
44
Hex-4 size parallel drive
47
synchronous buck regulator application
PARAMETER
vs PARAMETER 2
FIGURE
PAGE
24
3.3-V 3-A Synchronous-Rectified Buck Regulator Circuit
Q1 drain voltage vs gate voltage at turn-on
Q1 drain voltage vs gate voltage at turn-off
Q1 drain voltage vs Q2 gate-source voltage
48
49
50
26
26
51, 52, 53
54
26, 27
27
Time
3 A
5 A
Output ripple voltage vs inductor current
55
27
9
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ꢀ ꢁ ꢂ ꢃ ꢄꢅꢅ ꢆ ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢃ ꢆ ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢇ ꢆ ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢈ ꢆ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢉ
ꢊ ꢋꢌꢍ ꢎ ꢏ ꢐꢎꢑꢂ ꢁꢒꢒ ꢊ ꢓꢔ ꢂꢕ ꢒ ꢀ ꢊꢖ ꢏ ꢗꢒ ꢖꢂ
SLVS132F − NOVEMBER 1995 − REVISED OCTOBER 2004
TYPICAL CHARACTERISTICS
RISE TIME
vs
FALL TIME
vs
SUPPLY VOLTAGE
SUPPLY VOLTAGE
22
22
C
= 1 nF
C
= 1 nF
L
L
20
18
16
14
20
18
16
14
T
= 125°C
= 75°C
= 25°C
A
T
= 125°C
A
T
A
T
A
= 75°C
= 25°C
T
A
T
A
T
A
= −50°C
T = −50°C
A
T
A
= −25°C
T
A
= −25°C
12
10
12
10
5
6
7
8
9
10
11
12
13 14
5
6
7
8
9
10
11
12
13 14
V
CC
− Supply Voltage − V
V
CC
− Supply Voltage − V
Figure 4
Figure 5
PROPAGATION DELAY TIME,
HIGH-TO-LOW-LEVEL OUTPUT
vs
PROPAGATION DELAY TIME,
LOW-TO-HIGH-LEVEL OUTPUT
vs
SUPPLY VOLTAGE
SUPPLY VOLTAGE
45
45
40
35
C
= 1 nF
C
= 1 nF
L
L
40
35
30
25
T
A
= 25°C
T
A
= 75°C
30
25
T
A
= 125°C
T =125°C
A
T
A
= 25°C
T
A
= 75°C
T
= −25°C
A
20
15
20
15
T
= −50°C
A
T
A
= −50°C
T
= −25°C
A
5
6
7
8
9
10 11
12 13 14
5
6
7
8
9
10
11
12
13 14
V
CC
− Supply Voltage − V
V
CC
− Supply Voltage − V
Figure 6
Figure 7
10
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ꢀ ꢁꢂꢃ ꢄ ꢅꢅ ꢆ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢃ ꢆ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢇ ꢆ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢈ ꢆ ꢀꢁ ꢂ ꢃꢄ ꢅꢉ
ꢊꢋꢌ ꢍ ꢎꢏ ꢐꢎ ꢑꢂꢁꢒ ꢒꢊ ꢓ ꢔꢂ ꢕꢒ ꢀ ꢊ ꢖꢏ ꢗ ꢒꢖ ꢂ
SLVS132F − NOVEMBER 1995 − REVISED OCTOBER 2004
TYPICAL CHARACTERISTICS
SUPPLY CURRENT
SUPPLY CURRENT
vs
vs
SUPPLY VOLTAGE
LOAD CAPACITANCE
16
14
12
10
8
2.5
2
V
= 10 V
CC
f = 100 kHz
= 25°C
Duty Cycle = 50%
= 1 nF
C
L
T
A
1 MHz
1.5
1
0.5
0
6
500 kHz
100 kHz
4
75 kHz
40 kHz
10
2
0
0
0.5
1
1.5
2
4
6
8
12
14
C
− Load Capacitance − nF
L
V
CC
− Supply Voltage − V
Figure 8
Figure 9
INPUT THRESHOLD VOLTAGE
SUPPLY CURRENT
vs
vs
SUPPLY VOLTAGE
AMBIENT TEMPERATURE
1.2
1.19
1.18
9
C
V
= 1 nF
T
A
= 25°C
L
= 10 V
8
7
6
5
4
3
2
CC
Duty Cycle = 50%
f = 100 kHz
+ Threshold
1.17
1.16
1.15
1.14
− Threshold
1.13
1.12
1.11
1.1
1
0
−50 −25
0
25
50
75
100
125
4
6
8
10
12
14
V
CC
− Supply Voltage − V
T
A
− Temperature − °C
Figure 10
Figure 11
11
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ꢀ ꢁ ꢂ ꢃ ꢄꢅꢅ ꢆ ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢃ ꢆ ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢇ ꢆ ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢈ ꢆ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢉ
ꢊ ꢋꢌꢍ ꢎ ꢏ ꢐꢎꢑꢂ ꢁꢒꢒ ꢊ ꢓꢔ ꢂꢕ ꢒ ꢀ ꢊꢖ ꢏ ꢗꢒ ꢖꢂ
SLVS132F − NOVEMBER 1995 − REVISED OCTOBER 2004
TYPICAL CHARACTERISTICS
REGULATOR OUTPUT VOLTAGE
REGULATOR OUTPUT VOLTAGE
vs
vs
REGULATOR INPUT VOLTAGE
REGULATOR INPUT VOLTAGE
14
13
12
13
12
11
10
9
R
= 10 kΩ
R
= 10 kΩ
L
T
= −55°C
L
A
T
A
= 25°C
T
A
= −55°C
T
A
= 125°C
11
10
9
T
= 125°C
A
T
A
= 25°C
8
7
6
8
7
6
5
4
5
4
4
8
12
16 20
24
28 32
36 40
4
6
8
10
12
14
Regulator Input Voltage − V
Regulator Input Voltage − V
Figure 12
Figure 13
REGULATOR QUIESCENT CURRENT
vs
PEAK SOURCE CURRENT
vs
REGULATOR INPUT VOLTAGE
SUPPLY VOLTAGE
50
45
2.5
2
R
= 0.5 Ω
L
T
= −55°C
A
f = 100 kHz
Duty Cycle = 5%
T
A
40
35
30
25
20
15
10
= 25°C
T
= 25°C
A
1.5
1
T
A
= 125°C
.5
0
R
= 10 kΩ
L
5
0
4
8
12 16
20
24
28
32
36
40
4
6
8
10
12
14
V
CC
− Supply Voltage − V
Regulator Input Voltage − V
Figure 14
Figure 15
12
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ꢀ ꢁꢂꢃ ꢄ ꢅꢅ ꢆ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢃ ꢆ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢇ ꢆ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢈ ꢆ ꢀꢁ ꢂ ꢃꢄ ꢅꢉ
ꢊꢋꢌ ꢍ ꢎꢏ ꢐꢎ ꢑꢂꢁꢒ ꢒꢊ ꢓ ꢔꢂ ꢕꢒ ꢀ ꢊ ꢖꢏ ꢗ ꢒꢖ ꢂ
SLVS132F − NOVEMBER 1995 − REVISED OCTOBER 2004
TYPICAL CHARACTERISTICS
PEAK SINK CURRENT
vs
SUPPLY VOLTAGE
2.5
2
R
= 0.5 Ω
L
f = 100 kHz
Duty Cycle = 5%
T
A
= 25°C
1.5
1
.5
0
4
6
8
10
12
14
V
CC
− Supply Voltage − V
Figure 16
SHOOT-THROUGH CURRENT
vs
SHOOT-THROUGH CURRENT
vs
INPUT VOLTAGE, LOW-TO-HIGH
INPUT VOLTAGE, HIGH-TO-LOW
6
5
4
3
6
5
V
C
T
= 10 V
= 0
= 25°C
V
C
T
= 10 V
= 0
= 25°C
CC
L
A
CC
L
A
4
3
2
2
1
0
1
0
10
8
6
4
2
0
0
2
4
6
8
10
V − Input Voltage, High-to-Low − V
I
V − Input Voltage, Low-to-High − V
I
Figure 17
Figure 18
13
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ꢀ ꢁ ꢂ ꢃ ꢄꢅꢅ ꢆ ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢃ ꢆ ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢇ ꢆ ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢈ ꢆ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢉ
ꢊ ꢋꢌꢍ ꢎ ꢏ ꢐꢎꢑꢂ ꢁꢒꢒ ꢊ ꢓꢔ ꢂꢕ ꢒ ꢀ ꢊꢖ ꢏ ꢗꢒ ꢖꢂ
SLVS132F − NOVEMBER 1995 − REVISED OCTOBER 2004
APPLICATION INFORMATION
The TPS2811, TPS2812 and TPS2813 circuits each contain one regulator and two MOSFET drivers. The regulator
can be used to limit V
to between 10 V and 13 V for a range of input voltages from 14 V to 40 V, while providing
CC
up to 20 mA of dc drive. The TPS2814 and TPS2815 both contain two drivers, each of which has two inputs. The
TPS2811 has inverting drivers, the TPS2812 has noninverting drivers, and the TPS2813 has one inverting and one
noninverting driver. The TPS2814 is a dual 2-input AND driver with one inverting input on each driver, and the
TPS2815 is a dual 2-input NAND driver. These MOSFET drivers are capable of supplying up to 2.1 A or sinking up
to 1.9 A (see Figures 15 and 16) of instantaneous current to n-channel or p-channel MOSFETs. The TPS2811 family
of MOSFET drivers have very fast switching times combined with very short propagation delays. These features
enhance the operation of today’s high-frequency circuits.
The CMOS input circuit has a positive threshold of approximately 2/3 of V , with a negative threshold of 1/3 of V
CC
and a very high input impedance in the range of 10 Ω. Noise immunity is also very high because of the Schmidt trigger
switching. In addition, the design is such that the normal shoot-through current in CMOS (when the input is biased
,
CC
9
halfway between V
and ground) is limited to less than 6 mA. The limited shoot-through is evident in the graphs in
CC
Figures 17 and 18. The input stage shown in the functional block diagram better illustrates the way the front end works.
The circuitry of the device is such that regardless of the rise and/or fall time of the input signal, the output signal will
always have a fast transition speed; this basically isolates the waveforms at the input from the output. Therefore, the
specified switching times are not affected by the slopes of the input waveforms.
The basic driver portion of the circuits operate over a supply voltage range of 4 V to 14 V with a maximum bias current
of 5 µA. Each driver consists of a CMOS input and a buffered output with a 2-A instantaneous drive capability. They
have propagation delays of less than 30 ns and rise and fall times of less than 20 ns each. Placing a 0.1-µF ceramic
capacitor between V
switching and high current surges of the driver when it is driving a MOSFET.
and ground is recommended; this will supply the instantaneous current needed by the fast
CC
The output circuit is also shown in the functional block diagram. This driver uses a unique combination of a bipolar
transistor in parallel with a MOSFET for the ability to swing from V to ground while providing 2 A of instantaneous
CC
driver current. This unique parallel combination of bipolar and MOSFET output transistors provides the drive required
at V
and ground to guarantee turn-off of even low-threshold MOSFETs. Typical bipolar-only output devices don’t
CC
easily approach V
or ground.
CC
The regulator, included in the TPS2811, TPS2812 and TPS2813, has an input voltage range of 14 V to 40 V. It
produces an output voltage of 10 V to 13 V and is capable of supplying from 0 to 20 mA of output current. In grounded
source applications, this extends the overall circuit operation to 40 V by clamping the driver supply voltage (V ) to
CC
a safe level for both the driver and the MOSFET gate. The bias current for full operation is a maximum of 150 µA.
A 0.1-µF capacitor connected between the regulator output and ground is required to ensure stability. For transient
response, an additional 4.7-µF electrolytic capacitor on the output and a 0.1-µF ceramic capacitor on the input will
optimize the performance of this circuit. When the regulator is not in use, it can be left open at both the input and the
output, or the input can be shorted to the output and tied to either the V
or the ground pin of the chip.
CC
14
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ꢀ ꢁꢂꢃ ꢄ ꢅꢅ ꢆ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢃ ꢆ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢇ ꢆ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢈ ꢆ ꢀꢁ ꢂ ꢃꢄ ꢅꢉ
ꢊꢋꢌ ꢍ ꢎꢏ ꢐꢎ ꢑꢂꢁꢒ ꢒꢊ ꢓ ꢔꢂ ꢕꢒ ꢀ ꢊ ꢖꢏ ꢗ ꢒꢖ ꢂ
SLVS132F − NOVEMBER 1995 − REVISED OCTOBER 2004
APPLICATION INFORMATION
matching and paralleling connections
Figures 21 and 22 show the delays for the rise and fall time of each channel. As can be seen on a 5-ns scale, there
is very little difference between the two channels at no load. Figures 23 and 24 show the difference between the two
channels for a 1-nF load on each output. There is a slight delay on the rising edge, but little or no delay on the falling
edge. As an example of extreme overload, Figures 25 and 26 show the difference between the two channels, or two
drivers in the package, each driving a 10-nF load. As would be expected, the rise and fall times are significantly slowed
down. Figures 28 and 29 show the effect of paralleling the two channels and driving a 1-nF load. A noticeable
improvement is evident in the rise and fall times of the output waveforms. Finally, Figures 30 and 31 show the two
drivers being paralleled to drive the 10-nF load and as could be expected the waveforms are improved. In summary,
the paralleling of the two drivers in a package enhances the capability of the drivers to handle a larger load. Because
of manufacturing tolerances, it is not recommended to parallel drivers that are not in the same package.
V
CC
TPS2811
+
0.1 µF
4.7 µF
8
1
Regulator
2
3
7
6
Output
50 Ω
1 nF
4
5
Figure 19. Test Circuit for Measuring Switching Characteristics
V
CC
TPS2811
+
0.1 µF
4.7 µF
8
1
Regulator
2
3
7
6
Output 1
50 Ω
C
L(1)
4
5
Output 2
C
L(2)
NOTE A: Input rise and fall times should be ≤10 ns for accurate measurement of ac parameters.
Figure 20. Test Circuit for Measuring Switching Characteristics with the Inputs Connected in Parallel
15
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ꢀ ꢁ ꢂ ꢃ ꢄꢅꢅ ꢆ ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢃ ꢆ ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢇ ꢆ ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢈ ꢆ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢉ
ꢊ ꢋꢌꢍ ꢎ ꢏ ꢐꢎꢑꢂ ꢁꢒꢒ ꢊ ꢓꢔ ꢂꢕ ꢒ ꢀ ꢊꢖ ꢏ ꢗꢒ ꢖꢂ
SLVS132F − NOVEMBER 1995 − REVISED OCTOBER 2004
APPLICATION INFORMATION
T
= 25°C
A
I
L
V = 14 V
C
Paralleled Input
V
O
at 1OUT (5 V/div, 5 ns/div)
= 0
V
O
at 2OUT (5 V/div, 5 ns/div)
V
at 1OUT (5 V/div, 5 ns/div)
at 2OUT (5 V/div, 5 ns/div)
O
V
O
T
= 25°C
A
I
L
V = 14 V
C
Paralleled Inputs
= 0
t − Time
t − Time
Figure 21. Voltage of 1OUT vs Voltage at
2OUT, Low-to-High Output Delay
Figure 22. Voltage at 1OUT vs Voltage
at 2OUT, High-to-Low Output Delay
T
= 25°C
A
I
L
V
O
at 1OUT (5 V/div, 10 ns/div)
V = 14 V
C
Paralleled Input
= 1 nF on Each Output
V
at 2OUT
O
(5 V/div, 10 ns/div)
V
at 1OUT
O
(5 V/div, 10 ns/div)
V
O
at 2OUT (5 V/div, 10 ns/div)
T
= 25°C
A
I
L
V = 14 V
C
Paralleled Input
= 1 nF Each Output
t − Time
t − Time
Figure 23. Voltage at 1OUT vs Voltage at
2OUT, Low-to-High Output Delay
Figure 24. Voltage at 1OUT vs Voltage at
2OUT, High-to-Low Output Delay
16
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ꢀ ꢁꢂꢃ ꢄ ꢅꢅ ꢆ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢃ ꢆ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢇ ꢆ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢈ ꢆ ꢀꢁ ꢂ ꢃꢄ ꢅꢉ
ꢊꢋꢌ ꢍ ꢎꢏ ꢐꢎ ꢑꢂꢁꢒ ꢒꢊ ꢓ ꢔꢂ ꢕꢒ ꢀ ꢊ ꢖꢏ ꢗ ꢒꢖ ꢂ
SLVS132F − NOVEMBER 1995 − REVISED OCTOBER 2004
APPLICATION INFORMATION
V
at 1OUT
O
(5 V/div, 20 ns/div)
V
at 2OUT
O
(5 V/div, 20 ns/div)
V
O
at (5 V/div, 20 ns/div)
V
O
at 2OUT (5 V/div, 20 ns/div)
T
V
C
= 25°C
A
T = 25°C
A
= 14 V
CC
V
= 14 V
CC
L
= 10 nF on Each Output
L
C
= 10 nF on Each Output
Paralleled Input
Paralleled Input
t − Time
t − Time
Figure 25. Voltage at 1OUT vs Voltage at
2OUT, Low-to-High Output Delay
Figure 26. Voltage at 1OUT vs Voltage at
2OUT, High-to-Low Output Delay
V
CC
TPS2811
Regulator
+
0.1 µF
4.7 µF
8
1
2
3
7
6
Output
50 Ω
C
L
4
5
NOTE A: Input rise and fall times should be ≤10 ns for accurate measurement of ac parameters.
Figure 27. Test Circuit for Measuring Paralleled Switching Characteristics
17
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ꢀ ꢁ ꢂ ꢃ ꢄꢅꢅ ꢆ ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢃ ꢆ ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢇ ꢆ ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢈ ꢆ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢉ
ꢊ ꢋꢌꢍ ꢎ ꢏ ꢐꢎꢑꢂ ꢁꢒꢒ ꢊ ꢓꢔ ꢂꢕ ꢒ ꢀ ꢊꢖ ꢏ ꢗꢒ ꢖꢂ
SLVS132F − NOVEMBER 1995 − REVISED OCTOBER 2004
APPLICATION INFORMATION
T
V
C
= 25°C
= 14 V
CC
= 1 nF
A
V (5 V/div, 20 ns/div)
I
L
V (5 V/div, 20 ns/div)
I
Paralleled Input
and Output
T
V
C
= 25°C
= 14 V
CC
= 1 nF
A
L
Paralleled Input
and Output
V
O
(5 V/div, 20 ns/div)
V
O
(5 V/div, 20 ns/div)
t − Time
t − Time
Figure 28. Input Voltage vs Output Voltage,
Low-to-High Propagation Delay of Paralleled
Drivers
Figure 29. Input Voltage vs Output Voltage,
High-to-Low Propagation Delay of Paralleled
Drivers
T
V
C
= 25°C
A
= 14 V
CC
= 10 nF
L
V (5 V/div, 20 ns/div)
I
Paralleled Input
and Output
V (5 V/div, 20 ns/div)
I
T
V
C
= 25°C
A
= 14 V
CC
V
O
(5 V/div, 20 ns/div)
= 10 nF
L
Paralleled Input
and Output
V
O
(5 V/div, 20 ns/div)
t − Time
t − Time
Figure 31. Input Voltage vs Output Voltage,
High-to-Low Propagation Delay of Paralleled
Drivers
Figure 30. Input Voltage vs Output Voltage,
Low-to-High Propagation Delay of Paralleled
Drivers
18
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ꢀ ꢁꢂꢃ ꢄ ꢅꢅ ꢆ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢃ ꢆ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢇ ꢆ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢈ ꢆ ꢀꢁ ꢂ ꢃꢄ ꢅꢉ
ꢊꢋꢌ ꢍ ꢎꢏ ꢐꢎ ꢑꢂꢁꢒ ꢒꢊ ꢓ ꢔꢂ ꢕꢒ ꢀ ꢊ ꢖꢏ ꢗ ꢒꢖ ꢂ
SLVS132F − NOVEMBER 1995 − REVISED OCTOBER 2004
APPLICATION INFORMATION
Figures 33 through 47 illustrate the performance of the TPS2811 driving MOSFETs with clamped inductive loads,
similar to what is encountered in discontinuous-mode flyback converters. The MOSFETs that were tested range in
size from Hex-1 to Hex-4, although the TPS28xx family is only recommended for Hex-3 or below.
The test circuit is shown in Figure 32. The layout rules observed in building the test circuit also apply to real
applications. Decoupling capacitor C1 is a 0.1-µF ceramic device, connected between V and GND of the TPS2811,
CC
with short lead lengths. The connection between the driver output and the MOSFET gate, and between GND and
the MOSFET source, are as short as possible to minimize inductance. Ideally, GND of the driver is connected directly
to the MOSFET source. The tests were conducted with the pulse generator frequency set very low to eliminate the
need for heat sinking, and the duty cycle was set to turn off the MOSFET when the drain current reached 50% of its
rated value. The input voltage was adjusted to clamp the drain voltage at 80% of its rating.
As shown, the driver is capable of driving each of the Hex-1 through Hex-3 MOSFETs to switch in 20 ns or less. Even
the Hex-4 is turned on in less than 20 ns. Figures 45, 46 and 47 show that paralleling the two drivers in a package
enhances the gate waveforms and improves the switching speed of the MOSFET. Generally, one driver is capable
of driving up to a Hex-4 size. The TPS2811 family is even capable of driving large MOSFETs that have a low gate
charge.
V
I
CR1
L1
Current
Loop
8
1
Regulator
+
V
−
V
DS
Q1
DS
2
3
7
6
V
GS
R1
50 Ω
4
5
V
CC
+
C2
4.7 µF
C1
0.1 µF
Figure 32. TPS2811 Driving Hex-1 through Hex-4 Devices
19
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ꢀ ꢁ ꢂ ꢃ ꢄꢅꢅ ꢆ ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢃ ꢆ ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢇ ꢆ ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢈ ꢆ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢉ
ꢊ ꢋꢌꢍ ꢎ ꢏ ꢐꢎꢑꢂ ꢁꢒꢒ ꢊ ꢓꢔ ꢂꢕ ꢒ ꢀ ꢊꢖ ꢏ ꢗꢒ ꢖꢂ
SLVS132F − NOVEMBER 1995 − REVISED OCTOBER 2004
APPLICATION INFORMATION
T
V
= 25°C
T
V
= 25°C
A
A
V
DS
(20 V/div, 0.5 µs/div)
= 14 V
= 14 V
CC
CC
V = 48 V
V = 48 V
I
I
V
DS
(20 V/div, 50 ns/div)
V
GS
(5 V/div, 50 ns/div)
I
D
(0.5 A/div, 0.5 µs/div)
t − Time
t − Time
Figure 33. Drain-Source Voltage vs Drain
Current, TPS2811 Driving an IRFD014
(Hex-1 Size)
Figure 34. Drain-Source Voltage vs
Gate-Source Voltage, at Turn-on,
TPS2811 Driving an IRFD014 (Hex-1 Size)
T
= 25°C
= 14 V
A
V
CC
V = 48 V
V
DS
(20 V/div, 50 ns/div)
I
V
DS
(50 V/div, 0.2 µs/div)
T
= 25°C
= 14 V
A
V
CC
V = 80 V
I
V
GS
(5 V/div, 50 ns/div)
V
GS
(0.5 A/div, 0.2 µs/div)
t − Time
t − Time
Figure 35. Drain-Source Voltage vs
Gate-Source Voltage, at Turn-off,
TPS2811 Driving an IRFD014 (Hex-1 Size)
Figure 36. Drain-Source Voltage vs Drain
Current, TPS2811 Driving an IRFD120
(Hex-2 Size)
20
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ꢀ ꢁꢂꢃ ꢄ ꢅꢅ ꢆ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢃ ꢆ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢇ ꢆ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢈ ꢆ ꢀꢁ ꢂ ꢃꢄ ꢅꢉ
ꢊꢋꢌ ꢍ ꢎꢏ ꢐꢎ ꢑꢂꢁꢒ ꢒꢊ ꢓ ꢔꢂ ꢕꢒ ꢀ ꢊ ꢖꢏ ꢗ ꢒꢖ ꢂ
SLVS132F − NOVEMBER 1995 − REVISED OCTOBER 2004
APPLICATION INFORMATION
T
V
= 25°C
T
V
= 25°C
A
A
= 14 V
V
DS
(50 V/div, 50 ns/div)
= 14 V
CC
CC
V = 80 V
V = 80 V
I
I
V
(50 V/div, 50 ns/div)
(5 V/div, 50 ns/div)
DS
V
GS
V
GS
(5 V/div, 50 ns/div)
t − Time
t − Time
Figure 37. Drain-Source Voltage vs
Gate-Source Voltage,
Figure 38. Drain-Source Voltage vs
Gate-Source Voltage,
at Turn-on, TPS2811 Driving an IRFD120
(Hex-2 Size)
at Turn-off, TPS2811 Driving an IRFD120
(Hex-2 Size)
T
V
= 25°C
A
= 14 V
CC
V = 80 V
I
V
DS
(50 V/div, 50 ns/div)
V
DS
(50 V/div, 2 µs/div)
T
= 25°C
= 14 V
A
V
CC
V = 80 V
V
GS
(5 A/div, 50 ns/div)
I
I
D
(5 A/div, 2 µs/div)
t − Time
t − Time
Figure 40. Drain-Source Voltage vs
Gate-Source Voltage, at Turn-on, TPS2811
Driving an IRF530 (Hex-3 Size)
Figure 39. Drain-Source Voltage vs Drain
Current, TPS2811 Driving an IRF530
(Hex-3 Size)
21
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ꢀ ꢁ ꢂ ꢃ ꢄꢅꢅ ꢆ ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢃ ꢆ ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢇ ꢆ ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢈ ꢆ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢉ
ꢊ ꢋꢌꢍ ꢎ ꢏ ꢐꢎꢑꢂ ꢁꢒꢒ ꢊ ꢓꢔ ꢂꢕ ꢒ ꢀ ꢊꢖ ꢏ ꢗꢒ ꢖꢂ
SLVS132F − NOVEMBER 1995 − REVISED OCTOBER 2004
APPLICATION INFORMATION
V
DS
(50 V/div, 0.2 µs/div)
V
DS
(50 V/div, 50 ns/div)
T
= 25°C
= 14 V
A
V
CC
V = 350 V
I
T
V
= 25°C
A
= 14 V
CC
V = 80 V
I
I
(2 A/div,
D
0.2 µs/div)
V
GS
(5 V/div, 50 ns/div)
t − Time
t − Time
Figure 41. Drain-Source Voltage vs Drain
Current,
Figure 42. Drain-Source Voltage vs
Gate-Source Voltage,
One Driver, TPS2811 Driving an IRF840
(Hex-4 Size)
at Turn-off, TPS2811 Driving an IRF530
(Hex-3 Size)
V
DS
(50 V/div, 50 ns/div)
V
DS
(50 V/div, 50 ns/div)
V
GS
(5 V/div, 50 ns/div)
V
GS
(5 V/div, 50 ns/div)
T
= 25°C
= 14 V
A
T
= 25°C
= 14 V
A
V
CC
V = 350 V
V
CC
V = 350 V
I
I
t − Time
t − Time
Figure 43. Drain-Source Voltage vs
Gate-Source Voltage, at Turn-on,
One Driver, TPS2811 Driving an IRF840
(Hex-4 Size)
Figure 44. Drain-Source Voltage vs Gate-Source
Voltage, at Turn-off, One Driver,
TPS2811 Driving an IRF840
(Hex-4 Size)
22
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ꢀ ꢁꢂꢃ ꢄ ꢅꢅ ꢆ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢃ ꢆ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢇ ꢆ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢈ ꢆ ꢀꢁ ꢂ ꢃꢄ ꢅꢉ
ꢊꢋꢌ ꢍ ꢎꢏ ꢐꢎ ꢑꢂꢁꢒ ꢒꢊ ꢓ ꢔꢂ ꢕꢒ ꢀ ꢊ ꢖꢏ ꢗ ꢒꢖ ꢂ
SLVS132F − NOVEMBER 1995 − REVISED OCTOBER 2004
APPLICATION INFORMATION
V
DS
(50 V/div, 0.2 µs/div)
V
(50 V/div,
50 ns/div)
DS
T
= 25°C
= 14 V
A
V
CC
V = 350 V
I
V
(5 V/div,
50 ns/div)
I
(2 A/div,
GS
D
0.2 µs/div)
T
= 25°C
= 14 V
A
V
CC
V = 350 V
I
t − Time
t − Time
Figure 46. Drain-Source Voltage vs Gate-Source
Voltage, at Turn-on, Parallel Drivers,
Figure 45. Drain-Source Voltage vs Drain
Current, Parallel Drivers,
TPS2811 Driving an IRF840 (Hex-4 Size)
TPS2811 Driving an IRF840 (Hex-4 Size)
V
DS
(50 V/div, 50 ns/div)
V
GS
(5 V/div, 50 ns/div)
T
= 25°C
= 14 V
A
V
CC
V = 350 V
I
t − Time
Figure 47. Drain-Source Voltage vs Gate-Source Voltage, at Turn-off,
Parallel Drivers, TPS2811 Driving an IRF840 (Hex-4 Size)
23
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ꢀ ꢁ ꢂ ꢃ ꢄꢅꢅ ꢆ ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢃ ꢆ ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢇ ꢆ ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢈ ꢆ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢉ
ꢊ ꢋꢌꢍ ꢎ ꢏ ꢐꢎꢑꢂ ꢁꢒꢒ ꢊ ꢓꢔ ꢂꢕ ꢒ ꢀ ꢊꢖ ꢏ ꢗꢒ ꢖꢂ
SLVS132F − NOVEMBER 1995 − REVISED OCTOBER 2004
APPLICATION INFORMATION
synchronous buck regulator
Figure 48 is the schematic for a 100-kHz synchronous-rectified buck converter implemented with a TL5001
pulse-width-modulation (PWM) controller and a TPS2812 driver. The bill of materials is provided in Table 1. The
converter operates over an input range from 5.5 V to 12 V and has a 3.3-V output capable of supplying 3 A
continuously and 5 A during load surges. The converter achieves an efficiency of 90.6% at 3 A and 87.6% at 5 A.
Figures 49 and 50 show the power switch switching performance. The output ripple voltage waveforms are
documented in Figures 54 and 55.
The TPS2812 drives both the power switch, Q2, and the synchronous rectifier, Q1. Large shoot-through currents,
caused by power switch and synchronous rectifier remaining on simultaneously during the transitions, are prevented
by small delays built into the drive signals, using CR2, CR3, R11, R12, and the input capacitance of the TPS2812.
These delays allow the power switch to turn off before the synchronous rectifier turns on and vice versa. Figure 51
shows the delay between the drain of Q2 and the gate of Q1; expanded views are provided in Figures 52 and 53.
Q1
IRF7406
L1
27 µF
3
1
J1
J2
+
+
+
+
C100
100 µF
16 V
C12
C7
C13
C5
100 µF
16 V
V
V
1
3.3 V
3.3 V
GND
GND
1
I
C11
0.47 µF
R5
100 µF
16 V
100 µF
16 V
10 µF
10 V
10 kΩ
2
3
4
2
3
4
I
2
CR1
1
GND
30BQ015
GND
R7
2
3.3 Ω
1
8
REG_IN
REG_OUT
1 OUT
2
3
4
7
6
5
1 IN
U2
3
Q2
R4
R3
C6
TPS2812D
GND
V
CC
IRF7201
2.32 kΩ
180 Ω
1000 pF
2 IN
2 OUT
1%
R13
10 kΩ
C4
R2
C3
C14
0.1 µF
0.022 µF
1.6 kΩ
0.0022
R6
15 Ω
µF
C2
0.033 µF
1
2
3
4
R10
1 kΩ
CR2
CR3
OUT
V
COMP
FB
CC
BAS16ZX
R1
U1
C15
1 µF
1.00 kΩ
1%
TL5001CD
R11
GND
RT
DTC
6
SCP
30 kΩ
8
7
5
BAS16ZX
+
R9
R8
C1
1 µF
90.9 kΩ
121 kΩ
1%
1%
R12
C9
10 kΩ
0.22 µF
Figure 48. 3.3-V 3-A Synchronous-Rectified Buck Regulator Circuit
NOTE: If the parasitics of the external circuit cause the voltage to violate the Absolute Maximum
Rating for the Output pins, Schottky diodes should be added from ground to output and from output
to Vcc.
24
www.ti.com
ꢀ ꢁꢂꢃ ꢄ ꢅꢅ ꢆ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢃ ꢆ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢇ ꢆ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢈ ꢆ ꢀꢁ ꢂ ꢃꢄ ꢅꢉ
ꢊꢋꢌ ꢍ ꢎꢏ ꢐꢎ ꢑꢂꢁꢒ ꢒꢊ ꢓ ꢔꢂ ꢕꢒ ꢀ ꢊ ꢖꢏ ꢗ ꢒꢖ ꢂ
SLVS132F − NOVEMBER 1995 − REVISED OCTOBER 2004
APPLICATION INFORMATION
Table 1. Bill of Materials,
3.3-V, 3-A Synchronous-Rectified Buck Converter
REFERENCE
DESCRIPTION
TL5001CD, PWM
VENDOR
U1
Texas Instruments,
Texas Instruments,
International Rectifier,
Zetex,
972-644-5580
972-644-5580
310-322-3331
516-543-7100
U2
TPS2812D, N.I. MOSFET Driver
3 A, 15 V, Schottky, 30BQ015
Signal Diode, BAS16ZX
1 µF, 16 V, Tantalum
0.033 µF, 50 V
CR1
CR2,CR3
C1
C2
C3
0.0022 µF, 50 V
C4
0.022 µF, 50 V
C5,C7,C10,C12
100 µF, 16 V, Tantalum, TPSE107M016R0100 AVX,
800-448-9411
708-803-6100
C6
C9
1000 pF, 50 V
0.22 µF, 50 V
C11
C13
C14
C15
J1,J2
L1
0.47 µF, 50 V, Z5U
10 µF, 10 V, Ceramic, CC1210CY5V106Z
TDK,
0.1 µF, 50 V
1.0 µF, 50 V
4-Pin Header
27 µH, 3 A/5 A, SML5040
IRF7406, P-FET
IRF7201, N-FET
1.00 kΩ, 1%
1.6 kΩ
Nova Magnetics, Inc.,
International Rectifier,
International Rectifier,
972-272-8287
310-322-3331
310-322-3331
Q1
Q2
R1
R2
R3
180 Ω
R4
2.32 kΩ, 1 %
10 kΩ
R5,R12,R13
R6
15 Ω
R7
3.3 Ω
R8
121 kΩ, 1%
90.9 kΩ, 1%
1 kΩ
R9
R10
R11
30 kΩ
NOTES: 2. Unless otherwise specified, capacitors are X7R ceramics.
3. Unless otherwise specified, resistors are 5%, 1/10 W.
25
www.ti.com
ꢀ ꢁ ꢂ ꢃ ꢄꢅꢅ ꢆ ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢃ ꢆ ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢇ ꢆ ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢈ ꢆ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢉ
ꢊ ꢋꢌꢍ ꢎ ꢏ ꢐꢎꢑꢂ ꢁꢒꢒ ꢊ ꢓꢔ ꢂꢕ ꢒ ꢀ ꢊꢖ ꢏ ꢗꢒ ꢖꢂ
SLVS132F − NOVEMBER 1995 − REVISED OCTOBER 2004
APPLICATION INFORMATION
V
D
(5 V/div, 20 ns/div)
V
V
(2 V/div, 20 ns/div)
(5 V/div, 20 ns/div)
G
D
V
G
(2 V/div, 20 ns/div)
T
= 25°C
A
I
O
T
= 25°C
A
I
O
V = 12 V
V
V = 12 V
V
= 3.3 V at 5A
= 3.3 V at 5A
t − Time
t − Time
Figure 49. Q1 Drain Voltage vs Gate Voltage,
at Switch Turn-on
Figure 50. Q1 Drain Voltage vs Gate Voltage,
at Switch Turn-off
T
= 25°C
A
I
O
V = 12 V
V
V
D
(5 V/div, 0.5 µs/div)
= 3.3 V at 5A
T
= 25°C
A
I
O
V = 12 V
V
= 3.3 V at 5A
V
D
(5 V/div, 20 ns/div)
V
GS
(2 V/div, 0.5 µs/div)
V
GS
(2 V/div, 20 ns/div)
t − Time
t − Time
Figure 52. Q1 Drain Voltage vs Q2
Gate-Source Voltage
Figure 51. Q1 Drain Voltage vs Q2
Gate-Source Voltage
26
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ꢀ ꢁꢂꢃ ꢄ ꢅꢅ ꢆ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢃ ꢆ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢇ ꢆ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢈ ꢆ ꢀꢁ ꢂ ꢃꢄ ꢅꢉ
ꢊꢋꢌ ꢍ ꢎꢏ ꢐꢎ ꢑꢂꢁꢒ ꢒꢊ ꢓ ꢔꢂ ꢕꢒ ꢀ ꢊ ꢖꢏ ꢗ ꢒꢖ ꢂ
SLVS132F − NOVEMBER 1995 − REVISED OCTOBER 2004
APPLICATION INFORMATION
T
= 25°C
V
D
(5 V/div, 20 ns/div)
A
I
O
V = 12 V
V
= 3.3 V at 5A
V
GS
(2 V/div, 20 ns/div)
t − Time
Figure 53. Q1 Drain Voltage vs Q2 Gate-Source Voltage
T
= 25°C
A
I
O
Inductor Current (2 A/div, 2 µs/div)
V = 12 V
V
= 3.3 V at 3A
Inductor Current (1 A/div, 2 µs/div)
T
= 25°C
A
I
O
V = 12 V
V
= 3.3 V at 5 A
1
2
1
2
Output Ripple Voltage (20 mV/div, 2 µs/div)
Output Ripple Voltage (20 mV/div, 2 µs/div)
t − Time
t − Time
Figure 54. Output Ripple Voltage vs
Inductor Current, at 3 A
Figure 55. Output Ripple Voltage vs
Inductor Current, at 5 A
27
www.ti.com
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
PACKAGING INFORMATION
Orderable Device
TPS2811D
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
Samples
Drawing
Qty
(1)
(2)
(3)
(4)
ACTIVE
SOIC
SOIC
D
8
8
8
8
8
8
8
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
2811
TPS2811DG4
TPS2811DR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
D
D
75
2500
2500
50
Green (RoHS
& no Sb/Br)
2811
SOIC
Green (RoHS
& no Sb/Br)
-40 to 125
-40 to 125
2811
TPS2811DRG4
TPS2811P
SOIC
D
Green (RoHS
& no Sb/Br)
2811
PDIP
P
Pb-Free
(RoHS)
TPS2811P
TPS2811P
PS2811
PS2811
TPS2811PE4
TPS2811PW
TPS2811PWG4
PDIP
P
50
Pb-Free
(RoHS)
N / A for Pkg Type
TSSOP
TSSOP
PW
PW
150
150
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Green (RoHS
& no Sb/Br)
TPS2811PWLE
TPS2811PWR
OBSOLETE
ACTIVE
TSSOP
TSSOP
PW
PW
8
8
TBD
Call TI
Call TI
2000
2000
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
PS2811
PS2811
2812
TPS2811PWRG4
TPS2812D
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
OBSOLETE
TSSOP
SOIC
SOIC
SOIC
SOIC
PDIP
PW
D
8
8
8
8
8
8
8
8
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Call TI
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
N / A for Pkg Type
Call TI
Green (RoHS
& no Sb/Br)
-40 to 125
-40 to 125
TPS2812DG4
TPS2812DR
D
75
Green (RoHS
& no Sb/Br)
2812
D
2500
2500
50
Green (RoHS
& no Sb/Br)
2812
TPS2812DRG4
TPS2812P
D
Green (RoHS
& no Sb/Br)
2812
P
Pb-Free
(RoHS)
TPS2812P
TPS2812P
TPS2812PE4
TPS2812PWLE
PDIP
P
50
Pb-Free
(RoHS)
TSSOP
PW
TBD
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
Orderable Device
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
Samples
Drawing
Qty
(1)
(2)
(3)
(4)
TPS2812PWR
TPS2812PWRG4
TPS2813D
ACTIVE
TSSOP
TSSOP
SOIC
SOIC
SOIC
SOIC
PDIP
PW
8
8
8
8
8
8
8
8
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
PS2812
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
PW
D
2000
75
Green (RoHS
& no Sb/Br)
PS2812
2813
Green (RoHS
& no Sb/Br)
TPS2813DG4
TPS2813DR
D
75
Green (RoHS
& no Sb/Br)
2813
D
2500
2500
50
Green (RoHS
& no Sb/Br)
2813
TPS2813DRG4
TPS2813P
D
Green (RoHS
& no Sb/Br)
2813
P
Pb-Free
(RoHS)
TPS2813P
TPS2813P
TPS2813PE4
PDIP
P
50
Pb-Free
(RoHS)
N / A for Pkg Type
TPS2813PWLE
TPS2813PWR
OBSOLETE
ACTIVE
TSSOP
TSSOP
PW
PW
8
8
TBD
Call TI
Call TI
2000
2000
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
PS2813
PS2813
2814
TPS2813PWRG4
TPS2814D
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
TSSOP
SOIC
SOIC
SOIC
SOIC
PDIP
PW
D
8
8
8
8
8
8
8
8
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
Green (RoHS
& no Sb/Br)
TPS2814DG4
TPS2814DR
TPS2814DRG4
TPS2814P
D
75
Green (RoHS
& no Sb/Br)
2814
D
2500
2500
50
Green (RoHS
& no Sb/Br)
-40 to 125
-40 to 125
2814
D
Green (RoHS
& no Sb/Br)
2814
P
Pb-Free
(RoHS)
TPS2814P
TPS2814P
PS2814
TPS2814PE4
TPS2814PW
PDIP
P
50
Pb-Free
(RoHS)
N / A for Pkg Type
TSSOP
PW
150
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
Orderable Device
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
Samples
Drawing
Qty
(1)
(2)
(3)
(4)
TPS2814PWG4
ACTIVE
TSSOP
PW
8
150
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
PS2814
TPS2814PWLE
TPS2814PWR
OBSOLETE
ACTIVE
TSSOP
TSSOP
PW
PW
8
8
TBD
Call TI
Call TI
2000
2000
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
-40 to 125
PS2814
PS2814
2815
TPS2814PWRG4
TPS2815D
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
TSSOP
SOIC
SOIC
SOIC
SOIC
PDIP
PDIP
PW
D
8
8
8
8
8
8
8
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
Green (RoHS
& no Sb/Br)
TPS2815DG4
TPS2815DR
TPS2815DRG4
TPS2815P
D
75
Green (RoHS
& no Sb/Br)
2815
D
2500
2500
50
Green (RoHS
& no Sb/Br)
-40 to 125
-40 to 125
2815
D
Green (RoHS
& no Sb/Br)
2815
P
Pb-Free
(RoHS)
TPS2815P
TPS2815P
TPS2815PE4
P
50
Pb-Free
(RoHS)
N / A for Pkg Type
TPS2815PWLE
TPS2815PWR
OBSOLETE
ACTIVE
TSSOP
TSSOP
PW
PW
8
8
TBD
Call TI
Call TI
2000
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
PS2815
PS2815
TPS2815PWRG4
ACTIVE
TSSOP
PW
8
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Addendum-Page 3
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TPS2811 :
Automotive: TPS2811-Q1
•
NOTE: Qualified Version Definitions:
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•
Addendum-Page 4
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Jun-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS2811DR
TPS2811DR
TPS2811PWR
TPS2812DR
TPS2812DR
TPS2812PWR
TPS2813DR
TPS2813DR
TPS2813PWR
TPS2814DR
TPS2814DR
TPS2814PWR
TPS2815DR
TPS2815PWR
SOIC
SOIC
D
D
8
8
8
8
8
8
8
8
8
8
8
8
8
8
2500
2500
2000
2500
2500
2000
2500
2500
2000
2500
2500
2000
2500
2000
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
6.4
6.4
7.0
6.4
6.4
7.0
6.4
6.4
7.0
6.4
6.4
7.0
6.4
7.0
5.2
5.2
3.6
5.2
5.2
3.6
5.2
5.2
3.6
5.2
5.2
3.6
5.2
3.6
2.1
2.1
1.6
2.1
2.1
1.6
2.1
2.1
1.6
2.1
2.1
1.6
2.1
1.6
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
TSSOP
SOIC
PW
D
SOIC
D
TSSOP
SOIC
PW
D
SOIC
D
TSSOP
SOIC
PW
D
SOIC
D
TSSOP
SOIC
PW
D
TSSOP
PW
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Jun-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS2811DR
TPS2811DR
TPS2811PWR
TPS2812DR
TPS2812DR
TPS2812PWR
TPS2813DR
TPS2813DR
TPS2813PWR
TPS2814DR
TPS2814DR
TPS2814PWR
TPS2815DR
TPS2815PWR
SOIC
SOIC
D
D
8
8
8
8
8
8
8
8
8
8
8
8
8
8
2500
2500
2000
2500
2500
2000
2500
2500
2000
2500
2500
2000
2500
2000
340.5
367.0
367.0
340.5
367.0
367.0
367.0
340.5
367.0
340.5
367.0
367.0
340.5
367.0
338.1
367.0
367.0
338.1
367.0
367.0
367.0
338.1
367.0
338.1
367.0
367.0
338.1
367.0
20.6
35.0
35.0
20.6
35.0
35.0
35.0
20.6
35.0
20.6
35.0
35.0
20.6
35.0
TSSOP
SOIC
PW
D
SOIC
D
TSSOP
SOIC
PW
D
SOIC
D
TSSOP
SOIC
PW
D
SOIC
D
TSSOP
SOIC
PW
D
TSSOP
PW
Pack Materials-Page 2
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