TPS28226D [TI]
High-Frequency 4-A Sink Synchronous MOSFET Drivers; 高频率4 -A水槽同步MOSFET驱动器
| 型号： | TPS28226D |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | High-Frequency 4-A Sink Synchronous MOSFET Drivers |
| 文件： | 总35页 (文件大小：1135K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS28226
www.ti.com
SLUS791–OCTOBER 2007
High-Frequency 4-A Sink Synchronous MOSFET Drivers
1
FEATURES
DESCRIPTION
•
Drives Two N-Channel MOSFETs with 14-ns
Adaptive Dead Time
The TPS28226 is a high-speed driver for N-channel
complimentary driven power MOSFETs with adaptive
dead-time control. This driver is optimized for use in
variety of high-current one and multi-phase dc-to-dc
converters. The TPS28226 is a solution that provides
highly efficient, small size low EMI emmissions.
•
•
Gate Drive Voltage: 6.8 V Up to 8.8 V
Wide Power System Train Input Voltage: 3 V
Up to 27 V
•
•
•
Wide Input PWM Signals: 2.0 V up to 13.2-V
Amplitude
The performance is achieved by up to 8.8-V gate
drive voltage, 14-ns adaptive dead-time control, 14-ns
propagation delays and high-current 2-A source and
4-A sink drive capability. The 0.4-Ω impedance for
the lower gate driver holds the gate of power
MOSFET below its threshold and ensures no
shoot-through current at high dV/dt phase node
transitions. The bootstrap capacitor charged by an
internal diode allows use of N-channel MOSFETs in
half-bridge configuration.
Capable Drive MOSFETs with ≥40-A Current
per Phase
High Frequency Operation: 14-ns Propagation
Delay and 10-ns Rise/Fall Time Allow FSW - 2
MHz
•
•
Capable Propagate <30-ns Input PWM Pulses
Low-Side Driver Sink On-Resistance (0.4 Ω)
Prevents dV/dT Related Shoot-Through
Current
The TPS28226 features
a 3-state PWM input
•
•
3-State PWM Input for Power Stage Shutdown
compatible with all multi-phase controllers employing
3-state output feature. As long as the input stays
within 3-state window for the 250-ns hold-off time, the
driver switches both outputs low. This shutdown
Space Saving Enable (input) and Power Good
(output) Signals on Same Pin
•
•
•
•
Thermal Shutdown
UVLO Protection
mode prevents
output-voltage.
a
load from the reversed-
Internal Bootstrap Diode
The other features include under voltage lockout,
thermal shutdown and two-way enable/power good
signal. Systems without 3-state featured controllers
can use enable/power good input/output to hold both
outputs low during shutting down.
Economical SOIC-8 and Thermally Enhanced
3-mm x 3-mm DFN-8 Packages
•
High Performance Replacement for Popular
3-State Input Drivers
The TPS28226 is offered in an economical SOIC-8
and thermally enhanced low-size Dual Flat No-Lead
(DFN-8) packages. The driver is specified in the
extended temperature range of –40°C to 125°C with
the absolute maximum junction temperature 150°C.
APPLICATIONS
•
Multi-Phase DC-to-DC Converters with Analog
or Digital Control
•
•
•
Desktop and Server VRMs and EVRDs
Portable/Notebook Regulators
Synchronous Rectification for Isolated Power
Supplies
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
UNLESS OTHERWISE NOTED this document contains
PRODUCTION DATA information current as of publication date.
Products conform to specifications per the terms of Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007, Texas Instruments Incorporated
TPS28226
www.ti.com
SLUS791–OCTOBER 2007
FUNCTIONAL BLOCK DIAGRAM
6
2
VDD
BOOT
UVLO
1
8
UGATE
PHASE
7
EN /PG
THERMAL
SD
SHOOT
−
HLD−OFF
TIME
THROUGH
PROTECTION
VDD
27K
3−STATE
INPUT
3
5
4
PWM
LGATE
GND
CIRCUIT
13K
TYPICAL APPLICATIONS
One-Phase POL Regulator
V
C
(6.8 V to 8 V)
V
IN
(3 V to 32 V − V
)
DD
6
2
VDD BOOT
TPS28226
1
8
UGATE
TPS40200
3
7
PHASE
PWM
VCC
OUT
V
OUT
ENBL
LGATE 5
GND
FB
GND
4
2
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SLUS791–OCTOBER 2007
TYPICAL APPLICATIONS (continued)
Driver for Synchronous Rectification with Complementary Driven MOSFETs
12 V
35 V to 75V
V
= 3.3 V
OUT
Primary High Side
V
High Voltage Driver
DD
HB
DRIVE
HI
HI
LI
HO
HS
PWM
LINEAR
REG.
CONTROLLER
LO
DRIVE
LO
TPS28226
BOOT
2
6
7
V
VDD
SS
V
(6.8 V to 8 V)
C
ISOLATION
AND
UGATE
EN/PG PHASE
1
8
FEEDBACK
3 PWM
5
4
LGATE
GND
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SLUS791–OCTOBER 2007
TYPICAL APPLICATIONS (continued)
Multi-Phase Synchronous Buck Converter
V
C
(6.8 V to 8 V)
V
IN
(3 V to 32 V − V
)
DD
6 VDD
BOOT
2
TPS28226
1
8
UGATE
3
PHASE
PWM
7
EN/PG
5
4
LGATE
GND
CS 1
To Controller
PWM1
To Driver
To Driver
PWM2
VIN
PWM3
6 VDD
BOOT
2
To Controller
CS 4 CSCN
TPS28226
PWM 4
1
8
UGATE
GND
VOUT
GNDS
PHASE
3
7
PWM
V
OUT
/PG
EN
Enable
5
4
LGATE
GND
ORDERING INFORMATION(1)(2)(3)
PART NUMBER
TPS28226
TEMPERATURE RANGE, TA = TJ
PACKAGE
TAPE AND REEL QTY.
Plastic 8-pin SOIC (D)
Plastic 8-pin SOIC (D)
Plastic 8-pin DFN (DRB)
Plastic 8-pin DFN (DRB)
75 per tube
2500
TPS28226D
TPS28226DR
TPS28226DRBT
TPS28226DRBR
-40C to 125C
250
3000
(1) SOIC-8 (D) and DFN-8 (DRB) packages are available taped and reeled. Add T suffix to device type (e.g. TPS28226DRBT) to order
taped devices and suffix R (e.g. TPS28226DRBR) to device type to order reeled devices.
(2) The SOIC-8 (D) and DFN-8 (DRB) package uses in Pb-Free lead finish of Pd-Ni-Au which is compatible with MSL level 1 at 255C to
260C peak reflow temperature to be compatible with either lead free or Sn/Pb soldering operations.
(3) In the DFN package, the pad underneath the center of the device is a thermal substrate. The PCB “thermal land” design for this
exposed die pad should include thermal vias that drop down and connect to one or more buried copper plane(s). This combination of
vias for vertical heat escape and buried planes for heat spreading allows the DFN to achieve its full thermal potential. This pad should
be either grounded for best noise immunity, and it should not be connected to other nodes.
4
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SLUS791–OCTOBER 2007
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
(1)(2)
TPS28226
VALUE
UNIT
–0.3 to 8.8
(3)
Input supply voltage range, VDD
Boot voltage, VBOOT
–0.3 to 33
DC
Phase voltage, VPHASE
–2 to 32 or VBOOT + 0.3 – VDD whichever is less
–7 to 33.1 or VBOOT + 0.3 – VDD whichever is less
–0.3 to 13.2
Pulse < 400 ns, E = 20 μJ
Input voltage range, VPWM, VEN/PG
VPHASE – 0.3 to VBOOT + 0.3, (VBOOT – VPHASE < 8.8)
V
Output voltage range, VUGATE
Pulse < 100 ns, E = 2 μJ
VPHASE – 2 to VBOOT + 0.3, (VBOOT – VPHASE < 8.8)
–0.3 to VDD + 0.3
Output voltage range, VLGATE
Pulse < 100 ns, E = 2 μJ
–2 to VDD + 0.3
ESD rating, HBM
2 k
ESD rating, HBM ESD rating, CDM
Continuous total power dissipation
Operating virtual junction temperature range, TJ
Operating ambient temperature range, TA
Storage temperature, Tstg
500
See Dissipation Rating Table
–40 to 150
–40 to 125
–65 to 150
300
°C
Lead temperature (soldering, 10 sec.)
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) These devices are sensitive to electrostatic discharge; follow proper device handling procedures.
(3) All voltages are with respect to GND unless otherwise noted. Currents are positive into, negative out of the specified terminal. Consult
Packaging Section of the Data book for thermal limitations and considerations of packages.
DISSIPATION RATINGS(1)
DERATING FACTOR
ABOVE TA = 25°C
TA < 25°C
POWER RATING
TA =70°C
POWER RATING
TA = 85°C
POWER RATING
BOARD
PACKAGE
RθJC
RθJA
High-K(2)
High-K(3)
D
39.4°C/W
1.4°C/W
100C/W
48.5C/W
10 mW/C
1.25 W
2.58 W
0.8 W
0.65 W
1.34 W
DRB
20.6 mW/C
1.65 W
(1) These thermal data are taken at standard JEDEC test conditions and are useful for the thermal performance comparison of different
packages. The cooling condition and thermal impedance RθJA of practical design is specific.
(2) The JEDEC test board JESD51-7, 3-inch x 3-inch, 4-layer with 1-oz internal power and ground planes and 2-oz top and bottom trace
layers.
(3) The JEDEC test board JESD51-5 with direct thermal pad attach, 3-inch x 3-inch, 4-layer with 1-oz internal power and ground planes and
2-oz top and bottom trace layers.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
6.8
3
TYP
MAX
8
UNIT
V
VDD Input supply voltage
7.2
VIN
TJ
Power input voltage
32 V–VDD
125
Operating junction temperature range
–40
C
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SLUS791–OCTOBER 2007
ELECTRICAL CHARACTERISTICS(1)
VDD = 7.2 V, EN/PG pulled up to VDD by 100-kΩ resistor, TA = TJ = –40°C to 125°C (unless otherwise noted)
PARAMETER
UNDER VOLTAGE LOCKOUT
TEST CONDITIONS
MIN
TYP MAX UNIT
Rising threshold
Falling threshold
Hysteresis
6.35 6.70
VPWM = 0 V
4.7
5.0
V
1.00
1.35
BIAS CURRENTS
IDD(off) Bias supply current
IDD Bias supply current
INPUT (PWM)
VEN/PG = low, PWM pin floating
VEN/PG = high, PWM pin floating
350
500
μA
VPWM = 5 V
VPWM = 0 V
185
–200
1.0
IPWM
Input current
μA
V
PWM 3-state rising threshold(2)
PWM 3-state falling threshold
VPWM PEAK = 5 V
3.4
3.8
4.0
2.1
tHLD_R 3-state shutdown Hold-off time
TMIN PWM minimum pulse to force UGATE pulse
250
30
ns
CL = 3 nF at UGATE , VPWM = 5 V
ENABLE/POWER GOOD (EN/PG)
Enable high rising threshold
Enable low falling threshold
Hysteresis
PG FET OFF
PG FET OFF
1.7
1.0
0.8
V
0.35
0.70
Power good output
VDD = 2.5 V
0.2
2.0
UPPER GATE DRIVER OUTPUT (UGATE)
Source resistance
500 mA source current
VUGATE-PHASE = 2.5 V
CL = 3 nF
1.0
2.0
10
Ω
A
(2)
Source current
tRU
Rise time
ns
Ω
Sink resistance
500 mA sink current
VUGATE-PHASE = 2.5 V
CL = 3 nF
1.0
2.0
10
2.0
(2)
Sink current
A
tFU
Fall time
ns
(1) Typical values for TA = 25C
(2) Not tested in production
6
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SLUS791–OCTOBER 2007
ELECTRICAL CHARACTERISTICS (continued)
VDD = 7.2 V, EN/PG pulled up to VDD by 100-kΩ resistor, TA = TJ = –40°C to 125°C (unless otherwise noted)
PARAMETER
LOWER GATE DRIVER OUTPUT (LGATE)
Source resistance
TEST CONDITIONS
MIN
TYP MAX UNIT
500 mA source current
1.0
2.0
10
0.4
4.0
5
2.0
1.0
Ω
A
Source current(3)
VLGATE = 2.5 V
CL = 3 nF
tRL
Rise time(3)
ns
Ω
Sink resistance
Sink current(3)
Fall time(3)
500 mA sink current
VLGATE = 2.5 V
CL = 3 nF
A
ns
SWITCHING TIME
tDLU
tDLL
tDTU
tDTL
UGATE turn-off propagation Delay
CL = 3 nF
CL = 3 nF
CL = 3 nF
CL = 3 nF
14
14
14
14
LGATE turn-off propagation Delay
ns
Dead time LGATE turn-off to UGATE turn-on
Dead time UGATE turn-off to LGATE turn-on
BOOTSTRAP DIODE
VF Forward voltage
Forward bias current 100 mA
1.0
V
THERMAL SHUTDOWN
Rising threshold(3)
Falling threshold(3)
Hysteresis
150
130
160
140
20
170
150
°C
(3) Not tested in production
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SLUS791–OCTOBER 2007
DEVICE INFORMATION
SOIC-8 Package (top view)
1
2
3
4
8
7
6
5
UGATE
BOOT
PWM
PHASE
EN/PG
VDD
GND
LGATE
DRB-8 Package (top view)
U G ATE
BOOT
PWM
1
2
3
4
8
7
6
5
PHASE
EN/PG
VDD
Exposed
Thermal
Die Pad
GND
LG AT E
FUNCTIONAL BLOCK DIAGRAM
6
7
2
VDD
BOOT
UVLO
UGATE
PHASE
1
8
EN /PG
THERMAL
SD
SHOOT
−
HLD−OFF
TIME
THROUGH
PROTECTION
VDD
27K
3−STATE
INPUT
3
5
4
PWM
LGATE
GND
CIRCUIT
13K
A. For the TPS28226DRB device the thermal PAD on the bottom side of package must be soldered and connected to
the GND pin and to the GND plane of the PCB in the shortest possible way. See Recommended Land Pattern in the
Application section.
8
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SLUS791–OCTOBER 2007
TERMINAL FUNCTIONS
TERMINAL
I/O
DESCRIPTION
SOIC-8
DRB-8
NAME
1
1
UGATE
O
Upper gate drive sink/source output. Connect to gate of high-side power N-Channel MOSFET.
Floating bootstrap supply pin for the upper gate drive. Connect the bootstrap capacitor between
2
2
BOOT
I/O this pin and the PHASE pin. The bootstrap capacitor provides the charge to turn on the upper
MOSFET.
The PWM signal is the control input for the driver. The PWM signal can enter three distinct states
3
4
3
4
PWM
GND
I
during operation, see the 3-state PWM Input section under DETAILED DESCRIPTION for further
details. Connect this pin to the PWM output of the controller.
—
—
Ground pin. All signals are referenced to this node.
Exposed Thermal
die pad
Connect directly to the GND for better thermal performance and EMI
pad
LGATE
VDD
Lower gate drive sink/source output. Connect to the gate of the low-side power N-Channel
MOSFET.
5
6
5
6
O
I
Connect this pin to a 5-V bias supply. Place a high quality bypass capacitor from this pin to GND.
Enable/Power Good input/output pin with 1MΩ impedance. Connect this pin to HIGH to enable and
LOW to disable the device. When disabled, the device draws less than 350μA bias current. If the
VDD is below UVLO threshold or over temperature shutdown occurs, this pin is internally pulled
low.
7
8
7
8
EN/PG
PHASE
I/O
I
Connect this pin to the source of the upper MOSFET and the drain of the lower MOSFET. This pin
provides a return path for the upper gate driver.
TRUTH TABLE
VDD FALLING > 3 V AND TJ < 150°C
VDD RISING < 3.5 V
OR TJ > 160°C
EN/PG FALLING > 1.0 V
EN/PG RISING
PIN
PWM > 1.5 V AND
PWM SIGNAL SOURCE IMPEDANCE
< 1.7 V
PWM < 1 V
TRISE/TFALL < 200 ns
>40 kΩ FOR > 250ns (3-State)(1)
LGATE
UGATE
EN/PG
Low
Low
Low
Low
Low
High
Low
Low
Low
Low
High
(1) During power up, the TPS28226 is in 3-state and both UGATE and LGATE outputs are kept low. To exit the 3-state condition, the PWM
signal should go high followed by one low PWM signal. The first high PWM pulse is ignored by the driver and keeps UGATE output low,
but the following low PWM signal drives LGATE high.
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SLUS791–OCTOBER 2007
TPS28226 TIMING DIAGRAM
Enter into 3-State at
PWM rise
Enter into 3-State at
PWM fall
Normal switching
Exit 3-State
90%
3-State
window
50%
50%
PWM
tPWM_MIN
tHLD_F
10%
tHLD_R
tRU
90%
10%
tRL
90%
90%
tDLU
UGATE
10%
tFU
90%
tDTU
10%
90%
tDLL
90%
tDTL
LGATE
10%
tFL
LGATE exits 3-State after PWM
goes High and then Low
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SLUS791–OCTOBER 2007
TYPICAL CHARACTERISTICS
BIAS SUPPLY CURRENT
vs
UNDER VOLTAGE LOCKOUT THRESHOLD
TEMPERATURE
(VEN/PG = Low, PWM Input Floating, VDD = 7.2V)
vs
TEMPERATURE
8.00
500
7.50
7.00
480
460
TPS28226 Rising
6.50
6.00
440
420
400
380
360
5.50
5.00
4.50
4.00
TPS28226 Falling
3.50
340
320
3.00
2.50
2.00
300
−40
25
125
−40
25
125
T − Temperature −° C
J
TJ − Temperature − C
Figure 1.
Figure 2.
ENABLE/POWER GOOD THRESHOLD
PWM 3-STATE THRESHOLDS, (5-V Input Pulses)
vs
vs
TEMPERATURE (VDD = 7.2 V)
TEMPERATURE, (VDD = 7.2 V)
2.00
5.0
4.5
4.0
2.5
Rising
1.75
1.50
Falling
1.25
1.00
0.75
0.50
0.25
0.00
3.0
2.5
2.0
1.5
Falling
Rising
1.0
0.5
0.0
−40
25
125
−40
25
125
T − Temperature −° C
J
T − Temperature −° C
J
Figure 3.
Figure 4.
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SLUS791–OCTOBER 2007
TYPICAL CHARACTERISTICS (continued)
UGATE DC OUTPUT IMPEDANCE
LGATE DC OUTPUT IMPEDANCE
vs
vs
TEMPERATURE, (VDD = 7.2 V)
TEMPERATURE (VDD = 7.2 V)
2.00
2.00
1.75
1.50
1.25
1.00
0.75
0.50
0.25
0
1.75
1.50
R
1.25
1.00
0.75
0.50
0.25
0
SOURCE
R
SOURCE
R
SINK
R
SINK
−40
25
125
−40
25
125
T − Temperature −° C
J
T − Temperature −° C
J
Figure 5.
Figure 6.
UGATE RISE AND FALL TIME
LGATE RISE AND FALL TIME
vs
TEMPERATURE (VDD = 7.2 V, CLOAD = 3 nF)
vs
TEMPERATURE (VDD = 7.2 V, CLOAD = 3 nF)
14
13
15
14
13
Rising
12
11
Rising
12
11
10
9
10
9
8
7
Falling
Falling
8
7
6
5
4
6
−40
25
125
−40
25
125
T − Temperature −° C
J
T − Temperature −° C
J
Figure 7.
Figure 8.
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SLUS791–OCTOBER 2007
TYPICAL CHARACTERISTICS (continued)
UGATE AND LGATE (Turning OFF Propagation Delays)
UGATE AND LGATE (Dead Time)
vs
vs
TEMPERTURE (VDD = 7.2 V, CLOAD = 3 nF)
TEMPERTURE (VDD = 7.2 V, CLOAD = 3 nF)
30
25
20.0
17.5
15.0
12.5
10.0
7.5
U
GATE
U
GATE
20
15
L
GATE
L
GATE
10
5.0
5
0
2.5
0.0
−40
25
125
−40
25
125
T − Temperature −° C
J
T − Temperature −° C
J
Figure 9.
Figure 10.
UGATE MINIMUM SHORT PULSE
BOOTSTRAP DIODE FORWARD VOLTAGE
vs
vs
TEMPERATURE (VDD = 7.2 V, CLOAD = 3 nF)
TEMPERATURE (VDD = 7.2 V, IF = 100 mA)
30
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
25
20
15
10
5
0
−40
25
125
−40
25
125
T − Temperature −° C
J
T − Temperature −° C
J
Figure 11.
Figure 12.
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SLUS791–OCTOBER 2007
TYPICAL CHARACTERISTICS (continued)
BIAS SUPPLY CURRENT
DRIVER DISSIPATED POWER
vs
vs
SWITCHING FREQUENCY
(VDD = 7.2 V, No Load, TJ = 25°C)
SWITCHING FREQUENCY
(Different Load Charge, VDD = 7.2 V, TJ = 25°C)
15
10
1200
1000
800
U
L
= 50 nC
= 50 nC
G
G
U
L
= 25 nC
= 100 nC
G
G
U
L
= 25 nC
= 50 nC
G
G
600
400
200
5
0
0
100 300 500 700 900 1100 1300 1500 1700 1900
100 300 500 700 900 1100 1300 1500 1700 1900
F
SW
− Switching Frequency − kHz
F
SW
− Switching Frequency − kHz
Figure 13.
Figure 14.
PWM INPUT RISING SWITCHING WAVEFORMS
= 7.2 V, C = 3 nF, T = 25°C
PWM INPUT FALLING SWITCHING WAVEFORMS
V
DD
L
J
V
DD
= 7.2 V, C = 3 nF, T = 25°C
L J
PWM
PWM
LGATE
UGATE
LGATE
UGATE
t − Time − 10 ns/div.
t − Time − 10 ns/div.
Figure 15.
Figure 16.
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TYPICAL CHARACTERISTICS (continued)
NORMAL AND 3-STATE OPERATION
ENTER/EXIT CONDITIONS
MINIMUM UGATE PULSE SWITCHING WAVEFORMS
V
DD
= 7.2 V, C = 3 nF, T = 25°C
L
J
PWM 30ns
PWM − 2 V/div.
LGATE
UGATE
3−St Trigger, High = 3−St
UGATE − 10 V/div.
LGATE − 10 V/div.
t − Time − 5 µs/div.
t − Time − 20 ns/div.
Figure 17.
Figure 18. The 3-state upper threshold reverts to the 2-V
level after the TPS28226 had been in 3-state for about
2.5 μs.
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DETAILED DESCRIPTION
Under Voltage Lockout (UVLO)
The TPS28226 incorporates an under voltage lockout circuit that keeps the driver disabled and external power
FETs in an OFF state when the input supply voltage VDD is insufficient to drive external power FETs reliably.
During power up, both gate drive outputs remain low until voltage VDD reaches UVLO threshold, typically 6.35 V
for the TPS28226. Once the UVLO threshold is reached, the condition of gate drive outputs is defined by the
input PWM and EN/PG signals. During power down the UVLO threshold is set lower, typically 5.0 V for the
TPS28226. The 1.35 V for the TPS28226 hysteresis is selected to prevent the driver from turning ON and OFF
while the input voltage crosses UVLO thresholds, especially with low slew rate. The TPS28226 has the ability to
send a signal back to the system controller that the input supply voltage VDD is insufficient by internally pulling
down the EN/PG pin. The TPS28226 releases EN/PG pin immediately after the VDD has risen above the UVLO
threshold.
Output Active Low
The output active low circuit effectively keeps the gate outputs low even if the driver is not powered up. This
prevents open gate conditions on the external power FETs and accidental turn ON when the main power stage
supply voltage is applied before the driver is powered up. For the simplicity, the output active low circuit is shown
in a block diagram as the resistor connected between LGATE and GND pins with another one connected
between UGATE and PHASE pins.
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Enable/Power Good
The Enable/Power Good circuit allows the TPS28226 to follow the PWM input signal when the voltage at EN/PG
pin is above 2.1 V maximum. This circuit has a unique two-way communication capability. This is illustrated by
Figure 19.
V
DD
= 6.8 V to 8.0 V for the TPS28226
V
CC
Driver TPS28226
2 V Rise
6
System
. 20 kΩ
EN/PG
Controller
1 V Fall
1 kΩ
7
R
DS(on)
= 1 kΩ
UVLO
1 M
Thermal SD
Figure 19. Enable/Power Good Circuit
The EN/PG pin has approximately 1-kΩ internal series resistor. Pulling EN/PG high by an external ≥ 20-kΩ
resistor allows two-way communication between controller and driver. If the input voltage VDD is below UVLO
threshold or thermal shut down occurs, the internal MOSFET pulls EN/PG pin to GND through 1-kΩ resistor. The
voltage across the EN/PG pin is now defined by the resistor divider comprised by the external pull up resistor,
1-kΩ internal resistor and the internal FET having 1-kΩ RDS(on). Even if the system controller allows the driver to
start by setting its own enable output transistor OFF, the driver keeps the voltage at EN/PG low. Low EN/PG
signal indicates that the driver is not ready yet because the supply voltage VDD is low or that the driver is in
thermal shutdown mode. The system controller can arrange the delay of PWM input signals coming to the driver
until the driver releases EN/PG pin. If the input voltage VDD is back to normal, or the driver is cooled down below
its lower thermal shutdown threshold, then the internal MOSFET releases the EN/PG pin and normal operation
resumes under the external Enable signal applied to EN/PG input. Another feature includes an internal 1-MΩ
resistor that pulls EN/PG pin low and disables the driver in case the system controller accidentally loses
connection with the driver. This could happen if, for example, the system controller is located on a separate PCB
daughter board.
The EN/PG pin can serve as the second pulse input of the driver additionally to PWM input. The delay between
EN/PG and the UGATE going high, provided that PWM input is also high, is only about 30ns. If the PWM input
pulses are synchronized with EN/PG input, then when PWM and EN/PG are high, the UGATE is high and
LGATE is low. If both PWM and EN/PG are low, then UGATE and LGATE are both low as well. This means the
driver allows operation of a synchronous buck regulator as a convertional buck regulator using the body diode of
the low side power MOSFET as the freewheeling diode. This feature can be useful in some specific applications
to allow startup with a pre-biased output or, to improve the efficiency of buck regulator when in power saving
mode with low output current.
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3-State Input
As soon as the EN/PG pin is set high and input PWM pulses are initiated (see Note below). The dead-time
control circuit ensures that there is no overlapping between UGATE and LGATE drive outputs to eliminate shoot
through current through the external power FETs. Additionally to operate under periodical pulse sequencing, the
TPS28226 has a self-adjustable PWM 3-state input circuit. The 3-state circuit sets both gate drive outputs low,
and thus turns the external power FETs OFF if the input signal is in a high impedance state for at least 250 ns
typical. At this condition, the PWM input voltage level is defined by the internal 27kΩ to 13kΩ resistor divider
shown in the block diagram. This resistor divider forces the input voltage to move into the 3-state window. Initially
the 3-state window is set between 1.0-V and 2.0-V thresholds. The lower threshold of the 3-state window is
always fixed at about 1.0 V. The higher threshold is adjusted to about 75% of the input signal amplitude. The
3-state upper threshold reverts to the 2-V level after the TPS28226 had been in 3-state for about 2.5 μs. The
self-adjustable upper threshold allows shorter delay if the input signal enters the 3-state window while the input
signal was high, thus keeping the high-side power FET in ON state just slightly longer than 250 ns time constant
set by an internal 3-state timer. Both modes of operation, PWM input pulse sequencing and the 3-state condition,
are illustrated in the timing diagrams shown in Figure 18. The self-adjustable upper threshold allows operation in
wide range amplitude of input PWM pulse signals. The waveforms in Figure 20 and Figure 21 illustrates the
TPS28226 operation at normal and 3-state mode with the input pulse amplitudes 6 V and 2.5 V accordingly. After
entering into the 3-state window and staying within the window for the hold-off time, the PWM input signal level is
defined by the internal resistor divider and, depending on the input pulse amplitude, can be pulled up above the
normal PWM pulse amplitude (Figure 21) or down below the normal input PWM pulse (Figure 20).
TPS28226 3-State Exit Mode:
•
To exit the 3-state operation mode, the PWM signal should go high and then low at least once.
This is necessary to restore the voltage across the bootstrap capacitor that could be discharged during the
3-state mode if the 3-state condition lasts long enough.
Figure 20. 6-V Amplitude PWM Pulse
Figure 21. 2.5-V Amplitude PWM Pulse
NOTE:
The driver sets UGATE low and LGATE high when PWM is low. When the PWM goes
high, UGATE goes high and LGATE goes low.
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IMPORTANT NOTE: Any external resistor between PWM input and GND with the value lower than 40kΩ can
interfere with the 3-state thresholds. If the driver is intended to operate in the 3-state mode, any resistor below
40kΩ at the PWM and GND should be avoided. A resistor lower than 3.5kΩ connected between the PWM and
GND completely disables the 3-state function. In such case, the 3-state window shrinks to zero and the lower
3-state threshold becomes the boundary between the UGATE staying low and LGATE being high and vice versa
depending on the PWM input signal applied. It is not necessary to use a resistor <3.5kΩ to avoid the 3-state
condition while using a controller that is 3-state capable. If the rise and fall time of the input PWM signal is
shorter than 250ns, then the driver never enter into the 3-state mode.
In the case where the low-side MOSFET of a buck converter stays on during shutdown, the 3-state feature can
be fused to avoid negative resonent voltage across the output capacitor. This feature also can be used during
start up with a pre-biased output in the case where pulling the output low during the startup is not allowed due to
system requirements. If the system controller does not have the 3-state feature and never goes into the
high-impedance state, then setting the EN/PG signal low will keep both gate drive outputs low and turn both low-
and high-side MOSFETs OFF during the shut down and start up with the pre-biased output.
The self-adjustable input circuit accepts wide range of input pulse amplitudes (2V up to 13.2V) allowing use of a
variety of controllers with different outputs including logic level. The wide PWM input voltage allows some
flexibility if the driver is used in secondary side synchronous rectifier circuit. The operation of the TPS28226 with
a 12-V input PWM pulse amplitude, and with VDD = 7.2V shown in Figure 22.
Figure 22. 12-V PWM Pulse at VDD = 7.2 V
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Bootstrap Diode
The bootstrap diode provides the supply voltage for the UGATE driver by charging the bootstrap capacitor
connected between BOOT and PHASE pins from the input voltage VDD when the low-side FET is in ON state.
At the very initial stage when both power FETs are OFF, the bootstrap capacitor is pre-charged through this path
including the PHASE pin, output inductor and large output capacitor down to GND. The forward voltage drop
across the diode is only 1.0V at bias current 100 mA. This allows quick charge restore of the bootstrap capacitor
during the high-frequency operation.
Upper And Lower Gate Drivers
The upper and lower gate drivers charge and discharge the input capacitance of the power MOSFETs to allow
operation at switching frequencies up to 2 MHz. The output stage consists of a P-channel MOSFET providing
source output current and an N-channel MOSFET providing sink current through the output stage. The ON state
resistances of these MOSFETs are optimized for the synchronous buck converter configuration working with low
duty cycle at the nominal steady state condition. The UGATE output driver is capable of propagating PWM input
puses of less than 30-ns while still maintaining proper dead time to avoid any shoot through current conditions.
The waveforms related to the narrow input PWM pulse operation are shown in Figure 17.
Dead-Time Control
The dead-time control circuit is critical for highest efficiency and no shoot through current operation througout the
whole duty cycle range with the different power MOSFETs. By sensing the output of driver going low, this circuit
does not allow the gate drive output of another driver to go high until the first driver output falls below the
specified threshold. This approach to control the dead time is called adaptive. The overall dead time also
includes the fixed portion to ensure that overlapping never exists. The typical dead time is around 14 ns,
although it varies over the driver internal tolerances, layout and external MOSFET parasitic inductances. The
proper dead time is maintained whenever the current through the output inductor of the power stage flows in the
forward or reverse direction. Reverse current could happen in a buck configuration during the transients or while
dynamically changing the output voltage on the fly, as some microprocessors require. Because the dead time
does not depend on inductor current direction, this driver can be used both in buck and boost regulators or in any
bridge configuration where the power MOSFETs are switching in a complementary manner. Keeping the dead
time at short optimal level boosts efficiency by 1% to 2% depending on the switching frequency. Measured
switching waveforms in one of the practical designs show 10-ns dead time for the rising edge of PHASE node
and 22 ns for the falling edge (Figure 28 and Figure 29 in the Application Section of the data sheet).
Large non-optimal dead time can cause duty cycle modulation of the dc-to-dc converter during the operation
point where the output inductor current changes its direction right before the turn ON of the high-side MOSFET.
This modulation can interfere with the controller operation and it impacts the power stage frequency response
transfer function. As the result, some output ripple increase can be observed. The TPS28226 driver is designed
with the short adaptive dead time having fixed delay portion that eliminates risk of the effective duty cycle
modulation at the described boundary condition.
Thermal Shutdown
If the junction temperature exceeds 160°C, the thermal shutdown circuit will pull both gate driver outputs low and
thus turning both, low-side and high-side power FETs OFF. When the driver cools down below 140°C after a
thermal shutdown, then it resumes its normal operation and follows the PWM input and EN/PG signals from the
external control circuit. While in thermal shutdown state, the internal MOSFET pulls the EN/PG pin low, thus
setting a flag indicating the driver is not ready to continue normal operation. Normally the driver is located close
to the MOSFETs, and this is usually the hottest spots on the PCB. Thus, the thermal shutdown feature of
TPS28226 can be used as an additional protection for the whole system from overheating.
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APPLICATION INFORMATION
Switching The MOSFETs
Driving the MOSFETs efficiently at high switching frequencies requires special attention to layout and the
reduction of parasitic inductances. Efforts need to be done both at the driver’s die and package level and at the
PCB layout level to keep the parasitic inductances as low as possible. Figure 23 shows the main parasitic
inductances and current flow during turning ON and OFF of the MOSFET by charging its CGS gate capacitance.
L bond wire
L trace
L pin
VDD
6
5
4
I source
Cvdd
Rsource
L trace
L trace
L bond wire
L pin
Driver
Output
Stage
Rg
LGATE
Rsink
I sink
Cgs
L pin
L bond wire
L trace
GND
Figure 23. MOSFET Drive Paths and Main Circuit Parasitics
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The ISOURCE current charges the gate capacitor and the ISINK current discharges it. The rise and fall time of
voltage across the gate defines how quickly the MOSFET can be switched. The timing parameters specified in
datasheet for both upper and lower driver are shown in Figure 15 and Figure 16 where 3-nF load capacitor has
been used for the characterization data. Based on these actual measurements, the analytical curves in Figure 24
and Figure 25 show the output voltage and current of upper and low side drivers during the discharging of load
capacitor. The left waveforms show the voltage and current as a function of time, while the right waveforms show
the relation between the voltage and current during fast switching. These waveforms show the actual switching
process and its limitations because of parasitic inductances. The static VOUT/ IOUT curves shown in many
datasheets and specifications for the MOSFET drivers do not replicate actual switching condition and provide
limited information for the user.
Voltage
Current
t − Time − ns
LGATE Current, A
Figure 24. LGATE Turning Off Voltage and Sink Current vs Time (Related Switching Diagram (right))
Voltage
Current
t − Time − ns
UGATE Current, A
Figure 25. UGATE Turning Off Voltage and Sink Current vs Time (Related Switching Diagram (right))
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Turning Off of the MOSFET needs to be done as fast as possible to reduce switching losses. For this reason the
TPS28226 driver has very low output impedance specified as 0.4Ω typ for lower driver and 1Ω typ for upper
driver at dc current. Assuming 8-V drive voltage and no parasitic inductances, one can expect an initial sink
current amplitude of 20A and 8A respectively for the lower and upper drivers. With pure R-C discharge circuit for
the gate capacitor, the voltage and current waveforms are expected to be exponential. However, because of
parasitic inductances, the actual waveforms have some ringing and the peak current for the lower driver is about
4A and about 2.5A for the upper driver (Figure 24 and Figure 25). The overall parasitic inductance for the lower
drive path is estimated as 4nH and for the upper drive path as 6nH. The internal parasitic inductance of the
driver, which includes inductances of bonded wires and package leads, can be estimated for SOIC-8 package as
2nH for lower gate and 4nH for the upper gate. Use of DFN-8 package reduces the internal parasitic inductances
by approximately 50%.
Layout Recommendations
To improve the switching characteristicsand efficiency of a design, the following layout rules need to be followed.
•
•
•
Locate the driver as close as possible to the MOSFETs.
Locate the VDD and bootstrap capacitors as close as possible to the driver.
Pay special attention to the GND trace. Use the thermal pad of the DFN-8 package as the GND by
connecting it to the GND pin. The GND trace or pad from the driver goes directly to the source of the
MOSFET but should not include the high current path of the main current flowing through the drain and
source of the MOSFET.
•
•
Use a similar rule for the PHASE node as for the GND.
Use wide traces for UGATE and LGATE closely following the related PHASE and GND traces. Eighty to 100
mils width is preferable where possible.
•
•
Use at least 2 or more vias if the MOSFET driving trace needs to be routed from one layer to another. For the
GND the number of vias are determined not only by the parasitic inductance but also by the requirements for
the thermal pad.
Avoid PWM and enable traces going close to the PHASE node and pad where high dV/dT voltage can induce
significant noise into the relatively high impedance leads.
It should be taken into account that poor layout can cause 3% to 5% less efficiency versus a good layout design
and can even decrease the reliability of the whole system.
Figure 26. One of Four Phases Driven by TPS28226 Driver in 4-phase VRM Reference Design
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The schematic of one of the phases in a multi-phase synchronous buck regulator and the related layout are
shown in Figure 26 and Figure 27. These help to illustrate good design practices. The power stage includes one
high-side MOSFET Q10 and two low-side MOSFETS (Q8 and Q9). The driver (U7) is located on bottom side of
PCB close to the power MOSFETs. The related switching waveforms during turning ON and OFF of upper FET
are shown in Figure 28 and Figure 29. The dead time during turning ON is only 10ns (Figure 28) and 22ns during
turning OFF (Figure 29).
Figure 27. Component Placement Based on Schematic in Figure 26
Figure 28. Phase Rising Edge Switching Waveforms (20ns/div) of the Power Stage in Figure 26
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Figure 29. Phase Falling Edge Switching Waveforms (10ns/div) of the Power State in Figure 26
List of Materials
The list of materials for this specific example is provided in the table. The component vendors are not limited to
those shown in the table below. It should be notd that, in this example, the power MOSFET packages were
chosen with drains on top. The decoupling capacitors C47, C48, C65, and C66 were chosen to have low profiles.
This allows the designer to meet good layout rules and place a heatsink on top of the FETs using an electrically
isolated and thermally conductive pad.
List of Materials
REF DES
COUNT
DESCRIPTION
MANUFACTURE
PART NUMBER
C47, C48,
C65, C66
4
Capacitor, ceramic, 4.7 μF, 16 V, X5R 10%, low profile 0.95 mm, 1206
TDK
C3216X5R1C475K
C41, C42
C50, C51
C23
2
2
1
3
Capacitor, ceramic, 10 μF, 16 V, X7R 10%, 1206
Capacitor, ceramic, 1000 pF, 50 V, X7R, 10%, 0603
Capacitor, ceramic, 0.22 μF, 16 V, X7R, 10%, 0603
Capacitor, ceramic, 1 μF, 16 V, X7R, 10%, '0603
TDK
Std
Std
Std
C3216X7R1C106K
Std
Std
Std
C25, C49,
C71
L3
1
2
1
1
2
1
Inductor, SMT, 0.12 μH, 31 A, 0.36 mΩ, 0.400 x 0.276
Mosfet, N-channel, VDS 30 V, RDS 2.4 mΩ, ID 45 A, LFPAK-i
Mosfet, N-channel, VDS 30 V, RDS 6.2 mΩ, ID 30 A, LFPAK-i
Resistor, chip, 0 Ω, 1/10 W, 1%, '0805
Pulse
Renesas
Renesas
Std
PA0511-101
RJK0301DPB-I
RJK0305DPB-I
Std
Q8, Q9
Q10
R32
R51, R52
U7
Resistor, chip, 2.2 Ω, 1/10 W, 1%, '0805
Std
Std
Device, High Frequency 4-A Sink Synchronous Buck MOSFET Driver,
DFN-8
Texas Instruments
TPS28226DRB
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Efficiency of Power Stage vs Load Current at Different Switching Frequencies
Efficiency achieved using TPS28226 driver with 8-V drive at different switching frequencies a similar industry 5-V
driver using the power stage in Figure 26 is shown in Figure 32, Figure 34, Figure 33, Figure 30 and Figure 31.
EFFICIENCY
vs
LOAD CURRENT
EFFICIENCY
vs
LOAD CURRENT
90
85
90
85
80
75
80
75
TI: 400kHz
Ind: 400kHz
TI: 500kHz
Ind: 500kHz
5
10
15
20
25
30
35
5
10
15
20
25
30
35
C
L
− Load Currnt − A
C
L
− Load Currnt − A
Figure 30.
Figure 31.
EFFICIENCY
vs
LOAD CURRENT
90
85
TI: 600kHz
Ind: 600kHz
80
75
5
10
15
20
25
30
35
C
L
− Load Currnt − A
Figure 32.
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EFFICIENCY
vs
LOAD CURRENT
EFFICIENCY
vs
LOAD CURRENT
90
90
85
TI: 700kHz
TI: 800kHz
Ind: 800kHz
Ind: 700kHz
85
80
80
75
75
5
10
15
20
25
30
35
5
10
15
20
25
30
35
C
L
− Load Currnt − A
Figure 33.
C
L
− Load Currnt − A
Figure 34.
When using the same power stage, the driver with the optimal drive voltage and optimal dead time can boost
efficiency up to 5%. The optimal 8-V drive voltage versus 5-V drive contributes 2% to 3% efficiency increase and
the remaining 1% to 2% can be attributed to the reduced dead time. The 7-V to 8-V drive voltage is optimal for
operation at switching frequency range above 400kHz and can be illustrated by observing typical RDS(on) curves
of modern FETs as a function of their gate drive voltage. This is shown in Figure 35.
DRIVE LOSS
vs
SWITCHING FREQUENCY
2.0
12−V
Estimation
1.5
SOIC−8
Package
Limit at 45°C
Rdson
Vg = 7V
@
Rdson
@
Vg = 5V
1.0
0.5
8−V
TPS28226
5−V
Ind. Std.
0.0
400
500
600
700
800
F
SW
− Switching Frequency − kHz
Figure 35. RDS(on) of MOSFET as Function of VGS
Figure 36. Drive Power as Function of VGS and FSW
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The plots show that the RDS(on) at 5-V drive is substantially larger than at 7 V and above that the RDS(on) curve is
almost flat. This means that moving from 5-V drive to an 8-V drive boosts the efficiency because of lower RDS(on)
of the MOSFETs at 8 V. Further increase of drive voltage from 8 V to 12 V only slightly decreases the conduction
losses but the power dissipated inside the driver increases dramatically (by 125%). The power dissipated by the
driver with 5V, 8V and 12V drive as a function of switching frequency from 400kHz to 800kHz. It should be noted
that the 12-V driver exceeds the maximum dissipated power allowed for an SOIC-8 package even at 400-kHz
switching frequency.
RELATED PRODUCTS
•
•
•
TPS40090, 2/3/4-Phase Multi-Phase Controller
TPS40091, 2/3/4-Phase Multi-Phase Controller
TPS28225, High-Frequency 4-A Sink Synchronous MOSFET Drivers
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PACKAGE MATERIALS INFORMATION
www.ti.com
5-Nov-2007
TAPE AND REEL BOX INFORMATION
Device
Package Pins
Site
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) (mm) Quadrant
(mm)
330
(mm)
12
TPS28226DR
TPS28226DRBR
TPS28226DRBT
D
8
8
8
SITE 27
SITE 41
SITE 41
6.4
3.3
3.3
5.2
3.3
3.3
2.1
1.1
1.1
8
8
8
12
12
12
Q1
Q2
Q2
DRB
DRB
330
12
180
12
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Nov-2007
Device
Package
Pins
Site
Length (mm) Width (mm) Height (mm)
TPS28226DR
TPS28226DRBR
TPS28226DRBT
D
8
8
8
SITE 27
SITE 41
SITE 41
342.9
346.0
190.0
336.6
346.0
212.7
20.64
29.0
DRB
DRB
31.75
Pack Materials-Page 2
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Following are URLs where you can obtain information on other Texas Instruments products and application solutions:
Products
Amplifiers
Data Converters
DSP
Applications
Audio
amplifier.ti.com
dataconverter.ti.com
dsp.ti.com
www.ti.com/audio
Automotive
Broadband
Digital Control
Military
www.ti.com/automotive
www.ti.com/broadband
www.ti.com/digitalcontrol
www.ti.com/military
Interface
interface.ti.com
logic.ti.com
Logic
Power Mgmt
Microcontrollers
RFID
power.ti.com
Optical Networking
Security
www.ti.com/opticalnetwork
www.ti.com/security
www.ti.com/telephony
www.ti.com/video
microcontroller.ti.com
www.ti-rfid.com
www.ti.com/lpw
Telephony
Low Power
Wireless
Video & Imaging
Wireless
www.ti.com/wireless
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