TPS2H160AQPWPRQ1 [TI]
具有可调节电流限制的 40V、160mΩ、2 通道汽车类智能高侧开关 | PWP | 16 | -40 to 125;
| 型号： | TPS2H160AQPWPRQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有可调节电流限制的 40V、160mΩ、2 通道汽车类智能高侧开关 | PWP | 16 | -40 to 125 开关 驱动 光电二极管 接口集成电路 驱动器 |
| 文件： | 总41页 (文件大小：2086K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TPS2H160-Q1
ZHCSF71D –DECEMBER 2015–REVISED DECEMBER 2019
TPS2H160-Q1 40V、160mΩ 双通道智能高侧开关
1 特性
•
诊断：
–
–
–
过流和接地短路检测
1
•
•
符合汽车类应用 要求
具有符合 AEC-Q100 标准的下列特性：
负载开路和电池短路检测
用于实现快速中断的全局故障
–
器件温度等级 1：–40°C 至 125°C 的环境工作
温度范围
•
16 引脚耐热增强型 PWP 封装
–
–
器件 HBM ESD 分类等级 H2
器件 CDM ESD 分类等级 C4B
2 应用
•
•
•
双通道 LED 驱动器，灯泡驱动器
•
•
提供功能安全
提供文档以帮助创建功能安全系统设计
具有丰富诊断功能的双通道 160mΩ 智能高侧开关
适用于子模块的双通道高侧开关
双通道高侧继电器，螺线管驱动器
–
–
–
版本 A：开漏状态输出
3 说明
版本 B：电流感应模拟输出
TPS2H160-Q1 系列是一款集成 160mΩ N 沟道金属氧
化物半导体 (NMOS) 功率场效应晶体管 (FET) 的双通
道智能高侧开关，配备全方位保护功能。
•
•
•
宽工作电压范围：3.4V 至 40V
超低待机电流：< 500nA
高精度电流感测：
该器件具有丰富的诊断功能和高精度电流感测 功能 ，
可对负载进行智能控制。
–
> 25mA 负载下为 ±17%
•
•
可使用外部电阻调节电流限值，> 500mA 的负载条
件下为 ±15%
该器件可从外部调节电流限值以限制浪涌或过载电流，
从而提升整个系统的可靠性。
保护：
–
–
–
–
通过（内部或外部）电流限制实现接地短路保护
具有锁闭选项的热关断以及热调节
感性负载负电压钳位，已优化转换率
失地保护和失电保护
器件信息(1)
器件型号
封装
通道
TPS2H160-Q1 版本A
TPS2H160-Q1 版本B
HTSSOP (16)
2
(1) 如需了解所有可用封装，请参阅产品说明书末尾的可订购产品
附录。
T48 路多路复用 LC6948
3.4-V to 40-V
Supply Voltage
驱动具有可调节电流限制的电容性负载
VS
IN1, 2
LED Strings,
Small Power Bulbs
DIAG_EN
THER
OUT1
Solenoids, Valves, Relays
FAULT
Sub-Modules:
Cameras, Sensors, Displays
SEL ST1
CS ST2
CL
Overcurrent is clamped
at the set value of 1 A.
OUT2
General Resistive, Capacitive,
Inductive Loads
GND
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLVSD74
TPS2H160-Q1
ZHCSF71D –DECEMBER 2015–REVISED DECEMBER 2019
www.ti.com.cn
目录
8.3 Feature Description................................................. 13
8.4 Device Functional Modes........................................ 24
Application and Implementation ........................ 26
9.1 Application Information............................................ 26
9.2 Typical Application ................................................. 26
1
2
3
4
5
6
7
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Device Comparison Table..................................... 3
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
7.1 Absolute Maximum Ratings ...................................... 4
7.2 ESD Ratings.............................................................. 5
7.3 Recommended Operating Conditions....................... 5
7.4 Thermal Information ................................................. 5
7.5 Electrical Characteristics........................................... 5
7.6 Switching Characteristics.......................................... 7
7.7 Typical Characteristics.............................................. 9
Detailed Description ............................................ 12
8.1 Overview ................................................................. 12
8.2 Functional Block Diagram ....................................... 13
9
10 Power Supply Recommendations ..................... 29
11 Layout................................................................... 30
11.1 Layout Guidelines ................................................. 30
11.2 Layout Examples................................................... 30
12 器件和文档支持 ..................................................... 32
12.1 接收文档更新通知 ................................................. 32
12.2 社区资源................................................................ 32
12.3 商标....................................................................... 32
12.4 静电放电警告......................................................... 32
12.5 Glossary................................................................ 32
13 机械、封装和可订购信息....................................... 32
8
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Revision C (February 2018) to Revision D
Page
•
向特性 部分添加了提供功能安全的链接.................................................................................................................................. 1
Changes from Revision B (August 2016) to Revision C
Page
•
•
Added footnote 2 to the Electrical Characteristics table......................................................................................................... 7
Added reverse current protection information to the Reverse-Current Protection section .................................................. 23
Changes from Revision A (June 2016) to Revision B
Page
•
•
•
•
更改了 ESD HBM 分类等级.................................................................................................................................................... 1
在第一页上添加重要图形 ........................................................................................................................................................ 1
Changed ESD Ratings table .................................................................................................................................................. 5
Changed Figure 7 .................................................................................................................................................................. 9
Changes from Original (December 2015) to Revision A
Page
•
将数据表从“产品预览”更改为“生产数据” ................................................................................................................................. 1
2
Copyright © 2015–2019, Texas Instruments Incorporated
TPS2H160-Q1
www.ti.com.cn
ZHCSF71D –DECEMBER 2015–REVISED DECEMBER 2019
5 Device Comparison Table
PART NUMBER
FAULT REPORTING MODE
Open-drain digital output
TPS2H160-Q1 Version A
TPS2H160-Q1 Version B
Current-sense analog output
6 Pin Configuration and Functions
PWP PowerPAD™ Package
16-Pin HTSSOP With Exposed Thermal Pad
TPS2H160-Q1 Version A Top View
IN1
IN2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
OUT1
OUT1
VS
DIAG_EN
NC
VS
Thermal
Pad
ST1
OUT2
OUT2
NC
ST2
CL
GND
THER
Not to scale
NC – No internal connection
PWP PowerPAD Package
16-Pin HTSSOP With Exposed Thermal Pad
TPS2H160-Q1 Version B Top View
IN1
IN2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
OUT1
OUT1
VS
DIAG_EN
FAULT
SEL
VS
Thermal
Pad
OUT2
OUT2
NC
CS
CL
GND
THER
Not to scale
NC – No internal connection
Copyright © 2015–2019, Texas Instruments Incorporated
3
TPS2H160-Q1
ZHCSF71D –DECEMBER 2015–REVISED DECEMBER 2019
www.ti.com.cn
Pin Functions
PIN
NO.
I/O
DESCRIPTION
NAME
VERSION A VERSION B
Adjustable current limit. Connect to device GND if external current limit is not
used.
CL
7
7
O
CS
—
3
6
3
O
I
Current-sense output
DIAG_EN
Enable-disable pin for diagnostics; internal pulldown
Global fault report with open-drain structure, ORed logic for dual-channel fault
conditions
FAULT
—
4
O
GND
IN1
8
8
—
I
Ground pin
1
2
1
2
Input control for channel 1 activation; internal pulldown
Input control for channel 2 activation; internal pulldown
No internal connection
IN2
I
NC
4, 10
5
10
—
O
O
I
ST1
ST2
SEL
THER
OUT1
OUT2
VS
—
Open-drain diagnostic status output for channel 1
Open-drain diagnostic status output for channel 2
CS channel-selection bit; internal pulldown
Thermal shutdown behavior control, latch off or auto-retry; internal pulldown
Output of the channel 1 high side-switch, connected to the load
Output of the channel 2 high side-switch, connected to the load
Power supply
6
—
—
5
9
9
I
15, 16
11, 12
13, 14
15, 16
11, 12
13, 14
O
O
I
Thermal
pad
—
—
—
Connect to device GND or leave floating
7 Specifications
7.1 Absolute Maximum Ratings
over operating ambient temperature range (unless otherwise noted)
(1)(2)
MIN
MAX
UNIT
V
Supply voltage
t < 400 ms
48
Reverse polarity voltage(3)
–36
–100
–0.3
–10
–0.3
–30
–2.7
—
V
Current on GND pin
t < 2 minutes
250
7
mA
V
Voltage on INx, DIAG_EN, SEL, and THER pins
Current on INx, DIAG_EN, SEL, and THER pins
Voltage on STx or FAULT pins
Current on STx or FAULT pins
Voltage on CS pin
—
7
mA
V
10
7
mA
V
Current on CS pin
30
7
mA
V
Voltage on CL pin
–0.3
—
Current on CL pin
6
mA
mJ
°C
°C
Inductive load switch-off energy dissipation, single pulse, single channel(4)
Operating junction temperature
Storage temperature, Tstg
—
40
150
150
–40
–65
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to the ground plane.
(3) Reverse polarity condition: t < 60 s, reverse current < IR(2), VINx = 0 V, all channels reverse, GND pin 1-kΩ resistor in parallel with diode.
(4) Test condition: VVS = 13.5 V, L = 8 mH, R = 0 Ω, TJ = 150°C. FR4 2s2p board, 2 × 70-μm Cu, 2 x 35-µm Cu. 600 mm2 thermal pad
copper area.
4
Copyright © 2015–2019, Texas Instruments Incorporated
TPS2H160-Q1
www.ti.com.cn
ZHCSF71D –DECEMBER 2015–REVISED DECEMBER 2019
7.2 ESD Ratings
VALUE
±4000
±750
UNIT
Human-body model (HBM), per AEC
Q100-002(1)
All pins
All pins
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per AEC
Q100-011
Corner pins (1, 8, 9, and
16)
±750
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
7.3 Recommended Operating Conditions
over operating ambient temperature range (unless otherwise noted)
MIN
MAX
40
UNIT
V
VVS
Supply operating voltage
4
0
Voltage on INx, DIAG EN, SEL, and THER pins
Voltage on STx and FAULT pins
Nominal dc load current
5
V
0
5
V
0
2.5
125
A
TA
Operating ambient temperature
–40
°C
7.4 Thermal Information
TPS2H160-Q1
THERMAL METRIC(1)
PWP (HTSSOP)
UNIT
16 PINS
40.4
26.5
21.1
0.8
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ψJB
20.9
1.6
RθJC(bot)
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Electrical Characteristics
5 V < VVS < 40 V; −40°C < TJ < 150°C, unless otherwise specified)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OPERATING VOLTAGE
VVS(nom)
VVS(uvr)
VVS(uvf)
V(uv,hys)
Nominal operating voltage
Undervoltage turnon
4
3.5
3
40
4
V
V
V
V
VVS rises up
3.7
3.2
0.5
Undervoltage shutdown
VVS falls down
3.4
Undervoltage shutdown, hysteresis
Copyright © 2015–2019, Texas Instruments Incorporated
5
TPS2H160-Q1
ZHCSF71D –DECEMBER 2015–REVISED DECEMBER 2019
www.ti.com.cn
Electrical Characteristics (continued)
5 V < VVS < 40 V; −40°C < TJ < 150°C, unless otherwise specified)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OPERATING CURRENT
VVS = 13.5 V, VINx = 5 V, VDIAG_EN = 0 V, IOUTx = 0.5 A,
current limit = 2 A, all channels on
I(op)
Nominal operating current(1)
Standby current
7
mA
VVS = 13.5 V, VINx = VDIAG_EN = VCS = VCL = VOUTx
THER = 0 V,
=
0.5
TJ = 25°C
I(off)
µA
VVS = 13.5 V, VINx = VDIAG_EN = VCS = VCL = VOUTx
THER = 0 V,
=
5
6
TJ = 125°C
Standby current with diagnostic
enabled
VVS = 13.5 V, VINx = 0 V, VDIAG_EN = 5 V, VVS – VOUTx
V(ol,off), not in open-load mode
>
I(off,diag)
mA
IN from high to low, if deglitch time > t(off,deg), the device
enters into standby mode.
t(off,diag)
Ilkg(out)
Standby mode deglitch time(1)
10
12.5
155
15
ms
µA
Output leakage current in off-state
VVS = 13.5 V, VINx = VDIAG_EN = VOUTx = 0
0.5
POWER STAGE
rDS(on)
On-state resistance(1)
ICL(int)
V
VS ≥ 3.5 V, TJ = 25°C
VS ≥ 3.5 V, TJ = 150°C
mΩ
V
280
15
Internal current limit
Internal current limit value, CL pin connected to GND
Internal current limit value under thermal shutdown
9
A
A
6.8
Current limit during thermal
shutdown(1)
ICL(TSD)
External current limit value under thermal shutdown. The
percentage of the external current limit setting value
60%
VDS(clamp)
Drain-to-source internal clamp voltage
45
65
V
V
OUTPUT DIODE CHARACTERISTICS
VF
Drain−source diode voltage
IN = 0, IOUTx = −0.15 A.
0.3
0.7
2.5
0.9
t < 60 s, VINx = 0 V, TJ = 25°C, single channel reversed,
short-to-battery condition
Continuous reverse current from
source to drain(1)
IR(1), IR(2)
A
t < 60 s, VINx = 0 V, GND pin 1-kΩ resistor in parallel with
diode. TJ = 25°C. Reverse-polarity condition, all channels
reversed
2
LOGIC INPUT (INx, DIAG_EN, SEL, THER)
VIH
VIL
Logic high-level voltage
Logic low-level voltage
2
V
V
0.8
230
350
INx, SEL, THER, VINx = VSEL = VTHER = 5 V
DIAG_EN. VVS = VDIAG_EN = 5 V
100
150
175
275
R(logic,pd)
Logic-pin pulldown resistor
kΩ
DIAGNOSTICS
Output leakage current under GND
Ilkg(GND_loss)
100
2.6
µA
V
loss condition
IN = 0 V, when VVS – VOUTx < V(ol,off), duration longer than
t(ol,off), then open load is detected, off state
V(ol,off)
Open-load detection threshold
1.6
400
–75
Open-load detection threshold deglitch IN = 0 V, when VVS – VOUTx < V(ol,off) , duration longer than
time (see Figure 3)
td(ol,off)
600
800
µs
µA
t(ol,off), then open load is detected, off state
VINx = 0 V, VDIAG_EN = 5 V, VVS = VOUTx = 13.5 V, TJ
125°C, open load
=
I(ol,off)
Off-state output sink current
VOL(STx)
Status low-output voltage
Fault low-output voltage
ISTx = 2 mA, version A only
IFAULT = 2 mA, version B only
0.2
0.2
V
V
VOL(FAULT)
Deglitch time when current limit
occurs(1)
Thermal shutdown threshold(1)
VINx = VDIAG_EN = 5 V, the deglitch time from current limit
toggling to FAULT, STx, CS report.
tCL(deg)
T(SD)
T(SD,rst)
T(SW)
80
180
µs
°C
°C
°C
°C
160
175
155
60
Thermal shutdown status reset
threshold(1)
Thermal swing shutdown threshold(1)
Hysteresis for resetting the thermal
shutdown or thermal swing(1)
T(hys)
10
(1) Value specified by design, not subject to production test
6
Copyright © 2015–2019, Texas Instruments Incorporated
TPS2H160-Q1
www.ti.com.cn
ZHCSF71D –DECEMBER 2015–REVISED DECEMBER 2019
Electrical Characteristics (continued)
5 V < VVS < 40 V; −40°C < TJ < 150°C, unless otherwise specified)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
CURRENT SENSE (Version B) AND CURRENT LIMIT
K(CS)
K(CL)
Current-sense ratio
290
2500
0.8
Current-limit ratio
Current limit internal threshold(1)
VCL(th)
V
VVS = 13.5 V, IOUTx ≥ 5 mA
VVS = 13.5 V, IOUTx ≥ 25 mA
VVS = 13.5 V, IOUTx ≥ 50 mA
VVS = 13.5 V, IOUTx ≥ 100 mA
VVS = 13.5 V, IOUTx ≥ 0.5 A
VVS = 13.5 V, I(limit) ≥ 0.25 A
VVS = 13.5 V, 0.5 A ≤ I(limit) ≤ 7 A
–85%
–17%
–8%
–4%
–3%
–20%
–15%
0
85%
17%
8%
dK(CS)
K(CS)
/
Current-sense accuracy, (ICS × K(CS)
IOUTx) /IOUTx × 100
–
4%
3%
External current limit accuracy(2)
,
20%
15%
4
dK(CL) / K(CL)
(IOUTx – ICL × K(CL)) × 100 / (ICL × K(CL)
)
VVS ≥ 6.5 V
VCS(lin)
Current-sense voltage linear range(1)
V
A
VVS
–
5 V ≤ VVS < 6.5 V
0
2.5
2.5
2.5
6.5
V
VS ≥ 6.5 V, VCS(lin) ≤ 4 V
5 V ≤ VVS < 6.5 V, VCS(lin) ≤ VVS – 2.5 V
VS ≥ 7 V, fault mode
0
0
IOUTx(lin)
Output-current linear range(1)
V
4.5
V
V
VCS(H)
Current sense pin output voltage(1)
Current-sense pin output current
Min(VVS – 2,
4.5)
5 V ≤ VVS < 7 V, fault mode
VCS = 4.5 V, VVS = 13.5 V
VDIAG_EN = 0 V, TJ =125ºC
6.5
ICS(H)
15
mA
µA
Current-sense leakage current in
disabled mode
Ilkg(CS)
0.5
(2) External current limit accuracy is only applicable to overload conditions greater than 1.5 × the current limit setting
7.6 Switching Characteristics
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Delay time, VOUTx 10% after VINx↑ (See
Figure 1.)
VVS = 13.5 V, VDIAG_EN = 5 V, IOUTx = 0.5 A, IN rising
edge to 10% of VOUTx
td(on)
20
50
90
µs
Delay time, VOUTx 90% after VINx↓ (See
Figure 1.)
VVS = 13.5 V, VDIAG_EN = 5 V, IOUTx = 0.5 A, IN falling
edge to 90% of VOUTx
td(off)
20
0.1
0.1
50
0.3
90
0.55
0.55
µs
VVS = 13.5 V, VDIAG_EN = 5 V, IOUTx = 0.5 A, VOUTx from
10% to 90%
dV/dt(on)
dV/dt(off)
Turnon slew rate
Turnoff slew rate
V/µs
V/µs
VVS = 13.5 V, VDIAG_EN = 5 V, IOUTx = 0.5 A, VOUTx from
90% to 10%
0.35
VVS = 13.5 V, IL = 0.5A. td, rise is the IN rising edge to
VOUTx = 90%.
td(match)
td(rise) – td(fall) (See Figure 1.)
–50
50
µs
td(fall) is the IN falling edge to VOUTx = 10%.
CURRENT-SENSE CHARACTERISTICS (See Figure 2.)
VVS = 13.5 V, VINx = 5 V, IOUTx = 0.5 A. current limit = 2 A.
tCS(off1)
tCS(on1)
tCS(off2)
tCS(on2)
tSEL
CS settling time from DIAG_EN disabled(1)
CS settling time from DIAG_EN enabled(1)
CS settling time from IN falling edge
CS settling time from IN rising edge
20
20
µs
µs
µs
µs
µs
DIAG_EN falling edge to 10% of VCS
.
VVS = 13.5 V, VINx = 5 V, IOUTx = 0.5 A. current limit is 2
A. DIAG_EN rising edge to 90% of VCS
.
VVS = 13.5 V, VDIAG_EN = 5 V, IOUTx = 0.5 A. current limit =
2 A. IN falling edge to 10% of VCS
20
50
100
150
50
VVS = 13.5 V, VDIAG_EN = 5 V, IOUTx = 0.5 A. current limit =
2 A. IN rising edge to 90% of VCS
Multi-sense transition delay from channel to VDIAG_EN = 5 V, current sense output delay when multi-
channel sense pin SEL transitions from channel to channel
(1) Value specified by design, not subject to production test
Copyright © 2015–2019, Texas Instruments Incorporated
7
TPS2H160-Q1
ZHCSF71D –DECEMBER 2015–REVISED DECEMBER 2019
www.ti.com.cn
VINx
90%
90%
dV/dt(off)
10%
dV/dt(on)
td(rise)
VOUTx
10%
td(on)
td(off)
td(fall)
Figure 1. Output Delay Characteristics
VINx
IOUTx
VDIAG_EN
VCS
tCS(on2)
tCS(off1)
tCS(on1)
tCS(off2)
Figure 2. CS Delay Characteristics
Open Load
VINx
VCS(H)
VCS
td(ol,off)
VSTx,VFAULT
td(ol,off)
Figure 3. Open-Load Blanking-Time Characteristics
SEL
tSEL
VCS(CH2)
VCS(CH1)
VCS
Figure 4. Multi-Sense Transition Delay
8
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7.7 Typical Characteristics
3.8
3.7
3.6
3.5
3.4
3.3
3.2
3.1
1.6
1.5
1.4
1.3
1.2
1.1
1
IN1 High
IN1 Low
IN2 High
IN2 Low
VVS Rising
VVS Falling
-45 -30 -15
0
15 30 45 60 75 90 105 120 135
Ambient Temperature (èC)
-45 -30 -15
0
15 30 45 60 75 90 105 120
Ambient Temperature (èC)
D001
D002
Figure 5. UVLO Voltage Threshold
Figure 6. INx Voltage Threshold
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1
1.6
1.5
1.4
1.3
1.2
1.1
1
DIAG_EN High
DIAG_EN Low
SEL High
SEL Low
-40
-20
0
20
40
60
Ambient Temperature (ºC)
80
100
120
-45 -30 -15
0
15 30 45 60 75 90 105 120
Ambient Temperature (èC)
D003
D004
A
Figure 7. DIAG_EN Voltage Threshold
Figure 8. SEL Voltage Threshold
59
58
57
56
55
54
53
52
0.9
0.85
0.8
Ch 1
Ch 2
OUT1
OUT2
0.75
0.7
0.65
0.6
0.55
0.5
-45 -30 -15
0
15 30 45 60 75 90 105 120
Ambient Temperature (èC)
-45 -30 -15
0
15 30 45 60 75 90 105 120
Ambient Temperature (èC)
D005
D001
Figure 9. Body-Diode Forward Voltage
Figure 10. Drain-to-Source Clamp Voltage
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Typical Characteristics (continued)
0.25
3.5 V
5 V
0.25
0.2
0.15
0.1
0.05
0
3.5 V
5 V
13.5 V
40 V
13.5 V
40 V
0.2
0.15
0.1
0.05
0
-45 -30 -15
0
15 30 45 60 75 90 105 120
Ambient Temperature (èC)
-45 -30 -15
0
15 30 45 60 75 90 105 120
Ambient Temperature (èC)
D007
D008
Figure 11. Channel-1 FET On-Resistance
Figure 12. Channel-2 FET On-Resistance
18
16
14
12
10
8
2
1.5
1
Ch 1
Ch 2
Ch 1
Ch 2
0.5
0
6
4
-0.5
2
0
-1
-45 -30 -15
0
15 30 45 60 75 90 105 120
Ambient Temperature (èC)
-45 -30 -15
0
15 30 45 60 75 90 105 120
Ambient Temperature (èC)
D009
D010
Figure 13. Current-Sense Ratio at 5 mA
Figure 14. Current-Sense Ratio at 25 mA
2
1
0.8
0.6
0.4
0.2
0
Ch 1
Ch 2
Ch 1
Ch 2
1.5
1
0.5
0
-0.2
-0.4
-0.6
-0.8
-0.5
-1
-45 -30 -15
0
15 30 45 60 75 90 105 120
Ambient Temperature (èC)
-45 -30 -15
0
15 30 45 60 75 90 105 120
Ambient Temperature (èC)
D011
D012
Figure 15. Current-Sense Ratio at 50 mA
Figure 16. Current-Sense Ratio at 100 mA
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Typical Characteristics (continued)
6
4
0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.6
-0.7
-0.8
-0.9
Ch 1
Ch 2
Ch 1
Ch 2
2
0
-2
-4
-6
-8
-10
-45 -30 -15
0
15 30 45 60 75 90 105 120
Ambient Temperature (èC)
-45 -30 -15
0
15 30 45 60 75 90 105 120
Ambient Temperature (èC)
D013
D014
Figure 17. Current-Sense Ratio at 500 mA
Figure 18. Current-Limit Ratio at 0.25 A
5
4
4
3
Ch 1
Ch 2
Ch 1
Ch 2
3
2
2
1
1
0
0
-1
-2
-3
-4
-5
-1
-2
-3
-4
-45 -30 -15
0
15 30 45 60 75 90 105 120
Ambient Temperature (èC)
-45 -30 -15
0
15 30 45 60 75 90 105 120
Ambient Temperature (èC)
D015
D016
Figure 19. Current-Limit Ratio at 0.5 A
Figure 20. Current-Limit Ratio at 1 A
3
2.5
2
Ch 1
Ch 2
1.5
1
0.5
0
-0.5
-1
-1.5
-2
-2.5
-3
-3.5
-4
-45 -30 -15
0
15 30 45 60 75 90 105 120
Ambient Temperature (èC)
D017
Figure 21. Current-Limit Ratio at 2 A
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8 Detailed Description
8.1 Overview
The TPS2H160-Q1 device is a smart high-side switch, with internal charge pump and dual-channel integrated
NMOS power FETs. Full diagnostics and high-accuracy current-sense features enable intelligent control of the
load. The adjustable current-limit function greatly improves the reliability of whole system. The device has two
versions with different diagnostic reporting, the open-drain digital output (version A) and the current-sense analog
output (version B).
For version A, the device implements the digital fault report with an open-drain structure. When a fault occurs,
the device pulls STx down to GND. A 3.3- or 5-V external pullup is required to match the microcontroller supply
level. The digital status of each channel can report individually, or globally by connecting the STx pins together.
For version B, high-accuracy current sense makes the diagnostics more accurate without further calibration. One
integrated current mirror can source 1 / K(CS) of the load current. The mirrored current flows into the CS-pin
resistor to become a voltage signal. K(CS) is a constant value across temperature and supply voltage. A wide
linear region from 0 V to 4 V allows a better real-time load-current monitoring. The CS pin can also report a fault
with pullup voltage of VCS(H)
.
The external high-accuracy current limit allows setting the current-limit value by applications. When overcurrent
occurs, the device improves system reliability by clamping the inrush current effectively. The device can also
save system cost by reducing the size of PCB traces and connectors, and the capacity of the preceding power
stage. Besides, the device also implements an internal current limit with a fixed value.
For inductive loads (relays, solenoids, valves), the device implements an active clamp between drain and source
to protect itself. During the inductive switching-off cycle, both the energy of the power supply and the load are
dissipated on the high-side switch. The device also optimizes the switching-off slew rate when the clamp is
active, which helps the system design by keeping the effects of transient power and EMI to a minimum.
The TPS2H160-Q1 device is a smart high-side switch for a wide variety of resistive, inductive, and capacitive
loads, including low-wattage bulbs, LEDs, relays, solenoids, heaters, and sub-modules.
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8.2 Functional Block Diagram
VS
Internal LDO
Internal Reference
Auxiliary Charge Pump
Output
Clamp
Temperature Sensor
Gate Driver
and
Charge Pump
2
INx
OUT1
OUT2
Oscillator
Protection
and
Diagnostics
THER
CS
Current-Sense
Mux
Current
Sense
SEL
CL
ESD
Protection
Current Limit
Current Limit
Reference
FAULT
DIAG_EN
GND
STx
Diagnosis
Temperature
Sensor
2
OTP
8.3 Feature Description
8.3.1 Pin Current and Voltage Conventions
For reference purposes throughout the data sheet, current directions on their respective pins are as shown by
the arrows in Figure 22. All voltages are measured relative to the ground plane.
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Feature Description (continued)
IINx
IVS
IOUTx
ISEL
VINx
VVS
INx
VS
OUTx
SEL
ISTx
VSTx, VFAULT
IFAULT
STx,
FAULT
IDIAG_EN
VDIAG_EN
DIAG_EN
CL
VOUTx
ICL
VCL
ICS
VCS
CS
ITHER
VTHER
VSEL
THER
GND
IGND
VGND
Ground Plane
Figure 22. Voltage and Current Conventions
8.3.2 Accurate Current Sense
High-accuracy current sense is implemented in the version-B device. It allows a better real-time monitoring effect
and more-accurate diagnostics without further calibration.
One integrated current mirror can source 1 / K(CS) of the load current, and the mirrored current flows into the
external current sense resistor to become a voltage signal. The current mirror is shared by the four channels.
K(CS) is the ratio of the output current and the sense current. It is a constant value across the temperature and
supply voltage. Each device is calibrated accurately during production, so post-calibration is not required. See
Figure 23 for more details.
VBAT
VS
IOUT / K(CS)
IOUT
OUTx
VCS(H)
FAULT
2´
CS
R(CS)
Figure 23. Current-Sense Block Diagram
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Feature Description (continued)
When a fault occurs, the CS pin also works as a fault report with a pullup voltage, VCS(H). See Figure 24 for more
details.
VCS
VCS(H)
VCS(lin)
Fault Report
Current Monitor
IOUTx
Normal Operating
On-State: Current Limit, Thermal Fault
Off-State: Open Load or Short to Battery
or Reverse Polarity
Figure 24. Current-Sense Output-Voltage Curve
Use Equation 1 to calculate R(CS)
.
V
CS ´ K(CS)
VCS
ICS
R(CS)
=
=
IOUTx
(1)
Take the following points into consideration when calculating R(CS)
.
•
Ensure VCS is within the current-sense linear region (VCS, IOUTx(lin)) across the full range of the load current.
Check R(CS) with Equation 2.
VCS(lin)
VCS
ICS
R(CS)
=
£
ICS
(2)
(3)
•
In fault mode, ensure ICS is within the source capacity of the CS pin (ICS(H)). Check R(CS) with Equation 3.
VCS(H,min)
VCS
ICS
R(CS)
=
³
ICS(H,min)
8.3.3 Adjustable Current Limit
A high-accuracy current limit allows high reliability of the design. It protects the load and the power supply from
overstressing during short-circuit-to-GND or power-up conditions. The current limit can also save system cost by
reducing the size of PCB traces and connectors, and the capacity of the preceding power stage.
When a current-limit threshold is hit, a closed loop activates immediately. The output current is clamped at the
set value, and a fault is reported out. The device heats up due to the high power dissipation on the power FET. If
thermal shutdown occurs, the current limit is set to ICL(TSD) to reduce the power dissipation on the power FET.
See Figure 25 for more details.
The device has two current-limit thresholds.
•
Internal current limit – The internal current limit is fixed at ICL(int). Tie the CL pin directly to the device GND for
large-transient-current applications.
•
External adjustable current limit – An external resistor is used to set the current-limit threashold. Use the
Equation 4 to calculate the R(CL). VCL(th) is the internal band-gap voltage. K(CL) is the ratio of the output current
and the current-limit set value. It is constant across the temperature and supply voltage. The external
adjustable current limit allows the flexibility to set the current limit value by applications.
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Feature Description (continued)
VCL(th)
IOUT
ICL
=
=
R(CL)
K(CL)
V
CL(th) ´ K(CL)
R(CL)
=
IOUT
(4)
VBAT
VS
IOUT / K(CL)
Internal Current Limit
‐
+
‐
+
+
IOUT
VCL(th)
2´
OUT
External Current Limit
‐
+
VCL(th)
CL
Figure 25. Current-Limit Block Diargam
Note that if using a GND network which causes a level shift between the device GND and board GND, the CL
pin must be connected with device GND.
For better protection from a hard short-to-GND condition (when the INx pins are enabled, a short to GND occurs
suddenly), the device implements a fast-trip protection to turn off the related channel before the current-limit
closed loop is set up. The fast-trip response time is less than 1 μs, typically. With this fast response, the device
can achieve better inrush current-suppression performance.
8.3.4 Inductive-Load Switching-Off Clamp
When switching an inductive load off, the inductive reactance tends to pull the output voltage negative. Excessive
negative voltage could cause the power FET to break down. To protect the power FET, an internal clamp
between drain and source is implemented, namely VDS(clamp)
VDS(clamp) = VVS - VOUT
.
(5)
During the period of demagnetization (tdecay), the power FET is turned on for inductance-energy dissipation. The
total energy is dissipated in the high-side switch. Total energy includes the energy of the power supply (E(VS)
)
and the energy of the load (E(load)). If resistance is in series with inductance, some of the load energy is
dissipated on the resistance.
16
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Feature Description (continued)
E
(HSS) = E(VS) + E(load) = E(VS) + E(L) - E(R)
(6)
When an inductive load switches off, E(HSS) causes high thermal stressing on the device.. The upper limit of the
power dissipation depends on the device intrinsic capacity, ambient temperature, and board dissipation condition.
VBAT
VDS(clamp)
IN
L
œ
OUT
R
GND
+
Figure 26. Drain-to-Source Clamping Structure
IN
VVS
VOUT
VDS(clamp)
E(HSS)
IOUT
t(decay)
Figure 27. Inductive Load Switching-Off Diagram
From the perspective of the high-side switch, E(HSS) equals the integration value during the demagnetization
period.
t(decay)
E(HSS)
=
VDS(clamp) ´IOUT (t)dt
ò
0
æ
ö
÷
÷
ø
R´IOUT(max) + VOUT
L
t(decay)
=
´lnç
ç
è
R
VOUT
é
ù
ú
æ
ö
÷
÷
ø
R´IOUT(max) + VOUT
VVS + VOUT
ê
E(HSS) = L ´
´ R´IOUT(max) - VOUT lnç
R2
ç
VOUT
ê
ú
è
ë
û
(7)
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Feature Description (continued)
When R approximately equals 0, E(HSD) can be given simply as:
VVS + VOUT
1
2
E(HSS)
=
´L ´IO2 UT(max
)
VOUT
(8)
Figure 28 is a waveform of the device driving an inductive load, and Figure 29 is waveform with an expanded
time scale. Channel 1 is the IN signal, channel 2 is the supply voltage VVS, channel 3 is the output voltage VOUT
channel 4 is the output current IOUT, and channel M is the measured power dissipation E(HSS)
,
.
On the waveform, the duration of VOUT from VVS to (VVS – VDS(clamp)) is around 120 µs. The device also optimizes
the switching-off slew rate when the clamp is active. This optimization can help the system design by keeping the
effects of transient power and EMI to a minimum. As shown in Figure 28 and Figure 29, the controlled slew rate
is around 0.5 V/µs.
Figure 28. Inductive Load Switching-Off Waveform
Figure 29. Inductive Load Switching-Off Expanded
Waveform
Note that for PWM-controlled inductive loads, it is recommended to add the external freewheeling circuitry shown
in Figure 30 to protect the device from repetitive power stressing. TVS is used to achieve the fast decay. See
Figure 30 for more details.
VS
Output
Clamp
OUTx
GND
D
L
TVS
Figure 30. Protection With External Circuitry
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Feature Description (continued)
8.3.5 Fault Detection and Reporting
8.3.5.1 Diagnostic Enable Function
The DIAG_EN pin enables or disables the diagnostic functions. If multiple devices are used, but the ADC
resource is limited in the microcontroller, the MCU can use GPIOs to set DIAG_EN high to enable the
diagnostics of one device while disabling the diagnostics of the other devices by setting DIAG_EN low. In
addition, the device can keep the power consumption to a minimum by setting DIAG_EN and INx low.
8.3.5.2 Multiplexing of Current Sense
For version B, SEL is used to multiplex the shared current-sense function between the two channels. See
Table 1 for more details.
Table 1. Diagnosis Configuration Table
CS ACTIVATED
DIAG_EN
INx
SEL
CS, FAULT, STx
PROTECTIONS AND DIAGNOSTICS
CHANNEL
H
L
Diagnostics disabled, full protection
Diagnostics disabled, no protection
L
—
—
High impedance
0
1
Channel 1
Channel 2
H
—
See Table 2
See Table 2
8.3.5.3 Fault Table
Table 2 applies when the DIAG_EN pin is enabled.
Table 2. Fault Table
STx
CS
FAULT
CONDITIONS
Normal
INx
L
OUTx THER CRITERION
FAULT RECOVERY
(VER. A) (VER. B) (VER. B)
L
—
—
—
—
H
0
H
—
—
In linear
region
H
H
H
H
Current limit
triggered
Overlaod, short to ground
H
L
L
—
—
L
L
VCS(H)
VCS(H)
L
L
Auto
Auto
Open load(1), short to battery,
reverse polarity
VVS – VOUTx
V(ol,off)
<
H
Output auto-retry. Fault
recovers when TJ < T(SD,rst) or
when INx toggles.
L
Thermal shutdown
Thermal swing
H
H
—
—
TSD triggered
TSW triggered
L
L
VCS(H)
L
L
Output latch off. Fault recovers
when INx toggles.
H
—
VCS(H)
Auto
(1) An external pullup is required for open-load detection.
8.3.5.4 STx and FAULT Reporting
For version A, two individual STx pins report the fault conditions, each pin for its respective channel. When a
fault condition occurs, it pulls STx down to GND. A 3.3- or 5-V external pullup is required to match the supply
level of the microcontroller. The digital status of each channel can be reported individually, or globally by
connecting all the STx pins together.
For version B, a global FAULT pin is used to monitor the global fault condition among all the channels. When a
fault condition occurs on any channel, the FAULT pin is pulled down to GND. A 3.3-V or 5-V external pullup is
required to match the supply level of the microcontroller.
After the FAULT report, the microcontroller can check and identify the channel in fault status by multiplexed
current sensing. The CS pin also works as a fault report with an internal pullup voltage, VCS(H)
.
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8.3.6 Full Diagnostics
8.3.6.1 Short-to-GND and Overload Detection
When a channel is on, a short to GND or overload condition causes overcurrent. If the overcurrent triggers either
the internal or external current-limit threshold, the fault condition is reported out. The microcontroller can handle
the overcurrent by turning off the switch. The device heats up if no actions are taken. If a thermal shutdown
occurs, the current limit is ICL(TSD) to keep the power stressing on the power FET to a minimum. The device
automatically recovers when the fault condition is removed.
8.3.6.2 Open-Load Detection
8.3.6.2.1 Channel On
When a channel on, benefiting from the high-accuracy current sense in a small current range, if an open-load
event occurs, it can be detected as an ultralow VCS and handled by the microcontroller. Note that the detection is
not reported on the STx or FAULT pins. The microcontroller must set the SEL pin to detect the channel-on open-
load fault proactively.
8.3.6.2.2 Channel Off
When a channel is off, if a load is connected, the output is pulled down to GND. But if an open load occurs, the
output voltage is close to the supply voltage (VVS – VOUTx < V(ol,off)), and the fault is reported out.
There is always a leakage current I(ol,off) present on the output due to internal logic control path or external
humidity, corrosion, and so forth. Thus, TI recommends an external pullup resistor to offset the leakage current
when an open load is detected. The recommended pullup resistance is 20 kΩ.
VBAT
Open-Load Detection in Off State
V(ol,off)
R(PU)
VDS
Load
Figure 31. Open-Load Detection in Off-State
8.3.6.3 Short-to-Battery Detection
Short-to-battery has the same detection mechanism and behavior as open-load detection, in both the on-state
and off-state. See Table 2 for more details.
In the on-state, reverse current flows through the FET instead of the body diode, leading to less power
dissipation. Thus, the worst case occurs in the off-state.
•
•
If VOUTx – VVS < V(F) (body diode forward voltage), no reverse current occurs.
If VOUTx – VVS > V(F), reverse current occurs. The current must be limited to less than IR(1). Setting an INx pin
high can minimize the power stress on its channel. Also, for external reverse protection, see Reverse-Current
Protection for more details.
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8.3.6.4 Reverse Polarity Detection
Reverse polarity detection has the same detection mechanism and behavior as open-load detection both in the
on-state and off-state. See Table 2 for more details.
In the on-state, the reverse current flows through the FET instead of the body diode, leading to less power
dissipation. Thus, the worst case occurs in the off-state. The reverse current must be limited to less than IR(2)
.
Set the related INx pin high to keep the power dissipation to a minimum. For external reverse-blocking circuitry,
see Reverse-Current Protection for more details.
8.3.6.5 Thermal Fault Detection
To protect the device in severe power stressing cases, the device implements two types of thermal fault
detection, absolute temperature protection (thermal shutdown) and dynamic temperature protection (thermal
swing). Respective temperature sensors are integrated close to each power FET, so the thermal fault is reported
by each channel. This arrangement can help the device keep the cross-channel effect to a minimum when some
channels are in a thermal fault condition.
8.3.6.5.1 Thermal Shutdown
Thermal shutdown is active when the absolute temperature TJ > T(SD). When thefrmal shutdown occurs, the
respective output turns off. The THER pin is used to configure the behavior after the thermal shutdown occurs.
•
When the THER pin is low, thermal shutdown operates in the auto-retry mode. The output automatically
recovers when TJ < T(SD) – T(hys), but the current is limited to ICL(TSD) to avoid repetitive thermal shutdown. The
thermal shutdown fault signal is cleared when TJ < T(SD,rst) or after toggling the related INx pin.
•
When the THER pin is high, thermal shutdown operates in the latch mode. The output latches off when
thermal shutdown occurs. When the THER pin goes from high to low, thermal shutdown changes to auto-retry
mode. The thermal shutdown fault signal is cleared after toggling the related INx pin.
Thermal swing activates when the power FET temperature is increasing sharply, that is, when ΔT = T(FET)
–
T(Logic) > T(sw), then the output turns off. The output automatically recovers and the fault signal clears when ΔT =
T(FET) – T(Logic) < T(sw) – T(hys). Thermal swing function improves the device reliability when subjected to repetitive
fast thermal variation. As shown in Figure 32, multiple thermal swings are triggered before thermal shutdown
occurs.
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Thermal Behavior After Short to GND
VTHER
VINx
T(SD)
T(SD,rst)
T(hys)
TJ
T(hys)
T(SW)
ICL
IOUTx
ICL(TSD)
VCS(H)
VCS
VFAULT
or VST
Figure 32. Thermal Behavior Diagram
8.3.7 Full Protections
8.3.7.1 UVLO Protection
The device monitors the supply voltage VVS, to prevent unpredicted behaviors when VVS is too low. When VVS
falls down to VVS(uvf), the device shuts down. When VVS rises up to VVS(uvr), the device turns on.
8.3.7.2 Loss-of-GND Protection
When loss of GND occurs, output is shut down regardless of whether the INx pin is high or low. The device can
protect against two ground-loss conditions, loss of device GND and loss of module GND.
8.3.7.3 Protection for Loss of Power Supply
When loss of supply occurs, the output is shut down regardless of whether the INx pin is high or low. For a
resistive or a capacitive load, loss of supply has no risk. But for a charged inductive load, the current is driven
from all the I/O pins to maintain the inductance current. To protect the system in this condition, TI recommends
the external free-wheeling diode as shown in Figure 33.
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ZHCSF71D –DECEMBER 2015–REVISED DECEMBER 2019
VBAT
VS
OUT
I/Os
MCU
High-Side Switch
L
Figure 33. Protection for Loss of Power Supply
8.3.7.4 Reverse-Current Protection
Reverse current occurs in two conditions: short to battery and reverse polarity.
•
When a short to the battery occurs, there is only reverse current through the body diode. IR(1) specifies the
limit of the reverse current.
•
In a reverse-polarity condition, there are reverse currents through the body diode and the device GND pin.
IR(2) specifies the limit of the reverse current. The GND pin maximum current is specified in the Absolute
Maximum Ratings.
To protect the device, TI recommends two types of external circuitry.
•
Adding a blocking diode. Both the IC and load are protected when in reverse polarity.
VBAT
VS
´
OUT
Load
Copyright © 2016, Texas Instruments Incorporated
Figure 34. Reverse-Current External Protection, Method 1
•
Adding a GND network. The reverse current through the device GND is blocked. The reverse current through
the FET is limited by the load itself. TI recommends a resistor in parallel with the diode as a GND network.
The recommended selection are 1-kΩ resistor in parallel with an >100-mA diode. If multiple high-side
switches are used, the resistor and diode can be shared among devices. The reverse current protection diode
in the GND network forward voltage should be less than 0.6 V in any circumstances. In addition a minimum
resistance of 4.7 K is recommended on the I/O pins.
Copyright © 2015–2019, Texas Instruments Incorporated
23
TPS2H160-Q1
ZHCSF71D –DECEMBER 2015–REVISED DECEMBER 2019
www.ti.com.cn
VBAT
VS
OUT
Load
Figure 35. Reverse-Current External Protection, Method 2
8.3.7.5 MCU I/O Protection
In some severe conditions, such as the ISO7637-2 test or the loss of battery with inductive loads, a negative
pulse occurs on the GND pin This pulse can cause damage on the connected microcontroller. TI recommends
serial resistors to protect the microcontroller, for example, 4.7-kΩ when using a 3.3-V microcontroller and 10-kΩ
for a 5-V microcontroller.
VBAT
I/Os
VS
OUT
MCU
High-Side Switch
Load
Figure 36. MCU I/O External Protection
8.4 Device Functional Modes
8.4.1 Working Modes
The device has three working modes, the normal mode, the standby mode, and the standby mode with
diagnostics.
Note that IN must be low for t > t(off,deg) to enter the standby mode, where t(off,deg) is the standby mode deglitch
time used to avoid false triggering. Figure 37 shows a working-mode diagram.
24
Copyright © 2015–2019, Texas Instruments Incorporated
TPS2H160-Q1
www.ti.com.cn
ZHCSF71D –DECEMBER 2015–REVISED DECEMBER 2019
Device Functional Modes (continued)
Standby Mode
(INx Low, DIAG Low)
DIAG_EN Low
AND
INx High to Low
for
t > t(off,deg)
DIAG_EN Low to High
DIAG_EN High to Low
INx Low to High
Standby Mode
With Diagnostics
(INx Low, DIAG High)
INx low to high
Normal Mode
(INx High)
DIAG_EN High
AND
INx High to Low
for
t > t(off,deg)
Figure 37. Working Modes
Copyright © 2015–2019, Texas Instruments Incorporated
25
TPS2H160-Q1
ZHCSF71D –DECEMBER 2015–REVISED DECEMBER 2019
www.ti.com.cn
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TPS2H160-Q1 device is capable of driving a wide variety of resistive, inductive, and capacitive loads,
including the low-wattage bulbs, LEDs, relays, solenoids, heaters, and sub-modules. Full diagnostics and high-
accuracy current-sense features enable intelligent control of the load. An external adjustable current limit
improves the reliability of the whole system by clamping the inrush or overload current.
9.2 Typical Application
The following figure shows an example of the external circuitry connections based on the version-B device.
VBAT
VS
R(ser)
IN1, 2
LED Strings,
Small Power Bulbs
R(ser)
R(ser)
DIAG_EN
SEL
Solenoids, Valves, Relays
OUT1
OUT2
MCU
5 V
Power Module:
Cameras, Sensors, Displays
R(pu)
R(ser)
FAULT
CS
General Resistive,Capacitive,
InductiveLoads
R(CS)
CL
GND
THER
R(CL)
Figure 38. Typical Application Diagram
9.2.1 Design Requirements
•
•
•
•
•
•
•
VVS range from 9 V to 16 V
Load range is from 0.1 A to 1 A for each channel
Current sense for fault monitoring
Expected current-limit value of 2.5 A
Automatic recovery mode when thermal shutdown occurs
Full diagnostics with 5-V MCU
Reverse-voltage protection with a blocking diode in the power-supply line
26
Copyright © 2015–2019, Texas Instruments Incorporated
TPS2H160-Q1
www.ti.com.cn
ZHCSF71D –DECEMBER 2015–REVISED DECEMBER 2019
Typical Application (continued)
9.2.2 Detailed Design Procedure
To keep the 1-A nominal current in the 0 to 4-V current-sense range, calculate the R(CS) resistor using
Equation 9. To achieve better current-sense accuracy, a 1% tolerance or better resistor is preferred.
V
CS´ K(CS)
VCS
ICS
4´ 290
R(CS)
=
=
=
= 1160 W
IOUT
1
(9)
To set the adjustable current limit value at 2.5-A, calculate R(CL) using Equation 10.
V
CL(th) ´ K(CL)
0.8´ 2500
R(CL)
=
=
= 800 W
IOUT
2.5
(10)
TI recommends R(ser) = 10 kΩ for 5-V MCU, and R(pu) = 10 kΩ as the pullup resistor.
9.2.3 Application Curves
Figure 39 shows a test example of soft-start when driving a big capacitive load. Figure 40 shows an expanded
waveform of the output current.
VVS = 12 V
INx = ↑
Current limit = 1 A
CH1 = INx
VS = 12 V
INx = ↑
Current limit = 1 A
CH1 = INx
Load current = 0.4
A
CL = 2.3 mF
Load current = 0.4
A
CL = 2.3 mF
CH2 = FAULT
CH3 = output
voltage
CH4 = output
current
CH2 = FAULT
CH3 = output
voltage
CH4 = output
current
Figure 40. Driving a Capacitive Load, Expanded Waveform
Figure 39. Driving a Capacitive Load
Copyright © 2015–2019, Texas Instruments Incorporated
27
TPS2H160-Q1
ZHCSF71D –DECEMBER 2015–REVISED DECEMBER 2019
www.ti.com.cn
Typical Application (continued)
Figure 41 shows a test example of PWM-mode driving. Figure 42 shows the expanded waveform of the rising
edge. Figure 43 shows the expanded waveform of the falling edge.
VVS = 13.5 V INx = 200-Hz PWM
at 50% duty cycle
CH1 = INx signal
VVS = 13.5 V INx = 200-Hz PWM
at 50% duty cycle
CH1 = INx signal
CH2 = CS voltage
CH3 = output
voltage
CH4 = output
current
CH2 = CS voltage
CH3 = output
voltage
CH4 = output
current
Figure 41. PWM Signal Driving
Figure 42. Expanded Waveform of Rising Edge
VVS = 13.5 V
INx = 200-Hz PWM at 50% duty cycle
CH3 = output voltage
CH1 = INx signal
CH4 = output current
CH2 = CS voltage
Figure 43. Expanded Waveform of Falling Edge
28
Copyright © 2015–2019, Texas Instruments Incorporated
TPS2H160-Q1
www.ti.com.cn
ZHCSF71D –DECEMBER 2015–REVISED DECEMBER 2019
10 Power Supply Recommendations
The device is qualified for both automotive and industrial applications. The normal power supply connection is a
12-V automotive system or 24-V industrial system. Detailed supply voltage should be within the range specified
in the Recommended Operating Conditions.
Copyright © 2015–2019, Texas Instruments Incorporated
29
TPS2H160-Q1
ZHCSF71D –DECEMBER 2015–REVISED DECEMBER 2019
www.ti.com.cn
11 Layout
11.1 Layout Guidelines
To prevent thermal shutdown, TJ must be less than 150°C. The HTSSOP package has good thermal impedance.
However, the PCB layout is very important. Good PCB design can optimize heat transfer, which is absolutely
essential for the long-term reliability of the device.
•
Maximize the copper coverage on the PCB to increase the thermal conductivity of the board. The major heat
flow path from the package to the ambient is through the copper on the PCB. Maximum copper is extremely
important when there are not any heat sinks attached to the PCB on the other side of the package.
•
•
Add as many thermal vias as possible directly under the package ground pad to optimize the thermal
conductivity of the board.
All thermal vias should either be plated shut or plugged and capped on both sides of the board to prevent
solder voids. To ensure reliability and performance, the solder coverage should be at least 85%.
11.2 Layout Examples
11.2.1 Without a GND Network
Without a GND network, tie the thermal pad directly to the board GND copper for better thermal performance.
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
OUT1
OUT1
VS
Thermal
Pad
(GND)
VS
GND
Figure 44. Layout Example Without a GND Network
30
Copyright © 2015–2019, Texas Instruments Incorporated
TPS2H160-Q1
www.ti.com.cn
ZHCSF71D –DECEMBER 2015–REVISED DECEMBER 2019
Layout Examples (continued)
11.2.2 With a GND Network
With a GND network, tie the thermal pad as one trace to the board GND copper.
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
OUT1
OUT1
VS
Thermal
Pad
(GND)
VS
OUT2
OUT2
GND
Network
GND
Figure 45. Layout Example With a GND Network
版权 © 2015–2019, Texas Instruments Incorporated
31
TPS2H160-Q1
ZHCSF71D –DECEMBER 2015–REVISED DECEMBER 2019
www.ti.com.cn
12 器件和文档支持
12.1 接收文档更新通知
要接收文档更新通知，请导航至 ti.com. 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产品
信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
12.2 社区资源
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.3 商标
PowerPAD, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
32
版权 © 2015–2019, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS2H160AQPWPRQ1
TPS2H160BQPWPRQ1
ACTIVE
ACTIVE
HTSSOP
HTSSOP
PWP
PWP
16
16
2000 RoHS & Green
2000 RoHS & Green
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 125
-40 to 125
2H160AQ
2H160BQ
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
30-Jan-2020
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS2H160AQPWPRQ1 HTSSOP PWP
TPS2H160BQPWPRQ1 HTSSOP PWP
16
16
2000
2000
330.0
330.0
12.4
12.4
6.9
6.9
5.6
5.6
1.6
1.6
8.0
8.0
12.0
12.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
30-Jan-2020
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS2H160AQPWPRQ1
TPS2H160BQPWPRQ1
HTSSOP
HTSSOP
PWP
PWP
16
16
2000
2000
350.0
350.0
350.0
350.0
43.0
43.0
Pack Materials-Page 2
PACKAGE OUTLINE
PWP0016A
PowerPAD TM HTSSOP - 1.2 mm max height
S
C
A
L
E
2
.
4
0
0
PLASTIC SMALL OUTLINE
C
6.6
6.2
TYP
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
14X 0.65
16
1
2X
5.1
4.9
4.55
NOTE 3
8
9
0.30
16X
0.19
4.5
4.3
B
0.1
C A B
(0.15) TYP
SEE DETAIL A
4X 0.166 MAX
NOTE 5
2X 1.34 MAX
NOTE 5
THERMAL
PAD
0.25
GAGE PLANE
3.3
2.7
17
1.2 MAX
0.15
0.05
0 - 8
0.75
0.50
DETAIL A
TYPICAL
(1)
3.3
2.7
4214868/A 02/2017
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-153.
5. Features may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
PWP0016A
PowerPAD TM HTSSOP - 1.2 mm max height
PLASTIC SMALL OUTLINE
(3.4)
NOTE 9
SOLDER MASK
DEFINED PAD
(3.3)
16X (1.5)
SYMM
SEE DETAILS
1
16
16X (0.45)
(1.1)
TYP
17
SYMM
(3.3)
(5)
NOTE 9
14X (0.65)
8
9
(
0.2) TYP
VIA
(1.1) TYP
METAL COVERED
BY SOLDER MASK
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:10X
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
EXPOSED
METAL
EXPOSED
METAL
0.05 MIN
ALL AROUND
0.05 MAX
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
PADS 1-16
4214868/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Size of metal pad may vary due to creepage requirement.
www.ti.com
EXAMPLE STENCIL DESIGN
PWP0016A
PowerPAD TM HTSSOP - 1.2 mm max height
PLASTIC SMALL OUTLINE
(3.3)
BASED ON
0.125 THICK
STENCIL
16X (1.5)
(R0.05) TYP
1
16
16X (0.45)
(3.3)
17
SYMM
BASED ON
0.125 THICK
STENCIL
14X (0.65)
9
8
SYMM
(5.8)
METAL COVERED
BY SOLDER MASK
SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
SOLDER PASTE EXAMPLE
EXPOSED PAD
100% PRINTED SOLDER COVERAGE BY AREA
SCALE:10X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
3.69 X 3.69
3.3 X 3.3 (SHOWN)
3.01 X 3.01
0.125
0.15
0.175
2.79 X 2.79
4214868/A 02/2017
NOTES: (continued)
10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
11. Board assembly site may have different recommendations for stencil design.
www.ti.com
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这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
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邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2023，德州仪器 (TI) 公司
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