TPS3103-EP [TI]
Ultra-Low Supply-Current/Supply-Voltage Supervisory Circuits; 超低电源电流/电源电压监控电路
| 型号： | TPS3103-EP |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Ultra-Low Supply-Current/Supply-Voltage Supervisory Circuits |
| 文件： | 总22页 (文件大小：508K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Production Data
TPS3103xxx-EP
TPS3106xxx-EP
TPS3110xxx-EP
www.ti.com
SLVS686–OCTOBER 2006
Ultra-Low Supply-Current/Supply-Voltage Supervisory Circuits
FEATURES
APPLICATIONS
•
Applications Using Low-Power DSPs,
Microcontrollers, or Microprocessors
•
Controlled Baseline
– One Assembly Site
– One Test Site
•
•
•
•
•
Portable- and Battery-Powered Equipment
Intelligent Instruments
Wireless Communication Systems
Industrial Equipment
– One Fabrication Site
•
•
Extended Temperature Performance of
–55°C to 125°C
Notebook/Desktop Computers
Enhanced Diminishing Manufacturing
Sources (DMS) Support
DESCRIPTION
•
•
•
Enhanced Product-Change Notification
The TPS310x and TPS311x families of supervisory
circuits provide circuit initialization and timing
supervision, primarily for DSP and processor-based
systems.
(1)
Qualification Pedigree
Precision Supply Voltage Supervision Range:
0.9 V, 1.2 V, 1.5 V, 1.6 V, 2 V, and 3.3 V
•
•
•
High Trip-Point Accuracy: 0.75%
During power-on, RESET is asserted when the
supply voltage (VDD) becomes higher than 0.4 V.
Thereafter, the supervisory circuit monitors VDD and
keeps the RESET output active as long as VDD
remains below the threshold voltage (VIT). An internal
timer delays the return of the output to the inactive
state to ensure proper system reset. The delay time
starts after VDD has risen above VIT. When VDD drops
below VIT, the output becomes active again.
Supply Current of 1.2 µA (Typ)
RESET Defined With Input Voltages as Low
as 0.4 V
•
Power-On Reset Generator With a Delay Time
of 130 ms
•
•
Push/Pull or Open-Drain RESET Outputs
SOT23-6 Package
All the devices of this family have a fixed-sense
threshold voltage (VIT) set by an internal voltage
divider.
The TPS3103 and TPS3106 have an active-low,
open-drain RESET output. The TPS3110 has an
active-low push/pull RESET.
(1) Component qualification in accordance with JEDEC and
industry standards to ensure reliable operation over an
extended temperature range. This includes, but is not limited
to, Highly Accelerated Stress Test (HAST) or biased 85/85,
temperature cycle, autoclave or unbiased HAST,
The product spectrum is designed for supply
voltages of 0.9 V up to 3.3 V. The circuits are
available in SOT23-6 packages. The TPS31xx family
is characterized for operation over a temperature
range of –55°C to 125°C.
electromigration, bond intermetallic life, and mold compound
life. Such qualification testing should not be viewed as
justifying use of this component beyond specified
performance and environmental limits.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2006, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Production Data
TPS3103xxx-EP
TPS3106xxx-EP
TPS3110xxx-EP
www.ti.com
SLVS686–OCTOBER 2006
3.3 V
1.6 V
VDD
VCORE
DSP
RESET
VIO
R3
TPS3106K33MDBVREP
R1
R2
RSTVDD
MR
SENSE
RSTSENSE
GND
GND
GND
Typical Application Circuit
2
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Production Data
TPS3103xxx-EP
TPS3106xxx-EP
TPS3110xxx-EP
www.ti.com
SLVS686–OCTOBER 2006
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
PIN DESCRIPTIONS
TPS3106
DBV PACKAGE
(TOP VIEW)
TPS3103
DBV PACKAGE
(TOP VIEW)
TPS3110
DBV PACKAGE
(TOP VIEW)
1
2
3
6
5
1
2
3
VDD
6
5
VDD
1
6
VDD
RSTVDD
GND
RESET
GND
MR
RESET
GND
2
5
WDI
RSTSENSE
SENSE
PFO
PFI
4
SENSE
4
3
MR
4
MR
TERMINAL FUNCTIONS
TERMINAL
DEVICE
All
DESCRIPTION
NAME
NO.
GND
2
Ground
Manual reset input. Pull low to force a reset. RESET remains low as long as MR is low and for
the timeout period after MR goes high. Leave unconnected or connect to VDD when unused.
MR
All
3
PFI
TPS3103
TPS3103
4
5
Power-fail input. Compares to 0.551 V with no additional delay. Connect to VDD if not used.
Power-fail output. Goes high when voltage at PFI rises above 0.551 V.
PFO
TPS3103,
TPS3110
RESET
1
5
1
Active-low reset output. Either push-pull or open-drain output stage.
Active-low reset output. Logic level at RSTSENSE only depends on the voltage at SENSE and
the status of MR.
RSTSENSE
RSTVDD
TPS3106
TPS3106
Active-low reset output. Logic level at RSTVDD only depends on the voltage at VDD and the
status of MR.
TPS3106,
TPS3110
Sense. A reset is asserted if the voltage at SENSE is lower than 0.551 V. Connect to VDD if
unused.
SENSE
VDD
4
6
All
Supply voltage. Powers the device and monitors its own voltage.
Watchdog timer input. If WDI remains high or low longer than the time-out period, reset is
triggered. The timer clears when reset is asserted or when WDI sees a rising edge or a falling
edge.
WDI
TPS3110
5
ORDERING INFORMATION(1)
(2)
ORDERABLE PART NUMBER
TPS3103E12MDBVREP(3)
TPS3103E15MDBVREP(3)
TPS3103H20MDBVREP(3)
TPS3103K33MDBVREP(3)
TPS3106E09MDBVREP(3)
TPS3106E16MDBVREP(3)
TPS3106K33MDBVREP
TPS3110E09MDBVREP(3)
TPS3110E12MDBVREP(3)
TPS3110E15MDBVREP(3)
TPS3110K33MDBVREP(3)
NOMINAL SUPPLY VOLTAGE
THRESHOLD VOLTAGE, VIT
SYMBOL
TBD
1.2 V
1.5 V
2 V
1.142 V
1.434 V
1.84 V
TBD
TBD
3.3 V
0.9 V
1.6 V
3.3 V
0.9 V
1.2 V
1.5 V
3.3 V
2.941 V
0.86 V
TBD
TBD
1.521 V
2.941 V
0.86 V
TBD
AAVM
TBD
1.142 V
1.434 V
2.941 V
TBD
TBD
TBD
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Custom threshold voltages are available. Minimum order quantities apply. Contact TI for details and availability.
(3) Product Preview
3
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Production Data
TPS3103xxx-EP
TPS3106xxx-EP
TPS3110xxx-EP
www.ti.com
SLVS686–OCTOBER 2006
AVAILABLE OPTIONS
DEVICE
TPS3103
TPS3106
TPS3110
RESET OUTPUT
RSTSENSE, RSTVDD OUTPUT
SENSE INPUT
WDI INPUT
PFO OUTPUT
Open drain
Open drain
Open drain
ü
ü
Push-pull
ü
ABSOLUTE MAXIMUM RATINGS(1)
over operating free-air temperature range (unless otherwise noted)
VALUE
UNIT
V
(2)
Supply voltage range, VDD
–0.3 to 3.6
–0.3 to 3.6
5
All other pins(2)
V
Maximum low output current, IOL
Maximum high output current, IOH
mA
mA
mA
mA
°C
–5
Input clamp current, IIK (VI < 0 or VI > VDD
)
±10
Output clamp current, IOK (VO < 0 or VO > VDD
Operating temperature range, TA
Storage temperature range, Tstg
Soldering temperature
)
±10
–55 to 125
–65 to 150
260
°C
°C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to GND. For reliable operation, the device must not be operated at 3.6 V for more than t = 1000h
continuously
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
0.4
MAX
3.3
UNIT
V
(1)
Supply voltage, VDD
Input voltage, VI
0
VDD + 0.3
V
High-level input voltage, VIH at MR, WDI
Low-level input voltage, VIL at MR, WDI
Input transition rise and fall rate at ∆t/∆V at MR, WDI
Operating temperature, TA
0.7 × VDD
V
0.3 × VDD
100
V
ns/V
°C
–55
125
(1) For proper operation of SENSE, PFI, and WDI functions: VDD ≥ 0.8 V.
ELECTRICAL CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VDD = 3.3 V, IOH = –3 mA
VDD = 1.8 V, IOH = –2 mA
VDD = 1.5 V, IOH = –1 mA
VDD = 0.9 V, IOH = –0.4 mA
VDD = 0.5 V, IOH = –5 µA
VDD = 3.3 V, IOL = 3 mA
VDD = 1.5 V, IOL = 2 mA
VDD = 1.2 V, IOL = 1 mA
VDD = 0.9 V, IOL = 500 µA
VDD = 0.4 V, IOL = 5 µA
0.8 × VDD
V
V
V
V
VOH
High-level output voltage
0.7 × VDD
VOL
Low-level output voltage
0.3
0.1
VOL
Low-level output voltage RESET only
4
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TPS3103xxx-EP
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TPS3110xxx-EP
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SLVS686–OCTOBER 2006
ELECTRICAL CHARACTERISTICS (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
0.854
1.133
1.423
1.512
1.829
2.905
2.867
0.540
0.530
TYP
0.86
MAX
0.866
1.151
1.445
1.534
1.857
2.970
3.005
0.569
0.575
UNIT
TPS31xxE09
TPS31xxE12
TPS31xxE15
TPS31xxE16
TPS31xxH20
TPS31xxK33
1.142
1.434
1.523
1.843
2.941
TA = 25°C
Negative-going input
threshold voltage(1)
VIT–
V
TA = 25°C
TA = Full Range
V
DD ≥ 0.8 V, TA = 25°C
0.551
0.551
20
Negative-going input
threshold voltage(2)
VIT – (S)
SENSE, PFI
V
V
DD ≥ 0.8 V, TA = Full Range
0.8 V ≤ VIT < 1.5 V
1.6 V ≤ VIT < 2.4 V
2.5 V ≤ VIT < 3.3 V
VHYS
Hysteresis at VDD input
30
mV
60
Temperature coefficient of VIT–, PFI,
SENSE
T(K)
TA = –55°C to 125°C
–0.012
15
–0.019
%/K
mV
VHYS
Hysteresis at SENSE, PFI input
MR
VDD ≥ 0.8 V
MR = VDD, VDD = 3.3 V
–30
–25
–47
–25
25
25
IIH
High-level input current
nA
SENSE, PFI,
WDI
SENSE, PFI, WDI = VDD
VDD = 3.3 V
,
MR
MR = 0 V, VDD = 3.3 V
–33
–25
25
µA
IIL
Low-level input current
SENSE, PFI,
WDI
SENSE, PFI, WDI = 0 V,
VDD = 3.3 V
nA
High-level output current
at RESET(3)
IOH
Open drain
VDD = VIT + 0.2 V, VOH = 3.3 V
200
3
nA
VDD > VIT (average current),
VDD < 1.8 V
1.2
2
VDD > VIT (average current),
VDD > 1.8 V
4.5
IDD
Supply current
µA
VDD < VIT, VDD < 1.8 V
VDD < VIT, VDD > 1.8 V
29
32
Internal pullup resistor at MR
Input capacitance at MR, SENSE, PFI, WDI VI = 0 V to VDD
70
100
1
130
kΩ
CI
pF
(1) To ensure the best stability of the threshold voltage, a bypass capacitor (ceramic, 0.1 µF) should be placed close to the supply
terminals.
(2) To ensure the best stability of the threshold voltage, a bypass capacitor (ceramic, 0.1 µF) should be placed close to the supply
terminals.
(3) Also refers to RSTVDD and RSTSENSE.
SWITCHING CHARACTERISTICS
RL = 1 MΩ, CL = 50 pF, and TA = –55°C to 125°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
DD ≥ 1.1 × VIT, MR = 0.7 × VDD
See Timing Diagrams
MIN
TYP
MAX UNIT
V
,
td
Delay time
65
130
195
40
ms
µs
µs
µs
µs
Propagation delay time, VDD to RESET or
high-to-low-level output RSTVDD delay
tPHL
tPHL
tPHL
tPLH
VIH = 1.1 × VIT, VIL = 0.9 × VIT
Propagation delay time, SENSE to RESET or
high-to-low-level output RSTSENSE delay
VDD ≥ 0.8 V, VIH = 1.1 × VIT, VIL = 0.9 × VIT
VDD ≥ 0.8 V, VIH = 1.1 × VIT, VIL = 0.9 × VIT
VDD ≥ 0.8 V, VIH = 1.1 × VIT, VIL = 0.9 × VIT
40
Propagation delay time,
PFI to PFO delay
40
high-to-low-level output
Propagation delay time,
PFI to PFO delay
300
low-to-high-level output
5
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TPS3110xxx-EP
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SLVS686–OCTOBER 2006
SWITCHING CHARACTERISTICS (continued)
RL = 1 MΩ, CL = 50 pF, and TA = –55°C to 125°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Propagation delay time, MR to RESET,
V
VDD
DD ≥ 1.1 × VIT, VIL = 0.3 × VDD, VIH = 0.7 ×
tPHL
high_to_low-level
output
RSTVDD,
RSTSENSE delay
1
5
µs
TIMING REQUIREMENTS
RL = 1 MΩ, CL = 50 pF, and TA = –55°C to 125°C (unless otherwise noted)
PARAMETER
tT(OUT) Time-out period
TEST CONDITIONS
MIN
TYP
1.1
MAX UNIT
at WDI
at VDD
at MR
V
DD ≥ 0.85 V
0.55
20
1.65
s
VIH = 1.1 × VIT, VIL = 0.9 × VIT–, VIT– = 0.86 V
V
V
V
V
DD ≥ VIT + 0.2 V, VIL = 0.3 × VDD, VIH = 0.7 × VDD
DD ≥ VIT, VIH = 1.1 × VIT – (S), VIL = 0.9 × VIT – (S)
DD ≥ 0.85 V, VIH = 1.1 × VIT – (S), VIL = 0.9 × VIT – (S)
DD ≥ VIT, VIL = 0.3 × VDD, VIH = 0.7 × VDD
0.1
20
tW
Pulse width
at SENSE
at PFI
µs
20
at WDI
0.3
FUNCTIONAL BLOCK DIAGRAMS
TPS3103
VDD
VIT-
+
_
MR
RESET
Reset Logic
and Timer
+
_
PFI
PFO
0.551 V
GND
6
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SLVS686–OCTOBER 2006
FUNCTIONAL BLOCK DIAGRAMS (continued)
TPS3106
VDD
VIT-
+
MR
RSTVDD
_
Reset Logic
and Timer
RSTSENSE
Reset Logic
and Timer
+
_
SENSE
GND
0.551 V
TPS3110
VDD
VIT-
+
_
MR
RESET
Reset Logic
and Timer
+
_
SENSE
0.551 V
Watchdog
Logic and
Control
WDI
GND
Table 1. TPS3103 FUNCTION TABLE
MR
L
V(PFI) > 0.551 V
VDD > VIT
RESET
PFO
L
0
1
0
0
1
1
X(1)
L
L
L
X
H
H
H
H
H
0
L
L
1
H
L
L
0
H
1
H
H
(1) X = Don’t care
7
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SLVS686–OCTOBER 2006
Table 2. TPS3106 FUNCTION TABLE
MR
L
V(SENSE) > 0.551 V
VDD > VIT
RSTVDD
RSTSENSE
X(1)
X
0
1
0
1
L
L
L
L
H
0
H
0
H
L
L
H
1
H
H
H
1
H
(1) X = Don’t care
Table 3. TPS3110 FUNCTION TABLE(1)
MR
L
V(SENSE) > 0.551 V
VDD > VIT
RESET
X(2)
X
0
1
0
1
L
L
L
L
H
H
0
H
0
H
1
H
1
(1) Function of watchdog timer not shown
(2) X = Don’t care
8
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SLVS686–OCTOBER 2006
TIMING DIAGRAMS
VDD
VIT
0.4 V
t
td
SENSE
VIT-(S) = 0.551 V
t
t
td
td
td
td
RESET
Output Condition
Undefined
Output Condition
Undefined
t
MR
t
t
PFI
VIT-(S) = 0.551 V
PFO
Output Condition
Undefined
Output Condition
Undefined
t
Figure 1. TPS3103 Timing
9
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SLVS686–OCTOBER 2006
TIMING DIAGRAMS (continued)
VDD
VIT
0.4 V
td
t
td
RSTVDD
Output Condition
Undefined
Output Condition
Undefined
t
SENSE
VIT-(S) = 0.551 V
t
td
RSTSENSE
Output Condition
Undefined
Output Condition
Undefined
t
td
MR
t
Figure 2. TPS3106 Timing
10
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SLVS686–OCTOBER 2006
TIMING DIAGRAMS (continued)
VDD
VIT
0.4 V
td
t
SENSE
VIT-(S) = 0.551 V
td
td
td
t
td
td
RESET
Output Condition
Undefined
Output Condition
Undefined
t(TOUT)
WDI
x = Don’t Care
MR
t
Figure 3. TPS3110 Timing
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TYPICAL CHARACTERISTICS
0.30
TPS3103xxx-EP
TPS3106xxx-EP
TPS3110xxx-EP
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SLVS686–OCTOBER 2006
TPS3110E09
SUPPLY CURRENT
vs
TPS3110E09
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
SUPPLY VOLTAGE
20
18
16
14
12
10
8
TA = 85°C
SENSE = VDD
MR = Open
VDD = 0.9 V
SENSE = GND
MR = GND
WDI = GND
0.25
0.20
0.15
0.10
0.05
0
RESET = Open
WDI: Triggered
TA = 25°C
TA = 0°C
TA = 85°C
TA = 25°C
TA = 0°C
TA = -40°C
6
TA = -40°C
4
2
0
0
0.5
1.0
1.5
2.0
2.5
3.0
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
VDD - Supply Voltage - V
IOL - Low-Level Output Current - mA
Figure 4.
Figure 5.
TPS3110E09
TPS3110E09
HIGH-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
HIGH-LEVEL OUTPUT CURRENT
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0.90
0.85
0.80
0.75
0.70
0.65
0.60
VDD = 3.3 V
SENSE = GND
MR = GND
WDI = GND
TA = 85°C
TA = 25°C
TA = 85°C
TA = 0°C
TA = -40°C
TA = 25°C
TA = 0°C
VDD = 0.9 V
TA = -40°C
SENSE = VDD
MR = VDD
WDI: Triggered
0
2
4
6
8
10 12 14 16 18 20
0
-0.1
-0.2
-0.3
-0.4
-0.5
IOL - Low-Level Output Current - mA
IOH - High-Level Output Current - mA
Figure 6.
Figure 7.
12
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SLVS686–OCTOBER 2006
TYPICAL CHARACTERISTICS (continued)
TPS3110K33
HIGH-LEVEL OUTPUT VOLTAGE
vs
MINIMUM PULSE DURATION AT VDD
vs
HIGH-LEVEL OUTPUT CURRENT
THRESHOLD OVERDRIVE VOLTAGE
3.4
3.2
50
45
40
35
30
25
20
15
10
VDD = 3.3 V
MR: Open
SENSE = VDD
SENSE = VDD
MR = VDD
WDI: Triggered
3.0
2.8
2.6
2.4
2.2
TA = -40°C
VDD = 3.3 V
TA = 0°C
TA = 25°C
TA = 85°C
VDD = 0.9 V
5
0
2.0
0
-5
-10
-15
-20
-25
0
0.1
0.2
0.3
0.4
0.5
VDD - Threshold Overdrive Voltage - V
IOH - Low-Level Output Current - mA
Figure 8.
Figure 9.
NORMALIZED THRESHOLD VOLTAGE
vs
FREE-AIR TEMPERATURE
1.008
1.006
1.004
1.002
1.000
0.998
0.996
0.994
0.992
-50
0
50
100
TA - Free-Air Temperature - °C
Figure 10.
13
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APPLICATION INFORMATION
The TPS31xx family has a quiescent current in the 1-µA to 2-µA range. When RESET is active, triggered by the
voltage monitored at VDD, the quiescent current increases to about 20 µA (see the Electrical Characteristics).
In some applications, it is necessary to minimize the quiescent current even during the reset period. This is
especially true when the voltage of a battery is supervised and the RESET is used to shut down the system or
for an early warning. In this case, the reset condition lasts for a longer period of time. The current drawn from
the battery should almost be zero, especially when the battery is discharged.
For this kind of application, either the TPS3103 or TPS3106 is a good fit. To minimize current consumption,
select a version where the threshold voltage is lower than the voltage monitored at VDD. The TPS3106 has two
reset outputs. One output (RSTVDD) is triggered from the voltage monitored at VDD. The other output
(RSTSENSE) is triggered from the voltage monitored at SENSE. In the application shown in Figure 11, the
TPS3106E09 is used to monitor the input voltage of two NiCd or NiMH cells. The threshold voltage
(V(TH) = 0.86 V) was chosen as low as possible to ensure that the supply voltage is always higher than the
threshold voltage at VDD. The voltage of the battery is monitored using the SENSE input. The voltage divider
was calculated to assert a reset using the RSTSENSE output at 2 × 0.8 V = 1.6 V.
VTRIP
ǒ Ǔ
R1 + R2
* 1
VIT S
(
)
(1)
where:
VTRIP is the voltage of the battery at which a reset is asserted and
VIT(S) is the threshold voltage at SENSE = 0.551 V.
R1 was chosen for a resistor current in the 1-µA range.
With VTRIP = 1.6 V:
R1 ≈ 1.9 × R2
R1 = 820 kΩ, R2 = 430 kΩ
VDD
R3
TPS3106E09DBV
R1
MR
2 Cell
NiMH
RSTVDD
SENSE
Reset Output
RSTSENSE
GND
R2
Figure 11. Battery Monitoring with 3-µA Supply Current for Device and Resistor Divider
14
Submit Documentation Feedback
Production Data
TPS3103xxx-EP
TPS3106xxx-EP
TPS3110xxx-EP
www.ti.com
SLVS686–OCTOBER 2006
APPLICATION INFORMATION (continued)
Watchdog
The TPS3110 device integrates a watchdog timer that must be periodically triggered by a positive or negative
transition of WDI. When the supervising system fails to retrigger the watchdog circuit within the time-out interval,
RESET becomes active for the time period (tD). This event also reinitializes the watchdog timer.
Manual Reset (MR)
Many µC-based products require manual-reset capability, allowing an operator or logic circuitry to initiate a
reset. Logic low at MR asserts reset. Reset remains asserted while MR is low and for a time period (tD) after MR
returns high. The input has an internal 100-kΩ pullup resistor, so it can be left open if it is unused.
Connect a normally open momentary switch from MR to GND to create a manual reset function. External
debounce is not required. If MR is driven from long cables or if the device is used in noisy environments,
connecting a 0.1-µF capacitor from MR to GND provides additional noise immunity.
PFI, PFO
The TPS3103 has an integrated power-fail input (PFI) comparator with a separate open-drain power-fail output
(PFO). The PFI and PFO can be used for low-battery detection, power-fail warning, or for monitoring a power
supply other than the main supply.
An additional comparator is provided to monitor voltages other than the nominal supply voltage. The PFI is
compared with an internal voltage reference of 0.551 V. If the input voltage falls below the power-fail threshold
(VIT – (S)), the PFO goes low. If it goes above 0.551 V plus approximately 15-mV hysteresis, the output returns to
high. By connecting two external resistors, it is possible to supervise any voltage above 0.551 V. The sum of
both resistors should be approximately 1 MΩ, to minimize power consumption and to ensure that the current into
the PFI pin can be neglected, compared with the current through the resistor network. The tolerance of the
external resistors should be not more than 1% to ensure minimal variation of sensed voltage. If the power-fail
comparator is unused, connect PFI to GND and leave PFO unconnected. For proper operation of the PFI
comparator, the supply voltage (VDD) must be higher than 0.8 V.
SENSE
The voltage at the SENSE input is compared with a reference voltage of 0.551 V. If the voltage at SENSE falls
below the sense-threshold (VIT–(S)), reset is asserted. On the TPS3106, a dedicated RSTSENSE output is
available. On the TPS3110, the logic signal from SENSE is OR-wired with the logic signal from VDD or MR. An
internal timer delays the return of the output to the inactive state, once the voltage at SENSE goes above
0.551 V plus about 15 mV of hysteresis. For proper operation of the SENSE comparator, the supply voltage
must be higher than 0.8 V.
2 V
VDD
VDD
(1) (1)
MSP430
Low-Power mC
TPS3103H20
R1
R2
MR
PFI
Px.x
Analog
Circuit
RESET
PFO
RESET
Py.x
GND
GND
-2 V
R2
R1
V(NEG_TH) = 0.551 V -
(VDD - 0.551 V)
(1) Resistor may be integrated in mC.
Figure 12. TPS3103 Monitoring a Negative Voltage
15
Submit Documentation Feedback
Production Data
TPS3103xxx-EP
TPS3106xxx-EP
TPS3110xxx-EP
www.ti.com
SLVS686–OCTOBER 2006
APPLICATION INFORMATION (continued)
3.3 V
1.5 V
VCORE
DSP
VIO
VDD
R1
R2
TPS3110K33
R1 + R2
R2
V(CORE_TH) = 0.551 V x
MR
RESET
Px.y
RESET
SENSE
WDI
GND
GND
GND
Figure 13. TPS3110 in a DSP System Monitoring Both Supply Voltages
16
Submit Documentation Feedback
PACKAGE OPTION ADDENDUM
www.ti.com
18-Sep-2008
PACKAGING INFORMATION
Orderable Device
TPS3106K33MDBVREP
V62/06643-07XE
Status (1)
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOT-23
DBV
6
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOT-23
DBV
6
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
6-Aug-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) W1 (mm)
(mm) (mm) Quadrant
TPS3106K33MDBVREP SOT-23
DBV
6
3000
180.0
9.0
3.15
3.2
1.4
4.0
8.0
Q3
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
6-Aug-2008
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SOT-23 DBV
SPQ
Length (mm) Width (mm) Height (mm)
182.0 182.0 20.0
TPS3106K33MDBVREP
6
3000
Pack Materials-Page 2
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