TPS311012DVB
更新时间:2024-09-18 01:53:44
品牌:TI
描述:ULTRALOW SUPPLY CURRENT/SUPPLY VOLTAGE SUPERVISORY CIRCUITS
TPS311012DVB 概述
ULTRALOW SUPPLY CURRENT/SUPPLY VOLTAGE SUPERVISORY CIRCUITS 超低电源电流/电源电压监控电路
TPS311012DVB 数据手册
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SLVS363B − AUGUST 2001 − REVISED SEPTEMBER 2004
TPS3103
DBV PACKAGE
(TOP VIEW)
features
ꢀ
Precision Supply Voltage Supervision
Range: 0.9 V, 1.2 V, 1.5 V, 1.6 V,
2 V, 3.3 V
1
2
3
6
5
V
DD
RESET
ꢀ
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High Trip Point Accuracy: 0.75%
GND
MR
PFO
PFI
Supply Current of 1.2 µA (Typ)
RESET Defined With Input Voltages as Low
as 0.4 V
4
TPS3106
DBV PACKAGE
(TOP VIEW)
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Power On Reset Generator With a Delay
Time of 130 ms
Push/Pull or Open-Drain RESET Outputs
SOT23-6 Package
V
1
2
3
RSTVDD
GND
6
5
DD
Temperature Range . . . −40°C to 85°C
RSTSENSE
SENSE
typical applications
4
MR
ꢀ
Applications Using Low-Power DSPs,
Microcontrollers or Microprocessors
TPS3110
DBV PACKAGE
(TOP VIEW)
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Portable/Battery-Powered Equipment
Intelligent Instruments
1
2
3
6
5
V
RESET
GND
Wireless Communication Systems
Programmable Controls
DD
WDI
Industrial Equipment
4
SENSE
MR
Notebook/Desktop Computers
Automotive Systems
typical application circuit
description
The TPS310x, TPS311x families of supervisory
3.3 V
1.6 V
circuits provide circuit initialization and timing
supervision, primarily for DSP and processor-
based systems.
V
V
V
IO
DD
core
DSP
RESET
R3
TPS3106E33DBV
During power on, RESET is asserted when the
R1
R2
supply voltage (V ) becomes higher than 0.4 V.
MR
RSTVDD
DD
Thereafter, the supervisory circuit monitors V
DD
SENSE
and keeps the RESET output active as long as
RSTSENSE
V
remains below the threshold voltage (V ). An
DD
IT
GND
GND
internal timer delays the return of the output to the
inactive state to ensure proper system reset. The
GND
delay time starts after V
has risen above the V .
DD
IT
When the V
drops below the V , the output
DD
IT
becomes active again.
All the devices of this family have a fixed-sense threshold voltage (V ) set by an internal voltage divider.
IT
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
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ꢤ ꢞꢜ ꢝꢞ ꢟ ꢠ ꢢ ꢞ ꢣ ꢧꢦ ꢤ ꢛ ꢝꢛ ꢤ ꢡ ꢢ ꢛꢞ ꢜꢣ ꢧ ꢦꢟ ꢢꢬ ꢦ ꢢꢦ ꢟ ꢠꢣ ꢞꢝ ꢀꢦꢅ ꢡ ꢣ ꢙꢜꢣ ꢢꢟ ꢥꢠ ꢦꢜꢢ ꢣ ꢣꢢ ꢡꢜ ꢪꢡꢟ ꢪ ꢭ ꢡꢟ ꢟ ꢡ ꢜꢢꢮꢫ
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Copyright 2001 − 2004 Texas Instruments Incorporated
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SLVS363B − AUGUST 2001 − REVISED SEPTEMBER 2004
description (continued)
The TPS3103 and TPS3106 have an active-low, open drain RESET output. The TPS3110 has an active-low
push/pull RESET.
The product spectrum is designed for supply voltages of 0.9 V up to 3.3 V. The circuits are available in a 6-pin
SOT-23 package. The TPS31xx family is characterized for operation over a temperature range of −40°C
to 85°C.
AVAILABLE OPTIONS
RSTSENSE,
RSTVDD OUTPUT
SENSE
INPUT
WDI
INPUT
DEVICE
PFO OUTPUT
RESET OUTPUT
TPS3103
TPS3106
TPS3110
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Open drain
Push-pull
ꢁ
Open drain
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Open drain
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PACKAGE INFORMATION
DEVICE NAME
THRESHOLD VOLTAGE,
T
A
MARKING
V
IT
‡
‡
§
§
TPS3103E12DBVR
TPS3103E15DBVR
TPS3103H20DBVR
TPS3103E12DBVT
TPS3103E15DBVT
TPS3103H20DBVT
1.142 V
1.434 V
1.84 V
PFWI
PFXI
PFYI
PGRI
PFZI
PGSI
PGBI
PGII
‡
§
‡
§
§
§
§
TPS3103K33DBVR
TPS3103K33DBVT
TPS3106E09DBVT
TPS3106E16DBVT
TPS3106K33DBVT
2.941 V
0.86 V
ꢂ
‡
TPS3106E09DBVR
‡
−40°C to 85°C
TPS3106E16DBVR
TPS3106K33DBVR
1.521 V
2.941 V
0.86 V
‡
‡
‡
‡
§
§
§
§
TPS3110E09DBVR
TPS3110E12DBVR
TPS3110E15DBVR
TPS3110E09DBVT
TPS3110E12DBVT
TPS3110E15DBVT
TPS3110K33DBVT
1.142 V
1.434 V
2.941 V
PGJI
PGKI
PGLI
ꢂ
‡
TPS3110K33DBVR
†
‡
§
TPS3106E09 and TPS3110K33 will be available in August 2001; all other versions will be available in October 2001.
The DBVR passive indicates tape and reel of 3000 parts.
The DBVT passive indicates tape and reel of 250 parts.
2
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SLVS363B − AUGUST 2001 − REVISED SEPTEMBER 2004
ordering information
TPS31 03
E
15 DBV
R
Reel
Package
Nominal Supply Voltage
Typical Reset Threshold Voltage
Functionality
Family
TYPICAL RESET
THRESHOLD VOLTAGE,
NOMINAL SUPPLY
DEVICE NAME
DEVICE NAME
VOLTAGE, V
N(dc)
V
IT
TPS310xx09DBV
TPS311xx09DBV
TPS310XEXXDBV
TPS311XEXXDBV
0.9 V
V
N(dc)
V
N(dc)
− 5%
− 8%
TPS310xx12DBV
TPS311xx12DBV
1.2 V
TPS310XHXXDBV
TPS310xx15DBV
TPS311xx15DBV
TPS310XKXXDBV
TPS311XKXXDBV
1.5 V
V
N(dc)
− 11%
TPS310xx16DBV
TPS310xx20DBV
1.6 V
2 V
TPS310xx33DBV-
TPS311xx33DBV
3.3 V
Function Tables
†
TPS3110
MR
V
V
DD
> V
RESET
(SENSE) > 0.551 V
IT
L
x
0
0
1
1
x
L
L
L
L
H
H
H
H
H
0
1
0
1
†
Function of watchdog-timer not shown
x = Don’t care
TPS3103
> V
IT
MR
L
V
(PFI)
> 0.551 V
V
DD
RESET
PFO
0
1
0
0
1
1
x
L
L
L
H
L
L
x
0
1
0
1
H
H
H
H
L
H
L
L
H
H
H
TPS3106
> V
IT
MR
L
V
V
DD
RSTVDD
RSTSENSE
(SENSE) > 0.551 V
x
x
0
1
0
1
L
L
L
L
H
0
0
1
1
H
H
L
L
H
H
H
H
H
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SLVS363B − AUGUST 2001 − REVISED SEPTEMBER 2004
functional block diagram
TPS3103
V
DD
V
IT−
+
_
MR
RESET
PFO
Reset Logic
and Timer
+
_
PFI
0.551 V
GND
TPS3106
V
DD
V
IT−
+
_
MR
RSTVDD
Reset Logic
and Timer
RSTSENSE
Reset Logic
and Timer
+
_
SENSE
GND
0.551 V
4
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SLVS363B − AUGUST 2001 − REVISED SEPTEMBER 2004
functional block diagram (continued)
TPS3110
V
DD
V
IT−
+
_
MR
RESET
Reset Logic
and Timer
+
_
SENSE
0.551 V
Watchdog
Logic and
Control
WDI
GND
5
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SLVS363B − AUGUST 2001 − REVISED SEPTEMBER 2004
timing diagram
V
DD
V
IT
0.4 V
t
t
t
d
d
SENSE
V
= 0.551 V
IT−(S)
t
t
t
t
d
d
d
t
RESET
Output Condition
Undefined
Output Condition
Undefined
t
MR
t
t
PFI
V
= 0.551 V
IT−(S)
PFO
Output Condition
Undefined
Output Condition
Undefined
t
Figure 1. Timing Diagram for TPS3103
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SLVS363B − AUGUST 2001 − REVISED SEPTEMBER 2004
timing diagram
V
V
DD
IT
0.4 V
t
t
d
t
d
RSTVDD
Output Condition
Undefined
Output Condition
Undefined
t
SENSE
V
= 0.551 V
IT−(S)
t
t
d
RSTSENSE
Output Condition
Undefined
Output Condition
Undefined
t
t
d
MR
t
Figure 2. Timing Diagram for TPS3106
7
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SLVS363B − AUGUST 2001 − REVISED SEPTEMBER 2004
timing diagram
V
V
DD
IT
0.4 V
t
t
t
t
d
d
SENSE
V
= 0.551 V
IT−(S)
t
t
d
d
t
t
RESET
d
d
Output Condition
Undefined
Output Condition
Undefined
t
(tout)
WDI
x = Don’t Care
MR
t
Figure 3. Timing Diagram for TPS3110
8
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SLVS363B − AUGUST 2001 − REVISED SEPTEMBER 2004
Terminal Functions
TERMINAL
PART
ALL
I/O
DESCRIPTION
NAME
GND
NO.
2
3
GND
Manual-reset input. Pull low to force a reset. RESET remains low as long as MR is low
MR
ALL
I
and for the timeout period after MR goes high. Leave unconnected or connect to V
when unused.
DD
PFI
TPS3103
TPS3103
4
5
1
I
Power-fail input compares to 0.551 V with no additional delay. Connect to V
Power-fail output. Goes high when voltage at PFI rises above 0.551 V.
Active-low reset output. Either push-pull or open-drain output stage
if not used.
DD
PFO
O
O
TPS3103
TPS3110
RESET
RSTSENSE
TPS3106
5
1
O
O
I
Active-low reset output. Logic level at RSTSENSE only depends on the voltage at
SENSE and the status of MR.
TPS3106
Active-low reset output. Logic level at RSTVDD only depends on the voltage at V
the status of MR.
and
RSTVDD
SENSE
DD
TPS3106
TPS3110
4
4
A reset will be asserted if the voltage at SENSE is lower than 0.551 V. Connect to V
unused
if
DD
ALL
6
5
Supply voltage. Powers the device and monitors its own voltage
V
DD
WDI
TPS3110
I
Watchdog timer input. If WDI remains high or low longer than the time-out period, then
reset is triggered. The timer clears when reset is asserted or when WDI sees a rising
edge or a falling edge.
detailed description
watchdog
The TPS3110 device integrates a watchdog timer that must be periodically triggered by a positive or negative
transition of WDI. When the supervising system fails to retrigger the watchdog circuit within the time-out interval,
RESET becomes active for the time period (t ). This event also reinitializes the watchdog timer.
d
manual reset (MR)
Many µC-based products require manual-reset capability, allowing an operator or logic circuitry to initiate a
reset. Logic low at MR asserts reset. Reset remains asserted while MR is low and for a time period (t ) after
d
MR returns high. The input has an internal 100-kΩ pull-up resistor, so it can be left open if it is unused.
Connect a normally open momentary switch from MR to GND to create a manual reset function. External
debounce is not required. If MR is driven from long cables or if the device is used in noisy environments,
connecting a 0.1-µF capacitor from MR to GND provides additional noise immunity.
PFI, PFO
The TPS3103 has an integrated power-fail (PFI) comparator with a separate open drain (PFO) output can be
used for low-battery detection, power-fail warning, or for monitoring a power supply other than the main supply.
An additional comparator is provided to monitor voltages other than the nominal supply voltage. The power-fail
input (PFI) will be compared with an internal voltage reference of 0.551 V. If the input voltage falls below the
power-fail threshold (V
), the power-fail output (PFO) goes low. If it goes above 0.551 V plus approximately
IT−(S)
15-mV hysteresis, the output returns to high. By connecting two external resistors, it is possible to supervise
any voltage above 0.551 V. The sum of both resistors should be approximately 1 MΩ, to minimize power
consumption and to assure that the current into the PFI pin can be neglected compared with the current through
the resistor network. The tolerance of the external resistors should be not more than 1% to ensure minimal
variation of sensed voltage. If the power-fail comparator is unused, connect PFI to GND and leave PFO
unconnected. For proper operation of the PFI-comparator the supply voltage (V ) must be higher than 0.8 V.
DD
9
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SLVS363B − AUGUST 2001 − REVISED SEPTEMBER 2004
SENSE
The voltage at the SENSE input is compared with a reference voltage of 0.551 V. If the voltage at SENSE falls
below the sense-threshold (V ), reset is asserted. On the TPS3106, a dedicated RSTSENSE output is
IT−(S)
available. On the TPS3110, the logic signal from SENSE is OR-wired with the logic signal from V
or MR. An
DD
internal timer delays the return of the output to the inactive state, once the voltage at SENSE goes above 0.551 V
plus about 15 mV of hysteresis. For proper operation of the SENSE-comparator, the supply voltage must be
higher than 0.8 V.
ABSOLUTE MAXIMUM RATINGS OVER OPERATING FREE-AIR TEMPERATURE (UNLESS
(1)
OTHERWISE NOTED)
(2)
Supply voltage, V
All other pins
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6 V
DD
(2)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 3.6 V
Maximum low output current, I
Maximum high output current, I
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −5 mA
OL
OH
Input clamp current, I (V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 mA
IK
OK
I
I
DD
Output clamp current, I
(V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 mA
O O DD
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Operating free-air temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 85°C
A
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
stg
Soldering temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is
not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(1)
(2)
All voltage values are with respect to GND. For reliable operation, the device must not be operated at 3.6 V for more than t=1000h continuously.
DISSIPATION RATING TABLE
T
≤ 25°C
DERATING FACTOR
T
= 70°C
T = 85°C
A
A
A
PACKAGE
POWER RATING
ABOVE T = 25°C
POWER RATING POWER RATING
A
DBV
437 mW
3.5 mW/°C
280 mW
227 mW
recommended operating conditions
MIN
0.4
0
MAX
3.3
UNIT
V
(1)
Supply voltage, V
DD
Input voltage, V
V
DD
+ 0.3
V
I
High-level input voltage, V at MR, WDI
IH
0.7 × V
DD
V
Low-level input voltage, V at MR, WDI
IL
0.3 × V
DD
V
Input transition rise and fall rate at ∆t/∆V at MR, WDI
100
85
ns/V
°C
Operating free-air temperature range, T
−40
A
(1)
For proper operation of SENSE, PFI, and WDI functions: V
DD
≥ 0.8 V
10
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SLVS363B − AUGUST 2001 − REVISED SEPTEMBER 2004
electrical characteristics over recommended operating conditions (unless otherwise noted)
PARAMETERS
TEST CONDITIONS
MIN
TYP
MAX UNIT
V
V
V
V
V
V
V
V
V
V
= 3.3 V,
= 1.8 V,
= 1.5 V,
= 0.9 V,
= 0.5 V,
= 3.3 V,
= 1.5 V,
= 1.2 V,
= 0.9 V,
= 0.4 V,
I
I
I
I
I
I
I
I
I
I
= −3 mA
= −2 mA
= −1 mA
= −0.4 mA
= −5 µA
= 3 mA
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
OH
OH
OH
OH
OH
OL
OL
OL
OL
OL
0.8 × V
DD
V
High-level output voltage
V
OH
OL
0.7 × V
DD
= 2 mA
0.3
V
Low-level output
voltage
= 1 mA
V
= 500 µA
= 5 µA
RESET only
TPS31xxE09
TPS31xxE12
TPS31xxE15
TPS31xxE16
TPS31xxH20
TPS31xxK33
0.1
0.866
1.151
1.445
0.854
1.133
1.423
1.512
1.829
2.919
0.86
1.142
1.434
1.523
1.843
2.941
Negative-going input
V
IT−
T
A
= 25°C
V
(1)
threshold voltage
1.534
1.857
2.963
Negative-going input
threshold voltage
V
V
SENSE, PFI
V
≥ 0.8 V, T = 25°C
0.542
0.551
0.559
V
IT−(S)
DD
A
(1)
0.8 V ≤ V < 1.5 V
20
30
IT
1.6 V ≤ V < 2.4 V
Hysteresis at V input
DD
mV
IT
hys
2.5 V ≤ V < 3.3 V
IT
50
T
Temperature coefficient of V , PFI, SENSE
IT−
T
= −40°C to 85°C
−0.012
15
−0.019
%/K
mV
(K)
A
V
Hysteresis at SENSE, PFI input
MR
V
≥ 0.8 V
hys
DD
MR = V , V
= 3.3 V
−25
−25
25
25
DD DD
I
IH
High-level input current
SENSE, PFI, WDI
nA
SENSE, PFI, WDI = V
,
DD
V
= 3.3 V
DD
MR = 0 V,
MR
V
DD
= 3.3 V
−47
−25
−33
−25
25
µA
I
I
Low-level input current
IL
SENSE, PFI, WDI SENSE, PFI, WDI = 0 V, V
DD
= 3.3 V
nA
High-level output
current at RESET
Open drain
V
= V + 0.2 V,
IT
V = 3.3 V
OH
200
3
nA
OH
DD
(2)
V
V
> V (average current),
< 1.8 V
DD
DD
IT
1.2
2
V
V
> V (average current),
> 1.8 V
DD
DD
IT
4.5
I
Supply current
µA
DD
V
< V
V
IT, DD
< 1.8 V
> 1.8 V
22
27
DD
DD
V
< V
V
IT, DD
Internal pull-up resistor at MR
70
100
1
130
kΩ
C
Input capacitance at MR, SENSE, PFI, WDI
V = 0 V to V
I DD
pF
i
(1)
(2)
To ensure the best stability of the threshold voltage, a bypass capacitor (ceramic, 0.1 µF) should be placed close to the supply terminals.
Also refers to RSTVDD and RSTSENSE
11
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SLVS363B − AUGUST 2001 − REVISED SEPTEMBER 2004
TIMING REQUIREMENTS AT R = 1 MΩ, C = 50 PF, T = −40°C TO 85°C
L
L
A
PARAMETER
TEST CONDITIONS
MIN
0.55
20
TYP
MAX
1.65
UNIT
t
Time-out period at WDI
V
V
V
V
V
V
≥ 0.85 V
1.1
s
t(out)
DD
at V
DD
= 1.1 × V , V = 0.9 × V , V
IT IL IT− IT−
= 0.86 V
= 0.7 × V
DD
IH
at MR
≥ V + 0.2 V, V = 0.3 × V
V
IH
0.1
20
DD
DD
DD
DD
IT
IL
IH
IH
IL
DD,
t
w
Pulse width
at SENSE
at PFI
≥ V ,
V
V
V
= 1.1 × V
= 1.1 × V
, V = 0.9 × V
IT−(S) IL
µs
IT
IT−(S)
≥ 0.85 V,
,V = 0.9 × V
IT−(S) IL
20
IT−(S)
at WDI
≥ V ,
IT
= 0.3 × V
DD,
V
IH
= 0.7 × V
DD
0.3
SWITCHING CHARACTERISTICS AT R = 1 MΩ, C = 50 PF, T = −40°C TO 85°C
L
L
A
PARAMETER
TEST CONDITIONS
MIN
TYP
130
MAX
UNIT
V
≥ 1.1 × V ,
IT
DD
t
d
Delay time
MR = 0.7 × V
DD
See timing diagram
,
65
195
ms
V
to RESET or
V
V
= 1.1 × V ,
IT
DD
IH
IL
t
t
Propagation delay time, high-to-low level output
Propagation delay time, low-to-high level output
40
40
PHL
RSTVDD delay
= 0.9 × V
IT
µs
V
DD
to RESET or
V
IH
V
IL
= 1.1 × V ,
IT
PLH
RSTVDD delay
= 0.9 × V
IT
V
V
V
≥ 0.8 V,
= 1.1 × V ,
= 0.9 × V
IT
DD
IH
IL
SENSE to RESET or
RSTSENSE delay
t
t
t
t
t
t
Propagation delay time, high-to-low level output
Propagation delay time, high-to-low level output
40
40
µs
µs
µs
µs
PHL
PLH
PHL
PLH
PHL
PLH
IT
V
V
V
≥ 0.8 V,
= 1.1 × V ,
= 0.9 × V
IT
DD
IH
IL
SENSE to RESET or
RSTSENSE delay
IT
V
V
V
≥ 0.8 V,
= 1.1 × V ,
= 0.9 × V
IT
DD
IH
IL
Propagation delay time, high-to-low level output PFI to PFO delay
Propagation delay time, low-to-high level output PFI to PFO delay
40
IT
V
V
V
≥ 0.8 V,
= 1.1 × V ,
= 0.9 × V
IT
DD
IH
IL
300
IT
MR to RESET.
Propagation delay time, low-to-high level output RSTVDD,
RSTSENSE delay
V
V
V
≥ 1.1 × V ,
IT
= 0.3 × V
= 0.7 × V
DD
IL
IH
,
1
5
µs
DD
DD
MR to RESET.
Propagation delay time, low-to-high level output RSTVDD,
RSTSENSE delay
12
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SLVS363B − AUGUST 2001 − REVISED SEPTEMBER 2004
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
Supply current
Low-level output voltage
High-level output voltage
Minimum pulse duration at V
vs Supply voltage at T = −40°C, 0°C, 25°C, 85°C
4
5, 6
7, 8
9
A
V
V
vs Low-level output current at T = −40°C, 0°C, 25°C, 85°C at 0.9 V, 3.3 V
A
OL
vs High-level output current at T = −40°C, 0°C, 25°C, 85°C at 0.9 V, 3.3 V
OH
A
t
w
vs Threshold overdrive voltage
vs Free-air temperature
DD
Normalized threshold voltage
V
IT
10
TPS3110E09
LOW-LEVEL OUTPUT VOLTAGE
vs
TPS3110E09
SUPPLY CURRENT
vs
LOW-LEVEL OUTPUT CURRENT
SUPPLY VOLTAGE
0.30
20
18
16
14
12
10
8
V = 0.9 V
DD
SENSE = GND
MR = GND
T
A
= 85°C
SENSE = V
MR = Open
RESET = Open
WDI: Triggered
DD
0.25
0.20
0.15
0.10
0.05
0
T
A
= 25°C
WDI = GND
T
A
= 0°C
T
A
= 85°C
T
A
= 25°C
T
A
= −40°C
T = 0°C
A
6
T
A
= −40°C
4
2
0
0
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
2
0
0.5
1
1.5
2
2.5
3
I
− Low-Level Output Current − mA
V
DD
− Supply Voltage − V
OL
Figure 4
Figure 5
13
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SLVS363B − AUGUST 2001 − REVISED SEPTEMBER 2004
TPS3110E09
TPS3110E09
LOW-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
HIGH-LEVEL OUTPUT CURRENT
0.90
0.85
0.80
0.75
0.70
0.65
0.60
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
V
= 3.3 V
DD
SENSE = GND
MR = GND
WDI = GND
T
= 85°C
A
T
= 25°C
A
T
= 85°C
A
T
A
= 0°C
T
= −40°C
T
= 25°C
A
A
T
A
= 0°C
V
= 0.9 V
DD
T = −40°C
A
SENSE = V
DD
MR = V
WDI : Triggered
DD
0
2
4
6
8
10 12 14 16 18 20
0
−0.1
−0.2
−0.3
−0.4
−0.5
I
− Low-Level Output Current − mA
I
− High-Level Output Current − mA
OL
OH
Figure 7
Figure 6
TPS3110K33
MINIMUM PULSE DURATION AT V
vs
HIGH-LEVEL OUTPUT VOLTAGE
vs
DD
THRESHOLD OVERDRIVE VOLTAGE
HIGH-LEVEL OUTPUT CURRENT
3.4
3.2
50
V
= 3.3 V
DD
SENSE = V
MR : Open
SENSE = V
DD
45
40
35
30
25
20
15
10
DD
MR = V
WDI : Triggered
DD
3
T
=−40°C
A
2.8
T
= 0°C
A
V
DD
= 3.3 V
2.6
2.4
2.2
2
T
= 25°C
A
T
= 85°C
A
V
DD
= 0.9 V
5
0
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
0
−5
−10
−15
−20
−25
V
DD
− Threshold Overdrive Voltage − V
I
− Low-Level Output Current − mA
OH
Figure 8
Figure 9
14
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SLVS363B − AUGUST 2001 − REVISED SEPTEMBER 2004
NORMALIZED THRESHOLD VOLTAGE
vs
FREE-AIR TEMPERATURE
1.008
1.006
1.004
1.002
1
0.998
0.996
0.994
0.992
−50
0
50
100
T
A
− Free-Air Temperature − °C
Figure 10
APPLICATION INFORMATION
3.3 V
1.5 V
V
V
IO
V
DD
CORE
R1
R2
TPS3110K33
DSP
R1 ) R2
V
+ 0.551 V
MR
(CORE_th)
R2
RESET
Px.y
RESET
SENSE
WDI
GND
GND
GND
Figure 11. TPS3110 in a DSP-System Monitoring Both Supply Voltages
15
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SLVS363B − AUGUST 2001 − REVISED SEPTEMBER 2004
APPLICATION INFORMATION
2 V
V
V
DD
TPS3103H20
MR
DD
MSP430
Low Power µC
Px.x
†
†
R1
R2
Analog
Circuit
RESET
RESET
Py.x
PFI
PFO
GND
GND
−2 V
R2
R1
ǒ
Ǔ
V
+ 0.551 V *
V
* 0.551 V
(neg_th)
DD
†
Resistor may be integrated in µC
Figure 12. TPS3103 Monitoring a Negative Voltage
16
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SLVS363B − AUGUST 2001 − REVISED SEPTEMBER 2004
APPLICATION INFORMATION
The TPS310x family has a quiescent current in the 1-µA to 2-µA range. When RESET, triggered by the voltage
monitored at V , is active, the quiescent current increases to about 20 µA (see electrical characteristics).
DD
In some applications it is necessary to minimize the quiescent current even during the reset period. This is
especially true when the voltage of a battery is supervised and the RESET is used to shut down the system or
for an early warning. In this case the reset condition will last for a longer period of time. Especially when the
battery is discharged, the current drawn from the battery should almost be zero.
For this kind of applications the TPS3103 or TPS3106 are a good fit. To minimize current consumption it must
be assured to select a version where the threshold voltage is lower than the voltage monitored at V . The
DD
TPS3106 has two reset outputs. One output (RSTVDD) is triggered from the voltage monitored at V . The
DD
other output (RSTSENSE) is triggered from the voltage monitored at SENSE. In the application shown in
Figure 13, the TPS3106E09 is used to monitor the input voltage of two NiCd or NiMH cells. The threshold
voltage (V
= 0.86 V) was chosen as low as possible to ensure that the supply voltage is always higher than
(th)
the threshold voltage at V . The voltage of the battery is monitored using the SENSE input. The voltage divider
was calculated to assert a reset using the RSTSENSE output at 2 x 0.8 V = 1.6 V.
DD
ǒVTRIP Ǔ
R1 + R2
*1
VIT(S)
Where:
V
V
is the voltage of the battery at which a reset is asserted
is the threshold voltage at SENSE = 0.551 V.
TRIP
IT(S)
R1 was chosen for a resistor current in the 1-µA range.
With V = 1.6 V:
TRIP
R1 ≈ 1.9 × R2
R1 = 820 k, R2 = 430 k
V
DD
TPS3106E09DBV
R3
R1
R2
MR
SENSE
2 Cell
NiMH
RSTVDD
Reset Output
RSTSENSE
GND
Figure 13. Battery Monitoring With 3-µA Supply Current for Device and Resistor Divider
17
PACKAGE OPTION ADDENDUM
www.ti.com
8-Aug-2005
PACKAGING INFORMATION
Orderable Device
TPS3103E12DBVR
TPS3103E12DBVRG4
TPS3103E12DBVT
TPS3103E12DBVTG4
TPS3103E15DBVR
TPS3103E15DBVRG4
TPS3103E15DBVT
TPS3103E15DBVTG4
TPS3103H20DBVR
TPS3103H20DBVRG4
TPS3103H20DBVT
TPS3103H20DBVTG4
TPS3103K33DBVR
TPS3103K33DBVRG4
TPS3103K33DBVT
TPS3103K33DBVTG4
TPS3106E09DBVR
TPS3106E09DBVRG4
TPS3106E09DBVT
TPS3106E09DBVTG4
TPS3106E16DBVR
TPS3106E16DBVRG4
TPS3106E16DBVT
TPS3106K33DBVR
TPS3106K33DBVRG4
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOT-23
DBV
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
8-Aug-2005
Orderable Device
TPS3106K33DBVT
TPS3106K33DBVTG4
TPS3110E09DBVR
TPS3110E09DBVRG4
TPS3110E09DBVT
TPS3110E09DBVTG4
TPS3110E12DBVR
TPS3110E12DBVRG4
TPS3110E12DBVT
TPS3110E12DBVTG4
TPS3110E15DBVR
TPS3110E15DBVRG4
TPS3110E15DBVT
TPS3110K33DBVR
TPS3110K33DBVRG4
TPS3110K33DBVT
TPS3110K33DBVTG4
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOT-23
DBV
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
8-Aug-2005
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 3
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
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TI warrants performance of its hardware products to the specifications applicable at the time of sale in
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TI assumes no liability for applications assistance or customer product design. Customers are responsible for
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Amplifiers
amplifier.ti.com
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dsp.ti.com
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Military
www.ti.com/broadband
www.ti.com/digitalcontrol
www.ti.com/military
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Logic
interface.ti.com
logic.ti.com
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power.ti.com
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microcontroller.ti.com
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Wireless
www.ti.com/wireless
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Copyright 2005, Texas Instruments Incorporated
TPS311012DVB 相关器件
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TPS311033DVB | TI | ULTRALOW SUPPLY CURRENT/SUPPLY VOLTAGE SUPERVISORY CIRCUITS | 获取价格 | |
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