TPS3123G15DBV [TI]
ULTRA-LOW VOLTAGE PROCESSOR SUPERVISORY CIRCUITS; 超低电压处理器监控电路
| 型号： | TPS3123G15DBV |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | ULTRA-LOW VOLTAGE PROCESSOR SUPERVISORY CIRCUITS |
| 文件： | 总13页 (文件大小：232K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS3123J12, TPS3123G15, TPS3123J18, TPS3124J12, TPS3124G15
TPS3124J18, TPS3125J12, TPS3125G15, TPS3125J18, TPS3125L30
ULTRA-LOW VOLTAGE PROCESSOR SUPERVISORY CIRCUITS
SLVS227 – AUGUST 1999
features
typical applications
Minimum Supply Voltage of 0.75 V
Supply Voltage Supervision Range:
Applications Using Low Voltage DSPs,
Microcontrollers or Microprocessors
– 1.2 V, 1.5 V, 1.8 V (TPS3123, TPS3124,
TPS3125)
– 3 V (TPS3125 Devices only)
Wireless Communication Systems
Portable/Battery-Powered Equipment
Programmable Controls
Power-On Reset Generator With Fixed
Delay Time of 180 ms
Intelligent Instruments
Industrial Equipment
Manual Reset Input (TPS3123 and TPS3125)
Watchdog Timer Retriggers the RESET
Notebook/Desktop Computers
Automotive Systems
Output at V
≥ V
DD
IT
Supply Current of 14 µA (Typ)
SOT23–5 Package
DBV PACKAGE
(TOP VIEW)
Temperature Range . . . –40°C to 85°C
1
5
V
DD
RESET
GND
TPS3123
2.5 V
1.2 V
2
3
4
5
WDI
MR
V
DD
MR
1
V
DD
RESET
GND
CV
DV
DD
DD
TPS3124
TPS3125J12
2
GND
RESET
3
TMS320UVC5402
XF
4
5
WDI
RESET
WDI
1
V
DD
MR
RESET
GND
TPS3125
RESET
RESET
GND
V
DD
2
TPS3823-25
GND
3
4
MR
RESET
Figure 1. Typical Dual-Voltage DSP Application
description
The TPS3123, TPS3124, TPS3125 family of ultra-low voltage processor supervisory circuits provides circuit
initialization and timing supervision, primarily for DSP and processor-based systems.
During power-on, RESET is asserted when the supply voltage (V ) becomes higher than 0.75 V. Thereafter,
DD
the supply voltage supervisor monitors V and keeps RESET output active as long as V remains below the
DD
DD
thresholdvoltageV . Aninternaltimerdelaysthereturnoftheoutputtotheinactivestate(high)toensureproper
IT
system reset. The delay time, t
= 180 ms starts after V
has risen above the threshold voltage V .
dtyp
DD IT
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS3123J12, TPS3123G15, TPS3123J18, TPS3124J12, TPS3124G15
TPS3124J18, TPS3125J12, TPS3125G15, TPS3125J18, TPS3125L30
ULTRA-LOW VOLTAGE PROCESSOR SUPERVISORY CIRCUITS
SLVS227 – AUGUST 1999
description (continued)
When the supply voltage drops below the threshold voltage V , the output becomes active (low) again. No
IT
external components are required. All the devices of this family have a fixed-sense threshold voltage V set
IT
by an internal voltage divider.
The TPS3123-xx and TPS3125-xx devices incorporate a manual reset input, MR. A low level at MR causes
RESET to become active. The TPS3124-xx devices do not have the input MR, but include a high-level output
RESET same as the TPS3125-xx devices. In addition the TPS3123-xx and TPS3124-xx have a watchdog timer
that need to be triggered periodically by a positive or negative transition at WDI. When the supervising system
fails to retrigger the watchdog circuit within the time-out interval t
= 0.8 s, RESET output becomes active for
tout
the time period t . This event also reinitializes the watchdog timer.
d
The circuits are available in a 5-pin SOT23-5 package. The TPS3123, TPS3124, TPS3125 devices are
characterized for operation over a temperature range of –40°C to 85°C.
PACKAGE INFORMATION STANDARD VERSIONS
T
DEVICE NAME
THRESHOLD VOLTAGE
MARKING
PBNI
PBOI
PBPI
A
†
‡
TPS3123J12DBVR
TPS3123J12DBVT
1.08 V
1.40 V
1.62 V
1.08 V
1.40 V
1.62 V
1.08 V
1.40 V
1.62 V
2.64 V
†
‡
TPS3123G15DBVR
TPS3123G15DBVT
†
†
‡
‡
TPS3123J18DBVR
TPS3124J12DBVR
TPS3124G15DBVR
TPS3123J18DBVT
TPS3124J12DBVT
TPS3124G15DBVT
PBQI
PBRI
PBSI
†
‡
–40°C to 85 C
†
‡
TPS3124J18DBVR
TPS3125J12DBVR
TPS3125G15DBVR
TPS3124J18DBVT
TPS3125J12DBVT
TPS3125G15DBVT
†
‡
PBTI
†
‡
PBUI
PBVI
†
‡
TPS3125J18DBVT
TPS3125J18DBVR
†
‡
TPS3125L30DBVR
TPS3125L30DBVT
PBXI
†
‡
The DBVR passive indicates tape and reel of 3000 parts.
The DBVT passive indicates tape and reel of 250 parts.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS3123J12, TPS3123G15, TPS3123J18, TPS3124J12, TPS3124G15
TPS3124J18, TPS3125J12, TPS3125G15, TPS3125J18, TPS3125L30
ULTRA-LOW VOLTAGE PROCESSOR SUPERVISORY CIRCUITS
SLVS227 – AUGUST 1999
ordering information application specific versions
TPS312
3
J
12 DBV
R
Reel
Package
Nominal Supply Voltage
Typical Reset Threshold Voltage
Functionality
Family
TYPICAL RESET
THRESHOLD
NOMINAL SUPPLY
DEVICE NAME
VOLTAGE, V
DEVICE NAME
NOM
VOLTAGE–V
IT–
TPS312xx12DBV
TPS312xx15DBV
TPS312xx18DBV
TPS312xx30DBV
1.2 V
1.5 V
1.8 V
3.0 V
TPS312xAxxDBV
TPS312xBxxDBV
TPS312xCxxDBV
TPS312xDxxDBV
TPS312xExxDBV
TPS312xFxxDBV
TPS312xGxxDBV
TPS312xHxxDBV
TPS312xIxxDBV
TPS312xJxxDBV
TPS312xKxxDBV
TPS312xLxxDBV
TPS312xMxxDBV
TPS312xNxxDBV
TPS312xOxxDBV
V
V
V
V
V
V
V
V
V
–1%
NOM
NOM
NOM
NOM
NOM
NOM
NOM
NOM
NOM
–2%
–3%
–4%
–5%
–6%
–7%
–8%
–9%
V
NOM
–10%
–11%
–12%
–13%
–14%
–15%
V
NOM
NOM
NOM
NOM
NOM
V
V
V
V
NOTE: Ten standard versions will be available at product introduction.
For the application specific versions contact the local TI sales office for availability and lead time.
Function Tables
TPS3123
TPS3124
RESET RESET
TPS3125
MR
L
VDD > V
RESET
VDD > V
MR
L
VDD > V
IT
RESET RESET
IT
IT
0
1
0
1
L
L
0
1
L
H
L
0
1
0
1
L
L
H
H
H
L
L
H
L
H
L
H
L
H
H
H
H
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS3123J12, TPS3123G15, TPS3123J18, TPS3124J12, TPS3124G15
TPS3124J18, TPS3125J12, TPS3125G15, TPS3125J18, TPS3125L30
ULTRA-LOW VOLTAGE PROCESSOR SUPERVISORY CIRCUITS
SLVS227 – AUGUST 1999
functional block diagram
V
DD
Device Power Supply
R1
†
MR
R2
R3
RESET
RESET
Reset Logic
+ Timer
§
GND
Reference
Voltage
Watch Dog
Logic +
Timer
Transition
Detector
‡
WDI
†
‡
§
TPS3123 and TPS3125 Only
TPS3123 and TPS3124 Only
TPS3124 and TPS3125 Only
timing diagram TPS3123 and TPS3125
G
A
B
C
D
E
F
V
DD
V
IT
<0,85 V
MR
t
t
RESET
t
t
t
d
d
d
t
Output Undefined
Output Undefined
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS3123J12, TPS3123G15, TPS3123J18, TPS3124J12, TPS3124G15
TPS3124J18, TPS3125J12, TPS3125G15, TPS3125J18, TPS3125L30
ULTRA-LOW VOLTAGE PROCESSOR SUPERVISORY CIRCUITS
SLVS227 – AUGUST 1999
timing diagram TPS3123 and TPS3124
A
B
V
DD
V
IT
<0,85 V
t
G
MR
(TPS3123)
t
J
C
D
E
F
H
WDI
*
*
*
*
*
t
t
t
t
t
t
d
d
d
d
d
RESET
t
t
t
tout
tout
tout
t
Output Undefined
* = WDI Disabled
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS3123J12, TPS3123G15, TPS3123J18, TPS3124J12, TPS3124G15
TPS3124J18, TPS3125J12, TPS3125G15, TPS3125J18, TPS3125L30
ULTRA-LOW VOLTAGE PROCESSOR SUPERVISORY CIRCUITS
SLVS227 – AUGUST 1999
†
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage, V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6 V
DD
All other pins (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 3.6 V
Maximum low output current, I
Maximum high output current, I
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –5 mA
OL
OH
Input clamp current, I (V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±10 mA
IK
OK
I
I
DD
Output clamp current, I
(V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±10 mA
O O DD
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Operating free-air temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 85°C
A
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
Soldering temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to GND.
DISSIPATION RATING TABLE
DERATING FACTOR
T
≤ 25°C
T
A
= 70°C
T = 85°C
A
A
PACKAGE
POWER RATING
ABOVE T = 25°C
POWER RATING POWER RATING
A
DBV
437 mW
3.5 mW/°C
280 mW 227 mW
recommended operating conditions at specified temperature range
MIN
MAX
3.3
UNIT
T
= 0°C to 85°C
0.75
0.85
0
A
Supply voltage, V
V
DD
T
A
= –40°C to 85°C
3.3
Input voltage, V
V
+0.3
V
V
I
DD
High-level input voltage, V
IH
0.7×V
DD
Low-level input voltage, V
0.3×V
V
IL
Input transition rise and fall rate at WDI, ∆t/∆V
Operating free-air temperature range, T
DD
1
µs/V
°C
–40
85
A
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS3123J12, TPS3123G15, TPS3123J18, TPS3124J12, TPS3124G15
TPS3124J18, TPS3125J12, TPS3125G15, TPS3125J18, TPS3125L30
ULTRA-LOW VOLTAGE PROCESSOR SUPERVISORY CIRCUITS
SLVS227 – AUGUST 1999
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
MR pullup resistor (internal)
27
kΩ
WDI
MR
WDI = V
DD
= 3.3 V
–1
–20
–1
1
–55
1
I
I
High-level input current
Low-level input current
µA
µA
IH
MR = 0.7×V
WDI = 0 V,
MR = 0 V,
,
V
V
V
= 3.3 V
= 3.3 V
DD
DD
DD
DD
OH
OH
OH
OH
WDI
MR
IL
= 3.3 V
–80
–170
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
= 1.5 V,
I
I
I
I
I
I
I
I
= –1 mA
= –4.5 mA
= –8 µA
= –1 mA
RESET
RESET
= 3.3 V,
= 0.75 V,
= 1.5 V,
= 0.75 V,
= 1.5 V,
= 1.5 V,
= 3.3 V,
V
High-level output voltage
Low-level output voltage
0.8×V
V
V
OH
OL
DD
= 15 µA
= 1.4 mA
= 1.4 mA
= 3 mA
OL
OL
OL
OL
RESET
RESET
0.2×V
DD
V
0.4
1.12
1.45
1.68
2.71
TPS312xJ12
TPS312xG15
TPS312xJ18
TPS312xL30
1.04
1.35
1.56
2.57
1.08
1.40
1.62
2.64
15
Negative-going input threshold
voltage (see Note 2)
V
V
T
A
= –40°C to 85°C
V
IT–
1 V < V
IT–
< 1.4 V
<2 V
< 3 V
Hysteresis at V
input
1.4 V < V
IT–
20
mV
hys
DD
2 V < V
30
IT–
V
DD
V
DD
V
DD
V
DD
= 0.75 V
= 3.3 V
= 0.75 V
= 3.3 V
14
TPS3123-xx
TPS3124-xx
WDI = V
MR unconnected
,
DD
22
30
25
I
Supply current
µA
DD
14
TPS3125-xx
(see Note 3)
MR unconnected
18
C
Input capacitance at MR, WDI
V = 0 V to 3.3 V
I
5
pF
i
NOTES: 2. To ensure best stability of the threshold voltage, a bypass capacitor (ceramic, 0.1 µF) should be placed near the supply terminal.
3. The supply current during delay time t is typical 5 µA higher.
d
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS3123J12, TPS3123G15, TPS3123J18, TPS3124J12, TPS3124G15
TPS3124J18, TPS3125J12, TPS3125G15, TPS3125J18, TPS3125L30
ULTRA-LOW VOLTAGE PROCESSOR SUPERVISORY CIRCUITS
SLVS227 – AUGUST 1999
timing requirements at R = 1 MΩ, C = 50 pF, T = 25°C
L
L
A
PARAMETER
TEST CONDITIONS
MIN
6
TYP
MAX
UNIT
At V
V
V
= V
+0.2 V,
V
= V
–0,2 V
DD
IH
IT–
IL
IL
IT–
t
w
Pulse width
At MR
1
µs
≥ V
+0.2 V,
V
= 0.3xV
,
V = 0.7×V
IH DD
DD
IT–
DD
At WDI
0.1
switching characteristics at R = 1 MΩ, C = 50 pF, T = 25°C
L
L
A
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
V
≥ V +0.2 V,
DD
IT–
t
t
t
Watchdog time out
Delay time
0.8
1.4
2.1
260
0.1
s
tout
See timing diagram
V
> V +0.2 V,
IT–
DD
See timing diagram
100
180
ms
d
MR to RESET delay
(TPS3123/25 only)
Propagation delay time, high-to-low-level output
PHL
V
V
V
≥ V
= 0.2 × V
DD
= 0.8 × V
+0.2 V,
DD
IL
IH
IT–
µs
,
MR to RESET delay
(TPS3125 only)
t
t
t
Propagation delay time, low-to-high-level output
Propagation delay time, high-to-low-level output
Propagation delay time, low-to-high-level output
0.1
10
10
DD
PLH
PHL
PLH
V
V
to RESET delay
to RESET delay
DD
V
V
= V
–0.2 V,
+0.2 V
IT–
IL
IH
IT–
= V
µs
DD
(TPS3124/25 only)
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS3123J12, TPS3123G15, TPS3123J18, TPS3124J12, TPS3124G15
TPS3124J18, TPS3125J12, TPS3125G15, TPS3125J18, TPS3125L30
ULTRA-LOW VOLTAGE PROCESSOR SUPERVISORY CIRCUITS
SLVS227 – AUGUST 1999
TYPICAL CHARACTERISTICS
SUPPLY CURRENT
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
vs
SUPPLY VOLTAGE
25
20
750
500
250
T
A
= 25°C
TPS3123J12
= 0.75 V
V
DD
TPS3123J12
T
= 85°C
A
T
A
= 25°C
= 0°C
15
10
0
T
A
0
0
1
2
3
3.3
0
50
100
150
200
250
V
DD
– Supply Voltage – V
I
OL
– Low-Level Output Current – µA
Figure 2
Figure 3
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
850
800
1.5
1.25
1
TPS3123J12
= 0.85 V
TPS3125L30
= 1.5 V
V
DD
MR = Open
V
DD
MR = Open
T
= 85°C
A
T
A
= 85°C
700
600
500
400
T
A
= 25°C
T
= 25°C
A
T
A
= 0°C
T
A
= 0°C
T
A
= –40°C
T
A
= –40°C
0.75
0.5
0.25
0
300
200
100
0
0
100
200
300
400
500
0
1
2
3
4
5
6
I
– Low-Level Output Current – µA
OL
I
– Low-Level Output Current – mA
OL
Figure 4
Figure 5
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS3123J12, TPS3123G15, TPS3123J18, TPS3124J12, TPS3124G15
TPS3124J18, TPS3125J12, TPS3125G15, TPS3125J18, TPS3125L30
ULTRA-LOW VOLTAGE PROCESSOR SUPERVISORY CIRCUITS
SLVS227 – AUGUST 1999
TYPICAL CHARACTERISTICS
LOW-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
HIGH-LEVEL OUTPUT CURRENT
3.3
3
1.6
TPS3125L30
= 3.3 V
TPS3123J12
V
V
= 1.5 V
DD
MR = Open
DD
MR = Open
1.4
1.2
T
= 85°C
2.75
2.5
A
T
= 25°C
= 0°C
A
T
A
2.25
2
T
= –40°C
1
A
T = –40°C
A
T
= 85°C
A
1.75
1.5
1.25
1
0.8
T
= 25°C
A
0.6
0.4
T
A
= 0°C
0.75
0.5
0.25
0
0.2
0
0
5
10
15
20
25
30
0
–1
–2
–3
–4
–5
I
– Low-Level Output Current – mA
I
– High-Level Output Current – mA
OL
OH
Figure 6
Figure 7
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
NORMALIZED INPUT THRESHOLD VOLTAGE
vs
FREE-AIR TEMPERATURE
3.4
3
1.005
1.004
TPS3123J12
TPS312xJ12
V
= 3.3 V
DD
MR = Open
2.75
2.5
2.25
2
1.003
1.002
T
A
= 85°C
1.75
1.5
1.25
1
T
A
= –40°C
T
= 25°C
A
1.001
1
T
A
= 0°C
0.75
0.5
0.999
0.25
0
0.998
0
–5
–10
–15
–20
–25
–30
–40
–20
0
20
40
60
80
I
– High-Level Output Current – mA
OH
T
A
– Free-Air Temperature – °C
Figure 8
Figure 9
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS3123J12, TPS3123G15, TPS3123J18, TPS3124J12, TPS3124G15
TPS3124J18, TPS3125J12, TPS3125G15, TPS3125J18, TPS3125L30
ULTRA-LOW VOLTAGE PROCESSOR SUPERVISORY CIRCUITS
SLVS227 – AUGUST 1999
TYPICAL CHARACTERISTICS
NORMALIZED INPUT THRESHOLD VOLTAGE
MINIMUM PULSE DURATION
vs
THRESHOLD OVERDRIVE
vs
FREE-AIR TEMPERATURE
1.005
1.004
4.5
4
TPS312xL30
MR = Open
V
IT
T
= 2.64 V
= 25°C
TPS312xL30
A
3.5
3
1.003
1.002
2.5
2
1.001
1
1.5
1
0.5
0
0.999
0.998
–40
–20
0
20
40
60
80
0
50
100
150
200
250
300
T
A
– Free-Air Temperature – °C
V
DD
– Threshold Overdrive – mV
Figure 10
Figure 11
MINIMUM PULSE DURATION
vs
THRESHOLD OVERDRIVE
3.5
3
MR = Open
= 1.08 V
V
IT
T
= 25°C
A
TPS312xJ12
2.5
2
1.5
1
0.5
0
0
50
V
100
150
200
250
300
– Threshold Overdrive – mV
DD
Figure 12
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS3123J12, TPS3123G15, TPS3123J18, TPS3124J12, TPS3124G15
TPS3124J18, TPS3125J12, TPS3125G15, TPS3125J18, TPS3125L30
ULTRA-LOW VOLTAGE PROCESSOR SUPERVISORY CIRCUITS
SLVS227 – AUGUST 1999
MECHANICAL DATA
DBV (R-PDSO-G5)
PLASTIC SMALL-OUTLINE
0,50
M
0,20
0,95
0,30
5
4
0,15 NOM
1,70
1,50
3,00
2,60
1
3
Gage Plane
3,00
2,80
0,25
0°–8°
0,55
0,35
Seating Plane
0,10
1,45
0,95
0,05 MIN
4073253-4/E 05/99
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion.
D. Falls within JEDEC MO-178
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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Copyright 1999, Texas Instruments Incorporated
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