TPS3306-18QDRG4Q1 [TI]

具有电源故障监视功能的汽车类双处理器监控器 | D | 8 | -40 to 125;
TPS3306-18QDRG4Q1
型号: TPS3306-18QDRG4Q1
厂家: TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述:

具有电源故障监视功能的汽车类双处理器监控器 | D | 8 | -40 to 125

监控 光电二极管 电源管理电路 电源电路
文件: 总12页 (文件大小:255K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
ꢀꢁ ꢂ ꢃ ꢃ ꢄ ꢅ ꢆꢇꢈ ꢆꢉ ꢇ ꢊ ꢀꢁ ꢂ ꢃ ꢃ ꢄ ꢅ ꢆꢇ ꢋ ꢆꢉꢇ ꢊ ꢀ ꢁꢂꢃ ꢃ ꢄ ꢅ ꢆꢌ ꢄ ꢆꢉ ꢇ ꢊ ꢀ ꢁꢂꢃ ꢃ ꢄ ꢅ ꢆꢌ ꢈ ꢆꢉ ꢇ ꢊ ꢀ ꢁꢂꢃ ꢃ ꢄꢅ ꢆꢃ ꢃꢆ ꢉꢇ  
ꢍꢎ ꢏꢐ ꢁ ꢑꢒ ꢓꢔꢂ ꢂꢒ ꢑ ꢂꢎ ꢁꢔꢑꢕꢖ ꢂꢒ ꢑꢗ ꢓꢖ ꢑꢓꢎꢖ ꢀꢂ ꢘ ꢖꢀ ꢙ ꢁꢒ ꢘꢔ ꢑ ꢚꢏ ꢖꢐ  
SGLS241A − MARCH 2004 − REVISED JUNE 2006  
D
Qualification in Accordance With  
AEC-Q100  
D
Supply Voltage Range . . . 2.7 V to 6 V  
D
D
D
D
Defined RESET Output From V 1.1 V  
DD  
D
Qualified for Automotive Applications  
SO-8 Package  
D
Customer-Specific Configuration Control  
Can Be Supported Along With  
Major-Change Approval  
Temperature Range . . . −40°C to 125°C  
Applications Include:  
− Multivoltage DSPs and Processors  
− Portable Battery-Powered Equipment  
− Embedded Control Systems  
− Intelligent Instruments  
D
D
Dual Supervisory Circuits With Power Fail  
for DSP and Processor-Based Systems  
Voltage Monitor for Power Fail or  
Low-Battery Warning  
− Automotive Systems  
D
Watchdog Timer With 0.8-s Time-Out  
D PACKAGE  
(TOP VIEW)  
D
Power-On Reset Generator With Integrated  
100-ms Delay Time  
SENSE1  
SENSE2  
PFI  
V
DD  
WDI  
1
2
3
4
8
7
6
5
D
D
Open-Drain Reset and Power-Fail Output  
Supply Current of 15 µA (Typ)  
PFO  
Contact Texas Instruments for details. Q100 qualification data  
GND  
RESET  
available on request.  
description  
The TPS3306 family is a series of supervisory circuits designed for circuit initialization, which require two supply  
voltages, primarily in DSP and processor-based systems.  
The product spectrum of the TPS3306-xx is designed for monitoring two independent supply voltages of  
3.3 V/1.5 V, 3.3 V/1.8 V, 3.3 V/2 V, 3.3 V/2.5 V, or 3.3 V/5 V.  
TYPICAL OPERATING CIRCUIT  
3.3 V  
1.5 V  
AV  
DD  
CV  
DV  
TPS3306−15  
SENSE1  
DD  
DD  
R3 R4  
V
DD  
R1  
1%  
SENSE2  
PFI  
WDI  
PFO  
B_XF  
TMS320  
VC5441  
A_XF  
R2  
1%  
RESET  
GND  
RESET  
V
V
SS  
SSA  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
ꢀꢧ  
Copyright 2006 Texas Instruments Incorporated  
ꢣ ꢧ ꢤ ꢣꢜ ꢝꢱ ꢟꢞ ꢢ ꢪꢪ ꢨꢢ ꢠ ꢢ ꢡ ꢧ ꢣ ꢧ ꢠ ꢤ ꢬ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
ꢀ ꢁ ꢂ ꢃ ꢃꢄ ꢅ ꢆꢇ ꢈꢆꢉ ꢇꢊ ꢀꢁ ꢂ ꢃ ꢃ ꢄ ꢅ ꢆꢇꢋ ꢆꢉ ꢇ ꢊ ꢀꢁ ꢂ ꢃ ꢃꢄ ꢅ ꢆꢌ ꢄ ꢆꢉ ꢇ ꢊ ꢀ ꢁꢂꢃ ꢃ ꢄ ꢅ ꢆꢌ ꢈ ꢆꢉ ꢇ ꢊ ꢀ ꢁꢂꢃ ꢃ ꢄ ꢅ ꢆꢃ ꢃ ꢆꢉ ꢇ  
ꢍ ꢎꢏꢐ ꢁꢑ ꢒꢓ ꢔꢂꢂ ꢒꢑ ꢂ ꢎꢁ ꢔꢑꢕ ꢖ ꢂꢒ ꢑꢗ ꢓꢖ ꢑꢓꢎ ꢖꢀ ꢂ ꢘ ꢖꢀ ꢙ ꢁꢒ ꢘ ꢔꢑ ꢚꢏꢖ ꢐ  
SGLS241A − MARCH 2004 − REVISED JUNE 2006  
description (continued)  
The various supervisory circuits are designed to monitor the nominal supply voltage, as shown in the following  
supply-voltage monitoring table.  
SUPPLY-VOLTAGE MONITORING  
NOMINAL SUPERVISED VOLTAGE  
THRESHOLD VOLTAGE (TYP)  
DEVICE  
SENSE1  
3.3 V  
3.3 V  
3.3 V  
3.3 V  
5 V  
SENSE2  
1.5 V  
1.8 V  
2 V  
SENSE1  
2.93 V  
2.93 V  
2.93 V  
2.93 V  
4.55 V  
SENSE2  
1.4 V  
TPS3306-15  
TPS3306-18  
TPS3306-20  
TPS3306-25  
TPS3306-33  
1.68 V  
1.85 V  
2.25 V  
2.93 V  
2.5 V  
3.3 V  
During power on, RESET is asserted when the supply voltage, V  
becomes higher than 1.1 V. Thereafter, the  
DD,  
supervisory circuits monitor the SENSEn inputs and keep RESET active as long as SENSEn remains below  
the threshold voltage, V .  
IT  
An internal timer delays the return of the RESET output to the inactive state (high) to ensure proper system reset.  
The delay time, t  
= 100 ms, starts after SENSE1 and SENSE2 inputs have risen above V . When the  
d(typ)  
IT  
voltage at SENSE1 or SENSE2 input drops below the V , the output becomes active (low) again.  
IT  
The integrated power-fail (PFI) comparator with separate open-drain (PFO) output can be used for low-battery  
detection, power-fail warning, or for monitoring a power supply other than the main supply.  
The TPS3306-xx devices integrate a watchdog timer that is periodically triggered by a positive or negative  
transition of the watch-dog timer (WDI). When the supervising system fails to retrigger the watchdog circuit  
within the time-out interval, t  
= 0.50 s, RESET becomes active for the time period t . This event also  
t(out)  
d
reinitializes the watchdog timer. Leaving WDI unconnected disables the watchdog.  
The TPS3306-xx devices are available in standard 8-pin SO packages.  
The TPS3306-xxQ family is characterized for operation over a temperature range of −40°C to 125°C.  
AVAILABLE OPTIONS  
PACKAGED DEVICES  
SMALL OUTLINE (D)  
TOP-SIDE  
MARKING  
T
A
Tape and reel  
TPS3306-15QDRQ1  
TPS3306-18QDRQ1  
TPS3306-20QDRQ1  
TPS3306-25QDRQ1  
TPS3306-33QDRQ1  
615Q1  
618Q1  
620Q1  
625Q1  
633Q1  
Tape and reel  
Tape and reel  
Tape and reel  
Tape and reel  
−40_C to 125_C  
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
ꢀꢁ ꢂ ꢃ ꢃ ꢄ ꢅ ꢆꢇꢈ ꢆꢉ ꢇ ꢊ ꢀꢁ ꢂ ꢃ ꢃ ꢄ ꢅ ꢆꢇ ꢋ ꢆꢉꢇ ꢊ ꢀ ꢁꢂꢃ ꢃ ꢄ ꢅ ꢆꢌ ꢄ ꢆꢉ ꢇ ꢊ ꢀ ꢁꢂꢃ ꢃ ꢄ ꢅ ꢆꢌ ꢈ ꢆꢉ ꢇ ꢊ ꢀ ꢁꢂꢃ ꢃ ꢄꢅ ꢆꢃ ꢃꢆ ꢉꢇ  
ꢍꢎ ꢏꢐ ꢁ ꢑꢒ ꢓꢔꢂ ꢂꢒ ꢑ ꢂꢎ ꢁꢔꢑꢕꢖ ꢂꢒ ꢑꢗ ꢓꢖ ꢑꢓꢎꢖ ꢀꢂ ꢘ ꢖꢀ ꢙ ꢁꢒ ꢘꢔ ꢑ ꢚꢏ ꢖꢐ  
SGLS241A − MARCH 2004 − REVISED JUNE 2006  
FUNCTION/TRUTH TABLES  
SENSE1 > V  
SENSE2 > V  
RESET  
IT1  
IT2  
0
0
1
1
0
1
0
1
L
L
L
H
PFI > V  
01  
PFO  
LH  
HL  
TYPICAL DELAY  
0.5 µs  
IT  
10  
0.5 µs  
functional block diagram  
TPS3306  
SENSE 1  
R1  
R2  
V
DD  
+
_
SENSE 2  
RESET  
RESET  
Logic + Timer  
R3  
+
_
R4  
GND  
Reference  
Voltage  
of 1.25 V  
Oscillator  
PFO  
_
+
PFI  
Watchdog  
Logic + Timer  
Transition  
Detection  
WDI  
40 kΩ  
3
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
ꢃꢄ  
ꢈꢆ  
ꢀꢁ  
ꢇꢋ  
ꢀꢁ  
ꢎꢏ  
ꢒꢑ  
ꢔꢑꢕ  
ꢂꢒ  
ꢑꢗ  
SGLS241A − MARCH 2004 − REVISED JUNE 2006  
timing diagram  
SENSEn  
V
(nom)  
V
IT  
1.1 V  
t
t
WDI  
1
t
t(out)  
0
RESET  
1
Undefined  
Behavior  
Undefined  
Behavior  
0
t
t
t
t
d
d
d
Reset Due to  
Power Down  
Reset Due to WDI  
Reset Due to Power Drop Below V  
IT−  
Reset Due to Power Up  
Terminal Functions  
TERMINAL  
I/O  
DESCRIPTION  
NAME  
GND  
NO.  
4
3
6
5
1
2
7
8
I
I
Ground  
PFI  
Power-fail comparator input  
Power-fail comparator output, open drain  
Active-low reset output, open drain  
Sense voltage 1  
PFO  
O
O
I
RESET  
SENSE1  
SENSE2  
WDI  
I
Sense voltage 2  
I
Watchdog timer input  
V
I
Supply voltage  
DD  
detailed description  
watchdog  
In a microprocessor- or DSP-based system, it is not only important to supervise the supply voltage, it is also important  
to ensure correct program execution. The task of a watchdog is to ensure that the program is not stalled in an indefinite  
loop. The microprocessor, microcontroller, or DSP has to typically toggle the watchdog input (WDI) within 0.8 s to  
avoid a time-out occurring. Either a low-to-high or a high-to-low transition resets the internal watchdog timer. If the  
input is unconnected or tied with a high-impedance driver, the watchdog is disabled and is retriggered internally.  
4
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
ꢀꢁ ꢂ ꢃ ꢃ ꢄ ꢅ ꢆꢇꢈ ꢆꢉ ꢇ ꢊ ꢀꢁ ꢂ ꢃ ꢃ ꢄ ꢅ ꢆꢇ ꢋ ꢆꢉꢇ ꢊ ꢀ ꢁꢂꢃ ꢃ ꢄ ꢅ ꢆꢌ ꢄ ꢆꢉ ꢇ ꢊ ꢀ ꢁꢂꢃ ꢃ ꢄ ꢅ ꢆꢌ ꢈ ꢆꢉ ꢇ ꢊ ꢀ ꢁꢂꢃ ꢃ ꢄꢅ ꢆꢃ ꢃꢆ ꢉꢇ  
ꢍꢎ ꢏꢐ ꢁ ꢑꢒ ꢓꢔꢂ ꢂꢒ ꢑ ꢂꢎ ꢁꢔꢑꢕꢖ ꢂꢒ ꢑꢗ ꢓꢖ ꢑꢓꢎꢖ ꢀꢂ ꢘ ꢖꢀ ꢙ ꢁꢒ ꢘꢔ ꢑ ꢚꢏ ꢖꢐ  
SGLS241A − MARCH 2004 − REVISED JUNE 2006  
saving current while using the watchdog  
WDI is internally driven low during the first 7/8 of the watchdog time-out period, then momentarily pulses high,  
resetting the watchdog counter. For minimum watchdog input current (minimum overall power consumption), leave  
WDI low for the majority of the watchdog time-out period, pulsing it low-high-low once within 7/8 of the watchdog  
time-out period to reset the watchdog timer. If, instead, WDI is externally driven high for the majority of the time-out  
period, a current of 5 V/40 kΩ ≈ 125 µA can flow into WDI.  
V
DD  
V
IT  
t
t
t
WDI  
t
(tout)  
RESET  
t
t
d
d
Figure 1. Watchdog Timing  
power-fail comparator (PFI and PFO)  
An additional comparator is provided to monitor voltages other than the nominal supply voltage. The power-fail-input  
(PFI) is compared with an internal voltage reference of 1.25 V. If the input voltage falls below the power-fail threshold  
(V ) of 1.25 V (typ), the power-fail output (PFO) goes low. If PFO goes above 1.25 V plus about 10−mV hysteresis,  
PFI  
the output returns to high. By connecting two external resistors, it is possible to supervise any voltages above 1.25 V.  
The sum of both resistors should be approximately 1 M, to minimize power consumption and also to ensure that the  
current in the PFI pin can be neglected compared with the current through the resistor network. The tolerance of the  
external resistors should be not more than 1% to ensure minimal variation of sensed voltage. If the power-fail  
comparator is unused, connect PFI to ground and leave PFO unconnected.  
V
(SENSE)  
R
+ R  
2
1
V
= 1.25 V ×  
PFI,trip  
R
2
R1  
1%  
V
CC  
PFI  
PFO  
TPS3306  
GND  
R2  
1%  
5
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
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ꢍ ꢎꢏꢐ ꢁꢑ ꢒꢓ ꢔꢂꢂ ꢒꢑ ꢂ ꢎꢁ ꢔꢑꢕ ꢖ ꢂꢒ ꢑꢗ ꢓꢖ ꢑꢓꢎ ꢖꢀ ꢂ ꢘ ꢖꢀ ꢙ ꢁꢒ ꢘ ꢔꢑ ꢚꢏꢖ ꢐ  
SGLS241A − MARCH 2004 − REVISED JUNE 2006  
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)  
Supply voltage (see Note1): V  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V  
DD  
All other pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 7 V  
Maximum low output current, I  
Maximum high output current, I  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 mA  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −5 mA  
OL  
OH  
Input clamp current, I (V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA  
IK  
OK  
I
I
DD  
Output clamp current, I  
(V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA  
O O DD  
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table  
Operating free-air temperature range, T  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 125°C  
A
Storage temperature range, T  
Soldering temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260_C  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C  
stg  
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and  
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not  
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.  
NOTE 1: All voltage values are with respect to GND. For reliable operation, the device must not be operated at 7 V for more than t = 1000 h  
continuously.  
DISSIPATION RATING TABLE  
T
25°C  
DERATING FACTOR  
T
= 70°C  
T = 85°C  
A
A
A
PACKAGE  
POWER RATING  
ABOVE T = 25°C  
POWER RATING POWER RATING  
A
D
725 mW  
5.8 mW/°C  
464 mW 377 mW  
recommended operating conditions at specified temperature range  
MIN  
2.7  
0
MAX  
6
UNIT  
V
Supply voltage, V  
DD  
Input voltage at WDI and PFI, V  
V
DD  
+ 0.3  
V
I
Input voltage at SENSE1 and SENSE2, V  
0
(V  
DD  
+ 0.3)V /1.25 V  
IT  
V
I
High-level input voltage at WDI, V  
IH  
0.7 × V  
V
DD  
Low-level input voltage at WDI, V  
IL  
0.3 × V  
DD  
V
Operating free-air temperature range, T  
−40  
125  
°C  
A
6
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
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ꢍꢎ ꢏꢐ ꢁ ꢑꢒ ꢓꢔꢂ ꢂꢒ ꢑ ꢂꢎ ꢁꢔꢑꢕꢖ ꢂꢒ ꢑꢗ ꢓꢖ ꢑꢓꢎꢖ ꢀꢂ ꢘ ꢖꢀ ꢙ ꢁꢒ ꢘꢔ ꢑ ꢚꢏ ꢖꢐ  
SGLS241A − MARCH 2004 − REVISED JUNE 2006  
electrical characteristics over recommended operating free-air temperature range (unless  
otherwise noted)  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
V
V
= 2.7 V to 6 V, I  
= 20 µA  
0.2  
DD  
OL  
RESET,  
PFO  
= 3.3 V,  
I
= 2 mA  
0.4  
0.4  
V
OL  
Low-level output voltage  
V
V
DD  
OL  
V
V
= 6 V,  
I
I
= 3 mA  
DD  
OL  
Power-up reset voltage (see Note 2)  
1.1 V,  
= 20 µA  
0.4  
1.44  
1.74  
1.91  
2.34  
3.04  
4.68  
1.3  
DD  
OL  
1.35  
1.62  
1.79  
2.18  
2.84  
4.44  
1.2  
1.4  
1.68  
1.85  
2.25  
2.93  
4.55  
1.25  
10  
VSENSE1,  
VSENSE2  
Negative-going input threshold voltage  
(see Note 3)  
V
DD  
= 2.7 V to 6 V,  
V
IT  
V
T
A
= −40°C to 125°C  
PFI  
PFI  
V
IT  
V
IT  
V
IT  
V
IT  
V
IT  
V
IT  
V
IT  
= 1.25 V  
= 1.4 V  
15  
= 1.68 V  
= 1.86 V  
= 2.25 V  
= 2.93 V  
= 4.55 V  
15  
20  
V
Hysteresis  
mV  
hys  
VSENSEn  
20  
30  
40  
WDI = V  
DD  
= 6 V,  
I
I
Average high-level input current  
Average low-level input current  
WDI  
WDI  
100  
−15  
150  
−20  
µA  
µA  
H(AV)  
Time average (dc = 88%)  
WDI = 0 V,  
Time average (dc = 12%)  
V
= 6 V,  
DD  
L(AV)  
WDI  
WDI = V  
V
= 6 V  
120  
5
170  
10  
DD  
SENSE1  
SENSE2  
WDI  
= V  
= 6 V  
= 6 V  
I
H
High-level input current  
µA  
SENSE1  
SENSE2  
DD  
V
= V  
6
10  
DD  
I
I
I
Low-level input current  
Input current  
WDI = 0 V,  
V
= 6 V  
−120 −170  
30  
µA  
nA  
µA  
pF  
L
DD  
PFI  
V
DD  
= 6 V, 0 V V V  
−30  
I
I
DD  
Supply current  
15  
10  
40  
DD  
C
Input capacitance  
V = 0 V to V  
I DD  
i
NOTES: 2. The lowest supply voltage at which RESET becomes active. t , V  
15 µs/V.  
3. To ensure best stability of the threshold voltage, a bypass capacitor (ceramic 0.1 µF) should be placed close to the supply terminals.  
r
DD  
timing requirements at V  
= 2.7 V to 6 V, R = 1 M, C = 50 pF, T = 25°C  
DD  
L
L
A
PARAMETER  
TEST CONDITIONS  
MIN  
6
MAX  
UNIT  
µs  
SENSEn  
V
V
= V − 0.2 V,  
IT  
V
V
= V + 0.2 V  
IT  
SENSEnL  
= 0.7 × V  
SENSEnH  
= 0.3 × V  
DD  
t
w
Pulse width  
WDI  
,
100  
ns  
IH  
DD  
IL  
7
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
ꢀ ꢁ ꢂ ꢃ ꢃꢄ ꢅ ꢆꢇ ꢈꢆꢉ ꢇꢊ ꢀꢁ ꢂ ꢃ ꢃ ꢄ ꢅ ꢆꢇꢋ ꢆꢉ ꢇ ꢊ ꢀꢁ ꢂ ꢃ ꢃꢄ ꢅ ꢆꢌ ꢄ ꢆꢉ ꢇ ꢊ ꢀ ꢁꢂꢃ ꢃ ꢄ ꢅ ꢆꢌ ꢈ ꢆꢉ ꢇ ꢊ ꢀ ꢁꢂꢃ ꢃ ꢄ ꢅ ꢆꢃ ꢃ ꢆꢉ ꢇ  
ꢍ ꢎꢏꢐ ꢁꢑ ꢒꢓ ꢔꢂꢂ ꢒꢑ ꢂ ꢎꢁ ꢔꢑꢕ ꢖ ꢂꢒ ꢑꢗ ꢓꢖ ꢑꢓꢎ ꢖꢀ ꢂ ꢘ ꢖꢀ ꢙ ꢁꢒ ꢘ ꢔꢑ ꢚꢏꢖ ꢐ  
SGLS241A − MARCH 2004 − REVISED JUNE 2006  
switching characteristics at V  
= 2.7 V to 6 V, R = 1 M, C = 50 pF, T = 25°C  
DD  
L
L
A
FROM  
(INPUT)  
TO  
(OUTPUT)  
PARAMETER  
TEST CONDITIONS  
MIN  
0.5  
70  
TYP  
0.8  
100  
1
MAX  
1.2  
140  
5
UNIT  
s
V
V + 0.2 V,  
IT  
I(SENSEn)  
t
t
t
t
t
Watchdog time-out  
Delay time  
t(out)  
See timing diagram  
V
V + 0.2 V,  
I(SENSEn)  
IT  
ms  
µs  
d
See timing diagram  
Propagation (delay) time,  
high- to low-level output  
V
IH  
V
IL  
= V + 0.2 V,  
IT  
SENSEn  
PFI  
RESET  
PFO  
PHL  
PHL  
PLH  
= V − 0.2 V  
IT  
Propagation (delay) time,  
high- to low-level output  
0.5  
1
µs  
Propagation (delay) time,  
low- to high-level output  
TYPICAL CHARACTERISTICS  
NORMALIZED SENSE THRESHOLD VOLTAGE  
vs  
SUPPLY CURRENT  
vs  
SUPPLY VOLTAGE  
FREE-AIR TEMPERATURE AT V  
DD  
1.005  
18  
16  
14  
12  
10  
8
V
DD  
= 6 V  
1.004  
1.003  
1.002  
1.001  
1
TPS3306-33  
6
4
2
0.999  
0.998  
0.997  
0
−2  
−4  
SENSEn = V  
DD  
A
−6  
T = 25°C  
0.996  
0.995  
−8  
−10  
−40  
−15  
10  
35  
60  
85  
−0.5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7  
T
A
− Free-Air Temperature − °C  
V
DD  
− Supply Voltage − V  
Figure 2  
Figure 3  
8
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
ꢀꢁ ꢂ ꢃ ꢃ ꢄ ꢅ ꢆꢇꢈ ꢆꢉ ꢇ ꢊ ꢀꢁ ꢂ ꢃ ꢃ ꢄ ꢅ ꢆꢇ ꢋ ꢆꢉꢇ ꢊ ꢀ ꢁꢂꢃ ꢃ ꢄ ꢅ ꢆꢌ ꢄ ꢆꢉ ꢇ ꢊ ꢀ ꢁꢂꢃ ꢃ ꢄ ꢅ ꢆꢌ ꢈ ꢆꢉ ꢇ ꢊ ꢀ ꢁꢂꢃ ꢃ ꢄꢅ ꢆꢃ ꢃꢆ ꢉꢇ  
ꢍꢎ ꢏꢐ ꢁ ꢑꢒ ꢓꢔꢂ ꢂꢒ ꢑ ꢂꢎ ꢁꢔꢑꢕꢖ ꢂꢒ ꢑꢗ ꢓꢖ ꢑꢓꢎꢖ ꢀꢂ ꢘ ꢖꢀ ꢙ ꢁꢒ ꢘꢔ ꢑ ꢚꢏ ꢖꢐ  
SGLS241A − MARCH 2004 − REVISED JUNE 2006  
TYPICAL CHARACTERISTICS  
LOW-LEVEL OUTPUT VOLTAGE  
vs  
LOW-LEVEL OUTPUT CURRENT  
LOW-LEVEL OUTPUT VOLTAGE  
vs  
LOW-LEVEL OUTPUT CURRENT  
2.8  
2.4  
2
6.5  
6
V
DD  
= 2.7 V  
V
DD  
= 6 V  
5.5  
5
4.5  
4
1.6  
1.2  
0.8  
0.4  
0
3.5  
3
85°C  
85°C  
2.5  
2
−40°C  
1.5  
1
−40°C  
0.5  
0
0
1
2
3
4
5
6
7
8
9
10 11 12 13  
0
5
10 15 20 25 30 35 40 45 50 55 60  
I
− Low-Level Output Current − mA  
OL  
I
− Low-Level Output Current − mA  
OL  
Figure 4  
Figure 5  
MINIMUM PULSE DURATION AT SENSE  
vs  
THRESHOLD OVERDRIVE  
10  
9
V
DD  
= 6 V  
8
7
6
5
4
3
2
1
0
0
100 200 300 400 500 600 700 800 900 1000  
SENSE − Threshold Overdrive − mV  
Figure 6  
9
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
PACKAGE OPTION ADDENDUM  
www.ti.com  
29-May-2007  
PACKAGING INFORMATION  
Orderable Device  
TPS3306-15QDRQ1  
TPS3306-18QDRQ1  
TPS3306-20QDRQ1  
TPS3306-25QDRQ1  
TPS3306-33QDRQ1  
Status (1)  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
Package Package  
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)  
Qty  
Type  
Drawing  
SOIC  
D
8
8
8
8
8
2500  
2500  
2500  
2500  
2500  
Pb-Free  
(RoHS)  
CU NIPDAU Level-2-260C-1 YEAR  
CU NIPDAU Level-2-260C-1 YEAR  
CU NIPDAU Level-2-260C-1 YEAR  
CU NIPDAU Level-2-260C-1 YEAR  
CU NIPDAU Level-2-260C-1 YEAR  
SOIC  
SOIC  
SOIC  
SOIC  
D
D
D
D
Pb-Free  
(RoHS)  
Pb-Free  
(RoHS)  
Pb-Free  
(RoHS)  
Pb-Free  
(RoHS)  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in  
a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2)  
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check  
http://www.ti.com/productcontent for the latest availability information and additional product content details.  
TBD: The Pb-Free/Green conversion plan has not been defined.  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements  
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered  
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and  
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS  
compatible) as defined above.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame  
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)  
(3)  
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder  
temperature.  
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Addendum-Page 1  
IMPORTANT NOTICE  
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