TPS3306-25DR [TI]
DUAL PROCESSOR SUPERVISORY CIRCUITS WITH POWER-FAIL;
| 型号： | TPS3306-25DR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | DUAL PROCESSOR SUPERVISORY CIRCUITS WITH POWER-FAIL 光电二极管 |
| 文件： | 总18页 (文件大小：873K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS3306-15
TPS3306-18, TPS3306-20
TPS3306-25, TPS3306-33
www.ti.com
SLVS290C–APRIL 2000–REVISED DECEMBER 2006
DUAL PROCESSOR SUPERVISORY CIRCUITS WITH POWER-FAIL
FEATURES
APPLICATIONS
•
•
•
•
•
Multivoltage DSPs and Processors
•
Dual Supervisory Circuits With Power-Fail for
DSP and Processor-Based Systems
Portable Battery-Powered Equipment
Embedded Control Systems
Intelligent Instruments
•
Voltage Monitor for Power-Fail or Low-Battery
Warning
Automotive Systems
•
•
Watchdog Timer With 0.8 Second Time-Out
Power-On Reset Generator With Integrated
100 ms Delay Time
D OR DGK PACKAGE
(TOP VIEW)
•
•
•
•
•
•
Open-Drain Reset and Power-Fail Output
Supply Current of 15 µA (Typ.)
SENSE1
SENSE2
PFI
1
2
3
4
8
7
6
5
VDD
WDI
Supply Voltage Range: 7 V to 6 V
Defined RESET Output From VDD≥ 1.1 V
MSOP-8 and SO-8 Packages
TPS3306
PFO
RESET
GND
Temperature Range: –40°C to +85°C
DESCRIPTION
The TPS3306 family is a series of supervisory circuits designed for circuit initialization which require two supply
voltages, primarily in DSP and processor-based systems.
The product spectrum of the TPS3306-xx is designed for monitoring two independent supply voltages of
3.3 V/1.5 V, 3.3 V/1.8 V, 3.3 V/2 V, 3.3 V/2.5 V, or 3.3 V/5 V.
TYPICAL OPERATING CIRCUIT
3.3 V
1.5 V
AV
DD
CV
TPS3306–15
SENSE1
DD
DD
R3 R4
V
DD
DV
R1
1%
SENSE2
PFI
WDI
PFO
B_XF
TMS320
VC5441
A_XF
R2
1%
RESET
GND
RESET
V
V
SS
SSA
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Copyright © 2000–2006, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TPS3306-15
TPS3306-18, TPS3306-20
TPS3306-25, TPS3306-33
www.ti.com
SLVS290C–APRIL 2000–REVISED DECEMBER 2006
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
AVAILABLE OPTIONS
Table 1. SUPPLY VOLTAGE MONITORING
NOMINAL SUPERVISED VOLTAGE
THRESHOLD VOLTAGE (TYP)
DEVICE
SENSE1
3.3 V
3.3 V
3.3 V
3.3 V
5 V
SENSE2
1.5 V
1.8 V
2 V
SENSE1
SENSE2
1.4 V
TPS3306-15
TPS3306-18
TPS3306-20
TPS3306-25
TPS3306-33
2.93 V
2.93 V
2.93 V
2.93 V
4.55 V
1.68 V
1.85 V
2.25 V
2.93 V
2.5 V
3.3 V
For the most current package and ordering information, see the Package Option Addendum at the end of this
document, or see the TI website at www.ti.com.
DESCRIPTION (CONTINUED)
The various supervisory circuits are designed to monitor the nominal supply voltage, as shown in the Supply
Voltage Monitoring table.
During power-on, RESET is asserted when the supply voltage VDD becomes higher than 1.1 V. Thereafter, the
supervisory circuits monitor the SENSEn inputs and keep RESET active as long as SENSEn remains below the
threshold voltage VIT.
An internal timer delays the return of the RESET output to the inactive state (high) to ensure proper system
reset. The delay time, td(typ) = 100 ms, starts after SENSE1 and SENSE2 inputs have risen above the threshold
voltage VIT. When the voltage at SENSE1 or SENSE2 input drops below the threshold voltage VIT, the output
becomes active (low) again.
The integrated power-fail (PFI) comparator with separate open-drain (PFO) output can be used for low-battery
detection, power-fail warning, or for monitoring a power supply other than the main supply.
The TPS3306-xx devices integrate a watchdog timer that is periodically triggered by a positive or negative
transition of WDI. When the supervising system fails to retrigger the watchdog circuit within the time-out interval,
tt(out) = 0.50 s, RESET becomes active for the time period td. This event also reinitializes the watchdog timer.
Leaving WDI unconnected disables the watchdog.
The TPS3306-xx devices are available in either 8-pin MSOP or standard 8-pin SO packages, and are
characterized for operation over a temperature range of –40°C to +85°C.
2
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TPS3306-15
TPS3306-18, TPS3306-20
TPS3306-25, TPS3306-33
www.ti.com
SLVS290C–APRIL 2000–REVISED DECEMBER 2006
FUNCTION/TRUTH TABLES
SENSE1 > VIT1
SENSE2 > VIT2
RESET
0
0
1
1
0
1
0
1
L
L
L
H
FUNCTION/TRUTH TABLES
PFI > VIT
PFO
L
0
1
H
FUNCTIONAL BLOCK DIAGRAM
TPS3306
SENSE1
SENSE2
R1
R2
VDD
+
_
RESET
RESET
Logic + Timer
R3
+
_
R4
GND
Reference
Voltage
of 1.25 V
Oscillator
PFO
+
_
PFI
Watchdog
Logic + Timer
Transition
Detection
WDI
40 kW
3
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TPS3306-15
TPS3306-18, TPS3306-20
TPS3306-25, TPS3306-33
www.ti.com
SLVS290C–APRIL 2000–REVISED DECEMBER 2006
TIMING DIAGRAM
SENSEn
V
(nom)
V
IT
1.1 V
t
WDI
1
t
t(out)
0
t
t
RESET
1
Undefined
Behavior
Undefined
Behavior
0
t
d
t
d
t
d
RESET Because of
Power-Down
RESET Because of WDI
RESET Because of a Power Drop Below V
IT–
RESET Because of Power-Up
Table 4. Terminal Functions
TERMINAL
NAME
NO.
I/O
DESCRIPTION
GND
4
3
6
5
1
2
7
8
I
I
Ground
PFI
Power-fail comparator input
Power-fail comparator output, open-drain
Active-low reset output, open-drain
Sense voltage input 1
Sense voltage input 2
Watchdog timer input
PFO
O
O
I
RESET
SENSE1
SENSE2
WDI
I
I
VDD
I
Supply voltage
DETAILED DESCRIPTION
Watchdog
In a microprocessor- or DSP-based system, it is not only important to supervise the supply voltage, it is also
important to ensure correct program execution. The task of a watchdog is to ensure that the program is not
stalled in an indefinite loop. The microprocessor, microcontroller, or DSP typically has to toggle the watchdog
input within 0.8 s to avoid a time-out occurring. Either a low-to-high or a high-to-low transition resets the internal
watchdog timer. If the input is unconnected or tied with a high impedance driver, the watchdog is disabled and
will be retriggered internally.
4
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TPS3306-15
TPS3306-18, TPS3306-20
TPS3306-25, TPS3306-33
www.ti.com
SLVS290C–APRIL 2000–REVISED DECEMBER 2006
DETAILED DESCRIPTION (continued)
Saving Current While Using the Watchdog
The watchdog input is internally driven low during the first 7/8 of the watchdog time-out period, then momentarily
pulses high, resetting the watchdog counter. For minimum watchdog input current (minimum overall power
consumption), leave WDI low for the majority of the watchdog time-out period, pulsing it low-high-low once within
7/8 of the watchdog time-out period to reset the watchdog timer. If instead WDI is externally driven high for the
majority of the time-out period, a current of 5 V/40 kΩ = 125 µA can flow into WDI.
V
DD
V
IT
t
t
t
WDI
t
(tout)
RESET
t
d
t
d
Figure 1. Watchdog Timing
Power-Fail Comparator (PFI and PFO)
An additional comparator is provided to monitor voltages other than the nominal supply voltage. The
power-fail-input (PFI) will be compared with an internal voltage reference of 1.25 V. If the input voltage falls
below the power-fail threshold (VPFI) of typ. 1.25 V, the power-fail output (PFO) goes low. If it goes above 1.25 V
plus about 10 mV hysteresis, the output returns to high. By connecting two external resistors, it is possible to
supervise any voltages above 1.25 V. The sum of both resistors should be about 1 MΩ, to minimize power
consumption and also to assure that the current in the PFI pin can be neglected compared with the current
through the resistor network. The tolerance of the external resistors should be not more than 1% to ensure
minimal variation of sensed voltage. If the power-fail comparator is unused, connect PFI to ground and leave
PFO unconnected.
V
(SENSE)
R1
1%
V
CC
PFI
PFO
TPS3306
GND
R2
1%
R + R
1
2
V
= 1.25 V×
PFI,trip
R
2
5
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TPS3306-15
TPS3306-18, TPS3306-20
TPS3306-25, TPS3306-33
www.ti.com
SLVS290C–APRIL 2000–REVISED DECEMBER 2006
ABSOLUTE MAXIMUM RATINGS
Over operating free-air temperature range (unless otherwise noted).(1)
UNIT
7 V
(2)
Supply voltage, VDD (see
)
PFI pin
–0.3 V to VDD + 0.3 V
–0.3 V to 7 V
5 mA
(2)
All other pins (see
)
Maximum low output current, IOL
Maximum high output current, IOH
Input clamp current, IIK (VI < 0 or VI > VDD
– 5 mA
)
±20 mA
Output clamp current, IOK (VO < 0 or VO > VDD
Continuous total power dissipation
Operating free-air temperature range, TA
Storage temperature range, Tstg
Soldering temperature
)
±20 mA
See Dissipation Rating Table
–40°C to +85°C
–65°C to +150°C
260°C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to GND. For reliable operation, the device must not be operated at 7 V for more than t = 1000 h
continuously.
DISSIPATION RATING TABLE
T
A ≤ +25°C
DERATING FACTOR
ABOVE TA = +25°C
TA = +70°C
POWER RATING
TA = +85°C
POWER RATING
PACKAGE
POWER RATING
DGK
D
424 mW
3.4 mW/°C
5.8 mW/°C
271 mW
464 mW
220 mW
377 mW
725 mW
RECOMMENDED OPERATING CONDITIONS
At specified temperature range.
MIN
MAX
UNIT
Supply voltage, VDD
2.7
6
V
V
Input voltage at WDI and PFI, VI
Input voltage at SENSE1 and SENSE2, VI
High-level input voltage at WDI, VIH
Low-level input voltage at WDI, VIL
Operating free-air temperature range, TA
0
0
VDD + 0.3
(VDD + 0.3)VIT/1.25 V
V
0.7 x VDD
V
0.3 × VDD
+85
V
–40
°C
6
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TPS3306-15
TPS3306-18, TPS3306-20
TPS3306-25, TPS3306-33
www.ti.com
SLVS290C–APRIL 2000–REVISED DECEMBER 2006
ELECTRICAL CHARACTERISTICS
Over recommended operating free-air temperature range (unless otherwise noted).
PARAMETER
TEST CONDITIONS
VDD = 2.7 V to 6 V, IOL = 20 µA
VDD = 3.3 V, IOL= 2 mA
MIN
TYP
MAX
0.2
UNIT
V
RESET,
PFO
VOL
Low-level output voltage
0.4
0.4
VDD = 6 V, IOL = 3 mA
(1)
Power-up reset voltage (see
)
VDD ≥ 1.1 V, IOL = 20 µA
0.4
V
1.37
1.40
1.43
1.72
1.89
2.30
3
1.64
1.81
2.20
2.86
4.46
1.22
1.37
1.64
1.81
2.20
2.86
4.46
1.22
1.68
1.85
2.25
2.93
4.55
1.25
1.40
1.68
1.85
2.25
2.93
4.55
1.25
10
VSENSE1
VSENSE2
,
VDD = 2.7 V to 6 V
TA = 0°C to +85°C
V
4.64
1.28
1.44
1.73
1.90
2.32
3.02
4.67
1.29
PFI
Negative-going input threshold voltage
VIT
(2)
(see
)
VSENSE1
VSENSE2
,
VDD = 2.7 V to 6 V
TA = –40°C to +85°C
V
PFI
PFI
VIT = 1.25 V
VIT = 1.40 V
VIT = 1.68 V
VIT = 1.86 V
VIT = 2.25 V
VIT = 2.93 V
VIT = 4.55 V
15
15
Vhys
Hysteresis
20
mV
VSENSEn
20
30
40
WDI = VDD = 6 V, Time average
(dc = 88%)
IH(AV) Average high-level input current
100
–15
150
–20
WDI
WDI
µA
µA
WDI = 0 V, VDD = 6 V, Time
average (dc = 12%)
IL(AV)
Average low-level input current
High-level input current
WDI = VDD = 6 V
120
5
170
8
IH
SENSE1
SENSE2
WDI
VSENSE1 = VDD = 6 V
VSENSE2 = VDD = 6 V
WDI = 0 V, VDD, = 6 V
VDD = 6 V, 0 V ≤ VI ≤ VDD
6
9
IL
Low-level input current
Input current
–120
–170
25
µA
nA
µA
pF
II
PFI
–25
IDD
Ci
Supply current
15
10
40
Input capacitance
VI = 0 V to VDD
(1) The lowest supply voltage at which RESET becomes active. tr, VDD ≥ 15 µs/V.
(2) To ensure best stability of the threshold voltage, a bypass capacitor (ceramic 0.1 µF) should be placed close to the supply terminals.
7
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TPS3306-15
TPS3306-18, TPS3306-20
TPS3306-25, TPS3306-33
www.ti.com
SLVS290C–APRIL 2000–REVISED DECEMBER 2006
TIMING REQUIREMENTS
at VDD = 2.7 V to 6 V, RL= 1 MΩ, CL= 50 pF, TA= 25°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SENSEn
WDI
VSENSEnL = VIT– 0.2 V, VSENSEnH = VIT + 0.2 V
VIH = 0.7 × VDD, VIL= 0.3 × VDD
6
µs
tw
Pulse width
100
ns
SWITCHING CHARACTERISTICS
at VDD = 2.7 V to 6 V, RL= 1 MΩ, CL = 50 pF, TA= 25°C
PARAMETER
TEST CONDITIONS
I(SENSEn) ≥ VIT + 0.2 V,
See Timing Diagram
I(SENSEn) ≥ VIT + 0.2 V,
MIN
TYP
0.8
MAX
1.2
UNIT
V
tt(out)
td
Watchdog time-out
Delay time
0.5
s
V
70
100
1
140
5
ms
See Timing Diagram
Propagation (delay) time,
high-to-low level output
tPHL
tPHL
tPLH
SENSEn to RESET
PFI to PFO
VIH = VIT + 0.2 V, VIL = VIT– 0.2 V
µs
Propagation (delay) time,
high-to-low level output
0.5
1
µs
Propagation (delay) time,
low-to-high level output
TYPICAL CHARACTERISTICS
NORMALIZED SENSE THRESHOLD VOLTAGE
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
vs
FREE-AIR TEMPERATURE AT VDD
18
16
14
12
10
8
1.005
1.004
1.003
1.002
1.001
1
V
DD
= 6 V
TPS3306−33
6
4
2
0.999
0.998
0.997
0
−2
−4
SENSEn = V
DD
−6
T = 25°C
A
0.996
0.995
−8
−10
−0.5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7
−40
−15
10
35
60
85
V − Supply Voltage − V
DD
T
A
− Free-Air Temperature − °C
Figure 2.
Figure 3.
8
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TPS3306-15
TPS3306-18, TPS3306-20
TPS3306-25, TPS3306-33
www.ti.com
SLVS290C–APRIL 2000–REVISED DECEMBER 2006
TYPICAL CHARACTERISTICS (continued)
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
2.8
2.4
2
6.5
6
V
DD
= 2.7 V
V
DD
= 6 V
5.5
5
4.5
4
1.6
1.2
0.8
0.4
3.5
3
85°C
85°C
2.5
2
−40°C
1.5
1
−40°C
0.5
0
0
0
0
5
10 15 20 25 30 35 40 45 50 55 60
1
2
3
4
5
6
7
8
9 10 11 12 13
I
− Low-Level Output Current − mA
I
− Low-Level Output Current − mA
OL
OL
Figure 4.
Figure 5.
MINIMUM PULSE DURATION AT SENSE
vs
THRESHOLD OVERDRIVE
10
9
V
= 6 V
DD
8
7
6
5
4
3
2
1
0
0
100 200 300 400 500 600 700 800 900 1000
SENSE − Threshold Overdrive − mV
Figure 6.
9
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PACKAGE OPTION ADDENDUM
www.ti.com
17-Mar-2017
PACKAGING INFORMATION
Orderable Device
TPS3306-15D
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
ACTIVE
SOIC
SOIC
D
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
30615
30615
AIC
TPS3306-15DG4
TPS3306-15DGK
TPS3306-15DGKG4
TPS3306-15DGKR
TPS3306-15DGKRG4
TPS3306-15DR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
D
DGK
DGK
DGK
DGK
D
75
80
Green (RoHS
& no Sb/Br)
VSSOP
VSSOP
VSSOP
VSSOP
SOIC
Green (RoHS
& no Sb/Br)
80
Green (RoHS
& no Sb/Br)
AIC
2500
2500
2500
2500
75
Green (RoHS
& no Sb/Br)
AIC
Green (RoHS
& no Sb/Br)
AIC
Green (RoHS
& no Sb/Br)
30615
30615
30618
30618
AID
TPS3306-15DRG4
TPS3306-18D
SOIC
D
Green (RoHS
& no Sb/Br)
SOIC
D
Green (RoHS
& no Sb/Br)
TPS3306-18DG4
TPS3306-18DGK
TPS3306-18DGKG4
TPS3306-18DGKR
TPS3306-18DGKRG4
TPS3306-18DR
SOIC
D
75
Green (RoHS
& no Sb/Br)
VSSOP
VSSOP
VSSOP
VSSOP
SOIC
DGK
DGK
DGK
DGK
D
80
Green (RoHS
& no Sb/Br)
80
Green (RoHS
& no Sb/Br)
AID
2500
2500
2500
2500
75
Green (RoHS
& no Sb/Br)
AID
Green (RoHS
& no Sb/Br)
AID
Green (RoHS
& no Sb/Br)
30618
30618
30620
TPS3306-18DRG4
TPS3306-20D
SOIC
D
Green (RoHS
& no Sb/Br)
SOIC
D
Green (RoHS
& no Sb/Br)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
17-Mar-2017
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
TPS3306-25D
TPS3306-25DG4
TPS3306-25DGK
TPS3306-25DGKG4
TPS3306-25DGKR
TPS3306-25DGKRG4
TPS3306-25DR
ACTIVE
SOIC
SOIC
D
8
8
8
8
8
8
8
8
8
8
8
8
8
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
30625
30625
AIF
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
D
75
80
Green (RoHS
& no Sb/Br)
VSSOP
VSSOP
VSSOP
VSSOP
SOIC
DGK
DGK
DGK
DGK
D
Green (RoHS
& no Sb/Br)
80
Green (RoHS
& no Sb/Br)
AIF
2500
2500
2500
75
Green (RoHS
& no Sb/Br)
AIF
Green (RoHS
& no Sb/Br)
AIF
Green (RoHS
& no Sb/Br)
30625
30633
30633
AIG
TPS3306-33D
SOIC
D
Green (RoHS
& no Sb/Br)
TPS3306-33DG4
TPS3306-33DGK
TPS3306-33DGKG4
TPS3306-33DGKR
TPS3306-33DGKRG4
TPS3306-33DR
SOIC
D
75
Green (RoHS
& no Sb/Br)
VSSOP
VSSOP
VSSOP
VSSOP
SOIC
DGK
DGK
DGK
DGK
D
80
Green (RoHS
& no Sb/Br)
80
Green (RoHS
& no Sb/Br)
AIG
2500
2500
2500
Green (RoHS
& no Sb/Br)
AIG
Green (RoHS
& no Sb/Br)
AIG
Green (RoHS
& no Sb/Br)
30633
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
17-Mar-2017
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TPS3306 :
Automotive: TPS3306-Q1
•
NOTE: Qualified Version Definitions:
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Aug-2017
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS3306-15DGKR
TPS3306-15DR
VSSOP
SOIC
DGK
D
8
8
8
8
8
8
8
8
2500
2500
2500
2500
2500
2500
2500
2500
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
5.3
6.4
5.3
6.4
5.3
6.4
5.3
6.4
3.4
5.2
3.4
5.2
3.4
5.2
3.4
5.2
1.4
2.1
1.4
2.1
1.4
2.1
1.4
2.1
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
TPS3306-18DGKR
TPS3306-18DR
VSSOP
SOIC
DGK
D
TPS3306-25DGKR
TPS3306-25DR
VSSOP
SOIC
DGK
D
TPS3306-33DGKR
TPS3306-33DR
VSSOP
SOIC
DGK
D
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Aug-2017
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS3306-15DGKR
TPS3306-15DR
VSSOP
SOIC
DGK
D
8
8
8
8
8
8
8
8
2500
2500
2500
2500
2500
2500
2500
2500
358.0
367.0
358.0
367.0
358.0
367.0
358.0
367.0
335.0
367.0
335.0
367.0
335.0
367.0
335.0
367.0
35.0
38.0
35.0
38.0
35.0
38.0
35.0
38.0
TPS3306-18DGKR
TPS3306-18DR
VSSOP
SOIC
DGK
D
TPS3306-25DGKR
TPS3306-25DR
VSSOP
SOIC
DGK
D
TPS3306-33DGKR
TPS3306-33DR
VSSOP
SOIC
DGK
D
Pack Materials-Page 2
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Copyright © 2017, Texas Instruments Incorporated
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