TPS3431-Q1 [TI]

具有使能功能的汽车类标准可编程看门狗计时器;


型号：	TPS3431-Q1
厂家：	TEXAS INSTRUMENTS
描述：	具有使能功能的汽车类标准可编程看门狗计时器
文件：	总32页 (文件大小：2138K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TPS3431-Q1

ZHCSIJ8A –JULY 2018 –REVISED OCTOBER 2021

具有使能功能的TPS3431-Q1 汽车标准可编程监视器计时器

1 特性

3 说明

• 符合面向汽车应用的AEC-Q100 标准：

TPS3431-Q1 是一款具有使能功能的标准汽车类可编

程看门狗计时器，适用于汽车应用。看门狗超时可在

–40°C 至 +125°C 温度范围内实现 15% 的高计时精

度，在 25°C 下实现 2.5% 的典型计时精度，并且可通

过外部电容器或工厂编程的默认延迟设置进行编程。在

开发过程中，可以通过 Enable 引脚或 SET 逻辑引脚

将看门狗禁用，从而避免出现不必要的看门狗超时。

– 器件温度等级1：–40°C 至+125°C 的工作环

境温度范围

• 提供功能安全

– 可帮助进行功能安全系统设计的文档

• 出厂编程的精密看门狗计时器：

– 可在25°C 条件下实现±2.5%（典型值）的看门

狗超时(WDT) 精度

• 看门狗禁用功能

TPS3431-Q1 采用小型3.00mm ×

3.00mm 8 引脚 VSON 封装。TPS3431-Q1 具有可湿

性侧面，可轻松进行光学检查。

• 用户可编程看门狗超时

• 输入电压范围：V_DD= 1.8V 至6.5V

• 低静态电流：I_DD= 10µA（典型值）

• 低电平有效的开漏输出

• 使能输入(EN) 和使能输出(ENOUT)

• 采用小型3mm × 3mm 8 引脚VSON 封装

• 工作结温范围：

器件信息

封装⁽¹⁾

封装尺寸（标称值）

器件型号

TPS3431-Q1

VSON (8)

3.00mm × 3.00mm

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

–40°C 至+125°C

2 应用

• 汽车中心信息显示屏

• 汽车显示模块

• 数字驾驶舱处理单元

• 配电盒

• 座椅舒适模块

• 汽车外部放大器

• 摩托车仪表组

• 车身控制模块

3.3 V

7.5

V_DD

TPS3431

Microcontroller

2.5

ENOUT^*2

WDO

NMI (enable output)

NMI (watchdog fault)

GPIO

VDD

SET1

-2.5

-5

EN^*1

WDI

CWD

-7.5

-10

GND

-50

-25

100

125

Temperature (èC)

TPS3

A. 也可以将EN 保持浮动并将其从内部上拉至VDD

B. 也可以将ENOUT 保持浮动或将其连接至WDO

标准看门狗计时器电路

标准化看门狗超时(t_WD) 精度（SET1 = 1，CWD =

NC）

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SNVSB67

TPS3431-Q1

ZHCSIJ8A –JULY 2018 –REVISED OCTOBER 2021

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Table of Contents

8 Application and Implementation..................................13

8.1 Application Information............................................. 13

8.2 Typical Application.................................................... 15

8.3 Programmable Application........................................17

9 Power Supply Recommendations................................20

10 Layout...........................................................................21

10.1 Layout Guidelines................................................... 21

10.2 Layout Example...................................................... 21

11 Device and Documentation Support..........................22

11.1 Device Support........................................................22

11.2 Documentation Support.......................................... 22

11.3 接收文档更新通知................................................... 22

11.4 支持资源..................................................................22

11.5 Trademarks............................................................. 22

11.6 Electrostatic Discharge Caution..............................22

11.7 术语表..................................................................... 22

12 Mechanical, Packaging, and Orderable

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................3

6 Specifications.................................................................. 4

6.1 Absolute Maximum Ratings........................................ 4

6.2 ESD Ratings............................................................... 4

6.3 Recommended Operating Conditions.........................4

6.4 Thermal Information....................................................5

6.5 Electrical Characteristics.............................................5

6.6 Timing Requirements..................................................6

6.7 Timing Diagrams ........................................................7

6.8 Typical Characteristics................................................8

7 Detailed Description........................................................9

7.1 Overview.....................................................................9

7.2 Functional Block Diagram...........................................9

7.3 Feature Description.....................................................9

7.4 Device Functional Modes..........................................11

Information.................................................................... 22

4 Revision History

注：以前版本的页码可能与当前版本的页码不同

Changes from Revision * (July 2018) to Revision A (June 2021)

Page

• 删除了“可在工作温度范围内实现±15% 的看门狗超时和看门狗复位延迟精度”..............................................1

• 更新了整个文档中的表格、图和交叉参考的编号格式.........................................................................................1

• 添加了“提供功能安全”要点.............................................................................................................................1

• 使用网络链接更新了“应用”部分......................................................................................................................1

• 删除了“–40°C 至+125°C 温度范围内实现15% 的计时精度，”................................................................... 1

• 添加了“TPS3431-Q1 具有可湿性侧面，可轻松进行光学检查”。...................................................................1

• Updated ESD Ratings.........................................................................................................................................4

• Updated I_CWDmin and max spec........................................................................................................................5

• Updated V_CWDmin and max spec...................................................................................................................... 5

• Added a footnote to for t_INIT............................................................................................................................... 6

• Updated t_WDUmin and max boundry values from 0.85 and 1.15 to 0.905 and 1.095 respectively...................13

• Updated t_WDUmin and max values for all capacitors........................................................................................13

• Updated the equations 3 and 4 with t_WDmin and max boundry values from 0.85 and 1.15 to 0.905 and 1.095

respectively.......................................................................................................................................................17

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5 Pin Configuration and Functions

ENOUT

VDD

CWD

EN ^*1

GND

WDO

WDI

SET1

A. EN can also be left floating and is internally pulled-up to VDD

B. ENOUT can also be left floating or tied to WDO

图5-1. DRB Package: TPS3431

3-mm × 3-mm VSON-8

Top View

表5-1. Pin Functions

I/O

DESCRIPTION

NAME

VDD

NO.

Supply voltage pin. For noisy systems, connecting a 0.1-μF bypass capacitor is recommended.

Programmable watchdog timeout input. The watchdog timeout is set by connecting a capacitor between this pin and

ground. Connecting via a 10-kΩresistor to V_DDor leaving unconnected further enables the selection of the preset

watchdog timeouts; see the CWD Functionality section.

CWD

TheTPS3431-Q1 determines the watchdog timeout using 方程式1

Enable input pin. This pin is internally pulled up to V_DDand must be logic high or left floating. When EN goes logic

low, ENOUT goes logic low and WDI is ignored and WDO remains logic high. When EN goes logic high, ENOUT goes

high (asserts) after the watchdog reset delay time (t_RST). This pin can also be driven with an external push-button,

transistor, or microcontroller.

GND

Ground pin

—

Logic input. Grounding the SET1 pin disables the watchdog timer. SET1 and CWD select the watchdog timeouts; see

the SET1 section.

SET1

Watchdog input. A falling edge must occur at WDI before the timeout (t_WD) expires.

When the watchdog is not in use, the SET1 pin can be used to disable the watchdog. WDI is ignored when WDO is

low (asserted) and when the watchdog is disabled. If the watchdog is disabled, WDI cannot be left unconnected and

must be driven to either VDD or GND.

WDI

Watchdog open-drain active-low output. Connect WDO with a 1-kΩto 100-kΩresistor to the correct pull-up voltage

rail (V_PU). WDO goes low (asserts) when a watchdog timeout occurs. When a watchdog timeout occurs, WDO goes

low (asserts) for the watchdog reset delay time (t_RST). When EN goes low, WDO is in a high-impedance state and will

be pulled to logic high.

WDO

ENOUT

Enable open-drain active-high output. Connect ENOUT with a 1-kΩto 100-kΩresistor to the correct pull-up voltage

rail (V_PU). When EN goes logic high, ENOUT goes high impedance and pulls logic high (asserts) due to the external

pull-up resistor after the watchdog reset delay time (t_RST). When EN is forced logic low, ENOUT goes low after 200 ns

and remains logic low as long as EN is logic low.

Thermal pad

Connect the thermal pad to a large-area ground plane. The thermal pad is internally connected to GND.

—

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6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

MAX

UNIT

Supply voltage range

Output voltage range

VDD

–0.3

ENOUT, WDO

SET1, WDI, EN

CWD

Voltage ranges

VDD + 0.3⁽³⁾

±20

Output pin current

ENOUT, WDO

Input current (all pins)

±20

Continuous total power dissipation

See 节6.4

–40

See 节6.4

150

(2)

Operating junction, T_J

(2)

Temperature

Operating free-air temperature, T_A

Storage, T_stg

150

°C

–40

150

–65

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under

Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device

reliability.

(2) T_J= T_Aas a result of the low dissipated power in this device.

(3) The absolute maximum rating is V_DD+ 0.3 V or 7.0 V, whichever is smaller.

6.2 ESD Ratings

VALUE

UNIT

Human-body model (HBM), per AEC Q100-002⁽¹⁾

HBM ESD Classification Level 2

V_(ESD)

Electrostatic discharge

±4000

Charged-device model (CDM), per AEC Q100-011

CDM ESD Classification Level C4B

±1000

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

1.8

NOM

MAX

6.5

UNIT

VDD

V_SET1

C_CWD

CWD

R_PU

Supply pin voltage

SET1 pin voltage

6.5

Watchdog timing capacitor

Pullup resistor to VDD

Pullup resistor, ENOUT and WDO

EN pin current

0.1⁽¹⁾

1000⁽¹⁾

kΩ

°C

100

I_EN

I_WDO

T_J

Watchdog output current

Junction Temperature

125

–40

(1) Using a C_CWDcapacitor of 0.1 nF or 1000 nF gives a t_WDU(typ)of 62.74 ms or 77.45 seconds, respectively.

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6.4 Thermal Information

TPS3431-Q1

THERMAL METRIC⁽¹⁾

DRB (VSON)

8 PINS

47.7

UNIT

R_θJA

Junction-to-ambient thermal resistance

R_θJC(top)

R_θJB

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

51.5

22.2

°C/W

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

1.3

ψ_JT

22.3

ψ_JB

R_θJC(bot)

4.3

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953.

6.5 Electrical Characteristics

at 1.8 V ≤V_DD≤6.5 V over the operating temperature range of –40°C ≤T_J≤+125°C (unless otherwise noted); the

open-drain pullup resistors are 10 kΩ; typical values are at T_J= 25°C

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

GENERAL CHARACTERISTICS

(2) (3)

V_DD

I_DD

Supply voltage

1.8

6.5

µA

Supply current

(1)

V_POR

Power-on reset voltage

V_OL(MAX)= 0.25 V

0.8

WINDOW WATCHDOG FUNCTION

I_EN

EN pin internal pullup current

V_EN= 0V

500

347

620

375

700

403

1.224

0.4

I_CWD

V_CWD

V_OL

CWD pin charge current

CWD = 0.5 V

CWD pin threshold voltage

1.196

1.21

ENOUT, WDO output low

VDD = 5 V, I_SINK= 3 mA

I_D

ENOUT, WDO output leakage current

Low-level input voltage (EN, SET1)

High-level input voltage (EN, SET1)

Low-level input voltage (WDI)

High-level input voltage (WDI)

VDD = 1.8 V, V_WDO= 6.5 V

µA

V_IL

0.25

V_IH

0.8

V_IL(WDI)

V_IH(WDI)

0.3 × V_DD

0.8 × V_DD

(1) When V_DDfalls below V_POR, WDI and ENOUT is undefined.

(2) When V_DDfalls below VDD_MIN, WDI is ignored and ENOUT is driven low

(3) During power-on, V_DDmust be a minimum 1.8 V for at least 300 µs before WDI is active and ENOUT is high impedance.

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6.6 Timing Requirements

MIN

TYP

MAX

UNIT

GENERAL

t_INIT

CWD pin evaluation period ⁽¹⁾

EN, SET1 pin setup time

Startup delay⁽²⁾

381

µs

300

DELAY FUNCTION

t_{EN_ENOUT}EN to ENOUT delay

t_RSTWatchdog reset delay

WINDOW WATCHDOG FUNCTION

200

170

230

CWD = NC, SET1 = 1

1360

170

1600

200

1840

230

CWD = 10 kΩto VDD, SET1 = 1

CWD = NC, SET1 = 0

t_WD

Watchdog timeout

Watchdog disabled

CWD = 10 kΩto VDD, SET1 = 0

t_WD-setup

Setup time required for device to respond to changes on WDI after being enabled

Minimum WDI pulse duration

150

µs

t_WD-del

WDI to WDO delay

(1) Refer to 节8.1.1.2.

(2) During power-on, VDD must be a minimum 1.8 V for at least 300 µs before WDI is active and ENOUT is high impedance.

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6.7 Timing Diagrams

V_{DD (min)}

t_RST

VDD

WDI

V_POR

(1)

t = t_WD

t < t_WD

WDO

t_RST

图6-1. Timing Diagram

A. See 图6-2 for WDI timing requirements.

Correct

Operation

WDI

WDO

Late Fault

WDI

WDO

Valid

Region

Timing

t_WD(MIN)

t_WD(TYP)

t_WD(MAX)

= Tolerance Window

图6-2. Watchdog Timing Diagram

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6.8 Typical Characteristics

all typical characteristics curves are taken at 25°C with 1.8 V ≤VDD ≤6.5 V (unless other wise noted)

0.7

0.6

0.5

0.4

0.3

-40èC

0èC

25èC

105èC

125èC

V_IL

V_IH

-50

-25

25 50

Temperature (°C)

100

125

V_DD(V)

VDD = 1.8 V

图6-3. Supply Current vs V_DD

图6-4. EN Threshold vs Temperature

380

376

372

368

364

7.5

2.5

-2.5

-5

-7.5

-10

1.6 V

6.5 V

-50

-25

100

125

-50

-25

100

125

Temperature (èC)

TPS3

图6-5. CWD Charging Current vs Temperature

图6-6. Normalized Watchdog Timeout (t_WD

)

Accuracy (SET1 = 1, CWD = NC)

7.5

2.5

-2.5

-5

-7.5

-10

-50

-25

100

125

Temperature (èC)

TPS3

图6-7. Normalized Watchdog Timeout (t_WD) Accuracy (SET1 = 1, CWD = 10kΩ)

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7 Detailed Description

7.1 Overview

The TPS3431-Q1 is a standard programmable watchdog timer with enable/disable feature. This device includes

a precision watchdog timer that achieves 15% timing accuracy over the specified temperature range of –40°C

to +125°C.

7.2 Functional Block Diagram

ENOUT

VDD

Precision

Clock

WDO

VDD

State

Machine

Cap

Control

CWD

VDD

WDI SET1

GND

7.3 Feature Description

7.3.1 Enable Input (EN) and Enable Output (ENOUT)

The Enable (EN) input allows a processor or other logic circuits to initiate a single cycle watchdog reset by

momentarily bringing Enable low, or a permanent disable by keeping Enable low. After EN goes to a logic high

and V_DDis above V_{DD (min)}, ENOUT and WDO go logic high after the watchdog reset delay time (t_RST). If EN is

not controlled externally, then EN can either be connected to V_DDor left floating because the EN pin is internally

pulled up to VDD. When EN is forced logic low, ENOUT goes low after a propagation delay of 200 ns and WDO

goes high impedance and pulls to logic high due to the external pull-up resistor. Because WDO and ENOUT are

both open-drain outputs, these outputs can be tied together to create an OR logic function so that if either output

pulls down to logic low, the other will also pull down logic low.

7.3.2 Watchdog Mode

This section provides information for the watchdog mode of operation.

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7.3.2.1 CWD

The CWD pin provides the user the functionality of both high-precision, factory-programmed watchdog timing

options and user-programmable watchdog timing. The TPS3431-Q1 features three options for setting the

watchdog timer: connecting a capacitor to the CWD pin, connecting a pull-up resistor to VDD, and leaving the

CWD pin unconnected. The configuration of the CWD pin is evaluated by the device every time V_DDrises above

V_{DD (min)}. The pin evaluation is controlled by an internal state machine that determines which option is connected

to the CWD pin. The sequence of events typically takes 381 μs (t_INIT) to determine if the CWD pin is left

unconnected, pulled-up through a resistor, or connected to a capacitor. If the CWD pin is being pulled up to

VDD, a 10-kΩresistor is required.

7.3.2.2 Watchdog Input WDI

WDI is the watchdog timer input that controls the WDO output. The WDI input is triggered by the falling edge of

the input signal. To ensure proper functionality of the watchdog timer, always issue the WDI pulse before

t_WD(min). If the pulse is issued in this region, then WDO remains unasserted. Otherwise, the device asserts WDO,

putting the WDO pin into a low-impedance state therefore WDO will be logic low.

The watchdog input (WDI) is a digital pin. To ensure there is no increase in I_DD, drive the WDI pin to either VDD

or GND at all times. Putting the pin to an intermediate voltage can cause an increase in supply current (I_DD

)

because of the architecture of the digital logic gates. When EN is logic low, the watchdog is disabled and all

signals input to WDI are ignored. When EN is logic high, the device resumes normal operation and no longer

ignores the signal on WDI. If the watchdog is disabled, drive the WDI pin to either VDD or GND. 图 7-1 shows

the valid region for a WDI pulse to be issued to prevent WDO from being triggered and pulled low.

Correct

Operation

WDI

WDO

Late Fault

WDI

WDO

Valid

Region

Timing

t_WD(MIN)

t_WD(TYP)

t_WD(MAX)

= Tolerance Window

图7-1. Watchdog Timing Diagram

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7.3.2.3 Watchdog Output WDO

The TPS3431-Q1 features an active-low open-drain watchdog output that asserts when a pulse on WDI fails to

arrive within the watchdog timeout. When EN is logic high, the WDO signal maintains normal operation. When

the EN pin is logic low, the WDO pin goes to a high-impedance state and pulls logic high due to the external pull-

up resistor. Because WDO and ENOUT are both open-drain outputs, these outputs can be tied together to

create an OR logic function so that if either output pulls down to logic low, the other will also pull down logic low.

7.3.2.4 SET1

The SET1 pin can enable and disable the watchdog timer and should be used when disabling the watchdog

timer for longer than one watchdog reset cycle. If SET1 is set to GND, the watchdog timer is disabled and WDI is

ignored. If the watchdog timer is disabled, drive the WDI pin to either GND or VDD to ensure that there is no

increase in I_DD. When SET1 is logic high, the watchdog operates normally. The SET1 pin can be changed

dynamically; however, if the watchdog is going from disabled to enabled there is a 150 µs setup time where the

watchdog does not respond to changes on WDI, as shown in 图 7-2. Note: disabling using SET1 pin causes a

delay defined by the fixed 150-us setup time when enabling again.

VDD

t_RST

ENOUT

SET1

150 µs

Watchdog

Disabled

Enabled

Enabled/Disabled

when ENOUT or SET1 is logic low

图7-2. Enabling and Disabling the Watchdog

7.4 Device Functional Modes

表7-1 summarizes the functional modes of the TPS3431-Q1.

表7-1. Device Functional Modes

V_DD

---

ENOUT

---

WDI

---

WDO

---

V_DD< V_POR

---

Low

Ignored

High

_POR≤V_DD< V_DD(min)

t_PULSE< t_WD(min)

(1)

V_DD> V_{DD (min)}

High

(2)

t_PULSE> t_WD(min)

(1)

V_DD> V_{DD (min)}

High

Low

High

Low

(2)

(1)

V_DD> V_{DD (min)}

Ignored

High

(1) V_DDmust be above V_{DD (min)}for longer than 300 µs.

(2) Where t_pulseis the time between the falling edges on WDI.

7.4.1 V_DDis Below V_POR( V_DD< V_POR

)

When V_DDis less than V_POR, WDO is undefined and can be either high or low. The state of WDO largely

depends on the load that the WDO pin is experiencing.

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7.4.2 Above Power-On-Reset, But Less Than V_DD(min)(V_POR≤V_DD< V_DD(min)

)

When the voltage on V_DDis less than V_DD(min), and greater than or equal to V_POR, the WDO signal is asserted

(logic low). When EN is logic low, the watchdog output WDO is in a high-impedance state and logic low

regardless of the WDI signal that is input to the device.

7.4.3 Normal Operation (V_DD≥V_DD(min)

)

When V_DDis greater than or equal to V_DD(min)and EN is logic high, the WDO signal is determined by WDI. When

WDI is within the watchdog timeout, the internal MOSFET turns off and WDO is pulled high through external pull-

up resistor. When WDI is not within the watchdog timeout, the internal MOSFET turns on and WDO is pulled to

logic low. When EN is logic low, ENOUT goes to logic low and WDO goes to a high-impedance state and pulls to

logic high due to the external pull-up resistor.

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8 Application and Implementation

Note

以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客户应负责确定

器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。

8.1 Application Information

The following sections describe in detail proper device implementation, depending on the final application

requirements.

8.1.1 CWD Functionality

The TPS3431-Q1 features three options for setting the watchdog timeout: connecting a capacitor to the CWD

pin, connecting a pull-up resistor to VDD, and leaving the CWD pin unconnected. 图 8-1 shows a schematic

drawing of all three options. If this pin is connected to VDD through a 10-kΩ pullup resistor or left unconnected

(high impedance), then the factory-programmed watchdog timeouts are enabled; see the 节 8.1.1.1 section.

Otherwise, the watchdog timeout can be adjusted by placing a capacitor from the CWD pin to ground.

VDD

TPS3431

VDD

375 nA

CWD

C_CWD

CWD

Cap

Control

Cap

Control

Cap

Control

User Programmable

Capacitor to GND

CWD

Unconnected

10 kΩ Resistor

to VDD

图8-1. CWD Charging Circuit

8.1.1.1 Factory-Programmed Timing Options

If using the factory-programmed timing options (listed in 表 8-1), the CWD pin must either be unconnected or

pulled up to VDD through a 10-kΩ pull-up resistor. Using these options enables high-precision, 15% accurate

watchdog timing.

表8-1. Factory Programmed Watchdog Timing

INPUT

STANDARD WATCHDOG TIMEOUT WDT (t_WD)

UNIT

CWD

SET1

MIN

TYP

Watchdog disabled

1600

Watchdog disabled

200

MAX

1360

1840

10 kΩto VDD

170

230

8.1.1.2 CWD Adjustable Capacitor Watchdog Timeout

Adjustable capacitor timing is achievable by connecting a capacitor to the CWD pin. If a capacitor is connected

to CWD, then a 375-nA, constant-current source charges C_CWDuntil V_CWD= 1.21 V. 表 8-2 shows how to

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calculate t_WDusing 方程式 1 and the SET1 pin. The TPS3431-Q1 determines the watchdog timeout with the

formulas given in 方程式1, where C_CWDis in nanofarads and t_WDis in milliseconds.

t_WD(ms) = 77.4 x C_CWD(nF) + 55 (ms)

(1)

The TPS3431-Q1 is designed and tested using C_CWDcapacitors between 100 pF and 1 µF. Note that 方程式1 is

for ideal capacitors and capacitor tolerances vary the actual device timing. For the most accurate timing, use

ceramic capacitors with COG dielectric material. If a C_CWDcapacitor is used, 方程式 1 can be used to set t_WDfor

the watchdog timeout. 表8-3 shows the minimum and maximum calculated t_WDvalues using an ideal capacitor.

表8-2. Programmable CWD Timing

(1)

INPUT

WATCHDOG TIMEOUT WDT (t_WD

)

UNIT

CWD

C_CWD

SET1

MIN TYP

MAX

Watchdog disabled

_WD方程式1

t_WD× 0.905

t_WD× 1.095

(1) Calculated from 方程式1 using an ideal capacitor.

表8-3. t_WDValues for Common Ideal Capacitor Values

WATCHDOG TIMEOUT WDT (t_WD

)

C_CWD

UNIT

MIN⁽¹⁾

TYP

62.74

132.4

829

MAX⁽¹⁾

68.7

100 pF

1 nF

56.77

119.82

750

144.98

908

10 nF

100 nF

1 μF

7054

7795

77455

8536

70096

84814

(1) The minimum and maximum values are calculated using an ideal capacitor.

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8.2 Typical Application

3.3 V

V_DD

TPS3431

ENOUT^*2

Microcontroller

VDD

NMI (enable output)

NMI (watchdog fault)

GPIO

SET1

WDO

EN^*1

WDI

CWD

GND

A. EN can also be left floating and is internally pulled-up to VDD

B. ENOUT can also be left floating or tied to WDO

图8-2. Monitoring a Microcontroller with Standard Watchdog Timer

8.2.1 Design 1 Requirements

PARAMETER

Output logic voltage

DESIGN REQUIREMENT

3.3V Open-Drain

DESIGN RESULT

3.3V Open-Drain

t_WD(min)= 1360 ms, t_WD(TYP)= 1600 ms, t_WD(max)

1840 ms

Watchdog Timeout

Leave CWD disconnected: 1.6 seconds (typical)

35 µA

Maximum device current

consumption

33 µA when WDO is asserted

8.2.2 Detailed Design 1 Procedure

8.2.2.1 Calculating WDO Pullup Resistor Design 1

The TPS3431-Q1 uses an open-drain configuration for the WDO circuit, as shown in 图 8-3. When the internal

MOSFET is off, the external pull-up resistor pulls the drain of the transistor to VDD and when the MOSFET is

turned on, the MOSFET attempts to pull the drain to ground, thus creating an effective resistor divider. The

resistors in this divider must be chosen to ensure that V_OLis below the maximum value.

To choose the proper pull-up resistor, there are three key specifications to keep in mind: the pull-up voltage

(V_PU), the recommended maximum WDO pin current (I_WDO), and V_OL

The maximum V_OLis 0.4 V, meaning that the effective resistor divider created must be able to bring the voltage

on the reset pin below 0.4 V with I_WDOkept below 10 mA. For this example, with a V_PUof 3.3 V, a resistor must

be chosen to keep I_WDObelow 35 μA because this value is the maximum consumption current allowed. To

ensure this specification is met, a pull-up resistor value of 100 kΩ was selected, which sinks a maximum of 33

μA when WDO is asserted.

VDD

WDO

WATCHDOG

CONTROL

图8-3. WDO Open-Drain Configuration

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8.2.2.2 Setting the Watchdog Design 1

As illustrated in 图 8-1 there are three options for setting the watchdog timer. The design specifications in this

application allow for a factory-programmed timing option by leaving CWD floating. To ensure proper functionality,

a falling edge must be issued before t_WD(min)with is set for 1.36 seconds when CWD is not connected. 图 8-8

illustrates that a WDI signal with a period of 1 second keeps WDO from asserting.

图8-4 shows WDO asserting when the WDI signal has a period longer than t_WD(max)which is 1.84 seconds when

CWD is not connected. 图 8-5 shows a watchdog fault caused by missing WDI pulse followed by correct timing

WDI pulses to deactivate WDO.

8.2.3 Application Curves Design 1

Unless otherwise stated, application curves were taken at T_A= 25°C.

VDD

Ignore all pulses that occur before t_RST

First falling edge must occur before WDU

No pulse on WDI before WDU(max) so WDO asserts

Second falling edge occurs after WDU(max) triggering a watchdog reset

Falling edge on WDI occurs within WDU

WDI

WDO remains unasserted while

WDI is within watchdog window

WDO

WDO resets for t_RST

图8-5. WDO Fault Caused by missing WDI Pulses

图8-4. WDO Fault Caused by WDI Pulse Arriving

Too Late (After t_WD(max)

Followed by Correct Timing WDI Pulses

)

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8.3 Programmable Application

1.8 V

V_CORE

Microcontroller

TPS3431

ENOUT

TPS3890

NMI (enable output)

VDD

SENSE

RESET

GND

NMI (watchdog fault)

GPIO (WDI)

WDO

WDI

SET1

CWD

GPIO (SET1)

GND

4.7 µF

GND

2.7 nF

图8-6. Monitoring the Supply Voltage and Watchdog Supervision of a Microcontroller

8.3.1 Design 2 Requirements

PARAMETER

DESIGN REQUIREMENT

DESIGN RESULT

5.02 seconds (typ)

Watchdog disable for initialization Watchdog must remain disabled for 5 seconds until

period

logic enables the watchdog timer

Microcontroller controls SET1 on TPS3431 via a

GPIO

The Microcontroller can disable TPS3431 via SET1

and thus disable the watchdog for any reason.

Programmable disable feature

Output logic voltage

1.8-V Open-Drain

1.8V Open-Drain

Monitored rail (TPS3890)

1.8 V with a 5% threshold and 1% accuracy

Worst-case V_ITN= 1.714 V –4.7%

t_WD(min)= 213 ms, t_WD(TYP)= 264 ms, t_WD(max)

319 ms

Watchdog timeout (TPS3431)

265 ms typical

50 µA

Maximum device current

consumption

37 µA when WDO is asserted

8.3.2 Detailed Design 2 Procedure

8.3.2.1 Calculating WDO Pullup Resistor Design 2

The TPS3431-Q1 uses an open-drain configuration for the WDO circuit. When the internal MOSFET is off, the

external pull-up resistor pulls the drain of the transistor to VDD and when the MOSFET is turned on, the

MOSFET attempts to pull the drain to ground, thus creating an effective resistor divider. The resistors in this

divider must be chosen to ensure that V_OLis below the maximum value. To choose the proper pull-up resistor,

there are three key specifications to keep in mind: the pull-up voltage (V_PU), the recommended maximum WDO

pin current (I_WDO), and V_OL. The maximum V_OLis 0.4 V, meaning that the effective resistor divider created must

be able to bring the voltage on the reset pin below 0.4 V with I_WDOkept below 10 mA. For this example, with a

V_PUof 1.8 V, a resistor must be chosen to keep I_WDObelow 50 μA because this value is the maximum

consumption current allowed. To ensure this specification is met, a pull-up resistor value of 100 kΩ was

selected, which sinks a maximum of 18 μA when WDO is asserted.

8.3.2.2 Setting the Watchdog Design 2

As illustrated in 图 8-1 there are three options for setting the watchdog timer. The design specifications in this

application require the programmable timing option (external capacitor connected to CWD). When a capacitor is

connected to the CWD pin, the watchdog timer is governed by 方程式1. This equation estimation is only valid for

ideal capacitors and any temperature or voltage derating must be accounted for separately.

C_CWD(nF) = (t_WD(ms) –55) / 77.4 = (265 –55) / 77.4 = 2.71 nF

(2)

The nearest standard capacitor value is 2.7 nF. Selecting 2.7 nF for the C_CWDcapacitor gives the following

minimum and maximum timing parameters:

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t_WD(MIN)= 0.905 x t_WD(TYP)= 0.905 x (77.4 x 2.7 + 55) = 238.902 ms

t_WD(MAX)= 1.095 x t_WD(TYP)= 1.095x (77.4 x 2.7 + 55) = 289.058 ms

(3)

(4)

Capacitor tolerance also influences t_WD(MIN)and t_WD(MAX). Select a ceramic COG dielectric capacitor for high

accuracy. For 2.7 nF, COG capacitors are readily available with 5% tolerances. This selection results in a 5%

decrease in t_WD(MIN)and a 5% increase in t_WD(MAX), giving 213.16 ms and 318.75 ms, respectively. To ensure

proper functionality, a falling edge must be issued before t_WD(min). 图 8-8 illustrates that a WDI signal with a

period of 260 ms keeps WDO from asserting.

8.3.2.3 Watchdog Disabled During Initialization Period Design 2

The watchdog is often needed to be disabled during startup to allow for an initialization period. When the

initialization period is over, the watchdog timer is turned back on to allow the microcontroller to be monitored by

the TPS3431-Q1. To achieve this setup, EN on TPS3431 is controlled by TPS3890 supervisor. In this

application, the TPS3890 was chosen to monitor VDD as well, which means that the RESET on the TPS3890

stays low until V_DDrises above V_ITN. When VDD comes up, the delay time can be adjusted through the CT

capacitor on the TPS3890. With this approach, the RESET delay can be adjusted from a minimum of 25 μs to a

maximum of 30 seconds. For this design, a typical delay of 5 seconds is needed before the watchdog timer is

enabled. The CT capacitor calculation (see the TPS3890 data sheet) yields an ideal capacitance of 4.67 μF,

giving a closest standard ceramic capacitor value of 4.7 μF. When connecting a 4.7 μF capacitor from CT to

GND, the typical delay time is 5 seconds. 图 8-7 shows that when the watchdog is disabled, the WDO output

remains high. However when SET1 goes high and there is no WDI signal, WDO begins to assert. See the

TPS3890 datasheet for detailed information on the TPS3890. The ENOUT pin on the TPS3431 reflects the

status of the EN pin and can be connected to the microcontroller for monitoring or can be left floating if not being

used. When the TPS3431 is disabled, ENOUT is logic low and WDO is logic high so the user can also tie

ENOUT to WDO to force WDO to logic low when TPS3431 is disabled.

8.3.2.4 Programmable Disable Feature Design 2

The watchdog is often needed to be disabled during operation to prevent false watchdog faults. When the

watchdog is disabled, all pulses or lack of pulses on WDI are ignored and WDO is high impedance as shown in

图 8-9. When the watchdog is re-enabled, the watchdog timer is turned back on after a watchdog start-up delay

of 150 µs to allow the microcontroller to be monitored by the TPS3431-Q1. To achieve this setup, SET1 on

TPS3431 is controlled by a GPIO on the microcontroller and must be logic high to enable to watchdog. To

disable the watchdog, the microcontroller sets the GPIO connected to SET1 to logic low. To re-enable the

watchdog, the microcontroller sets the GPIO connected to SET1 back to logic high. This configuration is useful

when another device or signal is already using the EN pin on TPS3431, and a programmable disable feature

with minimal delay upon enable is still required. When the watchdog is disabled using SET1 instead of EN,

ENOUT remains unaffected which is useful when needing to disable the watchdog but not causing another

device connected to ENOUT to be disabled.

8.3.3 Application Curves Design 2

Unless otherwise stated, application curves were taken at T_A= 25°C.

VDD

2 V/div

VDD

2 V/div

6 seconds

SET1

265 ms

2 V/div

WDI

2 V/div

WDO

2 V/div

WDO

2 V/div

1 s/div

图8-7. Startup Without a WDI Signal

图8-8. Typical WDI Signal

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VDD

When watchdog is disabled, WDI is ignored

WDI

WDO is high-impedance and remains logic high due to pull-up resistor

WDO

图8-9. Watchdog Disabled With Missing WDI Pulse

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9 Power Supply Recommendations

This device is designed to operate from an input supply with a voltage range between 1.8 V and 6.5 V. An input

supply capacitor is not required for this device; however, if the input supply is noisy, then good analog practice is

to place a 0.1-µF capacitor between the VDD pin and the GND pin.

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10 Layout

10.1 Layout Guidelines

• Make sure that the connection to the VDD pin is low impedance. Good analog design practice is to place a

0.1-µF ceramic capacitor as near as possible to the VDD pin.

• If a C_CWDcapacitor or pull-up resistor is used, place these components as close as possible to the CWD pin.

If the CWD pin is left unconnected, make sure to minimize the amount of parasitic capacitance on the pin.

• Place the pull-up resistor on WDO as close to the pin as possible.

10.2 Layout Example

C_VDD

Vin

R_PU2

Vin

C_CWD

VDD

CWD

EN ^*1

GND

ENOUT ^*2

WDO

WDI

SET1

GND Plane

Denotes a via

A. EN can also be left floating and is internally pulled-up to VDD

B. ENOUT can also be left floating or tied to WDO

图10-1. TPS3431-Q1 Recommended Layout

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11 Device and Documentation Support

11.1 Device Support

11.2 Documentation Support

11.2.1 Related Documentation

For related documentation see the following:

• TPS3890 Low Quiescent Current, 1% Accurate Supervisor with Programmable Delay (SLVSD65)

• TPS3431EVM-780 Evaluation Module (SBVU033)

11.3 接收文档更新通知

要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新进行注册，即可每周接收产品信息更

改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

11.4 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的《使用条款》。

11.5 Trademarks

TI E2E^™is a trademark of Texas Instruments.

所有商标均为其各自所有者的财产。

11.6 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

11.7 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGE OPTION ADDENDUM

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23-Jun-2023

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

TPS3431SQDRBRQ1

ACTIVE

SON

DRB

3000 RoHS & Green

NIPDAU | SN

Level-2-260C-1 YEAR

-40 to 125

431DF

Samples

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF TPS3431-Q1 :

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

23-Jun-2023

Catalog : TPS3431

•

NOTE: Qualified Version Definitions:

Catalog - TI's standard catalog product

•

Addendum-Page 2

PACKAGE OUTLINE

DRB0008F

VSON - 1 mm max height

SCALE 4.000

PLASTIC SMALL OUTLINE - NO LEAD

3.1

2.9

PIN 1 INDEX AREA

3.1

2.9

0.1 MIN

(0.05)

SECTION A-A

TYPICAL

1 MAX

SEATING PLANE

0.08 C

0.05

0.00

EXPOSED

THERMAL PAD

1.6 0.05

(0.2) TYP

1.95

2.4 0.05

6X 0.65

0.35

0.25

PIN 1 ID

0.5

0.3

0.1

C A B

(OPTIONAL)

0.05

4222121/C 10/2016

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

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EXAMPLE BOARD LAYOUT

DRB0008F

VSON - 1 mm max height

PLASTIC SMALL OUTLINE - NO LEAD

(1.6)

SYMM

8X (0.6)

8X (0.3)

(2.4)

(0.95)

6X (0.65)

(R0.05) TYP

(0.55)

(2.8)

(

0.2) VIA

TYP

LAND PATTERN EXAMPLE

SCALE:20X

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

SOLDER MASK

OPENING

METAL

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4222121/C 10/2016

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

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EXAMPLE STENCIL DESIGN

DRB0008F

VSON - 1 mm max height

PLASTIC SMALL OUTLINE - NO LEAD

SYMM

METAL

TYP

8X (0.6)

8X (0.3)

(0.635)

SYMM

(1.07)

6X (0.65)

(R0.05) TYP

(1.47)

(2.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD

82% PRINTED SOLDER COVERAGE BY AREA

SCALE:25X

4222121/C 10/2016

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

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PACKAGE OUTLINE

DRB0008K

VSON - 1 mm max height

SCALE 4.000

PLASTIC SMALL OUTLINE - NO LEAD

3.1

2.9

3.1

2.9

PIN 1 INDEX AREA

0.07 MIN

(0.13)

SECTION A-A

TYPICAL

1.0

0.8

SEATING PLANE

0.08 C

0.05

0.00

1.6 0.05

(0.2) TYP

EXPOSED

THERMAL PAD

(0.19) TYP

1.95

SYMM

2.4 0.05

6X 0.65

0.35

SYMM

PIN 1 ID

(45 X 0.3)

0.25

0.5

0.3

0.1

C A B

0.05

4227074/D 08/2022

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.

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EXAMPLE BOARD LAYOUT

DRB0008K

VSON - 1 mm max height

PLASTIC SMALL OUTLINE - NO LEAD

(2.8)

(1.6)

8X (0.6)

8X (0.3)

(2.4)

SYMM

(0.95)

6X (0.65)

(R0.05) TYP

(

0.2) VIA

(0.55)

SYMM

TYP

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:20X

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

EXPOSED METAL

SOLDER MASK

OPENING

METAL

METAL UNDER

SOLDER MASK

OPENING

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4227074/D 08/2022

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

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EXAMPLE STENCIL DESIGN

DRB0008K

VSON - 1 mm max height

PLASTIC SMALL OUTLINE - NO LEAD

(2.8)

2X (1.5)

8X (0.6)

(1.06)

8X (0.3)

SYMM

(0.63)

6X (0.65)

(R0.05) TYP

SYMM

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD 9:

80% PRINTED SOLDER COVERAGE BY AREA

SCALE:25X

4227074/D 08/2022

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

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