TPS3613-01 [TI]
ADJUSTABLE BATTERY BACK UP SUPERVISOR FOR RAM RETENTION; 可调备用电池监督员RAM保持
| 型号： | TPS3613-01 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | ADJUSTABLE BATTERY BACK UP SUPERVISOR FOR RAM RETENTION |
| 文件： | 总15页 (文件大小：326K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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SLVS340B – DECEMBER 2000 – REVISED DECEMBER 2002
D
D
D
Supply Current of 40 µA (Max)
typical applications
Battery Supply Current of 100 nA (Max)
D
Fax Machines
Supply Voltage Supervision Range:
– Adjustable
– Other Versions Available on Request
D
D
D
D
D
D
D
D
Set-Top Boxes
Advanced Voice Mail Systems
Portable Battery Powered Equipment
Computer Equipment
D
D
Backup-Battery Voltage Can Exceed V
DD
Power-On Reset Generator With Fixed
100-ms Reset Delay Time
Advanced Modems
Automotive Systems
D
Active-High and Active-Low Reset Output
Portable Long-Time Monitoring Equipment
Point-of-Sale Equipment
D
Chip-Enable Gating . . . 3 ns (at V
Max Propagation Delay
= 5 V)
DD
D
D
10-Pin MSOP Package
MSOP (DGS) Package
(TOP VIEW)
Temperature Range . . . –40°C to 85°C
V
V
description
OUT
BAT
V
RESET
ACTUAL SIZE
3,05 mm x 4,98 mm
DD
GND
SENSE
RESET
CEOUT
The TPS3613-01 supervisory circuit monitors
MR
and controls processor activity by providing
backup-battery switchover for data retention of
CMOS RAM.
CEIN
During power on, RESET is asserted when the supply voltage (V
or V
) becomes higher than 1.1 V.
DD
BAT
Thereafter, the supply voltage supervisor monitors V
and keeps RESET output active as long as V
remains
DD
DD
below the threshold voltage V . An internal timer delays the return of the output to the inactive state (high) to
IT
ensure proper system reset. The delay time starts after V
has risen above the threshold voltage V .
DD
IT
When the supply voltage drops below the threshold voltage V , the output becomes active (low) again.
IT
The TPS3613-01 is available in a 10-pin MSOP package and is characterized for operation over a temperature
range of –40°C to 85°C.
typical operating circuit
Address
Power
Decoder
Supply
0.1 µF
Monitored
Voltage
CE
CMOS
RAM
CE
CMOS
RAM
Address Bus
uC
CEIN
CEOUT
Real-
Time
Clock
Backup
Battery
V
DD
V
BAT
R
R
x
y
V
CC
V
CC
V
CC
SENSE
8
8
RESET
RESET
Data Bus
16
TPS3613
MR
Switchover
Capacitor
Manual
Reset
V
OUT
V
CC
0.1 µF
GND
GND
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2002, Texas Instruments Incorporated
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ꢖ ꢕꢏ ꢏ ꢈ ꢗ ꢏ ꢎꢀ ꢎ ꢘꢀꢔ ꢕ ꢘ
SLVS340B – DECEMBER 2000 – REVISED DECEMBER 2002
PACKAGE INFORMATION
DEVICE NAME
T
A
MARKING
†
–40°C to 85°C
TPS3613–01DGSR
AFK
†
The DGSR passive indicates tape and reel of 2500 parts.
ordering information application specific versions
TPS361
3
–
01
DGS
R
‡
NOMINAL VOLTAGE , V
DEVICE NAME
NOM
Adjustable
TPS3613–01 DGS
Reel
Package
Nominal Supply Voltage
Functionality
‡
For other threshold voltages, contact the local TI sales office
for availability and lead-time.
Family
FUNCTION TABLE
SENSE > V
V
DD
> V
0
MR
0
CEIN
0
V
OUT
RESET
RESET
CEOUT
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
EN
IT
BAT
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
V
BAT
V
BAT
V
BAT
V
BAT
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
0
0
0
0
1
0
1
0
0
1
1
1
0
0
V
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
1
0
1
V
1
1
0
V
V
V
V
V
V
V
V
V
V
1
1
1
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
DIS
DIS
DIS
EN
1
0
1
1
1
0
1
1
1
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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SLVS340B – DECEMBER 2000 – REVISED DECEMBER 2002
functional schematic
TPS3613
V
BAT
+
_
Switch
Control
V
OUT
V
DD
R
RESET
Logic
+
MR
RESET
RESET
+
SENSE
Timer
_
Reference
Voltage
V
OUT
or 1.15 V
CEIN
CEOUT
timing diagram
V
BAT
V
DD
V
IT
t
t
t
V
OUT
RESET
t
t
d
d
3
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ꢖ ꢕꢏ ꢏ ꢈ ꢗ ꢏ ꢎꢀ ꢎ ꢘꢀꢔ ꢕ ꢘ
SLVS340B – DECEMBER 2000 – REVISED DECEMBER 2002
Terminal Functions
TERMINAL
NAME NO.
CEIN
I/O
DESCRIPTION
5
6
I
O
I
Chip-enable input
Chip-enable output
Ground
CEOUT
GND
3
MR
4
I
Manual reset input
Active-high reset output
Active-low reset output
Adjustable sense input
Backup-battery input
Input supply voltage
Supply output
RESET
RESET
SENSE
7
O
O
I
9
8
V
V
V
10
2
I
BAT
I
DD
1
O
OUT
detailed description
backup-battery switchover
In case of a brownout or power failure, it may be necessary to preserve the contents of RAM. If a backup battery
is installed at V , the device automatically switches the connected RAM to backup power when V fails. In
BAT
DD
order to allow the backup battery (e.g., 3.6-V lithium cells) to have a higher voltage than V , these supervisors
DD
do not connect V
to V
when V
is greater than V . V
only connects to V
(through a 15-Ω switch)
BAT
OUT
BAT
DD BAT
OUT
when V
falls below V and V
is greater than V . When V
recovers, switchover is deferred either until
DD
IT
BAT
DD
DD
V
crosses V
, or when V
rises above the reset threshold V . V
connects to V
through a 1-Ω (max)
DD
BAT
DD
IT OUT
DD
PMOS switch when V
crosses the reset threshold.
DD
V >V
DD BAT
V >V
DD IT
V
OUT
1
1
0
0
1
0
1
0
V
DD
DD
DD
V
V
V
BAT
V
DD
– Mode
V
IT
Hysteresis
V
BAT
– Mode
VBSW Hysteresis
Undefined
V
BAT
– Backup-Battery Supply Voltage
Figure 1. V
– V
Switchover
DD
BAT
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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SLVS340B – DECEMBER 2000 – REVISED DECEMBER 2002
detailed description (continued)
chip-enable signal gating
The internal gating of chip-enable (CE) signals prevents erroneous data from corrupting CMOS RAM during
an under-voltage condition. The TPS3613 use a series transmission gate from CEIN to CEOUT. During normal
operation (reset not asserted), the CE transmission gate is enabled and passes all CE transitions. When reset
is asserted, this path becomes disabled, preventing erroneous data from corrupting the CMOS RAM. The short
CE propagation delay from CEIN to CEOUT enables the TPS3613 device to be used with most processors.
The CE transmission gate is disabled and CEIN is high impedance (disable mode) while reset is asserted.
During a power-down sequence when V
crosses the reset threshold, the CE transmission gate is disabled
DD
and CEIN immediately becomes high impedance if the voltage at CEIN is high. If CEIN is low when reset is
asserted, the CE transmission gate is disabled when CEIN goes high, or 15 µs after reset asserts, whichever
occurs first. This allows the current write cycle to complete during power down. When the CE transmission gate
is enabled, the impedance of CEIN appears as a resistor in series with the load at CEOUT. The overall device
propagation delay through the CE transmission gate depends on V
, the source impedance of the drive
OUT
connected to CEIN, and the load at CEOUT. To achieve minimum propagation delay, the capacitive load at
CEOUT should be minimized, and a low-output-impedance driver is used.
In the disabled mode, the transmission gate is off and an active pullup connects CEOUT to V
turns off when the transmission gate is enabled.
. This pullup
OUT
CEIN
t
CEOUT
15 µs
t
RESET
t
Figure 2. Chip-Enable Timing
5
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ꢖ ꢕꢏ ꢏ ꢈ ꢗ ꢏ ꢎꢀ ꢎ ꢘꢀꢔ ꢕ ꢘ
SLVS340B – DECEMBER 2000 – REVISED DECEMBER 2002
†
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage:
V
(see Note1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
DD
MR and SENSE pins (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to (V
+ 0.3 V)
DD
Continuous output current at V
: I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400 mA
OUT O
All other pins, I
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±10 mA
O
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Operating free-air temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 85°C
A
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
Lead temperature soldering 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . 260°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to GND. For reliable operation the device must not be operated at 7 V for more than t=1000h
continuously.
DISSIPATION RATING TABLE
T
≤ 25°C
DERATING FACTOR
T
= 70°C
T = 85°C
A
A
A
PACKAGE
POWER RATING
ABOVE T = 25°C
POWER RATING POWER RATING
A
DGS
424 mW
3.4 mW/°C
271 mW
220 mW
recommended operating conditions
MIN
1.65
1.5
0
MAX
5.5
UNIT
V
Supply voltage, V
DD
Battery supply voltage, V
BAT
5.5
V
Input voltage, V
V
+ 0.3
V
I
DD
High-level input voltage, V
IH
0.7 x V
V
DD
Low-level input voltage, V
IL
0.3 x V
300
100
1
V
DD
Continuous output current at V
, I
mA
ns/V
V/µs
°C
OUT O
Input transition rise and fall rate at MR, ∆t/∆V
Slew rate at V or V
DD bat
Operating free-air temperature range, T
–40
85
A
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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SLVS340B – DECEMBER 2000 – REVISED DECEMBER 2002
electrical characteristics over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
= 1.8 V
I
= –400 µA
V
V
V
V
– 0.2 V
DD
OH
DD
DD
DD
DD
RESET
RESET
V
DD
V
DD
= 3.3 V,
= 5 V,
I
I
= –2 mA
= –3 mA
OH
OH
– 0.4 V
– 0.3 V
– 0.4 V
– 0.2 V
– 0.3 V
V
DD
= 1.8 V,
I
= –20 µA
OH
V
DD
V
DD
= 3.3 V,
= 5 V,
I
I
= –80 µA
= –120 µA
OH
OH
V
OH
High-level output voltage
V
CEOUT
V
OUT
= 1.8 V, I
= –1 mA
V
V
OH
OUT
Enable mode
V
OUT
V
OUT
= 3.3 V, I
= 5 V,
= –2 mA
= –5 mA
OH
OH
OUT
CEIN = V
I
OUT
CEOUT
Disable mode
RESET
V
V
= 3.3 V, I
= –0.5 mA
= 400 µA
V
OUT
– 0.4 V
OUT
OH
OL
= 1.8 V,
I
0.2
0.4
0.2
0.3
DD
V
V
= 3.3 V,
= 5 V,
I
I
= 2 mA
= 3 mA
DD
DD
OL
OL
RESET
V
OL
Low-level output voltage
V
V
CEOUT
V
OUT
= 1.8 V, I
= 1.0 mA
OL
Enable mode
CEIN = 0 V
V
OUT
V
OUT
= 3.3 V, I
= 5 V,
= 2 mA
= 5 mA
OL
OL
I
V
> 1.1 V or V
> 1.1 V,
DD
= 20 µA
BAT
V
res
Power-up reset voltage (see Note 2)
0.4
I
OL
= 8.5 mA,
I
O
V
DD
– 50 mV
V
= 1.8 V,
V
V
V
= 0 V
= 0 V
= 0 V
DD
BAT
BAT
BAT
I
V
= 125 mA,
= 3.3 V,
O
DD
V
DD
– 150 mV
– 200 mV
Normal mode
I
V
= 200 mA,
= 5 V,
O
DD
V
DD
V
OUT
V
I
V
= 0.5 mA,
O
V
– 20 mV
BAT
= 1.5 V, V
= 0 V
= 0 V
BAT
DD
Battery-backup mode
I
O
= 7.5 mA,
V
BAT
– 113 mV
V
V
V
= 3.3 V, V
BAT
DD
V
V
to V
OUT
on-resistance
on-resistance
= 5 V
0.6
1
DD
DD
R
Ω
V
DS(on)
to V
OUT
= 3.3 V
8
15
BAT
BAT
Negative-going input threshold voltage
(see Note 3)
V
V
1.13
1.15
1.17
IT
Sense
1.1 V < V < 1.65 V
IT
12
55
Hysteresis
mV
hys
V
(see Note 4)
V
= 1.8 V
BSW
MR
SENSE
DD
MR = 0.7 x V , V
I
I
I
High-level input current
Low-level input current
Input current
= 5 V
DD DD
–33
–110
–25
–76
–255
25
IH
µA
nA
µA
MR = 0 V,
V
DD
= 5 V
IL
I
V
V
V
V
V
= 1.15 V
DD
= V
= V
= V
= V
40
OUT
OUT
OUT
OUT
DD
I
V supply current
DD
DD
40
BAT
DD
–0.1
0.1
0.5
±1
I
I
V
BAT
supply current
µA
BAT
BAT
CEIN leakage current
Input capacitance
Disable mode,
V = 0 V to 5 V
V < V
DD
µA
lkg
I
C
5
pF
i
I
NOTES: 2. The lowest supply voltage at which RESET becomes active. t
≥ 15 µs/V.
r,(VDD)
3. To ensure best stability of the threshold voltage, a bypass capacitor (ceramic, 0.1 µF) should be placed near to the supply terminals.
4. For V < 1.6 V, V switches to V regardless of V
DD OUT BAT BAT
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ꢖ ꢕꢏ ꢏ ꢈ ꢗ ꢏ ꢎꢀ ꢎ ꢘꢀꢔ ꢕ ꢘ
SLVS340B – DECEMBER 2000 – REVISED DECEMBER 2002
timing requirements at R = 1 MΩ, C = 50 pF, T = –40°C to 85°C
L
L
A
PARAMETER
Pulse width SENSE
TEST CONDITIONS
MIN
TYP
TYP
MAX
UNIT
t
V
= V + 0.2 V,
IT
V = V – 0.2 V
IL IT
6
µs
w
IH
switching characteristics at R = 1 MΩ, C = 50 pF, T = –40°C to 85°C
L
L
A
PARAMETER
TEST CONDITIONS
MIN
60
MAX
UNIT
V
≥ V + 0.2 V,
IT
SENSE
t
t
Delay time
MR ≥ 0.7 x V
DD
See timing diagram
,
100
140
ms
d
Propagation (delay) time,
low-to-high-level output
15
50% RESET to 50% CEOUT
50% CEIN to 50% CEOUT,
V
= V
µs
PLH
OUT IT
V
DD
V
DD
V
DD
= 1.8 V
= 3.3 V
= 5 V
5
1.6
1
15
5
ns
C
= 50 pF only (see Note 5)
L
3
Propagation (delay) time,
high-to-low-level output
V
V
= V – 0.2 V,
= V + 0.2 V
IT
2
5
IL
IH
IT
t
PHL
µs
µs
SENSE to RESET
MR to RESET
V
V
V
≥ V + 0.2 V,
IT
0.1
1
3
SENSE
IL
IH
= 0.3 x V
= 0.7 x V
,
DD
DD
V
V
V
= V
= V
< V
IT
+ 0.2 V,
– 0.2 V,
IH
IL
BAT
BAT
BAT
Transition time
V
DD
to V
BAT
µs
NOTE 5: Assured by design
8
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SLVS340B – DECEMBER 2000 – REVISED DECEMBER 2002
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
Static drain-source on-state resistance (V
Static drain-source on-state resistance (V
to V
)
vs Output current
vs Output current
3
4
DD
OUT
to V
)
r
BAT
OUT
DS(on)
Static drain-source on-state resistance (CEIN to CEOUT) vs Input voltage at CEIN
5
I
Supply current
vs Supply voltage
6
DD
V
IT
Input threshold voltage at RESET
High-level output voltage at RESET
vs Free-air temperature
7
8, 9
V
OH
vs High-level output current
10, 11, 12,
13
High-level output voltage at CEOUT
Low-level output voltage at RESET
Low-level output voltage at CEOUT
vs Low-level output current
vs Low-level output current
14, 15
16, 17
V
OL
STATIC DRAIN-SOURCE ON-STATE RESISTANCE
STATIC DRAIN-SOURCE ON-STATE RESISTANCE
(V
to V
vs
)
(V
to V
vs
)
DD
OUT
BAT
OUT
OUTPUT CURRENT
OUTPUT CURRENT
1000
900
20
17.5
15
V
V
= 3.3 V
DD
V
BAT
= 3.3 V
= GND
BAT
T
A
= 85°C
800
700
600
500
T
= 85°C
A
12.5
10
T
= 25°C
A
T
= 25°C
A
T
= 0°C
A
T
= 0°C
A
T
A
= –40°C
7.5
5
T
A
= –40°C
50
75
100
125
150
175
200
2.5
4.5
6.5
8.5
10.5
12.5
14.5
I
O
– Output Current – mA
I
O
– Output Current – mA
Figure 3
Figure 4
9
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ꢖ ꢕꢏ ꢏ ꢈ ꢗ ꢏ ꢎꢀ ꢎ ꢘꢀꢔ ꢕ ꢘ
SLVS340B – DECEMBER 2000 – REVISED DECEMBER 2002
TYPICAL CHARACTERISTICS
STATIC DRAIN-SOURCE ON-STATE RESISTANCE
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
(CEIN to CEOUT)
vs
INPUT VOLTAGE AT CEIN
40
35
30
25
20
15
10
5
V
V
Mode
= 2.6 V
V
Mode
DD
BAT
BAT
or
V
BAT
= GND
T
= 85°C
A
T
= 25°C
A
30
25
T
A
= 0°C
T
= 25°C
A
T
= 85°C
A
20
15
10
T
= 0°C
A
T
= –40°C
A
T
= –40°C
A
I
V
= 5 mA
CEOUT
= 5 V
DD
5
0
0
0
1
2
3
4
5
0
1
2
3
4
5
6
V
– Input Voltage at CEIN – V
I(CEIN)
V
DD
– Supply Voltage – V
Figure 5
Figure 6
INPUT THRESHOLD VOLTAGE AT RESET
vs
FREE-AIR TEMPERATURE
1.001
1
0.999
0.998
0.997
0.996
0.995
–40 –30 –20 –10
0 10 20 30 40 50 60 70 80
T
A
– Free-Air Temperature – °C
Figure 7
10
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SLVS340B – DECEMBER 2000 – REVISED DECEMBER 2002
TYPICAL CHARACTERISTICS
HIGH-LEVEL OUTPUT VOLTAGE AT RESET
HIGH-LEVEL OUTPUT VOLTAGE AT RESET
vs
vs
HIGH-LEVEL OUTPUT CURRENT
HIGH-LEVEL OUTPUT CURRENT
5.1
5
6
5
4
3
2
1
V
V
= 5 V
DD
Expanded View
= GND
BAT
T
= –40°C
A
T
= –40°C
A
T
= 25°C
A
4.9
T
A
= 25°C
T
= 0°C
A
T
A
= 0°C
4.8
4.7
T
= 85°C
A
T
= 85°C
A
4.6
4.5
V
V
= 5 V
= GND
DD
BAT
0
–35
–5 –4.5 –4 –3.5 –3 –2.5 –2 –1.5 –1 –0.5
0
–30
–25
–20
–15
–10
–5
0
I – High-Level Output Current – mA
OH
I
– High-Level Output Current – mA
OH
Figure 8
Figure 9
HIGH-LEVEL OUTPUT VOLTAGE AT CEOUT
HIGH-LEVEL OUTPUT VOLTAGE AT CEOUT
vs
vs
HIGH-LEVEL OUTPUT CURRENT
HIGH-LEVEL OUTPUT CURRENT
3.5
3.35
3.30
3.25
3.20
V
V
= 3.3 V
V
= 3.3 V
(CEIN)
Expanded View
Enable Mode
Enable Mode
(CEIN)
= 5 V
V
DD
= 5 V
DD
3
2.5
2
T
A
= –40°C
T
= –40°C
A
T
A
= 0°C
= 25°C
T
A
T
A
= 25°C
T
A
= 0°C
1.5
1
T
A
= 85°C
T
A
= 85°C
3.15
3.10
0.5
0
–5 –4.5 –4 –3.5 –3 –2.5 –2 –1.5 –1 –0.5
0
–150 –130 –110 –90
–70
–50 –30
–10
I
– High-Level Output Current – mA
I
– High-Level Output Current – mA
OH
OH
Figure 10
Figure 11
11
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ꢖ ꢕꢏ ꢏ ꢈ ꢗ ꢏ ꢎꢀ ꢎ ꢘꢀꢔ ꢕ ꢘ
SLVS340B – DECEMBER 2000 – REVISED DECEMBER 2002
TYPICAL CHARACTERISTICS
HIGH-LEVEL OUTPUT VOLTAGE AT CEOUT
HIGH-LEVEL OUTPUT VOLTAGE AT CEOUT
vs
vs
HIGH-LEVEL OUTPUT CURRENT
HIGH-LEVEL OUTPUT CURRENT
3.5
3.4
3.3
3.2
3.1
3.5
V
V
= Open
= 1.65 V
Expanded View
Disable Mode
(CEIN)
DD
3
T
A
= –40°C
T = –40°C
A
2.5
T
= 25°C
A
T
A
= 25°C
T
A
= 0°C
2
T
A
= 0°C
1.5
T
= 85°C
A
3
2.9
2.8
2.7
T
A
= 85°C
1
0.5
0
Disable Mode
= Open
V
V
(CEIN)
= 1.65 V
DD
–1 –0.9 –0.8 –0.7 –0.6 –0.5 –0.4 –0.3 –0.2 –0.1
0
–4.5 –4 –3.5 –3 –2.5 –2 –1.5 –1 –0.5
0
I – High-Level Output Current – mA
OH
I
– High-Level Output Current – mA
OH
Figure 12
Figure 13
LOW-LEVEL OUTPUT VOLTAGE AT RESET
LOW-LEVEL OUTPUT VOLTAGE AT RESET
vs
vs
LOW-LEVEL OUTPUT CURRENT
LOW-LEVEL OUTPUT CURRENT
500
400
300
200
100
0
3.5
3
Expanded View
V
V
= 3.3 V
= GND
DD
BAT
T = 85°C
A
V
V
= 3.3 V
DD
= GND
BAT
2.5
2
T
A
= 25°C
T
= 0°C
A
T
A
= 0°C
T
A
= 25°C
1.5
1
T
A
= 85°C
T
= –40°C
A
T
= –40°C
A
0.5
0
1
2
3
4
5
0
0
5
10
15
20
25
I – Low-Level Output Current – mA
OL
I
– Low-Level Output Current – mA
OL
Figure 14
Figure 15
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SLVS340B – DECEMBER 2000 – REVISED DECEMBER 2002
TYPICAL CHARACTERISTICS
LOW-LEVEL OUTPUT VOLTAGE AT CEOUT
LOW-LEVEL OUTPUT VOLTAGE AT CEOUT
vs
vs
LOW-LEVEL OUTPUT CURRENT
LOW-LEVEL OUTPUT CURRENT
140
120
3.5
3
V
V
= GND
Enable Mode
Expanded View
(CEIN)
= 5 V
Enable Mode
DD
V
V
= GND
(CEIN)
= 5 V
DD
T
A
= 85°C
2.5
2
100
80
T
= 85°C
A
T
= 25°C
A
T
A
= 25°C
T
A
= 0°C
T
A
= 0°C
60
1.5
1
T
A
= –40°C
T
A
= –40°C
40
20
0
0.5
0
0
1
2
3
4
5
10 20 30 40 50 60 70 80 90 100
0
I – Low-Level Output Current – mA
OL
I
– Low-Level Output Current – mA
OL
Figure 16
Figure 17
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SLVS340B – DECEMBER 2000 – REVISED DECEMBER 2002
MECHANICAL DATA
DGS (S-PDSO-G10)
PLASTIC SMALL-OUTLINE PACKAGE
0,27
M
0,25
0,50
0,17
10
6
0,15 NOM
3,05
2,95
4,98
4,78
Gage Plane
0,25
0°–ā6°
1
5
0,69
0,41
3,05
2,95
Seating Plane
0,10
0,15
0,05
1,07 MAX
4073272/A 03/98
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion.
14
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