概述
规格参数
数据手册
替代型号TPS3618-50DGKR 概述
BATTERY-BACKUP SUPERVISOR FOR RAM RETENTION 电池备份监督员RAM保持 电源监控芯片 电源管理电路
TPS3618-50DGKR 规格参数
| 是否Rohs认证： | 符合 | 生命周期： | Obsolete |
| 零件包装代码： | MSOP | 包装说明： | 3.05 X 4.98 MM, GREEN, PLASTIC, VSSOP-8 |
| 针数： | 8 | Reach Compliance Code： | unknown |
| ECCN代码： | EAR99 | HTS代码： | 8542.39.00.01 |
| Factory Lead Time： | 1 week | 风险等级： | 5.44 |
| Is Samacsys： | N | 其他特性： | RESET THRESHOLD VOLTAGE IS 4.55V; POWER ON RESET GENERATOR |
| 可调阈值： | NO | 模拟集成电路 - 其他类型： | POWER SUPPLY MANAGEMENT CIRCUIT |
| JESD-30 代码： | S-PDSO-G8 | 长度： | 3 mm |
| 信道数量： | 1 | 功能数量： | 1 |
| 端子数量： | 8 | 最高工作温度： | 85 °C |
| 最低工作温度： | -40 °C | 封装主体材料： | PLASTIC/EPOXY |
| 封装代码： | TSSOP | 封装等效代码： | TSSOP8,.19 |
| 封装形状： | SQUARE | 封装形式： | SMALL OUTLINE, THIN PROFILE, SHRINK PITCH |
| 峰值回流温度（摄氏度）： | NOT SPECIFIED | 电源： | 1.8/5 V |
| 认证状态： | Not Qualified | 座面最大高度： | 1.1 mm |
| 子类别： | Power Management Circuits | 最大供电电流 (Isup)： | 0.04 mA |
| 最大供电电压 (Vsup)： | 5.5 V | 最小供电电压 (Vsup)： | 1.65 V |
| 标称供电电压 (Vsup)： | 5 V | 表面贴装： | YES |
| 温度等级： | INDUSTRIAL | 端子形式： | GULL WING |
| 端子节距： | 0.65 mm | 端子位置： | DUAL |
| 处于峰值回流温度下的最长时间： | NOT SPECIFIED | 宽度： | 3 mm |
| Base Number Matches： | 1 |
TPS3618-50DGKR 数据手册
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PDF下载TPS3617
TPS3618
www.ti.com
SLVS339C–DECEMBER 2000–REVISED NOVEMBER 2004
BATTERY-BACKUP SUPERVISOR FOR RAM RETENTION
FEATURES
DESCRIPTION
•
•
•
Supply Current of 40 µA (Max)
The TPS3617 and TPS3618 are battery-backup
supervisors that monitor 5 V supplies. They provide a
battery-backup function ideal for applications that
require data retention of CMOS RAM during fault
conditions. When the voltage at VDD drops below a
preset threshold (VIT), the active low push-pull
RESET output asserts, and VOUT switches from VDD
to VBAT. When VDD rises above the trip threshold,
Battery Supply Current of 100 nA (Max)
Precision 5-V Supply Voltage Monitor, Other
Voltage Options on Request
•
•
•
Backup-Battery Voltage Can Exceed VDD
Watchdog Timer With 800-ms Time-Out
Power-On Reset Generator With Fixed 100-ms
Reset Delay Time
VOUT switches immediately from VBAT to VDD
.
The RESET output remains low until the delay time
(td) expires. During power on, RESET is asserted
when the supply voltage (VDD or VBAT) goes higher
than 1.1 V.
•
Voltage Monitor for Power-Fail or Low-Battery
Monitoring
•
•
•
Battery Freshness Seal (TPS3617 Only)
8-Pin MSOP Package
The PFI and PFO pins are provided if additional
voltage monitoring is needed. If the voltage at PFI is
less than 1.15 V, the push-pull PFO pin will assert
low. When the voltage at PFI exceeds the threshold
voltage, PFO will go high.
Temperature Range: -40°C to 85°C
APPLICATIONS
•
•
•
•
•
•
•
•
•
Fax Machines
Set-Top Boxes
Advanced Voice Mail Systems
Portable Battery Powered Equipment
Computer Equipment
Advanced Modems
Automotive Systems
Portable Long-Time Monitoring Equipment
Point-of-Sale Equipment
These devices also feature a watchdog timer pin
(WDI) that monitors processor activity and asserts
RESET if the the processor is inactive longer than the
watchdog timeout period. If the watchdog timer is not
used, the WDI pin should be left floating.
The TPS3617 and TPS3618 are available in an 8-pin
MSOP package and are characterized for operation
over a temperature range of -40°C to 85°C.
Power
Supply
TPS3617
TPS3618
Microcontroller
or
Microprocessor
MSOP (DGK) Package
Backup
Battery
0.1 µF
(TOP VIEW)
V
V
BAT
DD
V
V
V
BAT
RESET
WDI
OUT
External
Source
DD
GND
PFI
RESET
I/O
RESET
WDI
PFO
R
R
x
PFI
I/O
PFO
Switchover
Capacitor
y
ACTUAL SIZE
3,05 mm x 4,98 mm
V
OUT
V
CC
0.1 µF
GND
GND
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2000–2004, Texas Instruments Incorporated
TPS3617
TPS3618
www.ti.com
SLVS339C–DECEMBER 2000–REVISED NOVEMBER 2004
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated
circuits be handled with appropriate precautions. Failure to observe proper handling and installation
procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision
integrated circuits may be more susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.
PACKAGE INFORMATION(1)
NOMINAL
SUPPLY
VOLTAGE
SPECIFIED
TEMPERATURE
RANGE
THRESHOLD
PACKAGE
MARKING
ORDERING
NUMBER
TRANSPORT MEDIA,
QUANTITY
PRODUCT
VOLTAGE (VIT)(2)
TPS3617-50DGK
TPS3617-50DGKR
TPS3618-50DGKT
TPS3618-50DGKR
Tube, 80
TPS3617-50
ASD
ANK
Tape and Reel, 2500
Tape and Reel, 250
Tape and Reel, 2500
5V
4.55V
-40°C to +125°C
TPS3618-50
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this data sheet, or refer to our
web site at www.ti.com.
(2) For other threshold votages, contact the local TI sales office for availability and lead time.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature (unless otherwise noted)(1)
TPS3617, TPS3618
UNIT
V
Input voltage range, VDD
-0.3 to 7
Input voltage range, PFI pin
Continuous output current at VOUT, IO
All other pins, IO
-0.3 to (VDD + 0.3)
V
400
mA
mA
°C
±10
(2)
Operating junction temperature range, TJ
Storage temperature range, TSTG
-40 to +85
-65 to +150
°C
Lead temperature soldering 1,6 mm (1/16 inch) from case for 10 seconds
Continuous total power dissipation
+260
°C
See Dissipation Rating Table
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Due to the low dissipated power in this device, it is assumed that TJ = TA.
DISSIPATION RATING TABLE
TA ≤ 25°C
DERATING FACTOR
TA = 70°C
TA = 85°C
PACKAGE
POWER RATING
ABOVE TA = 25°C
POWER RATING
POWER RATING
DGK
470 mW
3.76 mW/°C
301 mW
241 mW
2
TPS3617
TPS3618
www.ti.com
SLVS339C–DECEMBER 2000–REVISED NOVEMBER 2004
ELECTRICAL CHARACTERISTICS
1.65 V ≤ VDD≤ 5.5 V, RLRESET = 1 MΩ, CLRESET = 50 pF, over operating temperature range (TJ = -40°C to +85°C), unless
otherwise noted. Typical values are at TJ = 25°C.
PARAMETER
Input supply range
TEST CONDITIONS
MIN
TYP
MAX
5.5
UNIT
VDD
IDD
VBAT
IBAT
1.65
V
VOUT = VDD
VOUT = VBAT
40
VDD supply current
Battery supply range
VBAT supply current
µA
V
40
1.5
5.5
VOUT = VDD
VOUT = VBAT
-0.1
0.1
µ A
0.5
Slew rate at VDD or VBAT
Input volrage, any input
1
V/µs
V
VI
0
VDD + 0.3
VDD = 1.8 V, IOH = -400 µA
VDD - 0.2
RESET
VDD = 3.3 V, IOH = -2 mA,
VDD = 5 V, IOH = -3 mA
VDD - 0.4
VDD - 0.3
VDD - 0.4
VOH
High-level output voltage
V
VDD = 1.8 V, IOH = -20 µA
PFO
VDD = 3.3 V, IOH = -80 µA,
VDD = 5 V, IOH = -120 µA
VDD = 1.8 V, IOL = 400 µA
0.2
0.4
VOL
Low-level output voltage
RESET PFO
V
V
VDD = 3.3 V, IOL = 2 mA,
VDD = 5 V, IOL = 3 mA
VBAT > 1.1 V, or VDD > 1.1 V,
IOL = 20 µA
(1)
VRES
Power-up reset voltage
Normal mode
0.4
IO = 8.5 mA,VDD = 1.8 V, VBAT = 0 V
IO = 125 mA,VDD = 3.3 V, VBAT = 0 V
IO = 200 mA,VDD = 5 V, VBAT = 0 V
IO = 0.5 mA,VBAT = 1.5 V, VDD = 0 V
IO = 7.5 mA,VBAT = 3.3 V, VDD = 0 V
VDD = 5 V
VDD - 0.050
VDD - 0.150
VDD - 0.200
VBAT - 0.200
VBAT - 0.113
VOUT
V
Battery-backup mode
VDD to VOUT on-resistance
VBAT to VOUT on-resistance
0.6
8
1
RDS(on)
Ω
VBAT = 3.3 V
15
IO
Continuous output current at VOUT
300
mA
V
VIT
VPFI
TPS3617-50
4.46
1.13
4.55
1.15
20
Negative-going input
threshold voltage
TA = -40°C to 85°C
(2)
PFI
1.17
V
1.65 V < VIT < 2.5 V
2.5 V < VIT < 3.5 V
3.5 V < VIT < 5.5 V
VIT hysteresis
PFI hysteresis
40
VHYS
60
mV
12
(3)
VBSW hysteresis
VDD = 1.8 V
55
VIH
VIL
IIH
WDI high-level input voltage
WDI low-level input voltage
WDI high-level input current
0.7 x VDD
0.3 x VDD
150
(4)
WDI = VDD = 5 V
µA
µA
(4)
IIL
WDI low-level input current
WDI = 0 V, VDD = 5 V
-150
100
WDI input transition rise and fall rate, ∆t/∆V
ns/V
nA
II
PFI input current
PFI voltage < VDD
-25
25
PFO = 0 V, VDD = 1.8 V
PFO = 0 V, VDD = 3.3 V
PFO = 0 V, VDD = 5 V
-0.3
IOS
PFO short-circuit current
-1.1
mA
-2.4
(1) The lowest supply voltage at which RESET becomes active. tr, VDD ≥ 15 µs/V.
(2) To ensure the best stability of the threshold voltage, a bypass capacitor (ceramic, 0.1 µF) should be placed near the supply terminals.
(3) For VDD < 1.6 V, VOUT switches to VBAT regardless of VBAT
(4) For details on how to optimize current consumption when using WDI, refer to the Watchdog section of this data sheet.
.
3
TPS3617
TPS3618
www.ti.com
SLVS339C–DECEMBER 2000–REVISED NOVEMBER 2004
ELECTRICAL CHARACTERISTICS (continued)
1.65 V ≤ VDD≤ 5.5 V, RLRESET = 1 MΩ, CLRESET = 50 pF, over operating temperature range (TJ = -40°C to +85°C), unless
otherwise noted. Typical values are at TJ = 25°C.
PARAMETER
TEST CONDITIONS
VI = 0 V to 5 V
MIN
TYP
MAX
UNIT
pF
Ci
tw
Input capacitance, any input
5
VDD
VIH = VIT + 0.2 V, VIL = VIT - 0.2 V
6
µs
Pulse Width
VDD > VIT + 0.2 V, VIL = 0.3 x VDD
VIH = 0.7 x VDD
,
WDI
100
ns
ms
s
td
VDD ≥ VIT + 0.2 V,
See timing diagram
Delay time
60
100
0.8
2
140
1.12
5
t(tout)
VDD > VIT + 0.2 V,
See timing diagram
Watchdog time-out
0.48
VIL = VIT - 0.2 V,
VIH = VIT + 0.2 V
VDD to RESET
Propagation (delay) time,
high-to-low-level output
tPHL
µs
µs
VIL = VPFI - 0.2 V,
VIH = VPFI + 0.2 V
PFI to PFO
VDD to VBAT
3
5
3
Transition time
TIMING DIAGRAM
V
BAT
V
DD
V
IT
t
t
t
V
OUT
RESET
t
d
t
d
FUNCTION TABLE
VDD > VIT
VDD > VBAT
VOUT
VBAT
VDD
RESET
0
0
1
1
0
1
0
1
0
0
1
1
VDD
VDD
4
TPS3617
TPS3618
www.ti.com
SLVS339C–DECEMBER 2000–REVISED NOVEMBER 2004
PFO FUNCTION TABLE
PFI > VPFI
PFO
0
1
0
1
CONDITION: VDD > VDD(MIN)
TERMINAL FUNCTIONS
TERMINAL
NAME
GND
NO.
I/O
I
DESCRIPTION
3
4
5
7
8
2
1
6
Ground
PFI
I
Power-fail comparator input
PFO
RESET
VBAT
VDD
O
O
I
Power-fail comparator output; asserts low when PFI < 1.15 V
Active-low push-pull reset output
Backup-battery input
I
Input supply voltage
VOUT
WDI
O
I
Supply output
Watchdog input. Should be left floating if not used.
FUNCTIONAL BLOCK DIAGRAM
TPS3617
TPS3618
V
BAT
+
Switch
Control
V
OUT
_
V
DD
Reference
Voltage
or 1.15 V
RESET
Logic
+
RESET
+
_
Timer
GND
Oscillator
−
+
PFO
PFI
Watchdog
Logic
+
Transition
Detector
WDI
Control
40 kΩ
5
TPS3617
TPS3618
www.ti.com
SLVS339C–DECEMBER 2000–REVISED NOVEMBER 2004
TYPICAL CHARACTERISTICS
TABLE OF GRAPHS
FIGURE
Static drain-source on-state resistance (VDD to VOUT
)
Static drain-source on-state resistance (VBAT to VOUT
Supply current
vs Output current
vs Output current
vs Supply voltage
vs Free-air temperature
3
4
rDS(on)
)
IDD
VIT
5
Input threshold voltage at RESET
High-level output voltage at RESET
High-level output voltage at PFO
Low-level output voltage at RESET
Minimum pulse duration at VDD
6
7, 8
9, 10
11, 12
13
VOH
VOL
vs High-level output current
vs Low-level output current
vs Threshold voltage overdrive at VDD
vs Threshold voltage overdrive at PFI
Minimum pulse duration at PFI
14
STATIC DRAIN-SOURCE ON-STATE RESISTANCE
STATIC DRAIN-SOURCE ON-STATE RESISTANCE
(VDD to VOUT
vs
)
(VBAT to VOUT
vs
)
OUTPUT CURRENT
OUTPUT CURRENT
20
17.5
15
1000
900
800
700
V
BAT
= 3.3 V
V
V
= 3.3 V
DD
= GND
BAT
T
= 85°C
A
T
A
= 85°C
12.5
10
T
A
= 25°C
T
A
= 25°C
T
= 0°C
A
T
= 0°C
A
T
= −40°C
A
600
500
7.5
5
T
A
= −40°C
2.5
4.5
6.5
8.5
10.5
12.5
14.5
50
75
100
125
150
175
200
I
O
− Output Current − mA
I
O
− Output Current − mA
Figure 1.
Figure 2.
6
TPS3617
TPS3618
www.ti.com
SLVS339C–DECEMBER 2000–REVISED NOVEMBER 2004
SUPPLY CURRENT
vs
SUPPLE VOLTAGE
INPUT THRESHOLD VOLTAGE AT RESET
vs
FREE-AIR TEMPERATURE
1.001
1
30
V
V
Mode
= 2.6 V
V
Mode
DD
BAT
BAT
V
BAT
= GND
or
25
20
15
10
5
T
A
= 0°C
0.999
0.998
0.997
T
= 25°C
A
T
A
= 85°C
T
= −40°C
A
0.996
0.995
0
−40 −30 −20 −10
0 10 20 30 40 50 60 70 80
0
1
2
3
4
5
6
T
A
− Free-Air Temperature − °C
V
DD
− Supply Voltage − V
Figure 3.
Figure 4.
HIGH-LEVEL OUTPUT VOLTAGE AT RESET
vs
HIGH-LEVEL OUTPUT CURRENT
6
5
4
3
2
1
0
V
V
= 5 V
DD
= GND
BAT
T
= −40°C
A
T
= 25°C
A
T
= 0°C
A
T
A
= 85°C
−35
−30
−25
−20
−15
−10
−5
0
I
− High-Level Output Current − mA
OH
Figure 5.
7
TPS3617
TPS3618
www.ti.com
SLVS339C–DECEMBER 2000–REVISED NOVEMBER 2004
HIGH-LEVEL OUTPUT VOLTAGE AT RESET
HIGH-LEVEL OUTPUT VOLTAGE AT PFO
vs
vs
HIGH-LEVEL OUTPUT CURRENT
HIGH-LEVEL OUTPUT CURRENT
5.1
6
5
4
3
2
1
Expanded View
5
T
A
= −40°C
T
= −40°C
A
T
A
= 25°C
4.9
4.8
4.7
T
A
= 25°C
T = 0°C
A
T
A
= 0°C
T
A
= 85°C
T
A
= 85°C
V
DD
= 5.5 V
4.6
4.5
PFI = 1.4 V
= GND
V
V
= 5 V
DD
V
BAT
= GND
BAT
0
−2.5
−5 −4.5 −4 −3.5 −3 −2.5 −2 −1.5 −1 −0.5
0
−2
−1.5
−1
−0.5
0
I
− High-Level Output Current − mA
I
− High-Level Output Current − mA
OH
OH
Figure 6.
Figure 7.
HIGH-LEVEL OUTPUT VOLTAGE AT PFO
LOW-LEVEL OUTPUT VOLTAGE AT RESET
vs
vs
HIGH-LEVEL OUTPUT CURRENT
LOW-LEVEL OUTPUT CURRENT
3.5
3
5.55
5.50
5.45
5.40
5.35
5.30
5.25
5.20
Expanded View
V
V
= 3.3 V
DD
= GND
BAT
T
A
= −40°C
T
= 25°C
A
2.5
2
T
A
= 0°C
T
= 0°C
A
T
A
= 25°C
1.5
1
T
A
= 85°C
T
= 85°C
A
T
= −40°C
A
V
= 5.5 V
DD
0.5
0
PFI = 1.4 V
= GND
5.15
5.10
V
BAT
0
5
10
15
20
25
−200 −180−160−140 −120−100 −80 −60 −40 −20
0
I
− Low-Level Output Current − mA
I
− High-Level Output Current − µA
OL
OH
Figure 8.
Figure 9.
8
TPS3617
TPS3618
www.ti.com
SLVS339C–DECEMBER 2000–REVISED NOVEMBER 2004
LOW-LEVEL OUTPUT VOLTAGE AT RESET
MINIMUM PULSE DURATION AT VDD
vs
vs
LOW-LEVEL OUTPUT CURRENT
THRESHOLD VOLTAGE OVERDRIVE AT VDD
500
400
300
200
100
0
10
9
Expanded View
T
= 85°C
A
V
V
= 3.3 V
DD
8
= GND
BAT
7
T
A
= 25°C
6
T
A
= 0°C
5
4
3
2
T
= −40°C
A
1
0
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
1
1
2
3
4
5
0
I
− Low-Level Output Current − mA
Threshold Voltage Overdrive at V − V
DD
OL
Figure 10.
Figure 11.
MINIMUM PULSE DURATION AT PFI
vs
THRESHOLD VOLTAGE OVERDRIVE AT PFI
5
4.6
V
DD
= 1.65 V
4.2
3.8
3.4
3
2.6
2.2
1.8
1.4
1
0.6
1
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
Threshold Voltage Overdrive at PFI − V
Figure 12.
9
TPS3617
TPS3618
www.ti.com
SLVS339C–DECEMBER 2000–REVISED NOVEMBER 2004
DETAILED DESCRIPTION
BATTERY FRESHNESS SEAL (TPS3617 Only)
The battery freshness seal of the TPS3617 family disconnects the backup battery from the internal circuitry until
it is needed. This ensures that the backup battery connected to VBAT should be fresh when the final product is
put to use. The following steps explain how to enable the freshness seal mode:
1. Connect VBAT (VBAT> VBAT(min)).
2. Ground PFO.
3. Connect PFI to VDD (PFI = VDD).
4. Connect VDD to power supply (VDD > VIT) and keep connected for 5 ms < t < 35 ms.
The battery freshness seal mode is disabled by the positive-going edge of RESET when VDD is applied.
POWER-FAIL COMPARATOR (PFI AND PFO)
An additional comparator monitors voltages other than the nominal supply voltage. The power-fail-input (PFI) can
be compared with an internal voltage reference of 1.15 V. If the input voltage falls below the power-fail threshold
(V(PFI)) of 1.15 V typical, the power-fail output (PFO) goes low. If it goes above V(PFI) plus about 12-mV
hysteresis, the output returns to high. By connecting two external resistors it is possible to supervise any voltages
above V(PFI). The sum of both resistors should be about 1 MΩ, to minimize power consumption and also to
ensure that the current in the PFI pin can be neglected compared with the current through the resistor network.
The tolerance of the external resistors should be not more than 1% to ensure minimal variation of the sensed
voltage. If the power-fail comparator is unused, connect PFI to ground and leave the PFO unconnected.
WATCHDOG
In a microprocessor- or DSP-based system, it is not only important to supervise the supply voltage, it is also
important to ensure correct program execution. The task of a watchdog is to ensure that the program is not
stalled in an indefinite loop. The microprocessor, microcontroller, or DSP has to toggle the watchdog input within
0.8 s typically, to avoid a timeout from occurring. Either a low-to-high or a high-to-low transition resets the
internal watchdog timer. If the input is unconnected, the watchdog is disabled and should be retriggered
internally. See Figure 13 for the watchdog timing diagram.
V
OUT
V
IT
WDI
t
(tout)
RESET
t
d
t
d
t
d
Undefined
Figure 13. Watchdog Timing
10
TPS3617
TPS3618
www.ti.com
SLVS339C–DECEMBER 2000–REVISED NOVEMBER 2004
DETAILED DESCRIPTION (continued)
SAVING CURRENT WHILE USING THE WATCHDOG
The watchdog input is internally driven low during the first 7/8 of the watchdog time-out period, then momentarily
pulses high, resetting the watchdog counter. For minimum watchdog input current (minimum overall power
consumption), leave WDI low for the majority of the watchdog time-out period, pulsing it low-high-low once within
7/8 of the watchdog time-out period to reset the watchdog timer. If instead, WDI is externally driven high for the
majority of the time-out period, a current of e.g. 5.0 V/40 kΩ ≈ 125 µA can flow into WDI.
BACKUP-BATTERY SWITCHOVER
In case of a brownout or power failure, it may be necessary to preserve the contents of RAM. If a backup battery
is installed at VBAT, the device automatically switches the connected RAM to backup power when VDD fails. In
order to allow the backup battery (e.g., a 3.6-V lithium cell) to have a higher voltage than VDD, these supervisors
should not connect VBAT to VOUT when VBAT is greater than VDD. VBAT only connects to VOUT (through a 15-Ω
switch) when VDD falls below VIT and VBAT is greater than VDD. When VDD recovers, switchover is deferred either
until VDD crosses VBAT, or until VDD rises above the reset threshold VIT. VOUT connects to VDD through a 1-Ω
(max) PMOS switch when VDD crosses the reset threshold.
FUNCTION TABLE
VDD> VBAT
VDD> VIT
VOUT
VDD
1
1
0
0
1
0
1
0
VDD
VDD
VBAT
V
DD
– Mode
V
IT
Hysteresis
V
BAT
– Mode
VBSW Hysteresis
Undefined
V
BAT
– Backup-Battery Supply Voltage
Figure 14. VDD - VBAT Switchover
11
PACKAGE OPTION ADDENDUM
www.ti.com
8-Feb-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
MSOP
MSOP
MSOP
MSOP
Drawing
TPS3617-50DGK
TPS3617-50DGKR
TPS3618-50DGKR
TPS3618-50DGKT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
DGK
8
8
8
8
80
None
None
None
None
CU NIPDAU Level-1-220C-UNLIM
CU NIPDAU Level-1-220C-UNLIM
CU NIPDAU Level-1-220C-UNLIM
CU NIPDAU Level-1-220C-UNLIM
DGK
2500
2500
250
DGK
DGK
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional
product content details.
None: Not yet available Lead (Pb-Free).
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
IMPORTANT NOTICE
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TI warrants performance of its hardware products to the specifications applicable at the time of sale in
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Copyright 2005, Texas Instruments Incorporated
TPS3618-50DGKR CAD模型
引脚图
封装焊盘图
TPS3618-50DGKR 替代型号
| 型号 | 制造商 | 描述 | 替代类型 | 文档 |
| TPS3618-50DGKRG4 | TI | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO8, 3.05 X 4.98 MM, GREEN, PLASTIC, MSOP-8 | 完全替代 |
|
| TPS3618-50DGKT | TI | BATTERY-BACKUP SUPERVISOR FOR RAM RETENTION | 功能相似 |
|
| TPS3618-50DGKTG4 | TI | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO8, 3.05 X 4.98 MM, GREEN, PLASTIC, MSOP-8 | 功能相似 |
|
TPS3618-50DGKR 相关器件
| 型号 | 制造商 | 描述 | 价格 | 文档 |
| TPS3618-50DGKRG4 | TI | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO8, 3.05 X 4.98 MM, GREEN, PLASTIC, MSOP-8 | 获取价格 |
|
| TPS3618-50DGKT | TI | BATTERY-BACKUP SUPERVISOR FOR RAM RETENTION | 获取价格 |
|
| TPS3618-50DGKTG4 | TI | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO8, 3.05 X 4.98 MM, GREEN, PLASTIC, MSOP-8 | 获取价格 |
|
| TPS3619 | TI | 适用于 RAM 保持模式的电池备份监控器 | 获取价格 |
|
| TPS3619-33 | TI | BACKUP-BATTERY SUPERVISORS FOR RAM RETENTION | 获取价格 |
|
| TPS3619-33-EP | TI | BACKUP-BATTERY SUPERVISORS FOR RAM RETENTION | 获取价格 |
|
| TPS3619-33DGK | TI | BACKUP-BATTERY SUPERVISORS FOR RAM RETENTION | 获取价格 |
|
| TPS3619-33DGKG4 | TI | BACKUP-BATTERY SUPERVISORS FOR RAM RETENTION | 获取价格 |
|
| TPS3619-33DGKR | TI | BACKUP-BATTERY SUPERVISORS FOR RAM RETENTION | 获取价格 |
|
| TPS3619-33DGKRG4 | TI | BACKUP-BATTERY SUPERVISORS FOR RAM RETENTION | 获取价格 |
|
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