TPS3702AX33DDCT [TI]
用于过压和欠压监测的高精度窗口电压检测器 | DDC | 6 | -40 to 125;型号: | TPS3702AX33DDCT |
厂家: | TEXAS INSTRUMENTS |
描述: | 用于过压和欠压监测的高精度窗口电压检测器 | DDC | 6 | -40 to 125 |
文件: | 总27页 (文件大小:978K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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TPS3702
ZHCSD99 –JANUARY 2015
TPS3702 高精度、过压和欠压监视器
1 特性
3 说明
1
•
•
输入电压范围:2V 至 18V
高阈值精度:
TPS3702 是一款集成型过压和欠压窗口检测器,其采
用小型 SOT-6 封装。 这款高精度电压监视器非常适合
电源容限较窄且由低压电源轨供电运行的系统。 该器
件提供有 0.55% 和 1.0% 两个低阈值滞后选项,可防
止在受监视电源电压处于其标称工作范围内时出现错误
的复位信号。 并且内置有毛刺抑制功能和噪声滤波
器,进一步消除了错误信号所导致的错误复位。
–
–
0.25%(典型值)
0.9%(–40°C 至 125°C)
•
已针对 1V 和 5V 之间的标称电源轨优化的固定窗
口阈值
•
•
•
•
•
•
用于过压和欠压指示的开漏输出
内部毛刺抑制功能
TPS3702 无需使用任何外部电阻即可设置过压和欠压
复位阈值,因此进一步提高了总体精度、减小了解决方
案尺寸并降低了解决方案的成本。 每款器件的两种可
用阈值电压可使用 SET 引脚进行选择。 独立的
SENSE 输入引脚和 VDD 引脚可满足安全关键型和高
可靠性系统对于冗余的需求。 该器件还为 OV 和 UV
引脚提供了独立复位输出;可采用开漏配置将 UV 和
OV 引脚连接在一起。
可使用 SET 引脚调整阈值
低静态电流:7µA(典型值)
内部阈值滞后:0.55% 和 1.0%
小外形尺寸晶体管 (SOT)-6 封装
2 应用范围
•
现场可编程门阵列 (FPGA) 和特定用途集成电路
(ASIC) 应用
•
•
•
•
•
•
基于数字信号处理器 (DSP) 的系统
工业控制系统
该器件的静态电流典型值较低 (7µA),经测试能够在工
业温度范围(–40°C 至 125°C)内工作。
工厂自动化
器件信息(1)
个人电子产品
器件型号
TPS3702
封装
封装尺寸(标称值)
楼宇自动化
SOT (6)
2.90mm x 1.60mm
电机驱动器
(1) 如需了解所有可用封装,请见数据表末尾的可订购产品附录。
Undervoltage Accuracy vs Temperature
0.5
Unitꢀ1
Unitꢀ4
Unitꢀ2
Unitꢀ5
Unitꢀ3
Avg
0.4
0.3
0.2
0.1
0
典型应用电路
Nominal Monitored Rail
Up to 5 V
-0.1
-0.2
-0.3
-0.4
-0.5
R2
R1
TPS3702
SENSE
Up to
18 V
VDD
40 25ꢀ 10
5
20 35 50 65 80 95 110 125 140
UV
RST
NMI
Temperature (°C)
Overvoltage Accuracy vs Temperature
VDD
SET
GND
0.5
0.4
0.3
0.2
0.1
0
µ
P
Unitꢀ1
Unitꢀ4
Unitꢀ2
Unitꢀ5
Unitꢀ3
Avg
Up to
6.5 V
OV
-0.1
-0.2
-0.3
-0.4
-0.5
40ꢀ 25ꢀ 10
5
20 35 50 65 80 95 110 125 140
C001
Temperature (°C)
1
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
English Data Sheet: SBVS251
TPS3702
ZHCSD99 –JANUARY 2015
www.ti.com.cn
目录
7.3 Feature Description................................................. 11
7.4 Device Functional Modes........................................ 12
Application and Implementation ........................ 13
8.1 Application Information............................................ 13
8.2 Typical Application ................................................. 17
Power Supply Recommendations...................... 19
1
2
3
4
5
6
特性.......................................................................... 1
应用范围................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics........................................... 5
6.6 Timing Requirements................................................ 6
6.7 Typical Characteristics.............................................. 7
Detailed Description ............................................ 10
7.1 Overview ................................................................. 10
7.2 Functional Block Diagram ....................................... 10
8
9
10 Layout................................................................... 19
10.1 Layout Guidelines ................................................. 19
10.2 Layout Example .................................................... 19
11 器件和文档支持 ..................................................... 20
11.1 器件支持................................................................ 20
11.2 文档支持................................................................ 21
11.3 商标....................................................................... 21
11.4 静电放电警告......................................................... 21
11.5 术语表 ................................................................... 21
12 机械封装和可订购信息 .......................................... 21
7
4 修订历史记录
日期
修订版本
注释
2015 年 1 月
*
最初发布版本
2
Copyright © 2015, Texas Instruments Incorporated
TPS3702
www.ti.com.cn
ZHCSD99 –JANUARY 2015
5 Pin Configuration and Functions
DDC Package
SOT-6
(Top View)
UV
OV
1
2
3
6
5
4
GND
VDD
SET
SENSE
Pin Functions
PIN
I/O
DESCRIPTION
NO.
1
NAME
UV
Active-low, open-drain undervoltage output. This pin goes low when the SENSE voltage falls
below the internally set undervoltage threshold (VIT–). See the timing diagram in 图 1 for more
details. Connect this pin to a pull-up resistor terminated to the desired pull-up voltage.
O
—
I
2
GND
Ground
Input for the monitored supply voltage rail. When the SENSE voltage goes below the
undervoltage threshold, the UV pin is driven low.
3
SENSE
When the SENSE voltage goes above the overvoltage threshold, the OV pin is driven low.
Use this pin to configure the threshold voltages.
Refer to 表 3 for the desired configuration.
4
5
SET
VDD
I
I
Supply voltage input pin. To power the device, connect a voltage supply (within the range of 2 V
and 18 V) to VDD.
Good analog design practice is to place a 0.1-μF ceramic capacitor close to this pin.
Active-low, open-drain overvoltage output. This pin goes low when the SENSE voltage rises
above the internally set overvoltage threshold (VIT+). See the timing diagram in 图 1 for more
details. Connect this pin to a pull-up resistor terminated to the desired pull-up voltage.
6
OV
O
Copyright © 2015, Texas Instruments Incorporated
3
TPS3702
ZHCSD99 –JANUARY 2015
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
–0.3
MAX
20
UNIT
V
VDD
Voltage
Current
VUV, VOV
VSENSE, VSET
IUV, IOV
20
V
7
V
±40
mA
Continuous total power dissipation
Operating junction temperature, TJ
Storage temperature, Tstg
See the Thermal Information
(2)
–40
–65
125
150
°C
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) As a result of the low dissipated power in this device, it is assumed that TJ = TA.
6.2 ESD Ratings
VALUE
±2000
±750
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged device model (CDM), per JEDEC specification JESD22-C101(2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
2
NOM
MAX
18
UNIT
V
VDD
Supply pin voltage
Input pin voltage
SET pin voltage
Output pin voltage
Output pin current
Pull-up resistor
VSENSE
VSET
0
6.5
V
0
6.5
V
VUV, VOV
IUV, IOV
RPU
0
18
V
0.3
2.2
10
mA
kΩ
10,000
6.4 Thermal Information
SOT
THERMAL METRIC(1)
UNIT
6 PINS
201.6
47.8
51.2
0.7
RθJA
Junction-to-ambient thermal resistance
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ψJB
50.8
N/A
RθJC(bot)
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
4
Copyright © 2015, Texas Instruments Incorporated
TPS3702
www.ti.com.cn
ZHCSD99 –JANUARY 2015
6.5 Electrical Characteristics
At 2 V ≤ VDD ≤ 18 V, 1 V ≤ VSENSE ≤ 5 V, and over the operating free-air temperature range of –40°C to 125°C, unless
otherwise noted. Typical values are at TJ = 25°C.
PARAMETER
TEST CONDITIONS
MIN
2
TYP
MAX
18
UNIT
VDD
Supply voltage range
V
VIT+(OV)
VIT–(UV)
VHYS
Positive-going threshold accuracy
Negative-going threshold accuracy
Hysteresis voltage(1)
V
SET ≤ VIL(SET), VSET ≥ VIH(SET)
SET ≤ VIL(SET), VSET ≥ VIH(SET)
–0.9%
–0.9%
0.3%
±0.25%
±0.25%
0.55%
0.9%
0.9%
0.8%
0.8
V
TPS3702xXx
V(POR)
Power-on reset voltage(2)
VOL(max) = 0.25 V, IOUT = 15 µA
VDD = 2 V
V
6.0
7.0
1
10
µA
µA
µA
nA
mV
mV
mV
mV
mV
nA
nA
V
IDD
Supply current
VDD ≥ 5 V
12
ISENSE
ISET
Input current, SENSE pin
VSENSE = 5 V
1.5
Internal pull-up current, SET pin
VDD = 18 V, SET pin = GND
VDD = 1.3 V, IOUT = 0.4 mA
VDD = 2 V, IOUT = 3 mA
VDD = 5 V, IOUT = 5 mA
600
250
250
250
250
VOL
Low-level output voltage
VIL(set)
VIH(set)
ID(leak)
ILKG(od)
UVLO
Low-level SET pin input voltage
High-level SET pin input voltage
750
1.3
VPU = VDD
300
300
1.7
Open-drain output leakage current
Undervoltage lockout(3)
VDD = 2 V, VPU = 18 V
VDD falling
(1) Hysteresis is 0.55% of the nominal trip point.
(2) The outputs are undetermined below V(POR)
(3) When VDD falls below UVLO, UV is driven low and OV goes to high impedance.
.
Copyright © 2015, Texas Instruments Incorporated
5
TPS3702
ZHCSD99 –JANUARY 2015
www.ti.com.cn
6.6 Timing Requirements
At VDD = 2 V, 2.5% input overdrive(1) with RPU = 10 kΩ, VOH = 0.9 × VDD, and VOL = 400 mV, unless otherwise noted. RPU
refers to the pull-up resistor at the UV and OV pins.
MIN
NOM
19
MAX
UNIT
µs
tpd(HL)
tpd(LH)
tR
High-to-low propagation delay(2)
Low-to-high propagation delay(2)
Output rise time(3)
35
µs
2.2
µs
tF
Output fall time(3)
Startup delay(4)
0.22
300
µs
tSD
µs
(1) Overdrive = | (V(VDD) / VIT – 1) × 100% |.
(2) High-to-low and low-to-high refers to the transition at the SENSE pin.
(3) Output transitions from 10% to 90% for rise times and 90% to 10% for fall times.
(4) During the power-on sequence, VDD must be at or above 2 V for at least tSD before the output is in the correct state.
VDD(min)
VDD
V(POR)
VIT+(OV)
VHYS
VIT±(OV)
VIT+(UV)
SENSE
VHYS
VIT±(UV)
Undefined
tSD
Undefined
tSD
UV
OV
tSD
tpd(HL)
tpd(LH)
Undefined
tSD
Undefined
tSD
tSD
tpd(HL)
tpd(LH)
图 1. Timing Diagram
6
版权 © 2015, Texas Instruments Incorporated
TPS3702
www.ti.com.cn
ZHCSD99 –JANUARY 2015
6.7 Typical Characteristics
At TJ = 25°C, VDD = 3 V, and RPU = 10 kΩ, unless otherwise noted.
0.5
0.4
0.3
0.2
0.1
0
0.5
Unit 1
Unit 4
Unit 2
Unit 5
Unit 3
Avg
Unit 1
Unit 4
Unit 2
Unit 5
Unit 3
Avg
0.4
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.1
-0.2
-0.3
-0.4
-0.5
±40 ±25 ±10
5
20 35 50 65 80 95 110 125 140
±40 ±25 ±10
5
20 35 50 65 80 95 110 125 140
C001
Temperature (C)
Temperature (C)
C001
Performance is across VDD with SET high or low
Performance is across VDD with SET high or low
图 3. Overvoltage Accuracy vs Temperature
图 2. Undervoltage Accuracy vs Temperature
20000
20000
18000
16000
14000
12000
10000
8000
6000
4000
2000
0
18000
16000
14000
12000
10000
8000
6000
4000
2000
0
VIT- Accuracy (%)
VIT+ Accuracy (%)
Performance is across VDD with SET high or low
Performance is across VDD with SET high or low
图 4. Undervoltage Accuracy Distribution
图 5. Overvoltage Accuracy Distribution
1.65
1.6
12
10
8
-40C
105C
0C
125C
25C
UVLO Postive
UVLO Negative
1.55
1.5
6
4
1.45
1.4
2
0
±40 ±25 ±10
5
20 35 50 65 80 95 110 125 140
0
3
6
9
12
15
18
C001
C001
Temperature (C)
Supply Voltage (V)
图 7. Undervoltage Lockout Threshold vs Temperature
图 6. Supply Current vs Supply Voltage
版权 © 2015, Texas Instruments Incorporated
7
TPS3702
ZHCSD99 –JANUARY 2015
www.ti.com.cn
Typical Characteristics (接下页)
At TJ = 25°C, VDD = 3 V, and RPU = 10 kΩ, unless otherwise noted.
28
70
60
50
40
30
20
10
0
-40C
105C
0C
125C
25C
-40C
105C
0C
125C
25C
24
20
16
12
8
4
0
0
2
4
6
8
10
C001
0
0
0
2
4
6
8
10
Overdrive (%)
C001
Overdrive (%)
SENSE transitions from high to low
图 8. Undervoltage Propagation Delay vs Overdrive
SENSE transitions from low to high
图 9. Overvoltage Propagation Delay vs Overdrive
70
60
50
40
30
20
10
0
28
24
20
16
12
8
-40C
105C
0C
125C
25C
-40C
105C
0C
125C
25C
4
0
0
2
4
6
8
10
2
4
6
8
10
C001
Overdrive (%)
C001
Overdrive (%)
SENSE transitions from low to high
图 10. Undervoltage Propagation Delay vs Overdrive
SENSE transitions from high to low
图 11. Overvoltage Propagation Delay vs Overdrive
1
0.8
0.6
0.4
0.2
0
1
0.8
0.6
0.4
0.2
0
-40C
105C
0C
125C
25C
-40C
105C
0C
125C
25C
0
2
4
6
8
10
2
4
6
8
10
C001
Load (mA)
Load (mA)
C001
VDD = 1.8 V
VDD = 18 V
图 13. Low-Level Output Voltage vs Output Current
图 12. Low-Level Output Voltage vs Output Current
8
版权 © 2015, Texas Instruments Incorporated
TPS3702
www.ti.com.cn
ZHCSD99 –JANUARY 2015
Typical Characteristics (接下页)
At TJ = 25°C, VDD = 3 V, and RPU = 10 kΩ, unless otherwise noted.
700
VIH
VIL
600
500
400
300
±40 ±25 ±10
5
20 35 50 65 80 95 110 125 140
C001
Temperature (C)
图 14. SET Threshold vs Temperature
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9
TPS3702
ZHCSD99 –JANUARY 2015
www.ti.com.cn
7 Detailed Description
7.1 Overview
The TPS3702 family of devices combines two comparators and a precision reference for overvoltage and
undervoltage detection. The TPS3702 features a wide supply voltage range (2 V to 18 V) and highly accurate
window threshold voltages (0.9% over temperature). The TPS3702 is designed for systems that require an active
low signal if the voltage from the monitored power supply exits the accuracy band. The outputs can be pulled up
to 18 V and can sink up to 10 mA.
Unlike many other window comparators, the TPS3702 includes the resistors used to set the overvoltage and
undervoltage thresholds internal to the device. These internal resistors allow for lower component counts and
greatly simplifies the design because no additional margins are needed to account for the accuracy of external
resistors.
The TPS3702 is designed to assert active low output signals when the monitored voltage is outside the window
band. The relationship between the monitored voltage and the states of the outputs is shown in 表 1.
表 1. Truth Table
CONDITION
OUTPUT
UV low
STATUS
SENSE < VIT–(UV)
UV is asserted
SENSE > VIT–(UV) + VHYS
SENSE > VIT+(OV)
UV high
OV low
OV high
UV is high impedance
OV is asserted
SENSE < VIT+(OV) – VHYS
OV is high impedance
7.2 Functional Block Diagram
VDD
SENSE
UV
OV
Reference
Threshold
Logic
SET
GND
10
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TPS3702
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ZHCSD99 –JANUARY 2015
7.3 Feature Description
7.3.1 Input (SENSE)
The TPS3702 combines two comparators with a precision reference voltage and a trimmed resistor divider. Only
a single external input is monitored by the two comparators because the resistor divider is internal to the device.
This configuration optimizes device accuracy because all resistor tolerances are accounted for in the accuracy
and performance specifications. Both comparators also include built-in hysteresis that provides some noise
immunity and ensures stable operation.
The SENSE input can vary from ground to 6.5 V (7.0 V, absolute maximum), regardless of the device supply
voltage used. Although not required in most cases, for noisy applications good analog design practice is to place
a 1-nF to 10-nF bypass capacitor at the SENSE input in order to reduce sensitivity to transient voltages on the
monitored signal.
For the undervoltage comparator, the undervoltage output is driven to logic low when the SENSE voltage drops
below the undervoltage falling threshold, VIT–(UV). When the voltage exceeds the undervoltage rising threshold,
VIT+(UV) (which is VIT-(UV) + VHYS), the undervoltage output goes to a high-impedance state; see 图 1.
For the overvoltage comparator, the overvoltage output is driven to logic low when the voltage at SENSE
exceeds the overvoltage rising threshold, VIT+(OV). When the voltage drops below the overvoltage falling
threshold, VIT–(OV) (which is VIT+(OV) – VHYS), the overvoltage output goes to a high-impedance state; see 图 1.
Together, these two comparators form a window-detection function as described in the Window Comparator
Considerations section. Also see the 器件命名规则 section.
7.3.2 Outputs (UV, OV)
In a typical TPS3702 application, the outputs are connected to a reset or enable input of a processor [such as a
digital signal processor (DSP), application-specific integrated circuit (ASIC), or other processor type] or the
outputs are connected to the enable input of a voltage regulator [such as a dc-dc converter or low-dropout
regulator (LDO)].
The TPS3702 provides two open-drain outputs (UV and OV) and uses pull-up resistors to hold these lines high
when the output goes to a high-impedance state. Connect the pull-up resistors to the proper voltage rails to
enable the outputs to be connected to other devices at the correct interface voltage levels. The TPS3702 outputs
can be pulled up to 18 V, independent of the device supply voltage. To ensure proper voltage levels, give some
consideration when choosing the pull-up resistor values. The pull-up resistor value is determined by VOL, output
capacitive loading, and output leakage current (ID(leak)). These values are specified in the Electrical
Characteristics table. Use wired-OR logic to merge the undervoltage and overvoltage signals into one logic signal
that goes low if either outputs are asserted because of a fault condition.
表 1 describes how the outputs are either asserted low or high impedance. See 图 1 for a timing diagram that
describes the relationship between the threshold voltages and the respective output.
7.3.3 User-Configurable Accuracy Band (SET)
The TPS3702 has an innovative feature allowing each device to be set for one of two accuracy bands, 表 3
describes the available accuracy bands with nominal thresholds ranging from ±2% to ±10% of the monitored rail
nominal voltage. Forcing the voltage on the SET pin above the high-level SET pin input voltage, VIH(SET), sets the
thresholds for the tighter window whereas forcing the voltage on the SET pin below the low-level SET pin input
voltage, VIL(SET), sets the thresholds for the wider window.
Using the TPS3702Cxxx as an example, when VSET ≥ VIH(SET) the nominal thresholds are set to ±4% (see 图 15).
Thus, when the positive-going and negative-going threshold accuracy is accounted for, the device outputs an
active low signal for voltage excursions outside a ±4.9% band (worst case), which is calculated by taking the
nominal threshold percentage for that given part number and adding that value to the threshold accuracy found
in the Specifications section. Similarly, when VSET ≤ VIL(SET), the nominal thresholds are set to ±9% and the
device outputs an active low signal for voltage excursions outside the ±9.9% band (worst case).
The ability for the user to change the accuracy band allows a system to programmatically change the accuracy
band during certain conditions. One example is during system start up when the monitored voltage can be
slightly outside its typical accuracy specifications but a reset signal is not desired. In this case, VSET can be set
below VIL(SET) to detect voltage excursions outside the 10% band and, after the system is fully started up, VSET
can be pulled higher than VIH(SET), thus tightening the band to ±5%.
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11
TPS3702
ZHCSD99 –JANUARY 2015
www.ti.com.cn
Feature Description (接下页)
+9%
VIT+(OV)
Nom
+4%
-4%
Vmon
Nom
VIT-(UV)
Nom
-9%
VIH(SET)
SET
VIL(SET)
图 15. TPS3702Cxxx User-Configurable Accuracy Bands
Another benefit of allowing the user to change the accuracy band is the reduction in qualification costs. Users
who have multiple rail monitoring needs (such as some rails that must be within ±5% of the nominal voltage and
other rails that must be within ±10% of the same nominal voltage) benefit by only having to spend the time and
money qualifying one device instead of two.
7.4 Device Functional Modes
7.4.1 Normal Operation (VDD > UVLO)
When the voltage on VDD is greater than UVLO for approximately 300 µs (tSD), the undervoltage and
overvoltage signals correspond to the voltage on the SENSE pin; see 表 1.
7.4.2 Undervoltage Lockout (V(POR) < VDD < UVLO)
When the voltage on VDD is less than the device UVLO voltage but greater than the power-on reset voltage
(V(POR)), the undervoltage output is asserted and the overvoltage output is high impedance, regardless of the
voltage on SENSE.
7.4.3 Power-On Reset (VDD < V(POR)
)
When the voltage on VDD is lower than the required voltage to internally pull the asserted output to GND
(V(POR)), both outputs are undefined and are not to be relied upon for proper device function.
12
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TPS3702
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ZHCSD99 –JANUARY 2015
8 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPS3702 is a precision window comparator that can be used in several different configurations. The supply
voltage (VDD), the monitored voltage, and the output pullup voltage can be independent voltages or connected in
many configurations. 图 16 shows how the outputs operate with respect to the voltage on the SENSE pin.
VIT+(OV)
Overvoltage Limit
VIT+(OV) ꢀ (HYS)
VSENSE
VITꢀ(UV) +ꢁ(HYS)
VITꢀ(UV)
Undervoltage Limit
OV Pin
UV Pin
图 16. Window Comparator Operation
The following sections show the connection configurations and the voltage limitations for each configuration.
版权 © 2015, Texas Instruments Incorporated
13
TPS3702
ZHCSD99 –JANUARY 2015
www.ti.com.cn
Application Information (接下页)
8.1.1 Window Comparator Considerations
The inverting and noninverting configurations of the comparators form a window-comparator detection circuit by
using the internal resistor divider. The internal resistor divider allows for set voltage thresholds that already
account for the tolerances of the resistors in the resistor divider. The UV and OV pins signal undervoltage and
overvoltage conditions, respectively, on the SENSE pin, as shown in 图 17.
2 V to 18 V
VDD
Device
GND
Up to 6.5 V
To a system reset
or enable input
SENSE
UV
VIT-(UV)
VIT+(OV)
VDD
VIT-(UV) + VHYS
VIT+(OV) - VHYS
SET
OV
图 17. Window Comparator Schematic
The TPS3702 flags the overvoltage or undervoltage conditions with the most accuracy in order to ensure proper
system operation. The highest accuracy threshold voltages are VIT–(UV) and VIT+(OV), and correspond with the
falling SENSE undervoltage flag and the rising SENSE overvoltage flag, respectively. These thresholds represent
the accuracy when the monitored voltage changes from being within the desired window (when both the
undervoltage and overvoltage outputs are high) to when the monitored voltage goes outside the desired window,
indicating a fault condition. If the monitored voltage is outside of the valid window (VSENSE is less than the
undervoltage limit, VIT–(UV), or greater than overvoltage limit, VIT+(OV)), then the SENSE threshold voltages to
enter into the valid window are VIT+(UV) = VIT–(UV) + VHYS or VIT–(OV) = VIT+(OV) – VHYS
.
14
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TPS3702
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ZHCSD99 –JANUARY 2015
Application Information (接下页)
8.1.2 Input and Output Configurations
图 18 to 图 20 illustrate examples of the various input and output configurations.
VPULLUP
(up to 18 V)
2 V to 18 V
VDD
Up to 6.5 V
VPULLUP
SENSE
UV
VIT-(UV)
VIT-(UV) + VHYS
Device
VPULLUP
SET
OV
VIT+(OV) - VHYS VIT+(OV)
GND
图 18. Interfacing to Voltages Other Than VDD
2 V to 6.5 V
VDD
VDD
SENSE
UV
VIT-(UV)
VIT-(UV) + VHYS
Device
VDD
SET
OV
VIT+(OV) - VHYS VIT+(OV)
GND
图 19. Monitoring the Same Voltage as VDD with Wired-OR Logic
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15
TPS3702
ZHCSD99 –JANUARY 2015
www.ti.com.cn
Application Information (接下页)
2 V to 18 V
VDD
Device
GND
Up to 6.5 V
To a system reset
or enable input
SENSE
UV
VIT-(UV)
VIT+(OV)
VDD
VIT-(UV) + VHYS
VIT+(OV) - VHYS
SET
OV
图 20. Monitoring a Voltage Other Than VDD with Wired-OR Logic
Note that the SENSE input can also monitor voltages that are higher than VSENSE
or that may not be
(max)
designed for rail voltages with the use of an external resistor divider network. If a resistor divider is used to
reduce the voltage on the SENSE pin, ensure that the ISENSE current is accounted for so the accuracy is not
unexpectedly affected. As a general approximation, the current flowing through the resistor divider to ground
must be greater than 100 times the current going into the SENSE pin. See application report Optimizing Resistor
Dividers at a Comparator Input (SLVA450) for a more in-depth discussion on setting an external resistor divider.
8.1.3 Immunity to SENSE Pin Voltage Transients
The TPS3702 is immune to short voltage transient spikes on the input pins. Sensitivity to transients depends on
both transient duration and overdrive (amplitude) of the transient.
Overdrive is defined by how much the VSENSE exceeds the specified threshold, and is important to know because
the smaller the overdrive, the slower the response of the outputs (UV and OV). Threshold overdrive is calculated
as a percent of the threshold in question, as shown in 公式 1:
Overdrive = | (VSENSE / VIT – 1) × 100% |
where:
•
VIT is either VIT– or VIT+ for UV or OV.
(1)
图 8 to 图 11 illustrate the VSENSE minimum detectable pulse versus overdrive, and can be used to visualize the
relationship that overdrive has on propagation delay.
16
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TPS3702
www.ti.com.cn
ZHCSD99 –JANUARY 2015
8.2 Typical Application
SOC
3.3 V
1.8 V
1.2 V
VDD
VDD
VDD
SENSE
SET
UV
OV
SENSE
SET
UV
OV
SENSE
SET
UV
OV
RESET
TPS3702Cx33
TPS3702Cx18
TPS3702Cx12
图 21. ±5% Window Monitoring for SOC Power Rails
8.2.1 Design Requirements
表 2. Design Parameters
PARAMETER
DESIGN REQUIREMENT
DESIGN RESULT
3.3-V nominal, with alerts if outside of ±5% of 3.3 V
(including device accuracy)
Worst case VIT+(OV) = 3.463 V (4.94%),
Worst case VIT–(UV) = 3.139 V (4.86%)
1.8-V nominal, with alerts if outside of ±5% of 1.8 V
(including device accuracy)
Worst case VIT+(OV) = 1.889 V (4.94%),
Worst case VIT–(UV) = 1.712 V (4.86%)
Monitored rails
1.2-V nominal, with alerts if outside of ±5% of 1.2 V
(including device accuracy)
Worst case VIT+(OV) = 1.259 V (4.94%),
Worst case VIT–(UV) = 1.142 V (4.86%)
Output logic voltage
3.3-V CMOS
3.3-V CMOS
Maximum device current
consumption
50 µA
40.5 µA (max), 24 µA (typ)
8.2.2 Detailed Design Procedure
Determine which version of the TPS3702 best suits the application nominal rail and window tolerances. See 表 3
for selecting the appropriate device number for the application needs. If the nominal rail voltage to be monitored
is not listed as an option, a resistor divider can be used to reduce the voltage to a nominal voltage that is
available. The current ISENSE causes an error in the voltage detected at the SENSE pin because the SENSE
current only flows through the resistor at the top of the resistor divider. The larger the current through the resistor
divider to ground, the smaller this error will be. To optimize this resistor divider, refer to application report
Optimizing Resistor Dividers at a Comparator Input (SLVA450) for more information.
When the outputs switch to the high-Z state, the rise time of the UV or OV node depends on the pull-up
resistance and the capacitance on that node. Choose pull-up resistors that satisfy both the downstream timing
requirements and the sink current required to have a VOL low enough for the application; 10-kΩ to 1-MΩ resistors
are a good choice for low-capacitive loads.
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TPS3702
ZHCSD99 –JANUARY 2015
www.ti.com.cn
8.2.3 Application Curves
OV
2 V/div
OV
2 V/div
UV
2 V/div
UV
2 V/div
VDD
2 V/div
SENSE
2 V/div
Time (1 ms/div)
Time (1 ms/div)
VSENSE goes from 0 V to 3.47 V (VIT+(OV)), VDD = 3.3 V,
VPULLUP = 3.3 V
VDD goes from 0 V to 3.3 V, VSENSE = 3.47 V (above VIT+(OV)
)
图 22. TPS3702CX33 Window Comparator Function
图 23. TPS3702CX33 Startup with VPULLUP = 3 V
OV
2 V/div
UV
2 V/div
VDD
2 V/div
Time (1 ms/div)
VDD goes from 0 V to 3.3 V, VSENSE = 3.3 V
图 24. TPS3702CX33 Startup with VPULLUP = VDD
18
版权 © 2015, Texas Instruments Incorporated
TPS3702
www.ti.com.cn
ZHCSD99 –JANUARY 2015
9 Power Supply Recommendations
The TPS3702 is designed to operate from an input voltage supply range between 2 V and 18 V. An input supply
capacitor is not required for this device; however, if the input supply is noisy good analog practice is to place a
0.1-µF capacitor between the VDD pin and the GND pin. This device has a 20-V absolute maximum rating on the
VDD pin. If the voltage supply providing power to VDD is susceptible to any large voltage transient that can
exceed 20 V, additional precautions must be taken.
10 Layout
10.1 Layout Guidelines
•
•
Place the VDD decoupling capacitor close to the device.
Avoid using long traces for the VDD supply node. The VDD capacitor (CVDD), along with parasitic inductance
from the supply to the capacitor, can form an LC tank and create ringing with peak voltages above the
maximum VDD voltage.
10.2 Layout Example
Pullup
Voltage
RPU1
RPU2
Overvoltage
Flag
Undervoltage
Flag
6
5
1
CVDD
Input
Supply
2
Set
Voltage
Monitored
Voltage
3
4
图 25. Recommended Layout
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19
TPS3702
ZHCSD99 –JANUARY 2015
www.ti.com.cn
11 器件和文档支持
11.1 器件支持
11.1.1 开发支持
11.1.1.1 评估模块
评估模块 (EVM) 可与 TPS3702 配套使用,帮助评估初始电路性能。 TPS3702CX33EVM-683 评估模块(和相关
的用户指南)可在德州仪器 (TI) 网站上的产品文件夹中获取,也可直接从 TI 网上商店购买。
11.1.2 器件命名规则
表 3 以 TPS3702CX33 为例,介绍如何根据器件部件号确定器件的功能。
表 3. 器件命名约定
说明
命名规则
值
TPS3702
(高精度窗口比较器系列)
—
—
A
B
SET 引脚高电平 = ±2%,SET 引脚低电平 = ±6%
SET 引脚高电平 = ±3%,SET 引脚低电平 = ±7%
C
(标称阈值,受监视电压标称值的百分比)
C
SET 引脚高电平 = ±4%,SET 引脚低电平 = ±9%
D
SET 引脚高电平 = ±5%,SET 引脚低电平 = ±10%
X
0.55%
1.0%
1.0V
1.2V
1.8V
3.3V
5.0V
X
(滞后选项)
Y
10
12
18
33
50
33
(受监视电压标称值选项)
表 4 列出了 TPS3702 系列的已发布版本,其中包括标称欠压和过压阈值。 有关表 3 中所列的其他选项的详细信息
和可用性,请联系制造商;最低订购量适用。
表 4. 已发布器件的阈值
UV 阈值 (V)
SET ≤ VIL(SET)
UV 阈值 (V)
SET ≥ VIH(SET)
OV 阈值 (V)
SET ≤ VIL(SET)
OV 阈值 (V)
SET ≥ VIH(SET)
产品
标称电源 (V)
滞后 (%)
TPS3702CX10
TPS3702CX12
TPS3702AX18
TPS3702CX18
TPS3702AX33
TPS3702CX33
TPS3702CX50
1.0
1.2
1.8
1.8
3.3
3.3
5.0
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.91
1.09
1.69
1.64
3.10
3.00
4.55
0.96
1.15
1.76
1.73
3.23
3.17
4.80
1.09
1.31
1.91
1.96
3.50
3.60
5.45
1.04
1.25
1.84
1.87
3.37
3.43
5.20
20
版权 © 2015, Texas Instruments Incorporated
TPS3702
www.ti.com.cn
ZHCSD99 –JANUARY 2015
11.2 文档支持
11.2.1 相关文档ꢀ
优化比较器输入上的电阻分压器,SLVA450
《TPS3702CX33EVM-683 评估模块》,SBVU026
11.3 商标
All trademarks are the property of their respective owners.
11.4 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
11.5 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、首字母缩略词和定义。
12 机械封装和可订购信息
以下页中包括机械封装和可订购信息。 这些信息是针对指定器件可提供的最新数据。 这些数据会在无通知且不对
本文档进行修订的情况下发生改变。 欲获得该数据表的浏览器版本,请查阅左侧的导航栏。
版权 © 2015, Texas Instruments Incorporated
21
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS3702AX18DDCR
TPS3702AX18DDCT
TPS3702AX33DDCR
TPS3702AX33DDCT
TPS3702CX10DDCR
TPS3702CX10DDCT
TPS3702CX12DDCR
TPS3702CX12DDCT
TPS3702CX18DDCR
TPS3702CX18DDCT
TPS3702CX33DDCR
TPS3702CX33DDCT
TPS3702CX50DDCR
TPS3702CX50DDCT
ACTIVE SOT-23-THIN
ACTIVE SOT-23-THIN
ACTIVE SOT-23-THIN
ACTIVE SOT-23-THIN
ACTIVE SOT-23-THIN
ACTIVE SOT-23-THIN
ACTIVE SOT-23-THIN
ACTIVE SOT-23-THIN
ACTIVE SOT-23-THIN
ACTIVE SOT-23-THIN
ACTIVE SOT-23-THIN
ACTIVE SOT-23-THIN
ACTIVE SOT-23-THIN
ACTIVE SOT-23-THIN
DDC
DDC
DDC
DDC
DDC
DDC
DDC
DDC
DDC
DDC
DDC
DDC
DDC
DDC
6
6
6
6
6
6
6
6
6
6
6
6
6
6
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
ZAUO
ZAUO
ZAPO
ZAPO
ZARO
ZARO
ZAVO
ZAVO
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
ZAWO
ZAWO
ZAQO
ZAQO
ZASO
ZASO
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE OUTLINE
DDC0006A
SOT-23 - 1.1 max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
3.05
2.55
1.1
0.7
1.75
1.45
0.1 C
B
A
PIN 1
INDEX AREA
1
6
4X 0.95
1.9
3.05
2.75
4
3
0.5
0.3
0.1
6X
TYP
0.0
0.2
C A B
C
0 -8 TYP
0.25
GAGE PLANE
SEATING PLANE
0.20
0.12
TYP
0.6
0.3
TYP
4214841/C 04/2022
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Reference JEDEC MO-193.
www.ti.com
EXAMPLE BOARD LAYOUT
DDC0006A
SOT-23 - 1.1 max height
SMALL OUTLINE TRANSISTOR
SYMM
6X (1.1)
1
6
6X (0.6)
SYMM
4X (0.95)
4
3
(R0.05) TYP
(2.7)
LAND PATTERN EXAMPLE
EXPLOSED METAL SHOWN
SCALE:15X
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
SOLDERMASK DETAILS
4214841/C 04/2022
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DDC0006A
SOT-23 - 1.1 max height
SMALL OUTLINE TRANSISTOR
SYMM
6X (1.1)
1
6
6X (0.6)
SYMM
4X(0.95)
4
3
(R0.05) TYP
(2.7)
SOLDER PASTE EXAMPLE
BASED ON 0.125 THICK STENCIL
SCALE:15X
4214841/C 04/2022
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
www.ti.com
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