TPS3703A7110DSERQ1 [TI]

Overvoltage and Undervoltage Reset IC With Time Delay and Manual Reset;


型号：	TPS3703A7110DSERQ1
厂家：	TEXAS INSTRUMENTS
描述：	Overvoltage and Undervoltage Reset IC With Time Delay and Manual Reset
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中文：	中文翻译
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TPS3703-Q1

SBVS344D – NOVEMBER 2018 – REVISED MARCH 2021

TPS3703-Q1

Overvoltage and Undervoltage Reset IC With Time Delay and Manual Reset

1 Features

3 Description

•

AEC-Q100 qualified for automotive applications:

– Temperature grade 1: –40°C to +125°C, T_A

– Device HBM ESD classification level 2

– Device CDM ESD classification level C7B

Functional Safety-Capable

– Documentation available to aid functional safety

system design

Input voltage range: 1.7 V to 5.5 V

Undervoltage lockout (UVLO): 1.7 V

Low quiescent current: 7 µA (Max)

High threshold accuracy:

The TPS3703-Q1 device is an integrated overvoltage

(OV) and undervoltage (UV) monitor or reset IC in

industry’s smallest 6-pin DSE package. This highly

accurate voltage supervisor is ideal for systems

that operate on low-voltage supply rails and have

narrow margin supply tolerances. Low threshold

hysteresis prevent false reset signals when the

monitored voltage supply is in its normal range of

operation. Internal glitch immunity and noise filters

further eliminate false resets resulting from erroneous

signals.

•

The TPS3703-Q1 does not require any external

resistors for setting overvoltage and undervoltage

reset thresholds, which further optimizes overall

accuracy, cost, solution size, and improves reliability

for safety systems. The Capacitor Time (CT) pin is

used to select between the two available reset time

delays designed into each device and also to adjust

the reset time delay by connecting a capacitor. A

separate SENSE input pin and VDD pin allow for the

redundancy sought by high-reliability systems.

– ± 0.25% (typical)

– ± 0.7% (–40°C to +125°C)

Fixed window threshold levels

•

– 50-mV steps from 500 mV to 1.3 V

– 1.5 V, 1.8 V, 2.5 V, 2.8 V, 2.9 V 3.3 V, 5 V

– Available in UV threshold only

– Window tolerance available from ±3% to ±7%

User adjustable voltage threshold levels

Internal glitch immunity and hysteresis

Fixed time delay options: 50 µs, 1 ms, 5 ms, 10

ms, 20 ms, 100 ms, 200 ms

Programmable time delay option with a single

external capacitor

Open-drain active low UV and OV monitor

RESET voltage latching output mode

•

This device has a low typical quiescent current

specification of 4.5 µA (typical). The TPS3703-Q1 is

suitable for automotive applications and is qualified for

AEC-Q100 Grade 1.

•

Device Information⁽¹⁾

•

PART NUMBER

PACKAGE

BODY SIZE (NOM)

TPS3703-Q1

WSON (6)

1.50 mm × 1.50 mm

2 Applications

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

•

Advanced driver assistance system (ADAS)

ADAS domain controller

Automotive infotainment and cluster

Digital cockpit

HEV/EV

OV Threshold

Monitor Voltage

V_CORE

UV Threshold

TPS3703Q1

SENSE

Processor

RESET

Up to

5.5V

VDD

GND

10k ꢀ

RESET

-0.4

-0.3

-0.2

-0.1

0.1

0.2

0.3

0.4

Optional

V_IT+(OV)Accuracy (%)

D004

Integrated Overvoltage and Undervoltage

Detection

Typical Overvoltage Accuracy Distribution

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

TPS3703-Q1

SBVS344D – NOVEMBER 2018 – REVISED MARCH 2021

www.ti.com

Table of Contents

1 Features............................................................................1

2 Applications.....................................................................1

3 Description.......................................................................1

4 Revision History.............................................................. 2

5 Device Comparison.........................................................3

6 Pin Configuration and Functions...................................4

7 Specifications.................................................................. 5

7.1 Absolute Maximum Ratings........................................ 5

7.2 ESD Ratings............................................................... 5

7.3 Recommended Operating Conditions.........................5

7.4 Thermal Information....................................................6

7.5 Electrical Characteristics.............................................6

7.6 Timing Requirements..................................................7

7.7 Timing Diagrams.........................................................8

7.8 Typical Characteristics..............................................10

8 Detailed Description......................................................14

8.1 Overview...................................................................14

8.2 Functional Block Diagram.........................................14

8.3 Feature Description...................................................14

8.4 Device Functional Modes..........................................16

9 Application and Implementation..................................17

9.1 Application Information............................................. 17

9.2 Typical Applications.................................................. 22

10 Power Supply Recommendations..............................26

10.1 Power Supply Guidelines........................................26

11 Layout...........................................................................26

11.1 Layout Guidelines................................................... 26

11.2 Layout Example...................................................... 26

12 Device and Documentation Support..........................27

12.1 Device Support....................................................... 27

12.2 Documentation Support.......................................... 29

12.3 Receiving Notification of Documentation Updates..29

12.4 Support Resources................................................. 29

12.6 Electrostatic Discharge Caution..............................29

12.7 Glossary..................................................................29

13 Mechanical, Packaging, and Orderable

Information.................................................................... 29

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision C (February 2020) to Revision D (March 2021)

Page

•

Updated the numbering format for tables, figures, and cross-references throughout the document .................1

Included Functional Safety bullets .....................................................................................................................1

Replaced Device Comparison Table with device nomenclature legend............................................................. 3

Changes from Revision B (September 2019) to Revision C (February 2020)

Page

•

Changed reset time delay nomenclature (t_D): J to M by A to H..........................................................................7

Changes from Revision A (May 2019) to Revision B (September 2019)

Page

•

Deleted OV only throughout document. .............................................................................................................1

Changed from threshold tolerance to window tolerance throughout document. ................................................1

Added new voltage variants for window and UV only.........................................................................................3

Added pinout description for package................................................................................................................ 4

Changed functional block diagram for clarity between variants. ......................................................................14

Added UV only normal operation condition. .................................................................................................... 16

Changed equation to correctly reflect resistor divider. .....................................................................................20

Changed to R₁from R_SENSE............................................................................................................................ 20

Changes from Revision * (November 2018) to Revision A (May 2019)

Page

•

Changed from Advance Information to Production Data release ...................................................................... 1

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5 Device Comparison

Figure 5-1 shows the device nomenclature of the TPS3703-Q1. For all possible voltages, window tolerance, time

delays, and UV threshold options, see Table 12-1. Contact TI sales representatives or on TI's E2E forum for

details and availability of other options; minimum order quantities apply.

TPS 3703 X X XXX XXX RQ1

Time Delay Op on

Tolerance Op on

3: UV/OV = 3%

4: UV/OV = 4%

5: UV/OV = 5%

6: UV/OV = 6%

7: UV/OV = 7%

Nominal Threshold Op on

Package

DSE: WSON (6-pin)

A: CT (open) 10 ms, CT (VDD) = 200 ms

B: CT (open) 1 ms, CT (VDD) = 20 ms

C: CT (open) 5 ms, CT (VDD) = 100 ms

D: CT (open) 50 µs, CT (VDD) = 50 µs

…

050: 0.50V

...

500: 5.00V

Figure 5-1. Device Nomenclature Legend

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6 Pin Configuration and Functions

SENSE

VDD

GND

RESET

Figure 6-1. DSE Package, 6-Pin WSON, Top View

Table 6-1. Pin Functions

NAME

I/O

DESCRIPTION

NO.

Input for the monitored supply voltage rail. When the SENSE voltage goes above the overvoltage

threshold or below the undervoltage threshold, the RESET pin is driven low. Connect to VDD pin if

monitoring VDD supply voltage.

SENSE

VDD

Supply voltage input pin. Good analog design practice is to place a 0.1-μF ceramic capacitor close to

this pin.

Capacitor time delay pin. The CT pin offers two fixed time delays by connecting CT pin to VDD or

leaving it floating. Delay time can be programmed by connecting an external capacitor reference to

ground.

Active-low, open-drain output. This pin goes low when the SENSE voltage rises above the internally

overvoltage threshold (V_IT+) or below the undervoltage threshold (V_IT–). See the timing diagram in

Figure 8-2 for more details. Connect this pin to a pull-up resistor terminated to the desired pull-up

voltage.

RESET

GND

—

Ground

Manual reset (MR), pull this pin to a logic low (V_{MR_L}) to assert a reset signal . After the MR pin is

deasserted the output goes high after the reset delay time(t_D) expires. MR can be left floating when not

in use.

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7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

–0.3

MAX UNIT

V_DD

V_RESET

Voltage

V_CT

V_SENSE

V_MR

Current

I_RESET

±40

°C

Continuous total power dissipation

Operating junction temperature, T_J

Operating free-air temperature, T_A

Storage temperature, T_stg

See the Thermal Information

–40

–65

150

Temperature ⁽²⁾

(1) Stresses beyond values listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress

ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under

Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device

reliability.

(2) As a result of the low dissipated power in this device, it is assumed that T_J= T_A.

7.2 ESD Ratings

VALUE

±2000

±500

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

Electrostatic

discharge

V_(ESD)

All pins

Charged-device model (CDM), per AEC

Q100-011

Corner pins

±750

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification

7.3 Recommended Operating Conditions

MIN

1.7

NOM

MAX

5.5

UNIT

V_DD

Supply pin voltage

V_SENSE

V_CT

V_RESET

V_MR

I_RESET

T_J

Input pin voltage

5.5

CT pin voltage^{(1) (3)}

V_DD

5.5

Output pin voltage

MR pin voltage⁽²⁾

5.5

Output pin current

0.3

–40

℃

Junction temperature (free-air temperature)

125

(1) CT pin connected to VDD pin requires a pullup resistor; 10 kΩ is recommended.

(2) If the logic signal driving MR is less than V_DD, then additional current flows into V_DDand out of MR.

(3) The maximum rating is V_DDor 5.5 V, whichever is smaller.

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7.4 Thermal Information

TPS3703-Q1

DSE (WSON)

PINS

THERMAL METRIC⁽¹⁾

UNIT

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

184.2

°C/W

R_θJC(top)

R_θJB

30.6

86.4

Ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

13.4

Ψ_JB

86.1

R_θJC(bot)

N/A

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

7.5 Electrical Characteristics

At 1.7 V ≤ V_DD≤ 5.5 V, CT = MR = Open, RESET Voltage (V_RESET) = 10 kΩ to V_DD, RESET load = 10 pF, and over the

operating free-air temperature range of – 40°C to 125°C, unless otherwise noted. Typical values are at T_J= 25°C, typical

conditions at V_DD= 3.3 V.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

5.5

1.7

UNIT

V_DD

Supply voltage

1.7

UVLO

V_POR

V_IT+(OV)

V_IT-(UV)

V_HYS

Under voltage lockout⁽³⁾

Power on reset voltage⁽²⁾

Positive- going threshold accuracy

Negative-going threshold accuracy

Hysteresis voltage⁽¹⁾

V_DDfalling below 1.7 V

1.2

V_OL(max) = 0.25 V, I_OUT= 15 µA

–0.7

0.3

±0.25

0.55

4.5

0.7

0.8

I_DD

Supply current

V_DD≤ 5.5 V

µA

I_SENSE

Input current, SENSE pin

V_SENSE= 5 V

1.5

250

300

0.3

V_DD= 1.7 V, I_OUT= 0.4 mA

V_DD= 2 V, I_OUT= 3 mA

V_DD= 5 V, I_OUT= 5 mA

V_DD= V_RESET= 5.5 V

V_OL

Low level output voltage

I_LKG

Open drain output leakage current

MR logic low input

V_{MR_L}

V_{MR_H}

V_{CT_H}

R_MR

MR logic high input

1.4

High level CT pin voltage

Manual reset Internal pullup resistance

CT pin charge current

100

375

KΩ

I_CT

337

413

V_CT

CT pin comparator threshold voltage⁽⁴⁾

1.133

1.15

1.167

(1) Hysteresis is with respect of the tripoint (V_IT-(UV), V_IT+(OV)).

(2) V_PORis the minimum V_DDvoltage level for a controlled output state.

(3) RESET pin is driven low when V_DDfalls below UVLO.

(4) V_CTvoltage refers to the comparator threshold voltage that measures the voltage level of the external capacitor at CT pin.

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7.6 Timing Requirements

At 1.7 V ≤ V_DD≤ 5.5 V, CT = MR = Open, RESET Voltage (V_RESET) = 10 kΩ to V_DD, RESET load = 10 pF, and over the

operating free-air temperature range of – 40°C to 125°C, unless otherwise noted. Typical values are at T_J= 25°C, typical

conditions at V_DD= 3.3 V.

MIN

NOM

MAX UNIT

Reset time delay, TPS3703A, TPS3703E

Reset time delay, TPS3703B, TPS3703F

Reset time delay, TPS3703C, TPS3703G

CT = Open

CT = 10 kΩ to V_DD

CT = Open

140

0.7

200

260

1.3

CT = 10 kΩ to V_DD

CT = Open

t_D

3.5

6.5

CT = 10 kΩ to V_DD

100

130

CT = 10 kΩ to V_DD

CT = Open

Reset time delay, TPS3703D, TPS3703H

µs

t_PD

Propagation detect delay^{(1) (2)}

2.2

0.2

300

3.5

µs

t_R

Output rise time^{(1) (3)}

t_F

Output fall time^{(1) (3)}

t_SD

Startup delay⁽⁴⁾

t_{GI (VIT-)}

t_{GI (VIT+)}

t_{GI ( MR)}

t_{PD ( MR)}

t_{MR_W}

t_{D ( MR)}

Glitch Immunity undervoltage V_IT-(UV), 5% Overdrive⁽¹⁾

Glitch Immunity overvoltage V_IT+(OV), 5% Overdrive⁽¹⁾

Glitch Immunity MR pin

Propagation delay from MR low to assert RESET

MR pin pulse width duration to assert RESET

MR reset time delay

500

t_D

(1) 5% Overdrive from threshold. Overdrive % = [V_SENSE- V_IT] / V_IT; Where V_ITstands for V_IT-(UV)or V_IT+(OV)

(2) t_PDmeasured from threhold trip point (V_IT-(UV)or V_IT+(OV)) to RESET V_OLvoltage

(3) Output transitions from V_OLto 90% for rise times and 90% to V_OLfor fall times.

(4) During the power-on sequence, V_DDmust be at or above V_{DD (MIN)}for at least t_SD+ t_Dbefore the output is in the correct state.

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7.7 Timing Diagrams

Overdrive[2.5%] above V_IT+(OV)

[0.7%]

Accuracy across (-40ºC to 125ºC)

Accuracy at 25ºC

[ 0.4% = 0.7%-0.3%) ]

[ 0.15% = 0.7%-0.55%) ]

[0.25%]

0.5%

VIT_+(OV)

[ -0.1% = 0.7%-0.8%) ]

[-0.25%]

[-0.7%]

[-0.3%]

V_IT+(OV)- V_HYS

[-0.55%]

Hys band for V_IT+(OV)

[-0.8%]

[ -1.0% = -0.7%-0.3%) ]

[ -1.25% = -0.7%-0.55%) ]

[ -1.5% = -0.7%-0.8%) ]

0.5%

Nominal monitored voltage

All percentages are calculated with respect to typical V_IT

[ 1.5% = 0.7%+0.8%) ]

[ 1.25% = 0.7%+0.55%) ]

0.5%

[ 1.0% = 0.7%+0.3%) ]

[0.8%]

[0.55%]

[0.3%]

[0.7%]

V_IT-(UV)+ V_HYS

Hys band for V_IT-(UV)

Accuracy across (-40ºC to 125ºC)

Accuracy at 25ºC

[0.25%]

[ 0.1% = -0.7%+0.8%) ]

VIT_-(UV)

[ -0.15% = -0.7%+0.55%) ]

[ -0.4% = -0.7%+0.3% ]

[-0.25%]

0.5%

[-0.7%]

Overdrive [2.5%] below V_IT-(UV)

Figure 7-1. Voltage Threshold and Hysteresis Accuracy

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V_DD(MIN)

UVLO

V_DD

V_POR

V_IT+(OV)

Hysteresis

V_IT+(OV)- V_HYS

SENSE

V_IT

V_IT-(UV)+ V_HYS

V_IT-(UV)

RESET

t_D

t_PD

t_D

t_SD

A. V_DD= 2 V, R_PU= 10 kΩ to V_DD

B. Variant D (time delay bypass) has a ~40 µs pulse at RESET pin during power up window, this is present only when the power cycle off time is longer than 10 seconds, this behavior will not

occur if the SENSE pin is within window of operation during V_DDpower up.

Figure 7-2. SENSE Timing Diagram

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7.8 Typical Characteristics

at T_J= 25°C, V_DD= 3.3 V, and R_PU= 10 kΩ (unless otherwise noted)

0.2

0.15

0.1

0.8 V

1.2 V

1.8 V

3.3 V

5.0 V

0.8 V

1.2 V

1.8 V

3.3 V

5.0 V

0.15

0.1

0.05

-0.05

-0.1

-0.15

-0.2

-0.05

-0.1

-0.15

-0.2

-50

-25

100

125

-50

-25

100

125

Temperature (èC)

D001

D002

Tested across multiple voltage options

Figure 7-3. Undervoltage Accuracy vs Temperature

Figure 7-4. Overvoltage Accuracy vs Temperature

-0.4

-0.3

-0.2

-0.1

0.1

0.2

0.3

0.4

-0.3

-0.2

-0.1

0.1

0.2

0.3

0.4

V_IT-(UV)Accuracy (%)

V_IT+(OV)Accuracy (%)

D003

D004

Sample Size of 100 TPS3703A7125 units

Figure 7-5. Undervoltage Accuracy Distribution

Figure 7-6. Overvoltage Accuracy Distribution

0.6

0.8 V

1.2 V

1.8 V

3.3 V

5.0 V

0.8 V

1.2 V

1.8 V

3.3 V

5.0 V

0.58

0.56

0.54

0.52

0.5

0.58

0.56

0.54

0.52

0.5

-50

-25

100

125

-50

-25

100

125

Temperature (èC)

D005

D006

Tested across multiple voltage options

Figure 7-7. Undervoltage Hysteresis Voltage Accuracy vs

Temperature

Figure 7-8. Overvoltage Hysteresis Voltage Accuracy vs

Temperature

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7.8 Typical Characteristics (continued)

at T_J= 25°C, V_DD= 3.3 V, and R_PU= 10 kΩ (unless otherwise noted)

VDD = 1.7 V

VDD = 3.3 V

VDD = 5.5 V

VDD = 1.7 V

VDD = 3.3 V

VDD = 5.5 V

-50

-25

100

125

-50

-25

100

125

Temperature (èC)

D007

D008

Output ( RESET Pin) = High

Figure 7-9. Supply Current vs Temperature

Output ( RESET Pin) = Low

Figure 7-10. Supply Current vs Temperature

-40èC

25èC

125èC

10 15 20 25 30 35 40 45 50 55

Overdrive (%)

10 15 20 25 30 35 40 45 50 55

Overdrive (%)

D009

D010

VDD = 1.7 V

Figure 7-11. SENSE Glitch Immunity (VIT-) vs Overdrive

Figure 7-12. SENSE Glitch Immunity (VIT+) vs Overdrive

-40èC

25èC

125èC

-40èC

25èC

125èC

10 15 20 25 30 35 40 45 50 55

Overdrive (%)

10 15 20 25 30 35 40 45 50 55

Overdrive (%)

D011

D012

VDD = 5.5 V

Figure 7-13. SENSE Glitch Immunity (VIT-) vs Overdrive

Figure 7-14. SENSE Glitch Immunity (VIT+) vs Overdrive

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7.8 Typical Characteristics (continued)

at T_J= 25°C, V_DD= 3.3 V, and R_PU= 10 kΩ (unless otherwise noted)

0.3

0.25

0.2

0.15

0.1

0.05

0.25

0.2

0.15

0.1

-40èC

25èC

125èC

0.05

25èC

125èC

I_RESET(mA)

D013

D014

VDD = 1.7 V

VDD = 5.5 V

Figure 7-15. Low-Level Output Voltage vs RESET current

Figure 7-16. Low-Level Output Voltage vs RESET current

0.6

1.16

V_{MR_H}

V_{MR_L}

V_{MR_H}

V_{MR_L}

1.14

1.12

1.1

0.5

0.4

0.3

1.08

1.06

1.04

-50

-25

100

125

-50

-25

100

125

Temperature (èC)

D016

D015

VDD = 5.5 V

Figure 7-18. SET Threshold vs Temperature

VDD = 1.7 V

Figure 7-17. SET Threshold vs Temperature

390

500

100

385

380

375

370

365

-40èC

25èC

1.7 V

5.5 V

125èC

0.1

-50

-25

100

125

0.1

C_T(nF)

100

1000

Temperature (èC)

D017

D018

Figure 7-19. CT Current vs CT value

Figure 7-20. RESET Timeout vs CT Capacitor

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7.8 Typical Characteristics (continued)

at T_J= 25°C, V_DD= 3.3 V, and R_PU= 10 kΩ (unless otherwise noted)

-40èC

25èC

125èC

VDD = 1.7 V

VDD = 3.3 V

VDD = 5.5 V

0.1

C_T(nF)

-50

-25

100

125

Temperature (èC)

D019

D020

Figure 7-21. Timeout vs CT Capacitor (0.1 to 10 nF)

Figure 7-22. Detect Propagation Delay vs Temperature

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8 Detailed Description

8.1 Overview

The TPS3703-Q1 family of devices combines two voltage comparators and a precision voltage reference for

overvoltage and undervoltage detection. The TPS3703-Q1 features a highly accurate window threshold voltages

(±0.7% over temperature) and a variety voltage threshold variants.

The TPS3703-Q1 includes the resistors used to set the overvoltage and undervoltage thresholds internal to the

device. These internal resistors allow for lower component counts and greatly simplifies the design because no

additional margins are needed to account for the accuracy of external resistors.

TPS3703-Q1 version A, B and C has three time delay settings, two fixed by connecting CT pin to VDD through

a resistor and leaving CT floating and a programmable time delay setting that only requires a single capacitor

connected from CT pin to ground.

Manual Reset ( MR) allows for sequencing or hard reset by driving the MR pin below V_{MR_L}

The TPS3703-Q1 is designed to assert active low output signals when the monitored voltage is outside the safe

window. The relationship between the monitored voltage and the states of the outputs is shown in Table 8-1.

8.2 Functional Block Diagram

*For all possible voltages, window tolerance, time delays, and UV threshold options, see Table 12-1.

8.3 Feature Description

8.3.1 VDD

The TPS3703-Q1 is designed to operate from an input voltage supply range between 1.7 V to 5.5 V. An input

supply capacitor is not required for this device; however, if the input supply is noisy good analog practice is to

place a 1-µF capacitor between the VDD pin and the GND pin.

V_DDneeds to be at or above V_DD(MIN)for at least the start-up delay (t_SD+ t_D) for the device to be fully functional.

8.3.2 SENSE

The TPS3703-Q1 combines two comparators with a precision reference voltage and a trimmed resistor divider.

This configuration optimizes device accuracy because all resistor tolerances are accounted for in the accuracy

and performance specifications. Both comparators also include built-in hysteresis that provides noise immunity

and ensures stable operation.

Although not required in most cases, for noisy applications good analog design practice is to place a 1-nF to

10-nF bypass capacitor at the SENSE input in order to reduce sensitivity to transient voltages on the monitored

signal.

When monitoring VDD supply voltage, the SENSE pin can be connected directly to VDD. The output ( RESET) is

high impedance when voltage at the SENSE pin is between upper and lower boundary of threshold.

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8.3.3 RESET

In a typical TPS3703-Q1 application, the RESET output is connected to a reset or enable input of a processor

[such as a digital signal processor (DSP), application-specific integrated circuit (ASIC), or other processor type]

or the enable input of a voltage regulator [such as a DC-DC converter or low-dropout regulator (LDO)].

The TPS3703-Q1 has an open drain active low output that requires a pull-up resistor to hold these lines high

to the required voltage logic. Connect the pull-up resistor to the proper voltage rail to enable the output to be

connected to other devices at the correct interface voltage levels. To ensure proper voltage levels, give some

consideration when choosing the pull-up resistor values. The pull-up resistor value is determined by V_OL, output

capacitive loading, and output leakage current. These values are specified in Section 7. The open drain output

can be connected as a wired-OR logic with other open drain signals such as another TPS3703-Q1 RESET pin.

Table 8-1 describes the scenarios when the output ( RESET) is either asserted low or high impedance.

V_IT+(OV)

OV Limit

V_IT+(OV)- V_HYS

V_SENSE

V_IT-(UV)+ V_HYS

UV Limit

V_IT-(UV)

RESET

t_D

t_PD

t_D

t_PD

Figure 8-1. RESET output

8.3.4 Capacitor Time (CT)

The CT pin provides the user the functionality of both high-precision, factory-programmed, reset delay timing

options and user-programmable, reset delay timing. The CT pin can be pulled up to V_DDthrough a resistor, have

an external capacitor to ground, or can be left unconnected. The configuration of the CT pin is re-evaluated by

the device every time the voltage on the SENSE line enters the valid window (V_IT-(UV)< V_SENSE< V_IT+(OV)). The

pin evaluation is controlled by an internal state machine that determines which option is connected to the CT pin.

The sequence of events takes 450 μs to determine if the CT pin is left unconnected, pulled up through a resistor,

or connected to a capacitor. If the CT pin is being pulled up to V_DD, then a pull-up resistor is required, 10 kΩ is

recommended.

8.3.5 Manual Reset ( MR)

The manual reset ( MR) input allows a processor or other logic circuits to initiate a reset. A logic low on MR

causes RESET to assert. After MR returns to a logic high and the SENSE pin voltage is within a valid window

((V_IT-(UV)< V_SENSE< V_IT+(OV)) , RESET is deasserted after the reset delay time (t_D). If MR is not controlled

externally, then MR can either be connected to V_DDor left floating because the MR pin is internally pulled up to

V_DD. Figure Figure 8-2 shows the relation between MR and RESET.

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V_IT+(OV)

Hysteresis

V_IT+(OV)- V_HYS

SENSE

V_IT-(UV)+ V_HYS

V_IT-(UV)

Hysteresis

Pulse < V_{MR_L}

Pulse < t_{GI (MR)}

V_{MR_H}

V_{MR_L}

t_{MR_W}

RESET

t_D(MR)

t_{PD (MR)}

A. RESET pulls up to VDD with 10 kΩ.

B. To initiate and continue time reset counter both conditions must be met MR pin above V_{MR_H}or floating and V_SENSEbetween V_IT-(UV)

V_HYSand V_IT+(OV)- V_HYS

C. MR is ignored during output RESET low event

Figure 8-2. Manual Reset Timing Diagram

8.4 Device Functional Modes

Table 8-1. Functional Mode Truth Table

OUTPUT ( RESET

PIN)

DESCRIPTION

CONDITION

V_IT–(UV)< SENSE < V_IT+(OV)

SENSE > V_IT-(UV)

MR PIN

VDD PIN

V_DD> V_DD(MIN)

Normal Operation

Open or above V_{MR_H}

High

Normal Operation

(UV Only)

V_DD> V_DD(MIN)

Over Voltage

detection

SENSE > V_IT+(OV)

SENSE < V_IT-(UV)

Open or above V_{MR_H}

Low

Under Voltage

detection

Manual reset

V_IT–(UV)< SENSE < V_IT+(OV)

Below V_{MR_L}

V_DD> V_DD(MIN)

Low

UVLO engaged

Open or above V_{MR_H}

V_POR< V_DD< UVLO

8.4.1 Normal Operation (V_DD> V_DD(MIN)

)

When the voltage on V_DDis greater than V_DD(MIN)for approximately (t_SD+ t_D), the RESET output state will

correspond to the SENSE pin voltage with respect to the threshold limits, when SENSE voltage is outside of

threshold limits the RESET voltage will be low (V_OL).

8.4.2 Undervoltage Lockout (V_POR< V_DD< UVLO)

When the voltage on V_DDis less than the device UVLO voltage but greater than the power-on reset voltage

(V_POR), the RESET pin will be held low , regardless of the voltage on SENSE pin.

8.4.3 Power-On Reset (V_DD< V_POR

)

When the voltage on V_DDis lower than the required voltage (V_POR) to internally pull the asserted output to GND,

RESET signal is undefined and is not to be relied upon for proper device function.

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9 Application and Implementation

Note

Information in the following applications sections is not part of the TI component specification,

and TI does not warrant its accuracy or completeness. TI’s customers are responsible for

determining suitability of components for their purposes, as well as validating and testing their design

implementation to confirm system functionality.

9.1 Application Information

9.1.1 Voltage Threshold Accuracy

Voltage monitoring requirements vary depending on the voltage supply tolerance of the device being powered.

Due to the high precision of the TPS3703-Q1 (±0.7% Max), the device allows for a wider supply voltage margins

and threshold headroom for tight tolerance applications.

For example, take a DC/DC regulator providing power to a core voltage rail of an MCU. The MCU has a

tolerance of ±5% of the nominal output voltage of the DC/DC. The user sets an ideal voltage threshold of ±4%

which allows for ±1% of threshold accuracy. Since the TPS3703-Q1 threshold accuracy is higher than ±1%, the

user has more supply voltage margin which can allow for a relaxed power supply design. This gives flexibility

to the DC/DC to use a smaller output capacitor or inductor because of a larger voltage window for voltage

ripple and transients. There is also headroom between the minimum system voltage and voltage tolerance of the

MCU to ensure that the voltage supply will never be in the region of potential failure of malfunction without the

TPS3703-Q1 asserting a reset signal.

Figure 9-1 illustrates the supply undervoltage margin and accuracy of the TPS3703-Q1 for the example

explained above. Using a low accuracy supervisor will eat into the available budget for the power supply ripple

and transient response. This gives less flexibility to the user and a more stringent DC/DC converter design.

DC/DC nominal output

Supply

Regulator output voltage accuracy

Voltage

Margin

Margin for ripple and transients

Voltage

Threshold

Accuracy

0.7% Allowed threshold tolerance

- 0.7% Minimum system voltage

Potential Failure or Malfunction

Figure 9-1. TPS3703-Q1 Voltage Threshold Accuracy

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9.1.2 CT Reset Time Delay

The TPS3703-Q1 features three options for setting the reset delay (t_D): connecting a capacitor to the CT pin,

connecting a pull-up resistor to VDD, and leaving the CT pin unconnected. Figure 9-2 shows a schematic

drawing of all three options. To determine which option is connected to the CT pin, an internal state machine

controls the internal pulldown device and measures the pin voltage. This sequence of events takes 450 μs

to determine which timing option is used. Every time the voltage on the SENSE line enters the valid window

(V_IT-(UV)+ V_HYS< V_SENSE< V_IT+(OV)-V_HYS, the state machine determines the CT option.

VDD

I_CT

Cap

Control

Cap

Control

Cap

Control

User Programmable

Capacitor to GND

CT Unconnected

10 kΩ Resistor to VDD

Figure 9-2. CT Charging Circuit

9.1.2.1 Factory-Programmed Reset Delay Timing

To use the factory-programmed timing options, the CT pin must either be left unconnected or pulled up to VDD

through a 10 kΩ pull-up resistor. Using these options enables a high-precision reset delay timing, as shown in

Table 9-1.

Table 9-1. Reset Delay Time for Factory-Programmed Reset Delay Timing

RESET DELAY TIME (t_D)

VARIANT

VALUE

CT = Capacitor to GND

Programmable t_D

N/A

CT = Floating

CT = 10 kΩ to VDD

TPS3703A

TPS3703B

TPS3703C

TPS3703D

200

µs

100

9.1.2.2 Programmable Reset Delay-Timing

The TPS3703 reset time delay is based on internal current source (I_CT) to charge external capacitor (C_CT) and

read capacitor voltage with internal comparator. The minium value capacitor is 250 pF. There is no limitation on

maximum capacitor the only constrain is imposed by the initial voltage of the capacitor, if CT cap is zero or near

to zero then ideally there is no other constraint on the max capacitor. The typical ideal capacitor value needed for

a given delay time can be calculated using Equation 1, where C_CTis in nanofarads (nF) and t_Dis in ms:

t_D= 3.066 × C_CT+ 0.5 ms

(1)

To calculate the minimum and maximum-reset delay time use Equation 2 and Equation 3, respectively.

t_D(min)= 2.7427 × C_CT+ 0.3 ms

t_D(max)= 3.4636 × C_CT+ 0.7 ms

(2)

(3)

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The slope of the equation is determined by the time the CT charging current (I_CT) takes to charge the

external capacitor up to the CT comparator threshold voltage (V_CT). When RESET is asserted, the capacitor

is discharged through the internal CT pulldown resistor. When the RESET conditions are cleared, the internal

precision current source is enabled and begins to charge the external capacitor; when V_CT= 1.15 V, RESET

is unasserted. Note that in order to minimize the difference between the calculated RESET delay time and the

actual RESET delay time, use a use a high-quality ceramic dielectric COG, X5R, or X7R capacitor and minimize

parasitic board capacitance around this pin. Table 9-2 lists the reset delay time ideal capacitor values for C_CT

Table 9-2. Reset Delay Time for Ideal Capacitor Values

C_CT

250 pF

1 nF

RESET DELAY TIME (t_D), TYPICAL

1.27 ms

3.57 ms

3.26 nF

32.6 nF

65.2 nF

1uF

10.5 ms

100.45 ms

200.40 ms

3066.50 ms

9.1.3 RESET Latch Mode

The TPS3703-Q1 features a voltage latch mode on the RESET pin when connecting the CT pin to common

ground . A pull-down resistor is recommended to limit current consumption of the system. In latch mode, if the

RESET pin is low or triggers low, the pin will stay low regardless if V_SENSEis within the acceptable voltage

boundaries (V_IT–(UV)< V_SENSE< V_IT+(OV)). To unlatch the device provide a voltage to the CT pin that is greater

than the CT pin comparator threshold voltage, V_CT. The RESET pin will trigger high instantaneously without any

reset delay. A voltage greater than 1.2 V to recommended to ensure a proper unlatch. Use a series resistance

to limit current when an unlatch voltage is applied. For more information, Section 9.2.2 gives an example of a

typical latch application.

VDD

I_CT

10 kꢀ

V > V_CT

Voltage at CT

to Unlatch

Cap

Control

10 kꢀ Resistor to

GND to Latch

Figure 9-3. RESET Latch Circuit

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9.1.4 Adjustable Voltage Thresholds

The TPS3703-Q1 0.7% maximum accuracy allows for adjustable voltage thresholds using external resistors

without adding major inaccuracies to the device. In case that the desired monitored voltage is not available,

external resistor dividers can be used to set the desired voltage thresholds. Figure 9-4 illustrates an example of

how to adjust the voltage threshold with external resistor dividers. The resistors can be calculated depending on

the desired voltage threshold and device part number. TI recommends using the 0.8V voltage threshold device

such as the TPS3703B3080 because of the bypass mode of internal resistor ladder.

For example, consider a 2.0 V rail being monitored (V_MON) using the TPS3703B3080 variant. Using Equation

4, R1 = 15 kΩ given that R2 = 10 kΩ, V_MON= 2 V , and V_SENSE= 0.8 V. This device is typically meant to

monitor a 0.8 V rail with ±3% voltage thresholds. This means that the device undervoltage threshold (V_IT-(UV)

)

and overvoltage threshold (V_IT-(OV)) is 0.776 V and 0.824 V respectively. Using Equation 4 , V_MON= 1.94 V

when V_SENSE= V_IT-(UV). This can be denoted as V_MON-, the monitored undervoltage threshold where the device

will assert a reset signal. Using Equation 4 again, the monitored overvoltage threshold (V_MON+) = 2.06 V when

V_SENSE= V_IT+(OV). If a wider tolerance or UV only threshold is desired, use a device variant shown on Table 7 to

determine what device part number matches your application.

V_SENSE= V_MON× (R₂÷ (R₁+ R₂))

(4)

There are inaccuracies that must be taken into consideration while adjusting voltage thresholds. Aside from the

tolerance of the resistor divider, there is an internal resistance of the SENSE pin that may affect the accuracy

of the resistor divider. Although expected to be very high impedance, users are recommended to calculate the

values for design specifications. The internal sense resistance (R_SENSE) can be calculated by the sense voltage

(V_SENSE) divided by the sense current (I_SENSE) as shown in Equation 6. V_SENSEcan be calculated using Equation

4 depending on the resistor divider and monitored voltage. I_SENSEcan be calculated using Equation 5.

I_SENSE= (V_MON– V_SENSE) ÷ R₁– (V_SENSE÷ R₂)

(5)

(6)

R_SENSE= V_SENSE÷ I_SENSE

V_MON

VDD

10 lQ

TPS3703-Q1

SENSE RESET

V_sense

VDD

GND

Figure 9-4. Adjustable Voltage Threshold with External Resistor Dividers

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9.1.5 Immunity to SENSE Pin Voltage Transients

The TPS3703-Q1 is immune to short voltage transient spikes on the input pins. Sensitivity to transients depends

on both transient duration and overdrive (amplitude) of the transient.

Overdrive is defined by how much the V_SENSEexceeds the specified threshold, and is important to know

because the smaller the overdrive, the slower the response of the outputs ( RESET). Threshold overdrive is

calculated as a percent of the threshold in question, as shown in Equation 7:

Overdrive % = | (V_SENSE- (V_IT-(UV)or V_IT+(OV))) / V_IT(Nominal) × 100% |

(7)

where:

•

V_SENSEis the voltage at the SENSE pin

V_IT(Nominal) is the nominal threshold voltage

V_IT-(UV)and V_IT+(OV)represent the actual undervoltage or overvoltage tripping voltage

9.1.5.1 Hysteresis

Overvoltage and undervoltage comparators include built-in hysteresis that provides noise immunity and ensures

stable operation. For example if the voltage on the SENSE pin falls below V_IT-(UV)or above V_IT+(OV), then RESET

is asserted (driven low), then when the voltage on the SENSE pin is between the positive and negative threshold

voltages, RESET deasserts after the user-defined RESET delay time. Figure Figure 9-5 shows the relation

between V_IT-(UV),V_IT+(OV)and hysteresis voltage (V_HYS).

V_RESET

Window

(V_IT)

VOL

V_SENSE

VIT-(UV)

VIT-(UV) + VHYS

VIT+(OV) - VHYS

VIT+(OV)

Figure 9-5. SENSE Pin Hysteresis

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9.2 Typical Applications

9.2.1 Design 1: Multi-Rail Window Monitoring for Microcontroller Power Rails

A typical application for the TPS3703-Q1 is shown in Figure 9-6. The TPS3703-Q1 is used to monitor two PMIC

voltage rails that powers the core and I/O voltage of the microcontroller that requires accurate reset delay and

voltage supervision. Reference design TIDA-050008 is an ADAS power reference that focuses on improved

voltage supervision. It utilizes the TPS3703-Q1 to monitor the core voltage rail of a MCU similar to the circuit

below.

VDD

V_OUT

V_CORE

V_I/O

V_IN

VDD

10 lQ

PMIC

Microcontroller

RESET

TPS3703-Q1

SENSE

RESET

SENSE

RESET

VDD

GND

10 lQ

Figure 9-6. Two TPS3703-Q1 Monitoring Two Microcontroller Power Rails

9.2.1.1 Design Requirements

Table 9-3. Design Parameters

PARAMETER

DESIGN REQUIREMENT

DESIGN RESULT

3.3-V_I/Onominal, with alerts if outside of ±8% of 3.3

V (including device accuracy), 200 ms reset delay

Worst case V_IT+(OV)= 3.554 V (7.7%),

Worst case V_IT–(UV)= 3.046 V (-7.7%)

Monitored rails

1.2-V_COREnominal, with alerts if outside of ±5%

of 1.2 V (including device accuracy), 10 ms reset

delay

Worst case V_IT+(OV)= 1.256 V (4.7%),

Worst case V_IT–(UV)= 1.144 V (-4.7%)

Output logic voltage

5-V CMOS

50 µA

5-V CMOS

Maximum system supervision

current consumption

14 µA (7 µA Max each)

9.2.1.2 Detailed Design Procedure

Determine which version of the TPS3703-Q1 best suits the monitored rail (V_MON) and window tolerances found

on Table 7. The TPS3703-Q1 allows overvoltage and undervoltage monitoring for precise voltage supervision of

common rails between 0.5 V and 5.0 V. This application calls for very tight monitoring of the rail with only ±5%

of variation allowed on the 1.2V core rail. To ensure this requirement is met, the TPS3703-Q1 was chosen for

its ±4% thresholds. The 3.3V I/O is more flexible and can operate up to 8% variance. Since the TPS3703-Q1

comes in various tolerance options, the ±7% thresholds can be chosen for this voltage rail. To calculate the

worst-case for V_IT+(OV)and V_IT-(UV), the accuracy must also be taken into account. The worst-case for V_IT+(OV)

and V_IT-(UV)can be calculated shown in Equation 8 and Equation 9 respectively:

V_{IT+(OV-Worst Case)}= V_MON× (%Threshold + 0.7%) = 1.2 × (+4.7%) = 1.256 V

V_{IT-(UV-Worst Case)}= V_MON× (%Threshold - 0.7%) = 1.2 × (-4.7%) = 1.144V

(8)

(9)

When the outputs switch to a high impedance state, the rise time of the RESET pin depends on the pull-up

resistance and the capacitance on that node. Choose pull-up resistors that satisfy both the downstream timing

requirements and the sink current required to have a V_OLlow enough for the application; 10 kΩ to 1 MΩ resistors

are a good choice for low-capacitive loads.

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9.2.1.3 Application Curves

V_SENSEStart up from 0 V to 1.2 V, V_DD= 3.3 V, CT = OPEN

V_RESET= VDD = 3.3 V, TPS3703A4120

V_DDStart up from 0 V to 3.3 V, V_SENSE= 1.2 V, CT = OPEN

V_RESET= VDD = 3.3 V, TPS3703A4120

Figure 9-7. TPS3703-Q1 SENSE Start Up Function

Figure 9-8. TPS3703-Q1 VDD Start Up Function

V_IT-(UV),

1.141V

V_IT+(OV),

1.258V

V_SENSEramp from 0 V to 1.4 V, V_DD= 3.3 V, CT = OPEN

V_RESET= VDD = 3.3 V, TPS3703A4120

V_DDramp from 0 V to 3.3 V, V_SENSE= 1.2 V, CT = OPEN

V_RESET= VDD = 3.3 V,TPS3703A4120

Figure 9-9. TPS3703-Q1 Overvoltage and

Undervoltage Function

Figure 9-10. TPS3703-Q1 VDD Ramp Up Function

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9.2.2 Design 2: RESET Latch Mode

Another typical application for the TPS3703-Q1 is shown in Figure 9-6. The TPS3703-Q1 is used in a RESET

latch output mode. In latch mode, once RESET driven logic low, it will stay low regardless of the sense voltage. If

the RESET pin is low on start up, it will also stay low regardless of sense voltage.

V_CORE

VDD

Microcontroller

10 lQ

TPS3703-Q1

V_GPIO

SENSE

VDD

RESET

VDD

Microcontroller

10 lQ

V_GPIO

GND

10 lQ

Figure 9-11. Window Voltage Monitoring with RESET Latch

9.2.2.1 Design Requirements

Table 9-4. Design Parameters

PARAMETER

Monitored Rail

DESIGN REQUIREMENT

DESIGN RESULT

1.2-V_COREnominal, with alerts if outside of ±5%

of 1.2 V (including device accuracy), Latch when

RESET is low, until voltage is applied on CT pin.

Worst case V_IT+(OV)= 1.256 V (4.7%),

Worst case V_IT–(UV)= 1.144 V (-4.7%)

Output logic voltage

5-V CMOS

15 µA

5-V CMOS

Maximum device current

consumption

4.5 µA (Typ), 7 µA (Max)

9.2.2.2 Detailed Design Procedure

The RESET pin can be latched when the CT pin is connected to a common ground with a pull-down resistor.

A 10 kΩ resistors is recommended to limit current consumption. To unlatch the device provide a voltage to the

CT pin that is greater than the CT pin comparator threshold voltage, V_CT. A voltage greater than 1.15 V to

recommended to ensure a proper unlatch. Use a series resistance to limit current when an unlatch voltage is

applied. To go back into latch operation, disconnect the voltage on the CT pin. The RESET pin will trigger high

instanously without any reset delay.

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9.2.2.3 Application Curves

V_SENSEramp from 0 V to 1.4V, V_DD= 3.3 V, V_CT= 0 V V_RESET

= VDD = 3.3 V, TPS3703A4120

V_CTbiased at least to 1.15 V , V_SENSE= 1.2 V V_RESET= VDD

= 3.3 V, TPS3703A4120

Figure 9-12. TPS3703-Q1 SENSE Ramp Latch

Function

Figure 9-13. TPS3703-Q1 CT Bias Unlatch Function

V_Senseramp from 0 V to 1.4 V , V_DD= 3.3 V, V_RESET

V_DDramp up from 0 V to 3.3 V , V_SENSE= 1.2 V, CT = 0 V

V_RESET= VDD = 3.3 V, TPS3703A4120

VDD CT is pulled down after RESET is low, RESET becomes

latched TPS3703A4120

Figure 9-15. TPS3703-Q1 VDD Ramp Latch

Function

Figure 9-14. TPS3703-Q1 Overvoltage and

Undervoltage Latch Function

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10 Power Supply Recommendations

10.1 Power Supply Guidelines

This device is designed to operate from an input supply with a voltage range between 1.7 V to 5.5 V. It has a 6-V

absolute maximum rating on the VDD pin. It is good analog practice to place a 0.1-µF to 1-µF capacitor between

the VDD pin and the GND pin depending on the input voltage supply noise. If the voltage supply providing power

to VDD is susceptible to any large voltage transient that exceed maximum specifications, additional precautions

must be taken. See SNVA849 for more information.

11 Layout

11.1 Layout Guidelines

•

Place the external components as close to the device as possible. This configuration prevents parasitic errors

from occurring.

•

Avoid using long traces for the VDD supply node. The VDD capacitor, along with parasitic inductance from

the supply to the capacitor, can form an LC circuit and create ringing with peak voltages above the maximum

VDD voltage.

•

Avoid using long traces of voltage to the sense pin. Long traces increase parasitic inductance and cause

inaccurate monitoring and diagnostics.

Do not run sensitive analog traces in parallel with digital traces. Avoid crossing digital and analog traces if

possible, and only make perpendicular crossings when absolutely necessary.

11.2 Layout Example

Pull-Up Voltage

V_Sense

VDD

GND

Sense

VDD

10 kΩ

RESET

1 …F

GND

Figure 11-1. Recommended Layout

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12 Device and Documentation Support

12.1 Device Support

12.1.1 Device Nomenclature

Table 12-1 shows how to decode the function of the device based on its part number.

Table 12-1. Device Naming Convention

DESCRIPTION

NOMENCLATURE

VALUE

TPS3703

CT pin open = 10 ms, CT pin tied to VDD = 200 ms

CT programable with external capacitor

CT pin open = 1 ms, CT pin tied to VDD = 20 ms

CT programable with external capacitor

Window

(OV & UV)

CT pin open = 5 ms, CT pin tied to VDD = 100 ms

CT programable with external capacitor

CT pin open = 50 µs, CT pin tied to VDD = 50 µs

CT not programable

Time delay options: Every

part has two fixed time delay

and adjustable delay option via

external capacitor Part number

CT pin open = 10 ms, CT pin tied to VDD = 200 ms

CT programable with external capacitor

CT pin open = 1 ms, CT pin tied to VDD = 20 ms

CT programable with external capacitor

UV only

CT pin open = 5 ms, CT pin tied to VDD = 100 ms

CT programable with external capacitor

CT pin open = 50 µs, CT pin tied to VDD = 50 µs

CT not programable

Window threshold from nominal value = OV : 3%; UV: –3%

Window threshold from nominal value = OV : 4%; UV: –4%

Window threshold from nominal value = OV : 5%; UV: –5%

Window threshold from nominal value = OV : 6%; UV: –6%

Window threshold from nominal value = OV : 7%; UV: –7%

Tolerance options: Trigger or threshold

voltage as a percentage of the monitored

threshold voltage

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Product Folder Links: TPS3703-Q1

TPS3703-Q1

SBVS344D – NOVEMBER 2018 – REVISED MARCH 2021

www.ti.com

Table 12-1. Device Naming Convention

(continued)

DESCRIPTION

NOMENCLATURE

VALUE

Nominal monitor threshold voltage option

050

055

060

065

070

075

080

085

090

095

100

105

110

115

120

125

130

150

180

250

280

290

330

500

DSE

0.50 V

0.55 V

0.60 V

0.65 V

0.70 V

0.75 V

0.80 V

0.85 V

0.90 V

0.95 V

1.00 V

1.05 V

1.10 V

1.15 V

1.20 V

1.25 V

1.30 V

1.50 V

1.80 V

2.50 V

2.80 V

2.90 V

3.30 V

5.00 V

Package

WSON - 6 pin (1.5 mm × 1.5 mm)

Large reel

Reel

Automotive version

Q100 AEC

Submit Document Feedback

Product Folder Links: TPS3703-Q1

TPS3703-Q1

SBVS344D – NOVEMBER 2018 – REVISED MARCH 2021

www.ti.com

12.2 Documentation Support

12.2.1 Evaluation Module

An evaluation module (EVM) is available to assist in the initial circuit performance evaluation using the

TPS3703-Q1. The TPS3703-Q1 evaluation module (and related user guide) can be requested at the Texas

Instruments website through the product folders or purchased directly from the TI eStore .

12.3 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on

Subscribe to updates to register and receive a weekly digest of any product information that has changed. For

change details, review the revision history included in any revised document.

12.4 Support Resources

TI E2E^™support forums are an engineer's go-to source for fast, verified answers and design help — straight

from the experts. Search existing answers or ask your own question to get the quick design help you need.

Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do

not necessarily reflect TI's views; see TI's Terms of Use.

12.5 Trademarks

TI E2E^™is a trademark of Texas Instruments.

All trademarks are the property of their respective owners.

12.6 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

12.7 Glossary

TI Glossary

This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

Submit Document Feedback

Product Folder Links: TPS3703-Q1

PACKAGE OPTION ADDENDUM

www.ti.com

20-May-2021

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

TPS3703A4085DSERQ1

TPS3703A4120DSERQ1

TPS3703A4180DSERQ1

TPS3703A4280DSERQ1

TPS3703A4330DSERQ1

TPS3703A5090DSERQ1

TPS3703A5180DSERQ1

TPS3703A5290DSERQ1

TPS3703A7080DSERQ1

TPS3703A7100DSERQ1

TPS3703A7110DSERQ1

TPS3703A7120DSERQ1

TPS3703A7125DSERQ1

TPS3703A7180DSERQ1

TPS3703A7250DSERQ1

TPS3703A7280DSERQ1

TPS3703A7330DSERQ1

TPS3703B3080DSERQ1

TPS3703B4250DSERQ1

TPS3703B5180DSERQ1

ACTIVE

WSON

DSE

3000 RoHS & Green

NIPDAUAG

Level-1-260C-UNLIM

-40 to 125

NIPDAUAG

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

20-May-2021

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

TPS3703C7500DSERQ1

TPS3703E4080DSERQ1

ACTIVE

WSON

DSE

3000 RoHS & Green

NIPDAUAG

Level-1-260C-UNLIM

-40 to 125

NIPDAUAG

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF TPS3703-Q1 :

Addendum-Page 2

PACKAGE OPTION ADDENDUM

www.ti.com

20-May-2021

Catalog : TPS3703

•

NOTE: Qualified Version Definitions:

Catalog - TI's standard catalog product

•

Addendum-Page 3

PACKAGE MATERIALS INFORMATION

www.ti.com

21-May-2021

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TPS3703A4085DSERQ1 WSON

TPS3703A4120DSERQ1 WSON

TPS3703A4180DSERQ1 WSON

TPS3703A4280DSERQ1 WSON

TPS3703A4330DSERQ1 WSON

TPS3703A5090DSERQ1 WSON

TPS3703A5180DSERQ1 WSON

TPS3703A5290DSERQ1 WSON

TPS3703A7080DSERQ1 WSON

TPS3703A7100DSERQ1 WSON

TPS3703A7110DSERQ1 WSON

TPS3703A7120DSERQ1 WSON

TPS3703A7125DSERQ1 WSON

TPS3703A7180DSERQ1 WSON

TPS3703A7250DSERQ1 WSON

TPS3703A7280DSERQ1 WSON

TPS3703A7330DSERQ1 WSON

TPS3703B3080DSERQ1 WSON

DSE

3000

178.0

8.4

1.7

0.95

4.0

8.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

21-May-2021

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TPS3703B4250DSERQ1 WSON

TPS3703B5180DSERQ1 WSON

TPS3703C7500DSERQ1 WSON

TPS3703E4080DSERQ1 WSON

DSE

3000

178.0

8.4

1.7

0.95

4.0

8.0

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

TPS3703A4085DSERQ1

TPS3703A4120DSERQ1

TPS3703A4180DSERQ1

TPS3703A4280DSERQ1

TPS3703A4330DSERQ1

TPS3703A5090DSERQ1

TPS3703A5180DSERQ1

TPS3703A5290DSERQ1

TPS3703A7080DSERQ1

TPS3703A7100DSERQ1

TPS3703A7110DSERQ1

TPS3703A7120DSERQ1

TPS3703A7125DSERQ1

WSON

DSE

3000

205.0

200.0

33.0

Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

21-May-2021

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

TPS3703A7180DSERQ1

TPS3703A7250DSERQ1

TPS3703A7280DSERQ1

TPS3703A7330DSERQ1

TPS3703B3080DSERQ1

TPS3703B4250DSERQ1

TPS3703B5180DSERQ1

TPS3703C7500DSERQ1

TPS3703E4080DSERQ1

WSON

DSE

3000

205.0

200.0

33.0

Pack Materials-Page 3

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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

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These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

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permission to use these resources only for development of an application that uses the TI products described in the resource. Other

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TI’s products are provided subject to TI’s Terms of Sale (https:www.ti.com/legal/termsofsale.html) or other applicable terms available either

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applicable warranties or warranty disclaimers for TI products.IMPORTANT NOTICE

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

TPS3703A7110DSERQ1 [TI]

相关型号：

TPS3703A7120DSERQ1

TPS3703A7125DSERQ1

TPS3703A7180DSERQ1

TPS3703A7250DSERQ1

TPS3703A7280DSERQ1

TPS3703A7330DSER

TPS3703A7330DSERQ1

TPS3703B3080DSERQ1

TPS3703B4250DSERQ1

TPS3703B5180DSERQ1

TPS3703B6050DSER

TPS3703C7115DSERQ1