TPS37044BJOFDDFRQ1 [TI]
超高精度紧凑型汽车多通道窗口监控器 | DDF | 8 | -40 to 125;型号: | TPS37044BJOFDDFRQ1 |
厂家: | TEXAS INSTRUMENTS |
描述: | 超高精度紧凑型汽车多通道窗口监控器 | DDF | 8 | -40 to 125 监控 |
文件: | 总34页 (文件大小:3014K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
TPS3704
SNVSBZ2B – MARCH 2021 – REVISED DECEMBER 2021
TPS3704x Quad, Triple, Dual, Single Window or Standard Voltage Supervisor
1 Features
3 Description
•
Designed for high performance and safety:
– Input current (4 channels): IDD = 15 μA
(maximum)
– High threshold accuracy: ±1% (maximum)
– Built-in precision hysteresis:
VHYS (VIT > 800 mV) = 0.75% (typical)
Designed for a wide range of applications:
– Quad, triple, dual, or single voltage supervisor
The TPS3704x is a low-power precision window or
standard voltage supervisor that can be configured as
a quad, triple, dual, or single channel. Each channel
has a threshold accuracy of ±1% in an 8-pin
(1.6 mm x 2.9 mm) SOT-23 package offering a small
solution size. The TPS3704x includes a very accurate
threshold detection, with high resolution, that is ideal
for systems that operate on low-voltage supply rails
and have narrow margin supply tolerances. Built-in
low threshold hysteresis and a fixed reset delay (tD
options from 20 μs to 1200 ms) prevent false reset
signals when monitoring multiple voltage rails.
•
•
TPS37044, 3, 2, 1: 4, 3, 2, 1 - channels
– Input voltage range, VDD = 1.7 V to 6 V
– (UV / OV) threshold accuracy: ±0.1% (typical)
•
•
•
Each channel can be configured
independently: window, UV, or OV
Window tolerance: ±3% to ±11%
(can be programmed asymmetrical)
High threshold resolution:
The TPS3704x does not require any external
resistors for setting the over and under voltage
reset thresholds, which further optimizes overall high
accuracy, cost, solution size, and improves reliability
for safety systems.
VIT ≤ 0.8 V: 20 mV steps
VIT > 0.8 V: lower of 0.5% or 20 mV steps
VIT threshold voltages for each individual
channel can be set independently
Separate VDD and SENSEx pins allow monitoring of
rail voltages other than VDD or can be used as a
push-button input. Optional use of external resistors
are supported by the SENSEx pins. Each channel on
the TPS3704x can be customized to its own over and
under voltage window detection with an upper and
lower threshold tolerance that can be symmetric or
asymmetric.
•
– Push-button monitor on all channels
– Reset time delay (tD): fixed time delay options
Options: 23-fixed time options ranging from
20 µs (minimum) to 1200 ms (maximum)
– Temperature range: –40°C to +125°C
Multiple output topologies:
– TPS3704xxxO: open-drain, active-low (RESET)
– TPS3704xxxL: push-pull, active-low (RESET)
– TPS3704xxxH: push-pull, active-high (RESET)
•
•
Device Information
PART NUMBER
PACKAGE (1)
BODY SIZE (NOM)
TPS3704x
DDF (SOT-23 8-pin)
1.6 mm × 2.9 mm
2 Applications
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
•
•
•
•
•
•
•
Factory automation
Building automation
Medical
VDD
VDD
RESET1
RESET2
RESET3
RPULL_UP
RESET
Microcontroller
Motor drives
TPS37043
Grid infrastructure
Wireless infrastructure
Data center & enterprise computing
SENSE1 SENSE2 SENSE3
3.3 V
1.8 V
24 V VIN
Wide VIN
Buck
VI/O
DVDD
DC/DC
1.2 V
VCORE
Typical Application Circuit
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS3704
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SNVSBZ2B – MARCH 2021 – REVISED DECEMBER 2021
Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Device Nomenclature......................................................3
6 Pin Configuration and Functions...................................4
7 Specifications.................................................................. 6
7.1 Absolute Maximum Ratings........................................ 6
7.2 ESD Ratings............................................................... 6
7.3 Recommended Operating Conditions.........................6
7.4 Thermal Information....................................................7
7.5 Electrical Characteristics.............................................7
7.6 Timing Requirements..................................................8
7.7 Timing Diagrams ........................................................9
7.8 Typical Characteristics.............................................. 11
8 Detailed Description......................................................15
8.1 Overview...................................................................15
8.2 Functional Block Diagram.........................................15
8.3 Feature Description...................................................17
8.4 Device Functional Modes..........................................19
9 Application and Implementation..................................20
9.1 Application Information............................................. 20
9.2 Typical Application.................................................... 22
10 Power Supply Recommendations..............................25
10.1 Power Supply Guidelines........................................25
11 Layout...........................................................................26
11.1 Layout Guidelines................................................... 26
11.2 Layout Example...................................................... 26
12 Device and Documentation Support..........................27
12.1 Device Nomenclature..............................................27
12.2 Receiving Notification of Documentation Updates..28
12.3 Support Resources................................................. 28
12.4 Trademarks.............................................................28
12.5 Electrostatic Discharge Caution..............................28
12.6 Glossary..................................................................28
13 Mechanical, Packaging, and Orderable
Information.................................................................... 28
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (July 2021) to Revision B (November 2021)
Page
•
Change from Advance Information to Production Data...................................................................................... 1
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SNVSBZ2B – MARCH 2021 – REVISED DECEMBER 2021
5 Device Nomenclature
Figure 5-1 shows the device naming nomenclature to compare the different device variants. See Table 12-1 for a
more detailed explanation. See Table 12-2 for the available device variants.
TPS3704 X XX X X XXXR
DETECTION OPTIONS
Example:
** - Threshold (Tolerance%)
*J – Adjustable Variant
OUTPUT TYPE
RESET TIME DELAY PACKAGE
NUMBER OF CHANNELS
1: Single
2: Dual
3: Triple
4: Quad
O: Open Drain – Ac ve Low
L: Push Pull – Ac ve Low
H: Push Pull – Ac ve High
A:
B:
C:
D:
E:
F:
G:
H:
I:
J:
K:
L:
M:
N:
O:
P:
R:
S:
20 µs
1 ms
2 ms
3 ms
5 ms
DDF = SOT-23 8-pin
R = Large reel
A1 (Window)
CH1 = 3.4085 V / 3.184 V
CH2 = 1.245 V / 1.152 V
10 ms
15 ms
20 ms
25 ms
35 ms
40 ms
50 ms
70 ms
100 ms
140 ms
150 ms
200 ms
280 ms
400 ms
560 ms
800 ms
A2 (Window)
CH1 = 5.0 V (±4%)
...
A3 (Window)
CH1 = 3.3 V (±4%)
CH2 = 2.9 V (±4%)
CH3 = 1.8 V (±4%)
CH4 = 1.2 V (±4%)
…
AJ (Window) - Adjustable Variant
CH1 = 0.4 V (±4%)
CH2 = 0.8 V (±4%)
CH3 = 0.8 V (±4%)
CH4 = 0.8 V (±4%)
T:
U:
V:
W: 1120 ms
X: 1200 ms
…
BJ (Window) - Adjustable Variant
CH1 = 0.8 V (±4%)
CH2 = 0.8 V (±4%)
CH3 = 0.8 V (±4%)
CH4 = 0.8 V (±4%)
Figure 5-1. Device Naming Nomenclature
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6 Pin Configuration and Functions
VDD
SENSE1
SENSE2
GND
VDD
SENSE1
NC
RESET1
RESET1
1
8
1
8
2
3
4
7
6
5
2
3
4
7
6
5
NC
NC
NC
RESET2
NC
GND
NC
Not to scale
Not to scale
Figure 6-1. SOT-23 8-PIN DDF Package
Figure 6-2. SOT-23 8-PIN DDF Package
TPS37041
(Top View)
TPS37042
(Top View)
VDD
SENSE1
SENSE2
GND
VDD
SENSE1
SENSE2
GND
RESET1
RESET1
1
8
1
8
2
3
4
7
6
5
2
3
4
7
6
5
RESET2
RESET3
SENSE3
RESET2
SENSE4
SENSE3
Not to scale
Not to scale
Figure 6-3. SOT-23 8-PIN DDF Package
Figure 6-4. SOT-23 8-PIN DDF Package
TPS37043
(Top View)
TPS37044
(Top View)
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Table 6-1. Pin Functions
PIN
I/O
DESCRIPTION
NAME TPS37041 TPS37042 TPS37043 TPS37044
VDD
1
2
1
2
1
2
1
2
I
I
Supply Input. Bypass with a 0.1 µF capacitor to GND.
Connect directly to monitored voltage. RESET1/RESET1 is asserted when
SENSE1 falls outside of window threshold. No external capacitor is required
for this SENSE1 pin. For TPS37044 (quad version) RESET1/RESET1
asserts when either SENSE1 or SENSE2 falls outside of window threshold.
For noisy applications, placing a 10 nF to 100 nF ceramic capacitor close
to this pin may be needed for optimum performance. If the input pin is not
being used, it can be left floating.
SENSE1
Connect directly to monitored voltage. RESET2/RESET2 is asserted when
SENSE2 falls outside of window threshold. No external capacitor is required
for SENSE2 pin. For TPS37044 (quad version) RESET1/RESET1 asserts
when either SENSE1 or SENSE2 falls outside of window threshold. For
noisy applications, placing a 10 nF to 100 nF ceramic capacitor close to this
pin may be needed for optimum performance. If the input pin is not being
used, it can be left floating.
SENSE2
-
3
3
3
I
Connect directly to monitored voltage. RESET3/RESET3 is asserted when
SENSE3 falls outside of window threshold. No external capacitor is required
for SENSE3 pin. For TPS37044 (quad version) RESET2/RESET2 asserts
when either SENSE3 or SENSE4 falls outside of window threshold. For
noisy applications, placing a 10 nF to 100 nF ceramic capacitor close to this
pin may be needed for optimum performance. If the input pin is not being
used, it can be left floating.
SENSE3
SENSE4
-
-
-
-
5
-
5
6
I
I
Connect directly to monitored voltage. For TPS37044 (quad version)
RESET2/RESET2 asserts when either SENSE3 or SENSE4 falls outside of
window threshold. For noisy applications, placing a 10 nF to 100 nF ceramic
capacitor close to this pin may be needed for optimum performance. If the
input pin is not being used, it can be left floating.
RESET1/RESET1 asserts when SENSE1 falls outside of the over-voltage or
under-voltage threshold window.
RESET1/RESET1 stays asserted for the reset timeout period after SENSE1
fall back within the window threshold. Active-low, open-drain reset output,
requires an external pullup resistor. For TPS37044, RESET1/RESET1
asserts when either SENSE1 or SENSE2 fall outside of the window
threshold. The pin can be left floating if it is unused.
RESET1
/
RESET1
8
8
8
8
O
RESET2/RESET2 asserts when SENSE2 falls outside of the overvoltage or
undervoltage threshold window.
RESET2/RESET2 stays asserted for the reset timeout period after SENSE2
fall back within the window threshold. Active-low, open-drain reset output,
requires an external pullup resistor. For TPS37044, RESET2/RESET2
asserts when either SENSE3 or SENSE4 fall outside of the window
threshold. The pin can be left floating if it is unused.
RESET2
/
RESET2
-
-
7
7
6
7
O
O
RESET3/RESET3 asserts when SENSE3 falls outside of the overvoltage or
undervoltage threshold window.
RESET3/RESET3 stays asserted for the reset timeout period after SENSE3
fall back within the window threshold. Active-low, open-drain reset output,
requires an external pullup resistor. The pin can be left floating if it is
unused.
RESET3
/
RESET3
-
-
GND
NC
4
4
4
-
4
-
-
-
Ground
3, 5, 6, 7
5, 6
No Connect
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7 Specifications
7.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted) (1)
MIN
–0.3
–0.3
–0.3
MAX UNIT
VDD
6.5
6.5
6.5
±20
V
V
Voltage
Current
VRESET1, VRESET2, VRESET3
VSENSE1, VSENSE2, VSENSE3, VSENSE4
IRESET1, IRESET2,IRESET3 SINK
Continuous total power dissipation
Operating junction temperature, TJ
Operating free-air temperature, TA
Storage temperature, Tstg
V
mA
See the Thermal Information
-40
-40
-65
150
150
150
°C
°C
°C
Temperature (2)
(1) Stresses beyond values listed under Absolute Maximum Ratings (AMR) may cause permanent damage to the device. These are
stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to AMR-rated conditions for extended periods may affect device reliability.
(2) As a result of the low dissipated power in this device, it is assumed that TJ = TA.
7.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per ANSI/ESDA/
JEDEC JS-001 (1)
±2000
Electrostatic
discharge
V(ESD)
V
Charged device model (CDM), per JEDEC
specification JESD22-C101 (2)
±750
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process
7.3 Recommended Operating Conditions
MIN
1.7
0
NOM
MAX
6.0
6.0
6.0
5
UNIT
V
VDD
Supply pin voltage
VSENSE1,2,3,4
Input pin voltage
V
VRESET1, VRESET2, VRESET3
IRESET1, IRESET2, IRESET3 SINK
TA
Output pin voltage
0
V
Output pin current sink
Operating free air temperature
0.3
-40
mA
℃
125
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7.4 Thermal Information
TPS3704x
THERMAL METRIC (1)
DDF
PINS
121.5
60.6
42.3
2.2
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
ΨJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ΨJB
42.1
N/A
RθJC(bot)
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Electrical Characteristics
At 1.7 V ≤ VDD ≤ 6.0 V, RESETx Voltage (VRESETx) = 10 kΩ to VDD, RESETx load = 10 pF, and over the operating free-air
temperature range of – 40°C to 125°C, unless otherwise noted. Typical values are at TA = 25°C, typical conditions at VDD
3.3 V.
=
PARAMETER
TEST CONDITIONS
MIN TYP MAX
UNIT
VDD
Supply Voltage
1.7
1.2
6.0
1.6
V
UVLO
Under Voltage Lockout (1)
UVLO Hysteresis (2)
VDD falling below 1.7 V
1.4
65
V
UVLO(HYS)
VPOR
VDD rising below 1.7 V
mV
Power on reset voltage (3)
Threshold Programming Range
UV accuracy (25℃)
VOL (MAX) = 0.3 V, IOUT = 15 µA
0.7
V
VIT Range
VIT- (UV)
VIT+ (OV)
TOL_min
TOL_max
0.4
5.55
V
0.1
0.1
3
%
%
OV accuracy (25℃)
Tolerance Programming minimum
Tolerance Programming maximum
%
11
%
THR RES Low Threshold Programming Resolution Low VIT ≤ 0.8 V
THR RES Mid Threshold Programming Resolution Mid 0.8 V < VIT ≤ 4.0 V
Threshold Programming Resolution
20
0.5
mV / step
% / step
THR RES High
VIT > 4.0 V
20
mV / step
High
Accuracy for absolute threshold
including tolerance
VIT
VIT
VIT < 0.8 V
-1.6
1.6
1
%
%
Accuracy for absolute threshold
including tolerance
VIT = 0.8 V - 5.55 V
-1
VHYS
VHYS
IDD
VIT < 0.80V
1.1
1.4
1.7
1
%
%
VIT ≥ 0.80V
0.40 0.75
TPS3704x
VDD ≤ 6.0V
5.5
1
15
2.5
µA
µA
ISENSEx
Input current, SENSEx pin
VSENSEx = 5.5 V
Input current, SENSE pin (Bypass
internal resistor divider)- Adjustible
version
ISENSE_ADJ
VSENSEx = 5.5 V
350
nA
VOL
VOL
VOL
I(lkg)
Low level output voltage
VDD = 1.7 V, ISINK = 0.4 mA
VDD = 2 V, ISINK = 3 mA
VDD = 6.0 V, ISINK = 5 mA
VDD = VRESETx = 6.0 V
300
300
300
350
mV
mV
mV
nA
Low level output voltage
Low level output voltage
Open drain output leakage current
(1) RESETx pin is driven low when VDD falls below UVLO.
(2) Hysteresis is with respect of the tripoint (VIT- (UV), VIT+ (OV)).
(3) VPOR is the minimum VDD voltage level for a controlled output state. Slew rate = 100 mV / µs.
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7.6 Timing Requirements
At 1.7 V ≤ VDD ≤ 6.0 V, RESETx voltage (VRESETx) = 10 kΩ to VDD, RESETx load = 10 pF, and over the operating free-air
temperature range of – 40°C to 125°C, unless otherwise noted. Typical values are at TA = 25°C, typical conditions at VDD
3.3 V.
=
PARAMETER
Reset release time delay
Reset release time delay
Propagation detect delay (1)
TEST CONDITIONS
MIN NOM MAX UNIT
tD
Fixed delay option tD < 4 ms, overdrive = 10%
Fixed delay option tD > 5 ms, overdrive = 10%
Fixed time delay tD > 1 ms, overdrive 10%
-40
-30
tD
tD
40
30
%
%
tD
tPD
10 µs
µs
tGI(VIT-) Glitch Immunity Undervoltage (5% overdrive) (2)
tGI(VIT+) Glitch Immunity Overvoltage (5% overdrive) (2)
2
2
µs
tR
Ouptut rise (Push-Pull) (2) (3)
Output rise time (Open-Drain) (2) (3)
Output fall time (2) (3)
25
2.2
0.2
1
ns
tR
µs
tF
µs
tSTRT
Startup delay (4)
ms
(1) tPD measured from threshold trip point (VIT-(UV) or VIT+(OV)) to RESETx VOL voltage
(2) 5% Overdrive from threshold. Overdrive % = [(VSENSEx - VIT) / VIT]; Where VIT stands for VIT-(UV) or VIT+(OV)
(3) Output transitions from VOL to VOH or (VRESETx) for rise times and VOH or (VRESETx) to VOL for fall times.
(4) During the power-on sequence, VDD must be at or above VDD(MIN) for at least tSTRT + tD before the output is in the correct state. when
VDD is between VDD(MIN) and VPOR the RESETx pin will be engaged
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7.7 Timing Diagrams
Highest Absolute Limit for the Monitored Voltage Rail
[1%]
VIT+(OV)MAX
Accuracy band across
(-40ºC to 125ºC)
VIT+(OV) [typical]
VIT+(OV)MIN
[0.4% * (VIT+(OV)MIN)]
Hys band for VIT+(OV)
[VHYSMAX = 1% * (VIT+(OV)MIN )]
Power
Supply
Tolerance
Window
[VHYSMAX = 1% * (VIT-(UV)MIN )]
[0.4% * (VIT-(UV)MIN)]
Hys band for VIT-(UV)
[1%]
VIT-(UV)MIN
Accuracy band across
(-40ºC to 125ºC)
VIT-(UV) [typical]
VIT-(UV)MAX
Lowest Absolute Limit for the Monitored Voltage Rail
Figure 7-1. Voltage Threshold and Hysteresis Accuracy
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VDD(MIN)
UVLO
UVLO - UVLO(HYS)
VDD
VPOR
VIT+(OV)
Hysteresis
VIT+(OV) - VHYS
SENSEx
VIT
VIT-(UV) + VHYS
VIT-(UV)
Hysteresis
*See
Note C
RESETx
(-O: open-drain)
tSTRT + tD
tPD
tD
tPD
tD
A. Open-Drain timing diagram assumes the RESETx / RESETx pin is connected via an external pull-up resistor to VDD.
B. Be advised that Figure 7-2 shows the VDD falling slew rate is slow or the VDD decay time is much larger than the propagation detect delay (tPD) time.
C. RESETx/RESETx is asserted after a time delay, typical value of 100 μs, when VDD goes below the UVLO-UVLO(HYS) threshold.
Figure 7-2. SENSEx Timing Diagram
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7.8 Typical Characteristics
Typical characteristics show the typical performance of the TPS3704x device. Test conditions are TA = 25°C, VDD = 3.3 V,
and Rpull-upx = 10 kΩ, CLOAD = 50 pF, unless otherwise noted.
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0.00
-0.05
-0.10
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0.00
-0.05
-0.10
CH 1 - 5.0 V
CH 2 - 1.8 V
CH 3 - 0.8 V
CH 4 - 0.4 V
CH 1 - 5.0 V
CH 2 - 1.8 V
CH 3 - 0.8 V
CH 4 - 0.4 V
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Temperature (èC)
Temperature (èC)
UV_a
OV_a
Figure 7-3. Undervoltage Accuracy vs Temperature
Figure 7-4. Overvoltage Accuracy vs Temperature
1.80
1.70
1.60
1.50
1.40
1.30
1.20
1.10
1.00
0.90
0.80
0.70
0.60
1.80
1.70
1.60
1.50
1.40
1.30
1.20
1.10
1.00
0.90
0.80
0.70
0.60
CH 1 - 5.0 V
CH 2 - 1.8 V
CH 3 - 0.8 V
CH 4 - 0.4 V
CH 1 - 5.0 V
CH 2 - 1.8 V
CH 3 - 0.8 V
CH 4 - 0.4 V
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Temperature (èC)
Temperature (èC)
UV_H
OV_H
Figure 7-5. Undervoltage Hysteresis Voltage Accuracy vs
Temperature
Figure 7-6. Overvoltage Hysteresis Voltage Accuracy vs
Temperature
9
0.06
VDD = 3.3 V
-40èC
25èC
125èC
8
7
6
5
4
3
0.05
0.04
0.03
0.02
0.01
0
-50
-25
0
25
50
75
100
125
150
0
0.001
0.002
0.003
0.004
0.005
0.006
0.007
VOLV
Temperature (èC)
IRESET1 (A)
IDD_
Output ( RESETx Pin) = High
Figure 7-7. Supply Current vs Temperature
VDD = 1.7 V
Figure 7-8. Low-Level CH 1 Output Voltage vs RESET1 Current
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7.8 Typical Characteristics (continued)
Typical characteristics show the typical performance of the TPS3704x device. Test conditions are TA = 25°C, VDD = 3.3 V,
and Rpull-upx = 10 kΩ, CLOAD = 50 pF, unless otherwise noted.
0.06
0.05
0.04
0.03
0.02
0.01
0
0.06
0.05
0.04
0.03
0.02
0.01
0
-40èC
25èC
125èC
-40èC
25èC
125èC
0
0.001
0.002
0.003
0.004
0.005
0.006
0.007
VOLV
0
0.001
0.002
0.003
0.004
0.005
0.006
0.007
VOLV
IRESET1 (A)
IRESET2 (A)
VDD = 5 V
VDD = 1.7 V
Figure 7-9. Low-Level CH 1 Output Voltage vs RESET1 Current Figure 7-10. Low-Level CH 2 Output Voltage vs RESET2 Current
0.06
0.05
0.04
0.03
0.02
0.01
0
0.06
0.05
0.04
0.03
0.02
0.01
0
-40èC
25èC
125èC
-40èC
25èC
125èC
0
0.001
0.002
0.003
0.004
0.005
0.006
0.007
VOLV
0
0.001
0.002
0.003
0.004
0.005
0.006
0.007
VOLV
IRESET2 (A)
IRESET3 (A)
VDD = 5 V
VDD = 1.7 V
Figure 7-11. Low-Level CH 2 Output Voltage vs RESET2 Current Figure 7-12. Low-Level CH 3 Output Voltage vs RESET3 Current
0.06
0.05
0.04
0.03
0.02
0.01
0
0.06
0.05
0.04
0.03
0.02
0.01
0
-40èC
25èC
125èC
-40èC
25èC
125èC
0
0.001
0.002
0.003
0.004
0.005
0.006
0.007
VOLV
0
0.001
0.002
0.003
0.004
0.005
0.006
0.007
VOLV
IRESET3 (A)
IRESET4 (A)
VDD = 5 V
VDD = 1.7 V
Figure 7-13. Low-Level CH 3 Output Voltage vs RESET3 Current Figure 7-14. Low-Level CH 4 Output Voltage vs RESET4 Current
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7.8 Typical Characteristics (continued)
Typical characteristics show the typical performance of the TPS3704x device. Test conditions are TA = 25°C, VDD = 3.3 V,
and Rpull-upx = 10 kΩ, CLOAD = 50 pF, unless otherwise noted.
0.06
6
-40èC
-40oC
25èC
25oC
125èC
0.05
125oC
5
0.04
4
0.03
3
0.02
2
0.01
1
0
0
0
0.001
0.002
0.003
0.004
0.005
0.006
0.007
VOLV
0
3
6
9
12
15
IRESET4 (A)
Overdrive (%)
VDD = 5 V
VDD = 1.7 V
Figure 7-15. Low-Level CH 4 Output Voltage vs RESET4 Current
Figure 7-16. SENSE1 Glitch Immunity (VIT-) vs Overdrive
6
6
-40oC
25oC
-40oC
25oC
125oC
125oC
5
5
4
3
2
1
0
4
3
2
1
0
0
3
6
9
12
15
0
3
6
9
12
15
Overdrive (%)
Overdrive (%)
VDD = 1.7 V
VDD = 3.3 V
Figure 7-17. SENSE1 Glitch Immunity (VIT+) vs Overdrive
Figure 7-18. SENSE1 Glitch Immunity (VIT-) vs Overdrive
6
6
-40oC
25oC
-40oC
25oC
125oC
125oC
5
5
4
3
2
1
0
4
3
2
1
0
0
3
6
9
12
15
0
3
6
9
12
15
Overdrive (%)
Overdrive (%)
VDD = 3.3 V
VDD = 5 V
Figure 7-19. SENSE1 Glitch Immunity (VIT+) vs Overdrive
Figure 7-20. SENSE1 Glitch Immunity (VIT-) vs Overdrive
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7.8 Typical Characteristics (continued)
Typical characteristics show the typical performance of the TPS3704x device. Test conditions are TA = 25°C, VDD = 3.3 V,
and Rpull-upx = 10 kΩ, CLOAD = 50 pF, unless otherwise noted.
6
-40oC
25oC
125oC
5
4
3
2
1
0
0
3
6
9
12
15
Overdrive (%)
VDD = 5 V
Figure 7-21. SENSE1 Glitch Immunity (VIT+) vs Overdrive
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8 Detailed Description
8.1 Overview
TPS3704x is a family of quad, triple, dual, and single precision voltage supervisors where each channel has
overvoltage and undervoltage detection capability. The TPS3704x features a highly accurate window threshold
voltage where the upper and lower thresholds can be customized for symmetric or asymmetric tolerances. The
reset signal for the TPS3704x is asserted, with a fault detection time delay (tPD = 10 μs maximum), when the
sense voltage is outside of the overvoltage and undervoltage thresholds.
TPS3704x includes the resistors used to set the overvoltage and undervoltage thresholds internal to the
device. These internal resistors allow for lower component counts and greatly simplifies the design because
no additional margins are needed to account for the accuracy of external resistors. The level of integration in the
TPS3704x enables a total small solution size for any application.
The TPS3704x is capable to monitor any voltage rail with high resolution (VIT ≤ 0.8 V: 20 mV steps /
VIT > 0.8 V: 0.5% or 20 mV steps whichever is lower). Each channel in the TPS3704x can be configured
independently as a window, OV or UV supervisor. Also, the VIT threshold voltage for each channel can be
asymmetric. For example, a channel that is configured as an overvoltage supervisor can be setup with a +5%
tolerance whereas an undervoltage channel supervisor can be programmed with a -4% tolerance. If a window
supervisor is configured, the voltage threshold tolerance can either be symmetrical or asymmetrical.
The TPS3704x includes fixed reset time delay (tD) options ranging from 20 μs to 1200 ms and can monitor up to
four channels while maintaining an ultra-low IQ current of 15 μA (maximum).
8.2 Functional Block Diagram
POR
OTP
BANDGAP
OSCILLATOR
VDD
GND
VDD
VBG
CLK
+
–
VBG
UVLO
VREF_UVLO
SENSE1
SENSE1
CLK
UNDERVOLTAGE
+
VBG
RESET1
TIME DELAY
(counter)
–
VREF_UV
OTPUV_EN
OTPOV_EN
VREF_OV
SENSE1
UVLO
+
–
OVERVOLTAGE
Figure 8-1. TPS37041 Single-Channel Functional Block Diagram
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POR
OTP
BANDGAP
OSCILLATOR
VDD
GND
VDD
VBG
CLK
+
VBG
UVLO
–
VREF_UVLO
SENSE1
SENSE1
SENSE2
CLK
UNDERVOLTAGE
+
VBG
RESET1
RESET2
TIME DELAY
(counter)
–
VREF_UV
OTPUV_EN
OTPOV_EN
VREF_OV
SENSE1
UVLO
+
–
OVERVOLTAGE
Figure 8-2. TPS37042 Dual-Channel Functional Block Diagram
POR
OTP
BANDGAP
OSCILLATOR
VDD
GND
VDD
VBG
CLK
+
–
VBG
UVLO
VREF_UVLO
SENSE1
SENSE1
SENSE2
SENSE3
CLK
UNDERVOLTAGE
VBG
+
RESET1
RESET2
RESET3
TIME DELAY
(counter)
–
VREF_UV
OTPUV_EN
OTPOV_EN
VREF_OV
SENSE1
UVLO
+
–
OVERVOLTAGE
Figure 8-3. TPS37043 Triple-Channel Functional Block Diagram
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POR
OTP
BANDGAP
OSCILLATOR
VDD
GND
VDD
VBG
CLK
+
–
VBG
UVLO
VREF_UVLO
SENSE1
SENSE1
SENSE3
CLK
UNDERVOLTAGE
+
VBG
TIME DELAY
(counter)
–
VREF_UV
OTPUV_EN
OTPOV_EN
VREF_OV
SENSE1
UVLO
+
–
OVERVOLTAGE
RESET1
(SENSE1 and SENSE2)
RESET2
(SENSE3 and SENSE4)
SENSE2
SENSE2
SENSE4
CLK
UNDERVOLTAGE
+
VBG
TIME DELAY
(counter)
–
VREF_UV
OTPUV_EN
OTPOV_EN
VREF_OV
SENSE2
UVLO
+
–
OVERVOLTAGE
Figure 8-4. TPS37044 Quadruple-Channel Functional Block Diagram
*For available voltages, window tolerance, time delays, and UV/OV threshold options, see Table 12-2.
8.3 Feature Description
8.3.1 VDD
The TPS3704x is designed to operate from an input voltage supply range between 1.7 V to 6 V. The SENSEx
pins is monitored by the internal comparator. VDD also functions as the supply for the internal bandgap, internal
regulator, state machine, buffers and other control blocks. The reset signal is at a known state when VDD >
VPOR. Undervoltage lockout forces the reset output to be asserted when VDD falls below the minimum VDD
voltage.
VDD capacitor is not required for this device; however, if the input supply is noisy, then it is good design practice
to place a 0.1 μF to 1 µF bypass capacitor between the VDD pin and the GND pin to ensure enough charge is
available for the device to power up correctly. VDD needs to be at or above VDD(MIN) for start-up delay
(tSTRT + tD) to begin and for the device to be fully functional.
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8.3.2 SENSEx Input
The SENSEx input can monitor supply rails from 0 V to 5.55 V, regardless of the device supply voltage used.
The SENSEx pins are used to monitor critical voltage rails or push-button inputs. If the voltage on this pin drops
below VIT-(UV) or goes above VIT+(OV), then RESETx/RESETx is asserted. When the voltage on the SENSEx pin
rises above the positive threshold voltage VIT-(UV) + VHYS or goes below the negative threshold voltage VIT+(OV)
VHYS
-
,
RESETx/RESETx deasserts after the set RESETx/RESETx delay time. The internal comparators have built-in
hysteresis to ensure well-defined RESETx/RESETx assertions and deassertions even when there are small
changes on the voltage rail being monitored.
The TPS3704x combines comparators with a precision reference voltage and a trimmed resistor divider. This
configuration optimizes device accuracy because all resistor tolerances are accounted for in the accuracy and
performance specifications. The TPS3704x device is relatively immune to short transients on the SENSEx pin.
Although not required in most cases, for noisy applications, good analog design practice is to place a 10-nF
to 100-nF bypass capacitor at the SENSEx inputs to reduce sensitivity to transient voltages on the monitored
signals.
8.3.2.1 Immunity to SENSEx Pins Voltage Transients
The TPS3704x is immune to short voltage transient spikes on the input SENSEx pins. Sensitivity to transients
depends on both transient duration and overdrive (amplitude) of the transient.
Overdrive is defined by how much the VSENSEx exceeds the specified threshold, and is important to know
because the smaller the overdrive, the slower the response of the (RESETx/RESETx) outputs. Threshold
overdrive is calculated as a percent of the threshold in question, as shown in Equation 1:
Overdrive % = | (VSENSEx - (VIT-(UV) or VIT+(OV))) / VIT (Nominal) × 100% |
(1)
where:
•
•
•
VSENSEx is the voltage at the SENSEx pin
VIT (Nominal) is the nominal threshold voltage
VIT-(UV) and VIT+(OV) represent the actual undervoltage or overvoltage tripping voltage
8.3.2.1.1 SENSEx Hysteresis
Overvoltage and undervoltage comparators include built-in hysteresis that provides noise immunity and ensures
stable operation. For example, if the voltage on the SENSEx pin falls below VIT-(UV) or above VIT+(OV), then
RESETx/RESETx is asserted. When the voltage on the SENSEx pin is between the positive and negative
threshold voltages, RESETx/RESETx deasserts after the set RESETx/RESETx delay time. Figure 8-5 shows the
relation between VIT-(UV),VIT+(OV) and the hysteresis voltage (VHYS).
VRESETx
Window
(VIT)
VOL
VSENSEx
VIT-(UV)
VIT-(UV) + VHYS
VIT+(OV) - VHYS
VIT+(OV)
Figure 8-5. SENSEx Pin Hysteresis
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8.3.3 RESETx/RESETx
In a typical TPS3704x application, the RESETx/RESETx output is connected to a reset or enable input of
a processor [such as a digital signal processor (DSP), application-specific integrated circuit (ASIC), or other
processor type] or the enable input of a voltage regulator [such as a DC-DC converter or low-dropout regulator
(LDO)].
The TPS3704x has open drain active low outputs that requires an external pull-up resistor to hold these lines
high to the required voltage logic. Connect the external pull-up resistor to the proper voltage rail to enable the
output to be connected to other devices at the correct interface voltage levels. To ensure proper voltage levels,
give some consideration when choosing the external pull-up resistor values. The external pull-up resistor value is
determined by VOL, output capacitive loading, and output leakage current. These values are specified in
Section 7.5. The open drain output can be connected as a wired-OR logic with the other RESETx/RESETx open
drain pins.
VIT+(OV)
OV Limit
VIT+(OV) - VHYS
VSENSEx
VIT-(UV) + VHYS
UV Limit
VIT-(UV)
RESETx
tD
tD
tPD
tPD
Figure 8-6. RESETx output
8.4 Device Functional Modes
Table 8-1. Functional Mode Truth Table
OUTPUT RESETx /
(RESETx) PIN
DESCRIPTION
CONDITION
VDD PIN
VDD > VDD(MIN)
Normal Operation
VIT–(UV) < SENSEx < VIT+(OV)
High / (Low)
High / (Low)
Low / (High)
Low / (High)
Low / (High)
Normal Operation (UV Only) SENSEx > VIT-(UV)
VDD > VDD(MIN)
VDD > VDD(MIN)
VDD > VDD(MIN)
VPOR < VDD < UVLO
Over Voltage detection
Under Voltage detection
UVLO engaged
SENSEx > VIT+(OV)
SENSEx < VIT-(UV)
VIT–(UV) < SENSEx < VIT+(OV)
8.4.1 Normal Operation (VDD > VDD(MIN)
)
When the voltage on VDD is greater than VDD(MIN) for approximately (tSTRT + tD), the RESETx/RESETx output
state will correspond to the SENSEx pin voltage with respect to the threshold limits, when SENSEx voltage is
outside of threshold limits the RESETx/RESETx voltage will be asserted.
8.4.2 Undervoltage Lockout (VPOR < VDD < UVLO)
When the voltage on VDD is less than the device UVLO voltage but greater than the power-on reset voltage
(VPOR), the RESETx/RESETx pin will be asserted, regardless of the voltage on SENSEx pin.
8.4.3 Power-On Reset (VDD < VPOR
)
When the voltage on VDD is lower than the required voltage (VPOR) to internally pull the asserted output to GND,
RESETx/RESETx signal is undefined and is not to be relied upon for proper device function.
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
9.1.1 Voltage Threshold Accuracy
Voltage monitoring requirements vary depending on the voltage supply tolerance of the device being powered.
Due to the high precision of the TPS3704x (±1% maximum), the device allows for a wider supply voltage
margins and threshold headroom for tight tolerance applications.
For example, take a DC/DC regulator providing power to a core voltage rail of an MCU. The MCU has a
tolerance of ±5% of the nominal output voltage of the DC/DC. The user sets an ideal voltage threshold of ±4%
which allows for ±1% of threshold accuracy. Since the TPS3704x threshold accuracy is ±1%, the user has more
supply voltage margin which can allow for a relaxed power supply design. This gives flexibility to the DC/DC to
use a smaller output capacitor or inductor because of a larger voltage window for voltage ripple and transients.
There is also headroom between the minimum system voltage and voltage tolerance of the MCU to ensure that
the voltage supply will never be in the region of potential failure of malfunction without the TPS3704x asserting a
reset signal.
Figure 9-1 illustrates the supply undervoltage margin and accuracy of the TPS3704x for the example explained
above. Using a low accuracy supervisor will eat into the available budget for the power supply ripple and
transient response. This gives less flexibility to the user and a more stringent DC/DC converter design.
DC/DC nominal output
0%
Supply
Regulator output voltage accuracy
Voltage
Margin
Margin for ripple and transients
Voltage
Threshold
Accuracy
+ 1% Allowed threshold tolerance
4%
5%
- 1% Minimum system voltage
Potential Failure or Malfunction
Figure 9-1. TPS3704x Voltage Threshold Accuracy
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9.1.2 Adjustable Voltage Thresholds
The TPS3704x maximum accuracy (1%) allows for adjustable voltage thresholds using external resistors without
adding major inaccuracies to the device. In case that the desired monitored voltage is not available, external
resistor dividers can be used to set the desired voltage thresholds. Figure 9-2 illustrates an example of how to
adjust the voltage threshold with external resistor dividers. The resistors can be calculated depending on the
desired voltage threshold and device part number. TI recommends using an adjustable voltage threshold device
variant because of the bypass mode of internal resistor ladder.
For example, consider a 2.0 V rail being monitored (VMON) using the TPS3704 0.8 V adjustable variant. Using
Equation 2, R1 = 15 kΩ given that R2 = 10 kΩ, VMON = 2 V, and VSENSE1 = 0.8 V. This device is typically meant
to monitor a 0.8 V rail with ±4% voltage thresholds. This means that the device undervoltage threshold (VIT-(UV)
)
and overvoltage threshold (VIT+(OV)) is 0.768 V and 0.832 V respectively. Using Equation 2, VMON = 1.92 V
when VSENSE1 = VIT-(UV). This can be denoted as VMON-, the monitored undervoltage threshold where the device
will assert a reset signal. Using Equation 2 again, the monitored overvoltage threshold (VMON+) = 2.08 V when
VSENSE1 = VIT+(OV). If a wider tolerance or UV only threshold is desired, use a device variant shown on
Table 12-2 to determine what device part number matches your application.
VSENSE1 = VMON × (R2 / (R1 + R2))
(2)
There are inaccuracies that must be taken into consideration while adjusting voltage thresholds. Aside from the
tolerance of the resistor divider, there is an internal resistance of the SENSE1 pin that may affect the accuracy
of the resistor divider. Although expected to be very high impedance, users are recommended to calculate the
values for design specifications. The internal sense resistance RSENSE1 can be calculated by the sense voltage
VSENSE1 divided by the sense current ISENSE1 as shown in Equation 4. VSENSE1 can be calculated using
Equation 2 depending on the resistor divider and monitored voltage. ISENSE1 can be calculated using Equation 3.
ISENSE1 = [(VMON – VSENSE1) / R1] – (VSENSE1 / R2)
RSENSE1 = VSENSE1 / ISENSE1
(3)
(4)
VDD
VMON
10 k
VDD
R1
VDD
RESET1
NC
VSENSE1
SENSE1
NC
TPS37041
NC
NC
R2
GND
Figure 9-2. Adjustable Voltage Threshold with External Resistor Dividers
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9.2 Typical Application
9.2.1 Design 1: Multi-Rail Window Monitoring for Microcontroller Power Rails
A typical application for the TPS37042 is shown in Figure 9-3. The TPS37042 is used to monitor two PMIC
voltage rails that powers the core and I/O voltage of the microcontroller that requires accurate reset delay and
voltage supervision. It utilizes the TPS37042 to monitor the core voltage rail of a MCU similar to the circuit below.
VDD
VOUT1
VCORE
VI/O
Microcontroller
VIN
VOUT2
VDD
PMIC
10 kΩ
RESET
VDD
TPS37042
VDD
RESET1
RESET2
NC
SENSE1
SENSE2
GND
NC
Figure 9-3. TPS37042 Dual-Channel Monitoring Two Microcontroller Power Rails
9.2.1.1 Design Requirements
Table 9-1. Design Requirements
PARAMETER
DESIGN REQUIREMENT
DESIGN RESULT
3.3-VI/O nominal, with alerts if outside of ±8% of 3.3 V
(including device accuracy), 10 ms reset delay
Worst case VIT+(OV) = 3.533 V (7.06%)
Worst case VIT–(UV) = 3.071 V (-6.94%)
Monitored rails
1.2-VCORE nominal, with alerts if outside of ±5% of 1.2 V Worst case VIT+(OV) = 1.2484 V (4.03%)
(including device accuracy), 10 ms reset delay
Worst case VIT–(UV) = 1.1524 V (-3.97%)
Output logic voltage
5-V CMOS
5-V CMOS
Maximum system supervision
current consumption
25 µA
5.5 µA (15 µA max)
9.2.1.2 Detailed Design Procedure
Determine which version of the TPS3704x best suits the monitored rail (VMON) and window tolerances found on
Table 12-2. The TPS3704x allows overvoltage and undervoltage monitoring for precise voltage supervision of
common rails between 0.4 V and 5.55 V. This application calls for very tight monitoring of the rail with only ±5%
of variation allowed on the 1.2-VCORE rail. To ensure this requirement is met, the TPS37042 was chosen for its
±3% thresholds. The 3.3-VI/O is more flexible and can operate up to 8% variance. Since the TPS3704x comes in
various tolerance options, the ±6% thresholds can be chosen for this voltage rail. To calculate the worst-case for
VIT+(OV) and VIT-(UV), the accuracy must also be taken into account. The worst-case for VIT+(OV) and VIT-(UV) can
be calculated shown in Equation 5 and Equation 6 respectively:
VIT+(OV-Worst Case) = VMON × (1 + %Threshold ) × (1 + %Accuracy) = 1.2 × (1.03) × (1.01) = 1.2484 V
VIT-(UV-Worst Case) = VMON × (1 - %Threshold) × (1 - %Accuracy) = 1.2 × (0.97) × (0.99) = 1.1524V
(5)
(6)
Hysteresis is also needed to be taken into account when determining the OV and UV thresholds such that the
release point after the fault is higher than the power supply tolerance limits. Refer to Figure 7-1 for more details.
When the outputs switch to a high impedance state, the rise time of the RESETx/RESETx pin depends on the
pull-up resistance and the capacitance on that node. Choose pull-up resistors that satisfy both the downstream
timing requirements and the sink current required to have a VOL low enough for the application; 10 kΩ to 1 MΩ
resistors are a good choice for low-capacitive loads.
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9.2.2 Application Curves
These application curves were taken with the TPS3704Q1EVM. Please see the TPS3704Q1EVM User Guide for
more information.
VDD
VDD
tD = 20.4 ms
RESET1
SENSE1
Reset Delay (tD) = 21.2 ms
RESET1
RESET2
VSENSE1 start up 0 V to 3.3 V, VDD = 3.3 V, VRESET1 = 3.3 V,
VDD start up 0 V to 3.3 V, VSENSE1 = 3.3 V, VSENSE2 = 1.8 V,
TPS37044A7OHDDFR
VSENSE3_4 = 1.15 V, VRESET1_2 = 3.3 V, TPS37044A7OHDDFR
Figure 9-4. TPS37044 SENSE1 Start Up Function
Figure 9-5. TPS37044 VDD Start Up Function
VDD
VDD
VIT+(OV)
3.57 V
VIT-(UV)
VIT+(OV)
1.82 V
VIT-(UV)
1.70 V
SENSE1
RESET1
SENSE2
RESET1
3.02 V
VSENSE2 ramp 0 V to 2 V, OV/UV Threshold = 1.8 V
(+4%, -3.5%), VSENSE1 = 3.3 V, VDD = 3.3 V,
VRESET1 = 3.3 V, TPS37044A7OHDDFR
VSENSE1 ramp 0 V to 3.75 V, OV/UV Threshold = 3.3 V
(±8%), VSENSE2 = 1.8 V, VDD = 3.3 V, VRESET1 = 3.3 V,
TPS37044A7OHDDFR
Figure 9-7. TPS37044 Overvoltage and
Undervoltage Function
Figure 9-6. TPS37044 Overvoltage and
Undervoltage Function
VDD
SENSE3 = SENSE4
VDD
VIT+(OV)
1.22 V
VIT-(UV)
1.05 V
RESET2
SENSE3 = SENSE4
RESET2
VSENSE3_4 ramp 0 V to 1.5 V, OV/UV Threshold = 1.15
V (+7.5%, -5.5%), VDD = 3.3 V, VRESET2 = 3.3 V,
TPS37044A7OHDDFR
VDD ramp 0 V to 5 V, VSENSE3_4 = 1.2 V, VRESET2 = 3.3 V,
TPS37044A7OHDDFR
Figure 9-9. TPS37044 VDD Ramp Up Function
Figure 9-8. TPS37044 Overvoltage and
Undervoltage Function
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SENSE1
SENSE3
SENSE2
RESET1
SENSE4
RESET2
VSENSE3 toggling 0 V to 1.15 V [OV/UV Threshold = 1.15 V
VSENSE1 toggling 0 V to 3.3 V [OV/UV Threshold = 3.3 V
(±8%)], VSENSE2 toggling from 0 V to 1.8 V [OV/UV
Threshold = 1.8 V (+4%, -3.5%)], VDD = 3.3 V,
VRESET1 = 3.3 V, TPS37044A7OHDDFR
(+7.5%, -5.5%)], VSENSE4 toggling from 0 V to 1.15 V
[OV/UV Threshold = 1.15 V (+7.5%, -5.5%)], VDD = 3.3 V,
VRESET1 = 3.3 V, TPS37044A7OHDDFR
Figure 9-11. TPS37044 SENSE 3 and
SENSE 4 Toggling
Figure 9-10. TPS37044 SENSE 1 and
SENSE 2 Toggling
VDD
VDD
1 ms
SENSE1
SENSE1
RESET1
tPD = 1.32
s
RESET1
tD = 21.5 ms
VSENSE1 = 3.3 V, VSENSE1 = 0 V via push-button for 1 ms,
VDD = 3.3 V, VRESET1 = 3.3 V, TPS37044A7OHDDFR
VSENSE1 toggling from 3.3 V to 0 V, VDD = 3.3 V, VRESET1
toggling from 3.3 V to 0 V, TPS37044A7OHDDFR
Figure 9-12. TPS37044 SENSE1 Push-Button
Monitoring Function with Reset Time Delay
Figure 9-13. TPS37044 SENSE1
Propagation Delay Function
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10 Power Supply Recommendations
10.1 Power Supply Guidelines
This device is designed to operate from an input supply with a voltage range between 1.7 V to 6 V. It has a 6.5 V
absolute maximum rating on the VDD pin. It is good analog practice to place a 0.1 µF to 1 µF capacitor between
the VDD pin and the GND pin depending on the input voltage supply noise. If the voltage supply providing power
to VDD is susceptible to any large voltage transient that exceed maximum specifications, additional precautions
must be taken. See SNVA849 for more information.
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11 Layout
11.1 Layout Guidelines
•
Place the external components as close to the device as possible. This configuration prevents parasitic errors
from occurring.
•
Avoid using long traces for the VDD supply node. The VDD capacitor, along with parasitic inductance from
the supply to the capacitor, can form an LC circuit and create ringing with peak voltages above the maximum
VDD voltage.
•
•
Avoid using long traces of voltage to the sense pin. Long traces increase parasitic inductance and cause
inaccurate monitoring and diagnostics.
If SENSEx capacitors (CSENSEx) are used, place the capacitors as close as possible to the SENSEx pins to
further improve the noise immunity on the SENSEx pins. Placing a 10 nF to 100 nF capacitors between the
SENSEx pins and GND can reduce the sensitivity to transient voltages on the monitored signal.
Do not run sensitive analog traces in parallel with digital traces. Avoid crossing digital and analog traces if
possible, and only make perpendicular crossings when absolutely necessary.
•
11.2 Layout Example
CIN
Rpull-up1 Rpull-up2
VDD
RESET1
*CSENSE1
SENSE1
SENSE2
GND
RESET2
SENSE4
*CSENSE4
SENSE3
*CSENSE2
*CSENSE3
GND
Vias used to connect pins for application-specific connections
*CSENSEx capacitors can be added for improve noise immunity
Figure 11-1. Recommended Layout
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12 Device and Documentation Support
12.1 Device Nomenclature
Figure 5-1 in Section 5 and Table 12-1 shows how to decode the function of the device based on its part number
shown in Table 12-2.
Table 12-1. Device Naming Convention
DESCRIPTION
Generic Part number
NOMENCLATURE
VALUE
TPS3704x
TPS3704x
Channel Option
1
2
3
4
One-channel option
Dual-channel option
Triple-channel option
Quad-channel option
Please refer to Table 12-2
Open-Drain, Active-Low
Push-Pull, Active-Low
Push-Pull, Active-High
20 μs reset time delay
1 ms reset time delay
2 ms reset time delay
3 ms reset time delay
5 ms reset time delay
10 ms reset time delay
15 ms reset time delay
20 ms reset time delay
25 ms reset time delay
35 ms reset time delay
40 ms reset time delay
50 ms reset time delay
70 ms reset time delay
100 ms reset time delay
140 ms reset time delay
150 ms reset time delay
200 ms reset time delay
280 ms reset time delay
400 ms reset time delay
560 ms reset time delay
800 ms reset time delay
1120 ms reset time delay
1200 ms reset time delay
SOT-23 8-pin (1.6 mm × 2.9 mm)
Large Reel
Detection Options
Ax, Bx, Cx,...
Variant code (Output Topology)
O
L
H
A
B
C
D
E
F
Reset Time Delay Option
G
H
I
J
K
L
M
N
O
P
R
S
T
U
V
W
X
DDF
R
Package
Reel
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Table 12-2. Device Threshold Table
NUM
OF
CHAN.
ORDERABLE PART
NAME
RESET
TIME
VARIANT
SENSE1
SENSE2
SENSE3
SENSE4
0.8 V (±4%)
TPS37044BJOFDDFR TPS37044
4
10 ms
0.8 V (±4%)
0.8 V (±4%)
0.8 V (±4%)
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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4-Dec-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
PS37044AJOFDDFR
TPS37044BJOFDDFR
ACTIVE SOT-23-THIN
ACTIVE SOT-23-THIN
DDF
DDF
8
8
3000
3000
TBD
TBD
Call TI
Call TI
Call TI
-40 to 125
-40 to 125
Call TI
4BJOF
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
4-Dec-2021
OTHER QUALIFIED VERSIONS OF TPS3704 :
Automotive : TPS3704-Q1
•
NOTE: Qualified Version Definitions:
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•
Addendum-Page 2
PACKAGE OUTLINE
DDF0008A
SOT-23 - 1.1 mm max height
S
C
A
L
E
4
.
0
0
0
PLASTIC SMALL OUTLINE
C
2.95
2.65
SEATING PLANE
TYP
PIN 1 ID
AREA
0.1 C
A
6X 0.65
8
1
2.95
2.85
NOTE 3
2X
1.95
4
5
0.4
0.2
8X
0.1
C A
B
1.65
1.55
B
1.1 MAX
0.20
0.08
TYP
SEE DETAIL A
0.25
GAGE PLANE
0.1
0.0
0 - 8
0.6
0.3
DETAIL A
TYPICAL
4222047/B 11/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
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EXAMPLE BOARD LAYOUT
DDF0008A
SOT-23 - 1.1 mm max height
PLASTIC SMALL OUTLINE
8X (1.05)
SYMM
1
8
8X (0.45)
SYMM
6X (0.65)
5
4
(R0.05)
TYP
(2.6)
LAND PATTERN EXAMPLE
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4222047/B 11/2015
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
DDF0008A
SOT-23 - 1.1 mm max height
PLASTIC SMALL OUTLINE
8X (1.05)
SYMM
(R0.05) TYP
8
1
8X (0.45)
SYMM
6X (0.65)
5
4
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4222047/B 11/2015
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
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