TPS3779-Q1 [TI]
汽车类、推挽式、双通道、低功耗、高精度电压检测器;
| 型号： | TPS3779-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 汽车类、推挽式、双通道、低功耗、高精度电压检测器 |
| 文件： | 总25页 (文件大小：1385K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TPS3779-Q1, TPS3780-Q1
ZHCSF51A –JUNE 2016–REVISED SEPTEMBER 2016
TPS37xx-Q1
双通道、低功耗、高精度电压检测器
1 特性
3 说明
1
•
•
适用于汽车电子 应用
具有符合 AEC-Q100 的下列结果：
TPS3779-Q1 和 TPS3780-Q1 属于高精度双通道电压
检测器系列，同时拥有低功耗和小解决方案尺寸两大优
势。SENSE1 和 SENSE2 输入包括滞后特性，可抑制
短小毛刺脉冲，从而确保输出操作稳定而无错误触发。
该器件提供了两种不同的出厂设置滞后选项：5% 或
10%。
–
–
–
器件温度 1 级：-40°C 至 125°C 的环境运行温
度范围
器件人体放电模式 (HBM) 静电放电 (ESD) 分类
等级 H2
器件组件充电模式 (CDM) ESD 分类等级 C4B
TPS3779-Q1 和 TPS3780-Q1 配有可调节的 SENSEx
输入。这些输入可通过外部电阻分压器进行配置。当
SENSE1 和 SENSE2 输入上的电压低于下降阈值
时，OUT1 和 OUT2 被分别驱动为低电平。当
SENSE1 和 SENSE2 上升到高于上升阈值时，OUT1
和 OUT2 分别变为高电平。
•
•
•
•
•
•
•
采用小型封装的双通道检测器
高精度阈值和滞后：1.0%
低静态电流：2µA（典型值）
可调节检测电压：最低至 1.2V
5% 和 10% 滞后选项
温度范围：-40°C 至 +125°C
该器件的超低静态电流为 2µA（典型值），并且提供
了一套精确且节省空间的电压检测解决方案，非常适合
低功耗系统监视和便携式 输出电压电平信号。
推挽 (TPS3779-Q1) 和开漏 (TPS3780-Q1) 输出选
项
•
采用 SOT-23 封装
TPS3779-Q1 和 TPS3780-Q1 的工作电压范围为 1.5V
至 5.5V，工作温度范围为 –40°C 至 +125°C。
2 应用
•
•
•
•
数字信号处理器 (DSP)、微控制器和微处理器
器件信息(1)
高级驾驶员辅助系统 (ADAS)
信息娱乐和仪表板
器件型号
封装
SOT-23 (6)
封装尺寸（标称值）
TPS37xx-Q1
2.90mm x 1.60mm
电源排序 应用
(1) 如需了解所有可用封装，请见数据表末尾的可订购产品附录。
感测阈值 (VIT+) 偏差与温度间的关系
典型电路原理图
VDD = 1.5 V to 5.5 V
0.4
0.1 ꢀF
Sense 1 VDD = 1.5 V
0.32
0.24
0.16
0.08
0
Sense 1 VDD = 5.5 V
Sense 2 VDD = 1.5 V
Sense 2 VDD = 5.5 V
TPS3780 Only
VMON1
VPULLUP
VDD
R1
RPU1
To a reset or enable
input of the system.
VMON2
SENSE1
OUT1
OUT2
R3
R2
TPS37xx-Q1
RPU1
To a reset or enable
input of the system.
SENSE2
GND
-0.08
-0.16
-0.24
-0.32
-0.4
R4
Copyright © 2016, Texas Instruments Incorporated
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (èC)
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SBVS273
TPS3779-Q1, TPS3780-Q1
ZHCSF51A –JUNE 2016–REVISED SEPTEMBER 2016
www.ti.com.cn
目录
8.4 Device Functional Modes........................................ 11
Application and Implementation ........................ 12
9.1 Application Information............................................ 12
9.2 Typical Applications ................................................ 13
1
2
3
4
5
6
7
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Device Comparison Table..................................... 3
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
7.1 Absolute Maximum Ratings ...................................... 4
7.2 ESD Ratings.............................................................. 4
7.3 Recommended Operating Conditions....................... 4
7.4 Thermal Information.................................................. 4
7.5 Electrical Characteristics........................................... 5
7.6 Timing Requirements................................................ 6
7.7 Typical Characteristics.............................................. 7
Detailed Description ............................................ 10
8.1 Overview ................................................................. 10
8.2 Functional Block Diagrams ..................................... 10
8.3 Feature Description................................................. 11
9
10 Power-Supply Recommendations ..................... 15
11 Layout................................................................... 15
11.1 Layout Guidelines ................................................. 15
11.2 Layout Example .................................................... 15
12 器件和文档支持 ..................................................... 16
12.1 器件支持................................................................ 16
12.2 文档支持................................................................ 16
12.3 接收文档更新通知 ................................................. 16
12.4 相关链接................................................................ 16
12.5 社区资源................................................................ 17
12.6 商标....................................................................... 17
12.7 静电放电警告......................................................... 17
12.8 Glossary................................................................ 17
13 机械、封装和可订购信息....................................... 17
8
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Original (June 2016) to Revision A
Page
•
•
Added TPS3780A-Q1 row to Device Comparison Table ...................................................................................................... 3
Added TPS37xxA-Q1 row to VIT– parameter in Electrical Characteristics table..................................................................... 5
2
Copyright © 2016, Texas Instruments Incorporated
TPS3779-Q1, TPS3780-Q1
www.ti.com.cn
ZHCSF51A –JUNE 2016–REVISED SEPTEMBER 2016
5 Device Comparison Table
PRODUCT
HYSTERESIS (%)
OUTPUT
Push-pull
TPS3779B-Q1
TPS3779C-Q1
TPS3780A-Q1
TPS3780B-Q1
TPS3780C-Q1
5
10
0.5
5
Push-pull
Open-drain
Open-drain
Open-drain
10
6 Pin Configuration and Functions
DBV Package
6-Pin SOT-23
Top View
VDD
OUT1
OUT2
1
2
3
6
5
4
SENSE1
GND
SENSE2
Not to scale
Pin Functions
NAME
GND
NO.
I/O
DESCRIPTION
5
—
Ground
OUT1 is the output for SENSE1. OUT1 is asserted (driven low) when the voltage at SENSE1 falls below VIT–
OUT1 is deasserted (goes high) after SENSE1 rises higher than VIT+
.
.
OUT1
OUT2
2
3
O
O
OUT1 is a push-pull output for the TPS3779-Q1 and an open-drain output for the TPS3780-Q1.
The open-drain device (TPS3780-Q1) can be pulled up to 5.5 V independent of VDD; a pullup resistor is
required for this device.
OUT2 is the output for SENSE2. OUT2 is asserted (driven low) when the voltage at SENSE2 falls below VIT–
.
OUT2 is deasserted (goes high) after SENSE2 rises higher than VIT+
.
OUT2 is a push-pull output for the TPS3779-Q1 and an open-drain output for the TPS3780-Q1.
The open-drain device (TPS3780-Q1) can be pulled up to 5.5 V independent of VDD; a pullup resistor is
required for this device.
This pin is connected to the voltage to be monitored with the use of an external resistor divider.
When the voltage at this pin drops below the threshold voltage (VIT–), OUT1 is asserted.
SENSE1
SENSE2
VDD
6
4
1
I
I
I
This pin is connected to the voltage to be monitored with the use of an external resistor divider.
When the voltage at this pin drops below the threshold voltage (VIT–), OUT2 is asserted.
Supply voltage input. Connect a 1.5-V to 5.5-V supply to VDD in order to power the device. Good analog
design practice is to place a 0.1-µF ceramic capacitor close to this pin (required for VDD < 1.5 V).
Copyright © 2016, Texas Instruments Incorporated
3
TPS3779-Q1, TPS3780-Q1
ZHCSF51A –JUNE 2016–REVISED SEPTEMBER 2016
www.ti.com.cn
7 Specifications
7.1 Absolute Maximum Ratings
over operating junction temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
–0.3
–0.3
MAX
UNIT
VDD
7
OUT1, OUT2 (TPS3779-Q1 only)
VDD + 0.3
Voltage
V
OUT1, OUT2 (TPS3780-Q1 only)
7
SENSE1, SENSE2
7
Current
OUT1, OUT2
±20
125
150
mA
°C
(2)
Operating junction, TJ
Storage, Tstg
–40
–65
Temperature
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) For low-power devices, the junction temperature rise above the ambient temperature is negligible; therefore, the junction temperature is
considered equal to the ambient temperature (TJ = TA).
7.2 ESD Ratings
VALUE
±2000
±500
UNIT
Human-body model (HBM), per AEC Q100-002(1)
Charged-device model (CDM), per AEC Q100-011
V(ESD)
Electrostatic discharge
V
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
7.3 Recommended Operating Conditions
over operating junction temperature range (unless otherwise noted)
MIN
1.5
0
NOM
MAX
5.5
UNIT
Power-supply voltage
Sense voltage
V
V
SENSE1, SENSE2
OUT1, OUT2
5.5
Output voltage (TPS3779-Q1 only)
Output voltage (TPS3780-Q1 only)
Pullup resistor (TPS3780-Q1 only)
Current
0
VDD + 0.3
5.5
V
OUT1, OUT2
0
V
RPU
1.5
–5
10,000
5
kΩ
mA
µF
°C
OUT1, OUT2
CIN
TJ
Input capacitor
0.1
25
Junction temperature
–40
125
7.4 Thermal Information
TPS3779-Q1, TPS3780-Q1
THERMAL METRIC(1)
DBV (SOT-23)
6 PINS
193.9
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
134.5
39.0
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
30.4
ψJB
38.5
RθJC(bot)
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
4
Copyright © 2016, Texas Instruments Incorporated
TPS3779-Q1, TPS3780-Q1
www.ti.com.cn
ZHCSF51A –JUNE 2016–REVISED SEPTEMBER 2016
7.5 Electrical Characteristics
all specifications are over the operating temperature range of –40°C < TJ < +125°C and 1.5 V ≤ VDD ≤ 5.5 V (unless
otherwise noted); typical values are at TJ = 25°C and VDD = 3.3 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
5.5
UNIT
V
VDD
Input supply range
1.5
V(POR)
Power-on-reset voltage(1)
VOL (max) = 0.2 V, IOL = 15 µA
VDD = 3.3 V, no load
0.8
V
2.09
2.29
5.80
6.50
IDD
Supply current (into VDD pin)
µA
V
VDD = 5.5 V, no load
1.194
Positive-going input threshold
voltage
VIT+
V(SENSEx) rising
–1%
1%
TPS37xxA-Q1
(0.5% hysteresis)
1.188
1.134
1.074
TPS37xxB-Q1
V(SENSEx) falling
V
Negative-going input threshold
voltage
(5% hysteresis)
VIT–
TPS37xxC-Q1
(10% hysteresis)
V(SENSEx) falling
–1%
–15
1%
15
I(SENSEx) Input current
V(SENSEx) = 0 V or VDD
nA
V
VDD ≥ 1.5 V, ISINK = 0.4 mA
VDD ≥ 2.7 V, ISINK = 2 mA
VDD ≥ 4.5 V, ISINK = 3.2 mA
VDD ≥ 1.5 V, ISOURCE = 0.4 mA
VDD ≥ 2.7 V, ISOURCE = 1 mA
VDD ≥ 4.5 V, ISOURCE = 2.5 mA
0.25
0.25
0.30
VOL
Low-level output voltage
0.8 VDD
0.8 VDD
0.8 VDD
High-level output voltage
(TPS3779-Q1 only)
VOH
V
Open-drain output leakage
current (TPS3780-Q1 only)
Ilkg(OD)
High impedance, V(SENSEx) = V(OUTx) = 5.5 V
–250
250
nA
(1) Outputs are undetermined below V(POR)
.
Copyright © 2016, Texas Instruments Incorporated
5
TPS3779-Q1, TPS3780-Q1
ZHCSF51A –JUNE 2016–REVISED SEPTEMBER 2016
www.ti.com.cn
7.6 Timing Requirements
typical values are at TJ = 25°C and VDD = 3.3 V; SENSEx transitions between 0 V and 1.3 V
MIN
NOM
5.5
MAX
UNIT
µs
tPD(r)
tPD(f)
tSD
SENSEx (rising) to OUTx propagation delay
SENSEx (falling) to OUTx propagation delay
Startup delay(1)
10
µs
570
µs
(1) During power-on or when a VDD transient is below VDD(min), the outputs reflect the input conditions 570 µs after VDD transitions
through VDD(min).
VDD(min)
VDD
V(POR)
VIT+
SENSEx
VHYS
VITœ
Undefined
570 µs
Undefined
570 µs
OUTx
tSD
tPD(r)
tPD(f)
图 1. Timing Diagram
6
版权 © 2016, Texas Instruments Incorporated
TPS3779-Q1, TPS3780-Q1
www.ti.com.cn
ZHCSF51A –JUNE 2016–REVISED SEPTEMBER 2016
7.7 Typical Characteristics
at TJ = 25°C with a 0.1-µF capacitor close to VDD (unless otherwise noted)
0.4
0.32
0.24
0.16
0.08
0
5
4.5
4
Sense 1 VDD = 1.5 V
Sense 1 VDD = 5.5 V
Sense 2 VDD = 1.5 V
Sense 2 VDD = 5.5 V
TJ = -40°C
TJ = 0°C
TJ = 25°C
TJ = 85°C
TJ = 105°C
TJ = 125°C
3.5
3
2.5
2
-0.08
-0.16
-0.24
-0.32
-0.4
1.5
1
0.5
0
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
-40 -25 -10
5
20 35 50 65 80 95 110 125
Supply Voltage (V)
Temperature (èC)
SENSE1 = SENSE2 = 1.5 V
图 2. Supply Current vs Supply Voltage
图 3. Sense Threshold (VIT+) Deviation vs Temperature
0.4
4500
4000
3500
3000
2500
2000
1500
1000
500
Sense 1 VDD = 1.5 V
Sense 1 VDD = 5.5 V
Sense 2 VDD = 1.5 V
Sense 2 VDD = 5.5 V
0.32
0.24
0.16
0.08
0
-0.08
-0.16
-0.24
-0.32
-0.4
0
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (èC)
VIT+ Accuracy (%)
VDD = 5.5 V
图 4. Sense Threshold (VIT–) Deviation vs Temperature
图 5. Sense Threshold (VIT+
)
1.3
1.2
1.1
1
5500
5000
4500
4000
3500
3000
2500
2000
1500
1000
500
TJ = -40°C
TJ = 0°C
TJ = 25°C
TJ = 85°C
TJ = 105°C
TJ = 125°C
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0
0
1
2
3
4
5
Output Sink Current (mA)
VIT- Accuracy (%)
VDD = 5.5 V
图 7. Output Voltage Low vs Output Current
图 6. Sense Threshold (VIT–
)
(VDD = 1.5 V)
版权 © 2016, Texas Instruments Incorporated
7
TPS3779-Q1, TPS3780-Q1
ZHCSF51A –JUNE 2016–REVISED SEPTEMBER 2016
www.ti.com.cn
Typical Characteristics (接下页)
at TJ = 25°C with a 0.1-µF capacitor close to VDD (unless otherwise noted)
0.5
0.4
0.3
0.2
0.1
0
0.5
0.4
0.3
0.2
0.1
0
TJ = -40°C
TJ = 0°C
TJ = 25°C
TJ = 85°C
TJ = 105°C
TJ = 125°C
TJ = -40°C
TJ = 0°C
TJ = 25°C
TJ = 85°C
TJ = 105°C
TJ = 125°C
0
1
2
3
4
5
0
1
2
3
4
5
Output Sink Current (mA)
Output Sink Current (mA)
图 8. Output Voltage Low vs Output Current
图 9. Output Voltage Low vs Output Current
(VDD = 3.3 V)
(VDD = 5.5 V)
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1
3.75
3.5
3.25
3
TJ = -40°C
TJ = 0°C
TJ = 25°C
TJ = 85°C
TJ = 105°C
TJ = 125°C
TJ = -40°C
TJ = 0°C
TJ = 25°C
TJ = 85°C
TJ = 105°C
TJ = 125°C
2.75
2.5
2.25
2
0.9
0.8
0.7
1.75
1.5
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
Output Source Current (mA)
Output Source Current (mA)
图 10. Output Voltage High vs Output Current
图 11. Output Voltage High vs Output Current
(VDD = 1.5 V)
(VDD = 3.3 V)
5.75
6.1
5.9
5.7
5.5
5.3
5.1
4.9
4.7
TJ = -40°C
TJ = 0°C
TJ = 25°C
TJ = 85°C
TJ = 105°C
TJ = 125°C
5.5
5.25
5
4.75
4.5
Sense 1 VDD = 1.5 V
Sense 1 VDD = 5.5 V
Sense 2 VDD = 1.5 V
Sense 2 VDD = 5.5 V
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
-40 -25 -10
5
20 35 50 65 80 95 110 125
Output Source Current (mA)
Temperature (èC)
SENSE1 = SENSE2 = 0 V to 1.3 V
图 12. Output Voltage High vs Output Current
图 13. Propagation Delay from
(VDD = 5.5 V)
SENSEx High to Output High
8
版权 © 2016, Texas Instruments Incorporated
TPS3779-Q1, TPS3780-Q1
www.ti.com.cn
ZHCSF51A –JUNE 2016–REVISED SEPTEMBER 2016
Typical Characteristics (接下页)
at TJ = 25°C with a 0.1-µF capacitor close to VDD (unless otherwise noted)
14
12
10
8
1150
1050
950
850
750
650
550
450
350
250
VDD = 1.5 V
VDD = 5.5 V
6
Sense 1 VDD = 1.5 V
Sense 1 VDD = 5.5 V
Sense 2 VDD = 1.5 V
Sense 2 VDD = 5.5 V
4
-40 -25 -10
5
20 35 50 65 80 95 110 125
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (èC)
Temperature (èC)
SENSE1 = SENSE2 = 1.3 V to 0 V
图 14. Propagation Delay from
图 15. Startup Delay
SENSEx Low to Output Low
55
50
45
40
35
30
25
20
15
10
5
55
50
45
40
35
30
25
20
15
10
5
TJ = -40°C
TJ = 0°C
TJ = +25°C
TJ = +85°C
TJ = +105°C
TJ = +125°C
TJ = -40°C
TJ = 0°C
TJ = +25°C
TJ = +85°C
TJ = +105°C
TJ = +125°C
0
0
0
3
6
9
12
15
18
21
24
27
30
0
3
6
9
12
15
18
21
24
27
30
Overdrive (%)
Overdrive (%)
High-to-low transition occurs above the curve
High-to-low transition occurs above the curve
图 16. Minimum Transient Duration vs Overdrive
图 17. Minimum Transient Duration vs Overdrive
(VDD = 1.5 V)
(VDD = 5.5 V)
35
35
TJ = -40°C
TJ = 0°C
TJ = +25°C
TJ = +85°C
TJ = +105°C
TJ = +125°C
TJ = -40°C
TJ = 0°C
TJ = +25°C
TJ = +85°C
TJ = +105°C
TJ = +125°C
32.5
30
32.5
30
27.5
25
27.5
25
22.5
20
22.5
20
17.5
15
17.5
15
12.5
10
12.5
10
7.5
5
7.5
5
2.5
0
2.5
0
0
3
6
9
12
15
18
21
24
27
30
0
3
6
9
12
15
18
21
24
27
30
Overdrive (%)
Overdrive (%)
Low-to-high transition occurs above the curve
Low-to-high transition occurs above the curve
图 18. Minimum Transient Duration vs Overdrive
图 19. Minimum Transient Duration vs Overdrive
(VDD = 1.5 V)
(VDD = 5.5 V)
版权 © 2016, Texas Instruments Incorporated
9
TPS3779-Q1, TPS3780-Q1
ZHCSF51A –JUNE 2016–REVISED SEPTEMBER 2016
www.ti.com.cn
8 Detailed Description
8.1 Overview
The TPS3779-Q1 and TPS3780-Q1 are small, low quiescent current (IDD), dual-channel voltage detectors. These
devices have high-accuracy rising and falling input thresholds, and assert the output as shown in 表 1. The
output (OUTx pin) goes low when the SENSEx pin is less than VIT– and goes high when the pin is greater than
VIT+. The TPS3779-Q1 and TPS3780-Q1 offer two hysteresis options (5% and 10%) for use in a wide variety of
applications. These devices have two independent voltage-detection channels that can be used in systems
where multiple voltage rails are required to be monitored, or where one channel can be used as an early warning
signal and the other channel can be used as the system reset signal.
表 1. TPS3779-Q1, TPS3780-Q1 Truth Table
CONDITIONS
SENSE1 < VIT–
SENSE2 < VIT–
SENSE1 > VIT+
SENSE2 > VIT+
OUTPUT
OUT1 = low
OUT2 = low
OUT1 = high
OUT2 = high
8.2 Functional Block Diagrams
VDD
VDD
SENSE1
SENSE1
OUT1
OUT1
SENSE2
SENSE2
OUT2
OUT2
VIT+
VIT+
TPS3779-Q1
TPS3780-Q1
GND
GND
Copyright © 2016, Texas Instruments Incorporated
Copyright © 2016, Texas Instruments Incorporated
图 20. TPS3779-Q1 Block Diagram
图 21. TPS3780-Q1 Block Diagram
10
版权 © 2016, Texas Instruments Incorporated
TPS3779-Q1, TPS3780-Q1
www.ti.com.cn
ZHCSF51A –JUNE 2016–REVISED SEPTEMBER 2016
8.3 Feature Description
8.3.1 Inputs (SENSE1, SENSE2)
The TPS3779-Q1 and TPS3780-Q1 each have two comparators for voltage detection. Each comparator has one
external input; the other input is connected to the internal reference. The comparator rising threshold is designed
and trimmed to be equal to VIT+, and the falling threshold is trimmed to be equal to VIT–. The built-in falling
hysteresis options make the devices immune to supply rail noise and ensure stable operation.
The comparator inputs can swing from ground to 5.5 V, regardless of the device supply voltage used. Although
not required in most cases, for extremely noisy applications, good analog design practice is to place a 1-nF to
10-nF bypass capacitor at the comparator input in order to reduce sensitivity to transients and layout parasitic.
For each SENSEx input, the corresponding output (OUTx) is driven to logic low when the input voltage drops
below VIT–. When the voltage exceeds VIT+, the output (OUTx) is driven high; see 图 1.
8.3.2 Outputs (OUT1, OUT2)
In a typical device application, the outputs are connected to a reset or enable input of another device, such as a
digital signal processor (DSP), central processing unit (CPU), field-programmable gate array (FPGA), or
application-specific integrated circuit (ASIC); or the outputs are connected to the enable input of a voltage
regulator, such as a dc-dc or low-dropout (LDO) regulator.
The TPS3779-Q1 provides two push-pull outputs. The logic high level of the outputs is determined by the VDD
pin voltage. Pullup resistors are not required with this configuration, thus saving board space. However, all
interface logic levels must be examined. All OUTx connections must be compatible with the VDD pin logic level.
The TPS3780-Q1 provides two open-drain outputs (OUT1 and OUT2); pullup resistors must be used to hold
these lines high when the output goes to a high-impedance condition (not asserted). By connecting pullup
resistors to the proper voltage rails, the outputs can be connected to other devices at correct interface voltage
levels. The outputs can be pulled up to 5.5 V, independent of the device supply voltage. To ensure proper
voltage levels, make sure to choose the correct pullup resistor values. The pullup resistor value is determined by
VOL, the sink current capability, and the output leakage current (Ilkg(OD)). These values are specified in the
Electrical Characteristics table. By using wired-AND logic, OUT1 and OUT2 can be combined into one logic
signal. The Inputs (SENSE1, SENSE2) section describes how the outputs are asserted or deasserted. See 图 1
for a description of the relationship between threshold voltages and the respective output.
8.4 Device Functional Modes
8.4.1 Normal Operation (VDD ≥ VDD(min))
When the voltage on VDD is greater than VDD(min) for tSD, the output signals react to the present state of the
corresponding SENSEx pins.
8.4.2 Power-On-Reset (VDD < V(POR)
)
When the voltage on VDD is lower than the required voltage to internally pull the logic low output to GND
(V(POR)), both outputs are undefined and are not to be relied upon for proper system function.
版权 © 2016, Texas Instruments Incorporated
11
TPS3779-Q1, TPS3780-Q1
ZHCSF51A –JUNE 2016–REVISED SEPTEMBER 2016
www.ti.com.cn
9 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TPS3779-Q1 and TPS3780-Q1 are used as precision, dual-voltage detectors. The monitored voltage, VDD
voltage, and output pullup voltage (TPS3780-Q1 only) can be independent voltages or connected in any
configuration.
9.1.1 Threshold Overdrive
Threshold overdrive is how much VSENSE1 or VSENSE2 exceeds the specified threshold, and is important to know
because a smaller overdrive results in a slower OUTx response. Threshold overdrive is calculated as a percent
of the threshold in question, as shown in 公式 1:
Overdrive = | (VSENSE1,2 / VIT – 1) × 100% |
where
•
•
VIT is either VIT– or VIT+, depending on whether calculating the overdrive for the negative-going threshold or the
positive-going threshold, respectively
VSENSE1,2 is the voltage at the SENSE1 or SENSE2 input
(1)
图 16 illustrates the minimum detectable pulse on the SENSEx inputs versus overdrive, and is used to visualize
the relationship that overdrive has on tPD(f) for negative-going events.
9.1.2 Sense Resistor Divider
The resistor divider values and target threshold voltage can be calculated by using 公式 2 and 公式 3 to
determine VMON(UV) and VMON(PG), respectively.
R1
R2
≈
’
VMON(UV) = 1 +
× V
IT-
∆
÷
◊
«
(2)
(3)
R1
R2
≈
’
VMON(PG) = 1 +
× V
IT+
∆
÷
◊
«
where
•
•
•
R1 and R2 are the resistor values for the resistor divider on the SENSEx pins
VMON(UV) is the target voltage at which an undervoltage condition is detected
VMON(PG) is the target voltage at which the output goes high when VMONx rises
Choose RTOTAL (equal to R1 + R2) so that the current through the divider is approximately 100 times higher than
the input current at the SENSEx pins. The resistors can have high values to minimize current consumption as a
result of low input bias current without adding significant error to the resistive divider. For details on sizing input
resistors, see the Optimizing Resistor Dividers at a Comparator Input application report (SLVA450), available for
download from www.ti.com.
12
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TPS3779-Q1, TPS3780-Q1
www.ti.com.cn
ZHCSF51A –JUNE 2016–REVISED SEPTEMBER 2016
9.2 Typical Applications
9.2.1 Monitoring Two Separate Rails
VDD = 5 V
0.1 ꢀF
VMON1
VPULLUP
VDD
SENSE1
R1
R2
RPU1
To a reset or enable
input of the system.
VMON2
R3
OUT1
TPS3780C-Q1
RPU1
To a reset or enable
input of the system.
SENSE2
GND
OUT2
R4
Copyright © 2016, Texas Instruments Incorporated
图 22. Monitoring Two Separate Rails Schematic
9.2.1.1 Design Requirements
表 2. Design Parameters
PARAMETER
VDD
DESIGN REQUIREMENT
DESIGN RESULT
5 V
5 V
Hysteresis
10%
10%
3.3 V nominal, VMON(PG) = 2.9 V,
VMON(UV) = 2.6 V
Monitored voltage 1
VMON(PG) = 2.908 V, VMON(UV) = 2.618 V
3 V nominal, VMON(PG) = 2.6 V,
VMON(UV) = 2.4 V
Monitored voltage 2
Output logic voltage
VMON(PG) = 2.606 V, VMON(UV) = 2.371 V
3.3-V CMOS
3.3-V CMOS
9.2.1.2 Detailed Design Procedure
1. Select the TPS3780C-Q1. The C version is selected to satisfy the hysteresis requirement. The TPS3780-Q1
is selected for the output logic requirement. An open-drain output allows for the output to be pulled up to a
voltage other than VDD.
2. The resistor divider values are calculated by using 公式 2 and 公式 3. For SENSE1, R1 = 1.13 MΩ and R2 =
787 kΩ. For SENSE2, R3 (R1) = 681 kΩ and R4 (R2) = 576 kΩ.
9.2.1.3 Application Curve
VMON1 (500 mV/div)
VMON2(500 mV/div)
OUT1 (1 V/div)
OUT2 (1 V/div)
Time(5 ms/div)
图 23. Monitoring Two Separate Rails Curve
版权 © 2016, Texas Instruments Incorporated
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TPS3779-Q1, TPS3780-Q1
ZHCSF51A –JUNE 2016–REVISED SEPTEMBER 2016
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9.2.2 Early Warning Detection
VMON
0.1 ꢀF
VDD
SENSE1
R1
R2
R3
To a reset or enable
input of the system.
OUT1
TPS3779C-Q1
To a reset or enable
input of the system.
SENSE2
GND
OUT2
Copyright © 2016, Texas Instruments Incorporated
图 24. Early Warning Detection Schematic
9.2.2.1 Design Requirements
表 3. Design Parameters
PARAMETER
VDD
DESIGN REQUIREMENT
DESIGN RESULT
VMON
10%
VMON
10%
Hysteresis
Monitored voltage 1
Monitored voltage 2
VMON(PG) = 3.3 V, VMON(UV) = 3 V
VMON(PG) = 3.9 V, VMON(UV) = 3.5 V
VMON(PG) = 3.330 V, VMON(UV) = 2.997 V
VMON(PG) = 3.921 V, VMON(UV) = 3.529 V
9.2.2.2 Detailed Design Procedure
1. Select the TPS3779C-Q1. The C version is selected to satisfy the hysteresis requirement. The TPS3779-Q1
is selected to save on component count and board space.
2. Use 公式 4 to calculate the total resistance for the resistor divider. Determine the minimum total resistance of
the resistor network necessary to achieve the current consumption specification. For this example, the
current flow through the resistor network is chosen to be 1.41 µA. Use the key transition point for VMON2. For
this example, the low-to-high transition, VMON(PG), is considered more important.
VMON(PG_ 2)
3.9 V
RTOTAL
=
=
= 2.78 MW
I
1.41 ꢀA
where
•
•
VMON(PG_2) is the target voltage at which OUT2 goes high when VMON rises
I is the current flowing through the resistor network
(4)
3. After RTOTAL is determined, R3 can be calculated using 公式 5. Select the nearest 1% resistor value for R3.
In this case, 845 kΩ is the closest value.
V
1.194 V
IT+
R3 =
=
= 846 kW
I
1.41 ꢀA
(5)
4. Use 公式 6 to calculate R2. Select the nearest 1% resistor value for R2. In this case, 150 kΩ is the closest
value. Use the key transition point for VMON1. For this example, the high-to-low transition, VMON(UV), is
considered more important.
RTOTAL
2.78 MW
R2 =
ñ V - R3 =
ñ 1.074 V - 845 kW = 149 kW
IT-
VMON(UV_1)
3 V
where
•
VMON(UV_1) is the target voltage at which OUT1 goes low when VMON falls
(6)
14
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TPS3779-Q1, TPS3780-Q1
www.ti.com.cn
ZHCSF51A –JUNE 2016–REVISED SEPTEMBER 2016
5. Use 公式 7 to calculate R1. Select the nearest 1% resistor value for R1. In this case, 1.78 MΩ is a 1%
resistor.
R1 = RTOTAL - R2 - R3 = 2.78 MW -150 kW - 845 kW = 1.78 MW
(7)
9.2.2.3 Application Curve
VDD = VMON (1 V/div)
OUT1 (1 V/div)
OUT2 (1 V/div)
Time(5 ms/div)
图 25. Early Warning Detection Curve
10 Power-Supply Recommendations
The TPS3779-Q1 and TPS3780-Q1 are designed to operate from an input voltage supply range between 1.5 V
and 5.5 V. An input supply capacitor is not required for this device; however, good analog practice is to place a
0.1-µF or greater capacitor between the VDD pin and the GND pin. This device has a 7-V absolute maximum
rating on the VDD pin. If the voltage supply providing power to VDD is susceptible to any large voltage transient
that can exceed 7 V, additional precautions must be taken.
For applications where SENSEx is greater than 0 V before VDD, and is subject to a startup slew rate of less than
200 mV per 1 ms, the output can be driven to logic high in error. To correct the output, cycle the SENSEx lines
below VIT– or sequence SENSEx after VDD.
11 Layout
11.1 Layout Guidelines
Place the VDD decoupling capacitor close to the device.
Avoid using long traces for the VDD supply node. The VDD capacitor, along with parasitic inductance from the
supply to the capacitor, can form an LC tank circuit that creates ringing with peak voltages above the maximum
VDD voltage.
11.2 Layout Example
CIN
VDD
VMON1
R1
VPU
1
2
3
6
5
R5
R2
OUT1
OUT2
VPU
R4
4
R6
R3
VMON2
图 26. Example SOT-23 Layout
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15
TPS3779-Q1, TPS3780-Q1
ZHCSF51A –JUNE 2016–REVISED SEPTEMBER 2016
www.ti.com.cn
12 器件和文档支持
12.1 器件支持
12.1.1 开发支持
12.1.1.1 评估模块
评估模块 (EVM) 可与 TPS3779-Q1 和 TPS3780-Q1 配套使用，帮助评估初始电路性能。TPS3780EVM-154 评估
模块详细介绍了 TPS3780EVM-154 的设计套件和评估模块。
EVM 可通过德州仪器 (TI) 网站上的 TPS3779-Q1 和 TPS3780-Q1 产品文件夹获取，也可直接从 TI 网上商店购
买。
12.1.1.2 Spice 模型
分析模拟电路和系统的性能时，使用 SPICE 模型对电路性能进行计算机仿真非常有用。您可以从相应器件产品文
件夹中的仿真模型下获取 TPS3779-Q1 和 TPS3780-Q1 的 SPICE 模型。
12.1.2 器件命名规则
TPS3779xQyyyzQ1 和 TPS3780xQyyyzQ1 是这些器件的通用命名约定。TPS3779-Q1 和 TPS3780-Q1 代表此类
器件所属系列；x 用于表示滞后版本，yyy 预留给封装标识符，z 为封装数量。
•
•
•
•
•
示例：TPS3780CDBVRQ1
系列：TPS3780-Q1（开漏）
滞后：10%
DBV 封装：6 引脚小外形尺寸晶体管 (SOT)-23
封装数量：R 表示 3000 片
12.2 文档支持
12.2.1 相关文档ꢀ
相关文档如下：
•
•
《TPS3780EVM-154 评估模块》（文献编号：SLVU796）
应用报告《优化比较器输入端的电阻分压器》（文献编号：SLVA450）
12.3 接收文档更新通知
如需接收文档更新通知，请访问 www.ti.com.cn 网站上的器件产品文件夹。点击右上角的提醒我 (Alert me) 注册
后，即可每周定期收到已更改的产品信息。有关更改的详细信息，请查阅已修订文档中包含的修订历史记录。
12.4 相关链接
下面的表格列出了快速访问链接。范围包括技术文档、支持与社区资源、工具和软件，并且可以快速访问样片或购
买链接。
表 4. 相关链接
器件
产品文件夹
请单击此处
请单击此处
样片与购买
请单击此处
请单击此处
技术文档
请单击此处
请单击此处
工具与软件
请单击此处
请单击此处
支持与社区
请单击此处
请单击此处
TPS3779-Q1
TPS3780-Q1
16
版权 © 2016, Texas Instruments Incorporated
TPS3779-Q1, TPS3780-Q1
www.ti.com.cn
ZHCSF51A –JUNE 2016–REVISED SEPTEMBER 2016
12.5 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.6 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.7 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
12.8 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 机械、封装和可订购信息
以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对
本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
版权 © 2016, Texas Instruments Incorporated
17
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS3779BQDBVRQ1
TPS3779CQDBVRQ1
TPS3780AQDBVRQ1
TPS3780BQDBVRQ1
TPS3780CQDBVRQ1
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
DBV
DBV
DBV
DBV
DBV
6
6
6
6
6
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
12OE
12PE
12FE
12GE
12HE
NIPDAU
NIPDAU
NIPDAU
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Apr-2020
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS3779BQDBVRQ1
TPS3779CQDBVRQ1
TPS3780AQDBVRQ1
TPS3780BQDBVRQ1
TPS3780CQDBVRQ1
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
DBV
DBV
DBV
DBV
DBV
6
6
6
6
6
3000
3000
3000
3000
3000
178.0
178.0
178.0
178.0
178.0
9.0
9.0
9.0
9.0
9.0
3.23
3.23
3.23
3.23
3.23
3.17
3.17
3.17
3.17
3.17
1.37
1.37
1.37
1.37
1.37
4.0
4.0
4.0
4.0
4.0
8.0
8.0
8.0
8.0
8.0
Q3
Q3
Q3
Q3
Q3
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Apr-2020
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS3779BQDBVRQ1
TPS3779CQDBVRQ1
TPS3780AQDBVRQ1
TPS3780BQDBVRQ1
TPS3780CQDBVRQ1
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
DBV
DBV
DBV
DBV
DBV
6
6
6
6
6
3000
3000
3000
3000
3000
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
18.0
18.0
18.0
18.0
18.0
Pack Materials-Page 2
PACKAGE OUTLINE
DBV0006A
SOT-23 - 1.45 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
0.1 C
1.75
1.45
B
1.45 MAX
A
PIN 1
INDEX AREA
1
2
6
5
2X 0.95
1.9
3.05
2.75
4
3
0.50
6X
0.25
C A B
0.15
0.00
0.2
(1.1)
TYP
0.25
GAGE PLANE
0.22
0.08
TYP
8
TYP
0
0.6
0.3
TYP
SEATING PLANE
4214840/C 06/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Body dimensions do not include mold flash or protrusion. Mold flash and protrusion shall not exceed 0.25 per side.
4. Leads 1,2,3 may be wider than leads 4,5,6 for package orientation.
5. Refernce JEDEC MO-178.
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EXAMPLE BOARD LAYOUT
DBV0006A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
6X (1.1)
1
6X (0.6)
6
SYMM
5
2
3
2X (0.95)
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214840/C 06/2021
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
DBV0006A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
6X (1.1)
1
6X (0.6)
6
SYMM
5
2
3
2X(0.95)
4
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214840/C 06/2021
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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相关型号：
TPS3779ADBVR
Push-pull, low-power, dual-voltage detector in a small µSON package 6-SOT-23 -40 to 125
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