TPS3780BDBVR [TI]
采用小型 µSON 封装的漏极开路、低功耗双路电压检测器 | DBV | 6 | -40 to 125;型号: | TPS3780BDBVR |
厂家: | TEXAS INSTRUMENTS |
描述: | 采用小型 µSON 封装的漏极开路、低功耗双路电压检测器 | DBV | 6 | -40 to 125 光电二极管 电源管理电路 电源电路 |
文件: | 总17页 (文件大小:859K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
TPS3779
TPS3780
www.ti.com
SBVS216B –SEPTEMBER 2012–REVISED MAY 2013
Low-Power, Dual-Voltage Detector in Small µSON Package
Check for Samples: TPS3779, TPS3780
1
FEATURES
DESCRIPTION
The TPS3779 and TPS3780 are a family of two-
2
•
•
•
Very Small Package: 1.45-mm × 1-mm µSON
Low Quiescent Current: 1.8 µA (typ)
channel voltage detectors with low-power and high-
accuracy comparators, and are available in a very
small µSON package. The SENSE1 and SENSE2
inputs include a built-in hysteresis for filtering to reject
brief glitches, thereby ensuring stable output
operation without false triggering. This family offers
different factory-set hysteresis options of 0.5%, 1%,
5%, or 10%.
High Threshold and Hysteresis Accuracy:
1.0%
•
•
Adjustable Thresholds
Different Hysteresis Options:
–
0.5%, 1%, 5%, and 10%
•
•
Temperature Range: –40°C to +125°C
The TPS3779 and TPS3780 have adjustable SENSE
inputs that can be configured by an external resistor
divider. When the voltage at the SENSE1 or SENSE2
input goes below the falling threshold, OUT1 or OUT2
is driven low, respectively. When SENSE1 or
SENSE2 rises above the rising threshold, OUT1 or
OUT2 goes high, respectively.
Push-Pull (TPS3779) and Open-Drain
(TPS3780) Output Options
APPLICATIONS
•
DSPs, Microcontrollers, or Microprocessors
Applications
The devices have a very low quiescent current of
1.8 µA (typical) and provide a precise, space-
conscious solution for voltage detection suitable for
•
•
•
•
Portable and Battery-Powered Products
Cell Phones and PDAs
low-power
system-monitoring
and
portable
Notebook and Desktop Computers
Set-Top Boxes
applications. The TPS3779 and TPS3780 operate
from 1.5 V to 6.5 V, over the –40°C to +125°C
temperature range.
IN
DRY PACKAGE
1.45-mm ´ 1-mm SON
(TOP VIEW)
VCC1
VCC
OUT1
OUT2
RST
INT
SENSE1
TPS3779
SENSE2
DSP
CPU
SENSE1
GND
1
2
3
6
5
4
VCC
FPGA
V2
OUT1
OUT2
SENSE2
GND
GND
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2012–2013, Texas Instruments Incorporated
TPS3779
TPS3780
SBVS216B –SEPTEMBER 2012–REVISED MAY 2013
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
DEVICE INFORMATION
PRODUCT
TPS3779A
TPS3779B
TPS3779C
TPS3779D
TPS3780A
TPS3780B
TPS3780C
TPS3780D
HYSTERESIS (%)
OUTPUT
Push-pull
Push-pull
Push-pull
Push-pull
Open-drain
Open-drain
Open-drain
Open-drain
0.5
5
10
1
0.5
5
10
1
ABSOLUTE MAXIMUM RATINGS(1)
Over operating free-air temperature range, unless otherwise noted.
VALUE
–0.3 to +7
–0.3 to +7
–0.3 to +7
±20
UNIT
V
VCC
Voltage(2)
OUT1, OUT2
V
SENSE1, SENSE2
OUT pin
V
Current
mA
°C
°C
kV
V
Operating junction, TJ
Storage, Tstg
–40 to +125
–65 to +150
2
Temperature(3)
Human body model (HBM)
Charge device model (CDM)
Electrostatic discharge
(ESD) ratings
500
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated is not implied. Exposure to absolute
maximum- rated conditions for extended periods my affect device reliability.
(2) All voltages are with respect to the network ground terminal.
(3) As a result of the low dissipated power in this device, it is assumed that TJ = TA.
THERMAL INFORMATION
TPS3779
TPS3780
THERMAL METRIC(1)
UNITS
DRY (µSON)
6 PINS
306.7
θJA
Junction-to-ambient thermal resistance
θJCtop
θJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
174.1
173.4
°C/W
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
30.9
ψJB
171.6
θJCbot
65.2
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
2
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TPS3780
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SBVS216B –SEPTEMBER 2012–REVISED MAY 2013
ELECTRICAL CHARACTERISTICS
All specifications are over the operating temperature range of –40°C < TJ < +125°C and 1.5 V ≤ VCC ≤ 6.5 V, unless otherwise
noted. Typical values are at TJ = +25°C and VCC = 3.3 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
6.5
0.8
3.3
4.5
3.5
5
UNIT
V
VCC
Input supply range
Power-on reset voltage(1)
1.5
V(POR)
VOL (max) = 0.2 V, IOL = 15 µA
V
VCC = 3.3 V, no load, –40°C < TJ < +85°C
VCC = 3.3 V, no load, –40°C < TJ < +125°C
VCC = 6.5 V, no load, –40°C < TJ < +85°C
VCC = 6.5 V, no load, –40°C < TJ < +125°C
1.8
2
µA
µA
µA
µA
V
ICC
Supply current (into VCC pin)
1.20
Positive-going input threshold
voltage
VIT+
V(SENSE) rising 0°C < TJ < +85°C
–40°C < TJ < +125°C
–1%
–1%
+1%
+1.3%
TPS37xxA (0.5% hysteresis)
TPS37xxB (5% hysteresis)
TPS37xxC (10% hysteresis)
TPS37xxD (1% hysteresis)
1.194
1.14
V
V
V
V
1.08
1.188
Negative-going input threshold
voltage
TPS37xxA, TPS37xxD,
0°C < TJ < +85°C
VIT–
V(SENSE) falling
–1%
–1%
+1%
+1.3%
+1.3%
TPS37xxA, TPS37xxD,
–40°C < TJ < +125°C
TPS37xxB, TPS37xxC,
–40°C < TJ < +125°C
–1.3%
–5
I(SENSE)
Input current(2)
V(SENSE) = 0 V or VCC
5
0.25
0.25
0.3
nA
V
V
V
V
V
V
V
CC ≥ 1.2 V, ISINK = 0.4 mA
CC ≥ 2.7 V, ISINK = 2 mA
CC ≥ 4.5 V, ISINK = 3.2 mA
CC ≥ 1.7 V, ISINK = 0.4 mA
CC ≥ 2.7 V, ISINK = 1 mA
CC ≥ 4.5 V, ISINK = 2.5 mA
VOL
Low-level output voltage
V
V
0.8 VCC
0.8 VCC
0.8 VCC
V
High-level output voltage
(push-pull)
VOH
V
V
High impedance, V(SENSE_OUT) = 6.5 V,
–40°C < TJ < +85°C
–50
50
nA
nA
µs
Open-drain output leakage
current
Ilkg(OD)
High impedance, V(SENSE_OUT) = 6.5 V,
–40°C < TJ < +125°C
–250
250
SENSE (rising) to OUT
propagation delay
tPD(r)
tPD(f)
4
SENSE (falling) to OUT
propagation delay
Startup delay(3) (2)
6
µs
µs
350
(1) The lowest supply voltage (VCC) at which the output is active (trise(VCC) > 15 µs/V). Below V(POR), the output cannot be determined.
(2) Specified by design.
(3) During power-up, VCC must exceed 1.5 V for the start-up delay time before the output is in the correct state.
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TPS3780
SBVS216B –SEPTEMBER 2012–REVISED MAY 2013
www.ti.com
PIN CONFIGURATION
DRY PACKAGE
1.45-mm × 1-mm USON
(TOP VIEW)
SENSE1
GND
1
2
3
6
5
4
VCC
OUT1
OUT2
SENSE2
PIN DESCRIPTIONS
PIN
DESCRIPTION
NAME
NO.
GND
2
Ground
OUT2 is the output for SENSE2. OUT2 is asserted (driven low) when the voltage at SENSE2 falls
below VIT–. OUT2 is deasserted (goes high) after SENSE2 rises higher than VIT+. OUT2 is a push-pull
output for the TPS3779 and an open-drain output for the TPS3780. The open-drain device (TPS3780)
can be pulled up to 6.5 V independent of VCC; a pull-up resistor is required for this device.
OUT2
OUT1
4
5
OUT1 is the output for SENSE1. OUT1 is asserted (driven low) when the voltage at SENSE1 falls
below VIT–. OUT1 is deasserted (goes high) after SENSE1 rises higher than VIT+. OUT1 is a push-pull
output for the TPS3779 and an open-drain output for the TPS3780. The open-drain device (TPS3780)
can be pulled up to 6.5 V independent of VCC; a pull-up resistor is required for this device.
This pin is connected to the voltage to be monitored with the use of an external resistor divider. When
the voltage at this terminal drops below the threshold voltage (VIT–), OUT1 is asserted.
SENSE1
SENSE2
VCC
1
3
6
This pin is connected to the voltage to be monitored with the use of an external resistor divider. When
the voltage at this terminal drops below the threshold voltage (VIT–), OUT2 is asserted.
Supply voltage input. Connect a 1.5-V to 6.5-V supply to VCC in order to power the device. It is good
analog design practice to place a 0.1-µF ceramic capacitor close to this pin.
FUNCTIONAL BLOCK DIAGRAM
VCC
SENSE1
OUT1
SENSE2
OUT2
Hysteresis
Logic and
Control
GND
1.22 V
Figure 1. Block Diagram
4
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TPS3780
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SBVS216B –SEPTEMBER 2012–REVISED MAY 2013
TYPICAL CHARACTERISTICS
At TJ = +25°C and VCC = 3.3 V, unless otherwise noted
4
3.5
3
1.214
œ40°C
85°C
0°C
25°C
SENSE1, Vcc = 1.5 V
SENSE1, Vcc = 6.5 V
SENSE2, Vcc = 1.5 V
SENSE2, Vcc = 6.5 V
105°C
125°C
1.21
1.206
1.202
1.198
1.194
1.19
2.5
2
1.5
1
0.5
0
0
1
2
3
4
5
6
7
-50
-25
0
25
50
75
100
125
C001
C002
Supply Voltage (V)
Temperature (°C)
Figure 2. SUPPLY CURRENT vs SUPPLY VOLTAGE
Figure 3. SENSE THRESHOLD (VIT+) vs TEMPERATURE
0.4
0.35
œ40°C
SENSE1, Vcc = 1.5 V
SENSE1, Vcc = 6.5 V
SENSE2, Vcc = 1.5 V
SENSE2, Vcc = 6.5 V
0.3
0.2
0.1
0
0°C
0.3
0.25
0.2
25°C
85°C
105°C
125°C
0.15
0.1
-0.1
-0.2
-0.3
-0.4
0.05
0
-50
-25
0
25
50
75
100
125
0
0.5
1
1.5
2
C003
C004
Temperature (°C)
Output Sink Current (mA)
Figure 4. SENSE THRESHOLD (VIT–) vs TEMPERATURE
Figure 5. OUTPUT VOLTAGE LOW vs OUTPUT CURRENT
(VCC = 1.5 V)
0.35
0.35
œ40°C
œ40°C
0.3
0.25
0.2
0°C
0.3
0.25
0.2
0°C
25°C
85°C
105°C
125°C
25°C
85°C
105°C
125°C
0.15
0.1
0.15
0.1
0.05
0
0.05
0
0
0.5
1
1.5
2
2.5
3
0
0.5
1
1.5
2
2.5
3
3.5
4
C005
C006
Output Sink Current (mA)
Output Sink Current (mA)
Figure 6. OUTPUT VOLTAGE LOW vs OUTPUT CURRENT
(VCC = 3.3 V)
Figure 7. OUTPUT VOLTAGE LOW vs OUTPUT CURRENT
(VCC = 6.5 V)
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SBVS216B –SEPTEMBER 2012–REVISED MAY 2013
www.ti.com
TYPICAL CHARACTERISTICS (continued)
At TJ = +25°C and VCC = 3.3 V, unless otherwise noted
1.6
3.4
3.3
3.2
3.1
3
1.4
1.2
1
œ40°C
0°C
œ40°C
0°C
2.9
2.8
2.7
25°C
85°C
125°C
25°C
85°C
125°C
0.8
0.1
0.2
0.3
0.4
0.5
0
0.4
0.8
1.2
1.6
2
C007
C008
Output Source Current (mA)
Output Source Current (mA)
Figure 8. OUTPUT VOLTAGE HIGH vs OUTPUT CURRENT
(VCC = 1.5 V)
Figure 9. OUTPUT VOLTAGE HIGH vs OUTPUT CURRENT
(VCC = 3.3 V)
6.5
6.4
5
4
3
2
6.3
œ40°C
6.2
0°C
25°C
6.1
1
0
Vcc = 1.5 V
Vcc = 6.5 V
85°C
125°C
6
0
0.5
1
1.5
2
2.5
3
-50
-25
0
25
50
75
100
125
C009
C010
Output Source Current (mA)
Temperature (°C)
Figure 10. OUTPUT VOLTAGE HIGH vs OUTPUT CURRENT
(VCC = 6.5 V)
Figure 11. PROPAGATION DELAY FROM SENSE HIGH TO
OUTPUT HIGH (SENSE1 and SENSE2 = 0 V to 1.3 V)
10
8
6
4
Vcc = 1.5 V
Vcc = 6.5 V
2
0
-50
-25
0
25
50
75
100
125
C011
Temperature (°C)
Figure 12. PROPAGATION DELAY FROM SENSE LOW TO OUTPUT LOW (SENSE1 and SENSE2 = 1.3 V to 0 V)
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TPS3780
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SBVS216B –SEPTEMBER 2012–REVISED MAY 2013
DETAILED DESCRIPTION
OVERVIEW
The TPS3779 and TPS3780 belong to a family of ultrasmall, low quiescent current (ICC), dual-channel voltage
detectors. These devices have high-accuracy, rising and falling input thresholds, and assert the output as shown
in Table 1. The output (OUTx pin) goes low when the SENSEx pin is less than VIT– and goes high when the pin
is greater than VIT+. The TPS3779 and TPS3780 offer multiple hysteresis options from 0.5% to 10% for use in
wide variety of applications. These devices have two independent voltage detection channels that can be used in
systems where multiple voltage rails are required to be monitored, or where one channel can be used as an early
warning signal and the other channel used as the system reset signal.
Table 1. TPS33779, TPS3780 Truth Table
CONDITIONS
SENSE1 < VIT–
SENSE2 < VIT–
SENSE1 > VIT+
SENSE2 > VIT+
OUTPUT
OUT1 = low
OUT2 = low
OUT1 = high
OUT2 = high
INPUTS (SENSE1, SENSE2)
The TPS3779 and TPS3780 have two comparators for voltage detection. Each comparator has one external
input; the other input is connected to the internal reference. The comparator rising threshold is designed and
trimmed to be equal to VIT+ and the falling threshold is trimmed to be equal to VIT–. The built-in falling hysteresis
options make the devices immune to supply rail noise and ensures stable operation.
The comparator inputs can swing from ground to 6.5 V, regardless of the device supply voltage used. Although
not required in most cases, it is good analog design practice to place a 1-nF to 10-nF bypass capacitor at the
comparator input for extremely noisy applications in order to reduce sensitivity to transients and layout parasitic.
For each SENSE input, the corresponding output (OUTx) is driven to logic low when the input voltage drops
below VIT–. When the voltage exceeds VIT+, the output (OUTx) goes to a high-impedance state, as shown in
Figure 13.
VCC
V(POR)
VIT+
SENSEx
Hysteresis
VIT-
tpd(r)
tpd(f)
OUTx
Figure 13. Timing Diagram
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The TPS3779 and TPS3780 also have adjustable sense inputs that can be configured to monitor voltages using
external resistor divider, as shown in Figure 14.
VCC
V1
VCC
R1_V1
SENSE1
SENSE2
OUT1
OUT2
TPS3780
R1_V2
To System
Reset
V2
R2_V1
R2_V2
GND
Figure 14. Application Diagram
The resistor divider values and target threshold voltage can be calculated by using Equation 1 and Equation 2 to
determine VMON(no UV) and VMON(UV), respectively.
R1
R2
≈
’
VMON(UV) = 1 +
× V
IT-
∆
÷
◊
«
(1)
(2)
R1
R2
≈
’
VMON(no UV) = 1 +
× V
IT+
∆
÷
◊
«
Where:
•
•
•
R1 and R2 are the resistor values for the resistor divider on the SENSEx pins.
VMON(UV) is the target voltage at which an undervoltage condition is detected.
VMON(no UV) is the target voltage at which an undervoltage condition is removed when VMON rises.
Choose RTOTAL ( = R1 + R2) so that the current through the divider is approximately 100 times higher than the
input current at the SENSEx pins. The resistors can have high values to minimize current consumption as a
result of low input bias current without adding significant error to the resistive divider. For details on sizing input
resistors, refer to Application Report SLVA450, Optimizing Resistor Dividers at a Comparator Input, available for
download from www.ti.com.
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SBVS216B –SEPTEMBER 2012–REVISED MAY 2013
OUTPUTS (OUT1, OUT2)
In a typical device application, the outputs are connected to a reset or enable input of the processor, such as a
digital signal processor (DSP), central processing unit (CPU), field-programmable gate array (FPGA), or
application-specific integrated circuit (ASIC); or the outputs are connected to the enable input of a voltage
regulator, such as a dc-dc or low-dropout (LDO) regulator.
The TPS3779 provides two push-pull outputs. The logic high level of the outputs is determined by the VCC pin
voltage. With this configuration, pull-up resistors are not required and some board area can be saved. However,
all interface logic levels should be examined. All OUT connections must be compatible with the VCC pin logic
level.
The TPS3780 provides two open-drain outputs (OUT1 and OUT2); pull-up resistors must be used to hold these
lines high when the output goes to a high impedance condition (not asserted). By connecting pull-up resistors to
the proper voltage rails, the outputs can be connected to other devices at correct interface voltage levels. The
outputs can be pulled up to 6.5 V, independent of the device supply voltage. To ensure proper voltage levels,
make sure to choose the correct pull-up resistor values. The pull-up resistor value is determined by VOL, the sink
current capability, and the output leakage current (Ilkg(OD)). These values are specified in the Electrical
Characteristics table. By using wired-AND logic, OUT1 and OUT2 can be merged into one logic signal. The
Inputs (SENSE1, SENSE2) section describes how the outputs are asserted or deasserted. Refer to Figure 13 for
a description of the relationship between threshold voltages and the respective output.
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REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from the page numbers in the current version.
Changes from Revision A (March 2013) to Revision B
Page
•
Changed VIT– parameter in Electrical Characteristics table .................................................................................................. 3
Changes from Original (September 2012) to Revision A
Page
•
Changed data sheet from product preview to production data ............................................................................................. 1
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PACKAGE OPTION ADDENDUM
www.ti.com
9-May-2013
PACKAGING INFORMATION
Orderable Device
TPS3779ADRYR
TPS3779ADRYT
TPS3779BDRYR
TPS3779BDRYT
TPS3779CDRYR
TPS3779CDRYT
TPS3779DDRYR
TPS3779DDRYT
TPS3780ADRYR
TPS3780ADRYT
TPS3780BDRYR
TPS3780BDRYT
TPS3780CDRYR
TPS3780CDRYT
TPS3780DDRYR
TPS3780DDRYT
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
Top-Side Markings
Samples
Drawing
Qty
(1)
(2)
(3)
(4)
PREVIEW
SON
SON
SON
SON
SON
SON
SON
SON
SON
SON
SON
SON
SON
SON
SON
SON
DRY
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
5000
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
ZQ
ZQ
ZR
ZR
ZT
ZT
ZS
ZS
ZU
ZU
ZV
ZV
ZW
ZW
ZX
ZX
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
ACTIVE
DRY
DRY
DRY
DRY
DRY
DRY
DRY
DRY
DRY
DRY
DRY
DRY
DRY
DRY
DRY
250
5000
250
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
5000
250
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
5000
250
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
5000
250
Green (RoHS
& no Sb/Br)
ACTIVE
Green (RoHS
& no Sb/Br)
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
5000
250
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
5000
250
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
5000
250
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
9-May-2013
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
22-Jun-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS3780ADRYR
TPS3780ADRYT
SON
SON
DRY
DRY
6
6
5000
250
179.0
179.0
8.4
8.4
1.2
1.2
1.65
1.65
0.7
0.7
4.0
4.0
8.0
8.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
22-Jun-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS3780ADRYR
TPS3780ADRYT
SON
SON
DRY
DRY
6
6
5000
250
203.0
203.0
203.0
203.0
35.0
35.0
Pack Materials-Page 2
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相关型号:
TPS3780DDBVR
Open-drain, low-power, dual-voltage detector in Small µSON package 6-SOT-23 -40 to 125
TI
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