TPS38-Q1 [TI]
具有超低静态电流和延时功能的汽车类 65V 双通道监控器;型号: | TPS38-Q1 |
厂家: | TEXAS INSTRUMENTS |
描述: | 具有超低静态电流和延时功能的汽车类 65V 双通道监控器 监控 |
文件: | 总53页 (文件大小:4615K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
TPS38-Q1
ZHCSMU7D –AUGUST 2020 –REVISED JULY 2023
TPS38-Q1 适用于汽车、具有可编程检测和复位功能的宽VIN 65V 双通道过压或
欠压(OV 或UV)检测器
1 特性
3 说明
• 具有符合AEC-Q100 标准的下列特性:
TPS38-Q1 是一款65V 输入电压检测器,
IDD 为 1 μA,精度为 1%,并具有 10 μs 的快速检测
时间。该器件可直接连接到
– 器件温度等级1:–40°C 至+125°C 环境工作
温度范围TA
12V/24V 汽车电池系统,用于持续监测过压 (OV) 或欠
压 (UV) 条件;由于使用内部电阻分压器,它的总体解
决方案尺寸非常小。由于提供了广泛的迟滞电压选项,
可以忽略冷启动、启停和各种汽车电池电压瞬变。
SENSE 引脚上的内置迟滞特性有助于在监测电源电压
轨时防止出现错误的复位信号。
– 器件HBM ESD 分类等级2
– 器件CDM ESD 分类等级C7B
• 宽电源电压范围:2.7V 至65V
• SENSE 和RESET 引脚为65V 等级
• 低静态电流:1 μA(典型值)
• 灵活而广泛的电压阈值选项
表12-1
通过单独的 VDD 和 SENSE 引脚,可实现高可靠性汽
车系统所需的冗余,并且 SENSE 引脚可以监控比
VDD 更高和更低的电压。SENSE 引脚的高阻抗输入
支持使用可选的外部电阻器。通过 CTSx 和 CTRx 引
脚,可以对 RESET 信号的上升沿和下降沿进行延迟调
整。此外,CTSx 可忽略受监控电压轨上产生的电压干
扰,从而充当去抖动器;CTRx 具有手动复位 (MR) 的
作用,可用于强制系统复位。
– 2.7V 至36V(最高精度1.5%)
– 800 mV 选项(最高精度1%)
• 内置迟滞(VHYS
)
– 百分比选项:2% 至13%(阶跃1%)
– 固定选项:VTH < 8V = 0.5V、1V、1.5V、
2V、2.5V
• 可编程复位延时时间
– 10 nF = 12.8 ms, 10 μF = 12.8 s
• 可编程感测延时时间
TPS38-Q1 采用 WSON 或 SOT-23 封装。WSON 封
装具有可润湿侧翼,便于进行自动光学检测 (AOI) 和低
分辨率 X 射线检测。根据 IEC60664 中的指南,中心
垫片是不导电的,以增加 VDD 和 GND 之间的爬电距
离。
– 10 nF = 1.28 ms, 10 μF = 1.28 s
• 手动复位(MR) 特性
• 输出复位锁存特性
• 输出拓扑:
器件信息
封装1
– 通道1: 开漏或推挽
– 通道2: 开漏
封装尺寸(标称值)
2.5mm × 2.5mm
4.1mm × 1.9mm
器件型号
TPS38-Q1
TPS38-Q1
WSON (10) (DSK)
SOT-23 (14) (DYY)
2 应用
• 远程信息处理控制单元
• 紧急呼叫系统
• 音频放大器
• 音响主机和组合仪表
• 传感器融合和摄像头
• 车身控制模块
Low Iq, No external
resistors needed
0.95
0.90
0.85
0.80
0.75
0.70
0.65
0.60
0.55
0.50
DC/DC
MCU
VDD
VDD
GPIO
MCU Flag
RESET1
TPS38-Q1
RESET2
SENSE1
GND
SENSE2
GND
-40oC
25oC
Enable
Boost
125oC
Backup
Vba
Boost
Converter
0
5
10 15 20 25 30 35 40 45 50 55 60 65
Supply Voltage (V)
典型应用电路
典型IDD 与VDD
本文档旨在为方便起见,提供有关TI 产品中文版本的信息,以确认产品的概要。有关适用的官方英文版本的最新信息,请访问
www.ti.com,其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前,请务必参考最新版本的英文版本。
English Data Sheet: SNVSBI8
TPS38-Q1
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ZHCSMU7D –AUGUST 2020 –REVISED JULY 2023
Table of Contents
9.1 Adjustable Voltage Thresholds................................. 26
9.2 Application Information............................................. 27
9.3 Typical Application.................................................... 27
10 Power Supply Recommendations..............................30
10.1 Power Dissipation and Device Operation............... 30
11 Layout...........................................................................31
11.1 Layout Guidelines................................................... 31
11.2 Layout Example...................................................... 31
11.3 Creepage Distance................................................. 32
12 Device and Documentation Support..........................33
12.1 Device Nomenclature..............................................33
12.2 接收文档更新通知................................................... 34
12.3 支持资源..................................................................34
12.4 Trademarks.............................................................34
12.5 静电放电警告.......................................................... 34
12.6 术语表..................................................................... 34
13 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Device Comparison.........................................................3
6 Pin Configuration and Functions...................................4
7 Specifications.................................................................. 6
7.1 Absolute Maximum Ratings........................................ 6
7.2 ESD Ratings .............................................................. 6
7.3 Recommended Operating Conditions.........................6
7.4 Thermal Information ...................................................6
7.5 Electrical Characteristics.............................................7
7.6 Timing Requirements..................................................9
7.7 Timing Diagrams ......................................................10
7.8 Typical Characteristics..............................................12
8 Detailed Description......................................................15
8.1 Overview...................................................................15
8.2 Functional Block Diagram.........................................15
8.3 Feature Description...................................................16
8.4 Device Functional Modes..........................................25
9 Application and Implementation..................................26
Information.................................................................... 34
13.1 Package Option Addendum....................................41
13.2 Tape and Reel Information......................................42
13.3 Tray Information......................................................44
4 Revision History
注:以前版本的页码可能与当前版本的页码不同
Changes from Revision C (December 2021) to Revision D (July 2023)
Page
• 在数据表中针对 DYY 封装删除了“产品预发布”..............................................................................................1
Changes from Revision B (September 2021) to Revision C (December 2021)
Page
• 将“预告信息”更改为“量产数据发布”...........................................................................................................1
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English Data Sheet: SNVSBI8
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5 Device Comparison
Contact TI sales representatives or consult TI's E2E forum for details and availability; minimum order quantities
may apply.
Voltage Threshold
Hysteresis
CH 2
CH 1 CH 2
CH 1
XX XX X
X XXX R-Q1
TPS38 X
DYY
Large
AUTO
INDUSTRIAL
图5-1. Device Nomenclature
1. Sense logic: OV = overvoltage; UV = undervoltage
2. Reset topology: PP = Push-Pull; OD = Open-Drain
3. Reset logic: L = Active-Low; H = Active-High
4. A to I hysteresis options are only available for 2.7 V to 8 V threshold options
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6 Pin Configuration and Functions
GND
VDD
SENSE1
SENSE2
1
2
3
4
5
10
9
CTR2/MR
8
CTS2
7
CTS1
*
CTR1/MR
6
**
* Pin 4 Options
** Pin 5 Options
1.RESET1_UV##
2.RESET1_UV##
3.RESET1_OV##
4.RESET1_OV##
1.RESET2_UVOD
2.RESET2_UVOD
3.RESET2_OVOD
4.RESET2_OVOD
## OD (Open-Drain) or PP (Push-Pull)
图6-1. DSK Package,
10-Pin WSON,
TPS38-Q1 (Top View)
1
2
3
4
5
6
7
14
13
12
11
10
9
NC
VDD
GND
NC
CTR2/MR
CTS2
SENSE1
SENSE2
CTS1
NC
*
CTR1/MR
GND
8
**
* Pin 6 Options
** Pin 7 Options
1.RESET1_UV##
2.RESET1_UV##
3.RESET1_OV##
4.RESET1_OV##
1.RESET2_UVOD
2.RESET2_UVOD
3.RESET2_OVOD
4.RESET2_OVOD
## OD (Open-Drain) or PP (Push-Pull)
图6-2. DYY Package,
14-Pin SOT-23,
TPS38-Q1 (Top View)
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表6-1. Pin Functions
WSON SOT23
(DSK)
(DYY)
PIN
NAME
I/O
DESCRIPTION
PIN
PIN
NUM.
NUM.
VDD
1
2
1
3
I
Input Supply Voltage: Bypass with a 0.1 µF capacitor to GND.
This pin is connected to the voltage that will be monitored for fixed variants or to a resistor divider for
the adjustable variant. Depending on the SENSE1 sensing configuration, when the voltage on
SENSE1 pin detects an undervoltage (UV) or an overvoltage (OV) fault, RESET1/RESET1 asserts
after the sense time delay, set by CTS1. When the voltage on the SENSE1 pin transitions back to an
unfaulty UV or OV state, RESET1/RESET1 deasserts after the reset time delay, set by CTR1. For
noisy applications, placing a 10 nF to 100 nF ceramic capacitor close to this pin may be needed for
optimum performance.
SENSE1
I
This pin is connected to the voltage that will be monitored for fixed variants or to a resistor divider for
the adjustable variant. Depending on the SENSE2 sensing configuration, when the voltage on
SENSE2 pin detects an undervoltage (UV) or an overvoltage (OV) fault, RESET2/RESET2 asserts
after the sense time delay, set by CTS2. When the voltage on the SENSE2 pin transitions back to an
unfaulty UV or OV state, RESET2/RESET2 deasserts after the reset time delay, set by CTR2. For
noisy applications, placing a 10 nF to 100 nF ceramic capacitor close to this pin may be needed for
optimum performance.
SENSE2
3
4
5
4
6
7
I
Output Reset Signal For Channel 1: See 节5 for output topology options. RESET1/RESET1 asserts
when SENSE1 detects an undervoltage or overvoltage fault condition. RESET1/RESET1 remains
asserted for the reset time delay period after SENSE1 transitions out of an UV or OV fault condition.
For active low open-drain reset output, an external pullup resistor is required. Do not place external
pullup resistors on push-pull outputs.
RESET1/
RESET1
O
Reset output signal for: SENSE1
Sensing Topology: Undervoltage (UV) or Overvoltage (OV)
Output topology: Open Drain or Push Pull, Active Low or Active High
Output Reset Signal For Channel 2: See 节5 for output topology options. RESET2/RESET2 asserts
when SENSE2 detects an undervoltage or overvoltage fault condition. RESET2/RESET2 remains
asserted for the reset time delay period after SENSE2 transitions out of an UV or OV fault condition.
For active low open-drain reset output, an external pullup resistor is required.
Reset output signal for: SENSE2
RESET2/
RESET2
O
Sensing Topology: Undervoltage (UV) or Overvoltage (OV)
Output topology: Open Drain, Active Low or Active High
Channel 1 RESET Time Delay: User-programmable reset time delay for RESET1/RESET1. Connect
an external capacitor for adjustable time delay or leave the pin floating for the shortest delay.
Manual Reset: If this pin is driven low, the RESET1/RESET1 output will reset and become asserted.
The pin can be left floating or be connected to a capacitor. This pin should not be driven high.
CTR1/ MR
CTR2/ MR
6
9
9
-
-
Channel 2 RESET Time Delay: User-programmable reset time delay for RESET2/RESET2. Connect
an external capacitor for adjustable time delay or leave the pin floating for the shortest delay.
Manual Reset: If this pin is driven low, the RESET2/RESET2 output will reset and become asserted.
12
The pin can be left floating or be connected to a capacitor. This pin should not be driven high.
GND
NC
10
8, 13
-
-
Ground. All GND pins must be electrically connected to the board ground.
The PAD for the DSK package is not internally connected, the PAD can be connected to GND or be
left floating. For the DYY package, NC stands for “No Connect”. The pins are to be left floating.
PAD
2, 5, 14
Channel 1 SENSE Time Delay: Capacitor programmable sense delay: CTS1 pin offers a user-
adjustable sense delay time when asserting a reset condition. Connecting this pin to a ground-
referenced capacitor sets the RESET1/RESET1 delay time to assert.
CTS1
CTS2
7
8
10
11
O
O
Channel 2 SENSE Time Delay: Capacitor programmable sense delay: CTS2 pin offers a user-
adjustable sense delay time when asserting a reset condition. Connecting this pin to a ground-
referenced capacitor sets the RESET2/RESET2 delay time to assert.
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range, unless otherwise noted (1)
MIN
–0.3
–0.3
MAX
70
UNIT
V
Voltage
VDD, VSENSE1,VSENSE2, VRESET1, VRESET2, VRESET1, VRESET2
Voltage
VCTS1, VCTS2, VCTR1, VCTR2
IRESET1, IRESET2, IRESET1, IRESET2
Operating junction temperature, TJ
Operating Ambient temperature, TA
Storage, Tstg
6
V
Current
10
mA
°C
°C
°C
Temperature (2)
Temperature (2)
Temperature (2)
150
150
150
–40
–40
–65
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) As a result of the low dissipated power in this device, it is assumed that TJ = TA.
7.2 ESD Ratings
VALUE UNIT
Human body model (HBM), per AEC Q100-002 (1)
Charged device model (CDM), per AEC Q100-011
±2000
±750
V(ESD) Electrostatic discharge
V
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
2.7
0
NOM
MAX
65
UNIT
Voltage
Voltage
Voltage
Current
TJ
VDD
V
V
VSENSE1,VSENSE2, VRESET1, VRESET2, VRESET1, VRESET2
VCTS1, VCTS2, VCTR1, VCTR2
65
0
5.5
±5
V
IRESET1, IRESET2, IRESET1, IRESET2
Junction temperature (free air temperature)
0
mA
°C
125
–40
7.4 Thermal Information
TPS38-Q1
DSK
THERMAL METRIC (1)
UNIT
10-PIN
87.4
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
76.3
54.2
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
4.8
ψJT
54.2
ψJB
RθJC(bot)
34.8
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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English Data Sheet: SNVSBI8
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7.5 Electrical Characteristics
At VDD(MIN) ≤VDD ≤VDD (MAX), CTR1/MR = CTR2/MR = CTS1 = CTS2 = open, output reset pull-up resistor RPU = 10 kΩ,
voltage VPU = 5.5 V, and load CLOAD = 10 pF. The operating free-air temperature range TA = –40°C to 125°C, unless
otherwise noted. Typical values are at TA = 25°C and VDD = 16 V and VIT = 6.5 V (VIT refers to VITN or VITP).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VDD
VDD
Supply Voltage
2.7
65
V
V
UVLO (1)
Undervoltage Lockout
VDD Falling below VDD (MIN)
2.7
Power on Reset Voltage (2)
RESET, Active Low
(Open-Drain, Push-Pull )
VOL(MAX) = 300 mV
IOUT (Sink) = 15 µA
VPOR
1.4
1.4
V
V
Power on Reset Voltage (2)
RESET, Active High
(Push-Pull )
VOH(MIN) = 0.8 x VDD
IOUT (Source) = 15 µA
VPOR
VIT = 800 mV
1
1
2.6
2
µA
µA
V
DD (MIN) ≤VDD ≤VDD
(MAX)
(MAX)
IDD
Supply current into VDD pin
VIT = 2.7 V to 36 V
DD (MIN) ≤VDD ≤VDD
V
SENSE (Input)
Input current
(SENSE1, SENSE2)
ISENSE
VIT = 800 mV
VIT < 10 V
100
0.8
1.2
2
nA
µA
µA
µA
Input current
(SENSE1, SENSE2)
ISENSE
ISENSE
ISENSE
Input current
(SENSE1, SENSE2)
10 V < VIT < 26 V
VIT > 26 V
Input current
(SENSE1, SENSE2)
VIT = 2.7 V to 36 V
VIT = 800 mV (3)
-1.5
0.792
-1.5
1.5
0.808
1.5
%
V
Input Threshold Negative
(Undervoltage)
VITN
0.800
0.800
Input Threshold Positive
(Overvoltage)
VIT = 2.7 V to 36 V
%
VITP
VIT = 800 mV (3)
0.792
0.808
V
VIT = 0.8 V and 2.7 V to 36 V
VHYS Range = 2% to 13%
(1% step)
-1.5
1.5
%
VIT = 2.7 V to 8 V
VHYS = 0.5 V, 1 V, 1.5 V, 2 V,
2.5 V
VHYS
Hysteresis Accuracy (4)
-1.5
1.5
%
(VITP - VHYS) ≥2.4 V, OV
Only
RESET (Output)
VRESET = 5.5 V
VITN < VSENSE < VITP
300
300
300
nA
nA
Open-Drain leakage
(RESET1, RESET2)
Ilkg(OD)
VRESET = 65 V
VITN < VSENSE < VITP
2.7 V ≤VDD ≤65 V
IRESET = 5 mA
(5)
VOL
Low level output voltage
mV
High level output voltage
dropout
2.7 V ≤VDD ≤65 V
IRESET = 500 uA
VOH_DO
(VDD - VOH = VOH_DO
(Push-Pull only)
)
100
mV
V
High level output voltage
(Push-Pull only)
2.7 V ≤VDD ≤65 V
IRESET = 5 mA
(5)
VOH
0.8VDD
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7.5 Electrical Characteristics (continued)
At VDD(MIN) ≤VDD ≤VDD (MAX), CTR1/MR = CTR2/MR = CTS1 = CTS2 = open, output reset pull-up resistor RPU = 10 kΩ,
voltage VPU = 5.5 V, and load CLOAD = 10 pF. The operating free-air temperature range TA = –40°C to 125°C, unless
otherwise noted. Typical values are at TA = 25°C and VDD = 16 V and VIT = 6.5 V (VIT refers to VITN or VITP).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Capacitor Timing (CTS, CTR)
Internal resistance
RCTR
877
88
1000
100
1147
122
Kohms
Kohms
(CTR1 / MR , CTR2 / MR )
Internal resistance
(CTS1, CTS2
RCTS
)
Manual Reset (MR)
CTR1 / MR and
CTR2 / MR pin
logic high input
VMR_IH
VMR_IH
VMR_IL
VMR_IL
VDD = 2.7 V
2200
2500
mV
mV
mV
mV
CTR1 / MR and
CTR2 / MR pin
logic high input
VDD = 65 V
VDD = 2.7 V
VDD = 65 V
CTR1 / MR and
CTR2 / MR pin
logic low input
1300
1300
CTR1 / MR and
CTR2 / MR pin
logic low input
(1) When VDD voltage falls below UVLO, reset is asserted for Output 1 and Output 2. VDD slew rate ≤100 mV / µs
(2) VPOR is the minimum VDD voltage for a controlled output state. Below VPOR, the output cannot be determined. VDD dv/dt ≤100mV/µs
(3) For adjustable voltage guidelines and resistor selection refer to Adjustable Voltage Thresholds in Application and Implementation
section
(4) Hysteresis is with respect to VITP and VITN voltage threshold. VITP has negative hysteresis and VITN has positive hysteresis.
(5) For VOH and VOL relation to output variants refer to Timing Figures after the Timing Requirement Table
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7.6 Timing Requirements
At VDD(MIN) ≤VDD ≤VDD (MAX), CTR1/MR = CTR2/MR = CTS1 = CTS2 = open (1), output reset pull-up resistor RPU = 10
kΩ, voltage VPU = 5.5V, and CLOAD = 10 pF. VDD and SENSE slew rate = 1V / µs. The operating free-air temperature range
TA = –40°C to 125°C, unless otherwise noted. Typical values are at TA = 25°C and VDD = 16 V and VIT = 6.5 V (VIT refers
to either VITN or VITP).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Common timing parameters
VIT = 2.7 V to 36 V
CCTR1 = CCTR2 = Open
20% Overdrive from Hysteresis
100
40
µs
µs
µs
Reset release time delay
tCTR
(CTR1/MR, CTR2/MR) (2)
VIT = 800 mV
CCTR1 = CCTR2 = Open
20% Overdrive from Hysteresis
VIT = 2.7 V to 36 V
CCTS1 = CCTS2 = Open
20% Overdrive from VIT
34
8
90
Sense detect time delay
(CTS1, CTS2) (3)
tCTS
VIT = 800 mV
CCTS1 = CCTS2 = Open
20% Overdrive from VIT
17
2
µs
CCTR1/MR = CCTR2/MR = Open
tSD
Startup Delay (4)
ms
(1) CCTR1 = Reset delay channel 1, CCTR2 = Reset delay channel 2,
CCTS1 = Sense delay channel 1, CCTS2 = Sense delay channel 2
(2) CTR Reset detect time delay:
Overvoltage active-LOW output is measure from VITP - HYS to VOH
Undervoltage active-LOW output is measure from VITN + HYS to VOH
Overvoltage active-HIGH output is measure from VITP - HYS to VOL
Undervoltage active-HIGH output is measure from VITN + HYS to VOL
(3) CTS Sense detect time delay:
Active-low output is measure from VIT to VOL (or VPullup
Active-high output is measured from VIT to VOH
VIT refers to either VITN or VITP
)
(4) During the power-on sequence, VDD must be at or above VDD (MIN) for at least tSD before the output is in the correct state based on
VSENSE
tSD time includes the propagation delay (CCTR1 = CCTR2 = Open). Capaicitor in CCTR1 or CCTR2 will add time to tSD.
.
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7.7 Timing Diagrams
VDD(MIN)
VDD
UVLO(MIN)
VPOR
SENSEx
VSENSEx
VITN (UV) + VHYS
VITN (UV)
Hysteresis
*See
Note C
t < tCTSx
RESETx_UVxx
tSD + tCTRx
tCTSx
tCTRx
*See
Note C
RESETx_UVxx
tSD + tCTRx
tCTSx
tCTRx
A. For open-drain output option, the timing diagram assumes the RESETx_UVOD / RESETx_UVOD pin is connected via an external pull-up resistor to VDD.
B. Be advised that 图7-1 shows the VDD falling slew rate is slow or the VDD decay time is much larger than the propagation detect delay (tCTRx) time.
C. RESETx_UVxx / RESETx_UVxx is asserted when VDD goes below the UVLO(MIN) threshold after the time delay, tCTRx, is reached.
图7-1. SENSEx Undervoltage (UV) Timing Diagram
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VDD(MIN)
VDD
UVLO(MIN)
VPOR
VITP (OV)
SENSEx
Hysteresis
VITP (OV) - VHYS
VSENSEx
*See
Note C
t < tCTSx
RESETx_OVxx
tSD + tCTRx
tCTSx
tCTRx
*See
Note C
RESETx_OVxx
tSD + tCTRx
tCTSx
tCTRx
A. For open-drain output option, the timing diagram assumes the RESETx_OVOD / RESETx_OVOD pin is connected via an external pull-up resistor to VDD.
B. Be advised that 图7-2 shows the VDD falling slew rate is slow or the VDD decay time is much larger than the propagation detect delay (tCTRx) time.
C. RESETx_OVxx / RESETx_OVxx is asserted when VDD goes below the UVLO(MIN) threshold after the time delay, tCTRx, is reached.
图7-2. SENSEx Overvoltage (OV) Timing Diagram
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7.8 Typical Characteristics
Typical characteristics show the typical performance of the TPS38-Q1 device. Test conditions are TA = 25°C, RPU = 100 kΩ,
CLoad = 50 pF, unless otherwise noted.
0.95
0.90
0.85
0.80
0.75
0.70
0.65
0.60
0.55
0.50
0.90
0.85
0.80
0.75
0.70
0.65
0.60
0.55
0.50
-40oC
25oC
-40oC
25oC
125oC
125oC
0
5
10 15 20 25 30 35 40 45 50 55 60 65
Supply Voltage (V)
0
5
10 15 20 25 30 35 40 45 50 55 60 65
Supply Voltage (V)
RESET = High, VIT = 2.7 V
RESET = Low, VIT = 2.7 V
图7-3. VDD vs IDD (RESET = High, VIT = 2.7 V)
图7-4. VDD vs IDD (RESET = Low, VIT = 2.7 V)
1.30
1.25
1.20
1.15
1.10
1.05
1.00
0.95
0.90
0.85
0.80
1.40
1.35
1.30
1.25
1.20
1.15
1.10
1.05
1.00
0.95
0.90
-40oC
25oC
-40C
25oC
125C
125oC
0
5
10 15 20 25 30 35 40 45 50 55 60 65
0
5
10 15 20 25 30 35 40 45 50 55 60 65
Supply Voltage (V)
Supply Voltage (V)
RESET = High, VIT = 0.8 V
RESET = Low, VIT = 0.8 V
图7-5. VDD vs IDD (RESET = High, VIT = 0.8 V)
图7-6. VDD vs IDD (RESET = Low, VIT = 0.8 V)
1600
1400
1200
1000
800
600
400
200
0
1600
1400
1200
1000
800
600
400
200
0
-40oC
25oC
-40oC
25oC
125oC
125oC
0
5
10 15 20 25 30 35 40 45 50 55 60 65
0
5
10 15 20 25 30 35 40 45 50 55 60 65
Sense Voltage (V)
Sense Voltage (V)
VDD = 2.7 V
VDD = 65 V
图7-7. VSENSE vs ISENSE
图7-8. VSENSE vs ISENSE
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7.8 Typical Characteristics (continued)
Typical characteristics show the typical performance of the TPS38-Q1 device. Test conditions are TA = 25°C, RPU = 100 kΩ,
CLoad = 50 pF, unless otherwise noted.
0.21
0.18
0.15
0.12
0.09
0.06
0.03
0
0.21
0.18
0.15
0.12
0.09
0.06
0.03
0.00
-40oC
25oC
-40oC
25oC
125oC
125oC
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
IRESET (mA)
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
IRESET (mA)
VDD = 2.7 V
VDD = 65 V
图7-9. Open-Drain Active Low VOL vs IRESET
图7-10. Open-Drain Active Low VOL vs IRESET
0.21
0.21
-40oC
25oC
-40oC
25oC
0.18
0.15
0.12
0.09
0.06
0.03
0
0.18
0.15
0.12
0.09
0.06
0.03
0
125oC
125oC
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
IRESET (mA)
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
IRESET (mA)
VDD = 2.7 V
VDD = 65 V
图7-11. Open-Drain Active High VOL vs IRESET
图7-12. Open-Drain Active High VOL vs IRESET
0.21
0.21
-40oC
25oC
-40oC
25oC
0.18
0.15
0.12
0.09
0.06
0.03
0
0.18
0.15
0.12
0.09
0.06
0.03
0
125oC
125oC
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
IRESET (mA)
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
IRESET (mA)
VDD = 2.7 V
VDD = 65 V
图7-13. Push-Pull Active High VOL vs IRESET
图7-14. Push-Pull Active High VOL vs IRESET
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7.8 Typical Characteristics (continued)
Typical characteristics show the typical performance of the TPS38-Q1 device. Test conditions are TA = 25°C, RPU = 100 kΩ,
CLoad = 50 pF, unless otherwise noted.
0.21
0.18
0.15
0.12
0.09
0.06
0.03
0
0.21
0.18
0.15
0.12
0.09
0.06
0.03
0
-40oC
25oC
-40oC
25oC
125oC
125oC
0
5
10 15 20 25 30 35 40 45 50 55 60 65
Supply Voltage (V)
0
5
10 15 20 25 30 35 40 45 50 55 60 65
Supply Voltage (V)
图7-15. Open-Drain Active Low VOL vs VDD
图7-16. Open-Drain Active High VOL vs VDD
0.21
0.18
0.15
0.12
0.09
0.06
0.03
0
0.21
0.18
0.15
0.12
0.09
0.06
0.03
0
-40oC
25oC
-40oC
25oC
125oC
125oC
0
5
10 15 20 25 30 35 40 45 50 55 60 65
Supply Voltage (V)
0
5
10 15 20 25 30 35 40 45 50 55 60 65
Supply Voltage (V)
图7-17. Push-Pull Active Low VOL vs VDD
图7-18. Push-Pull Active High VOL vs VDD
70
60
50
40
30
20
10
0
70
60
50
40
30
20
10
0
-40oC
25oC
-40oC
25oC
125oC
125oC
0
5
10 15 20 25 30 35 40 45 50 55 60 65
Supply Voltage (V)
0
5
10 15 20 25 30 35 40 45 50 55 60 65
Supply Voltage (V)
图7-19. Push-Pull Active Low VOH vs VDD
图7-20. Push-Pull Active High VOH vs VDD
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8 Detailed Description
8.1 Overview
The TPS38-Q1 is a family of high voltage and low quiescent current reset IC with fixed threshold voltage.
Voltage divider is integrated to eliminate the need for external resistors and eliminate leakage current that comes
with resistor dividers. However, it can also support external resistor if required by application, the lowest
threshold 800 mV (bypass internal resistor ladder) is recommenced for external resistors use case to take
advantage of faster detection time and lower ISENSE current.
VDD, SENSE and RESET pins can support 65 V continuous operation; both VDD and SENSE voltage levels can
be independent of each other, meaning VDD pin can be connected at 2.7 V while SENSE pins are connected to
a higher voltage. One thing of note, the TPS38-Q1 does not have clamps within the device so external circuits or
devices must be added to limit the voltages to the absolute max limit.
Additional features include programmable sense time delay (CTS1, CTS2) and reset delay time and manual
reset (CTR1 / MR, CTR2 / MR).
8.2 Functional Block Diagram
VDD
CTS1
CTR1 / MR
*Device Op ons
Boxes shaded in blue
See Device Nomenclature
IQ
SubReg
POR
VDD
Voltage
Divider
SENSE1
-
Output
Logic select
(High/Low)
OV or UV
Select
Sense
Delay
Manual
Reset
Reset
Delay
RESET1
V
Ref Divider1
+
REFERENCE
RESET2
V
Ref Divider2
+
-
Output
Logic select
(High/Low)
OV or UV
Select
Sense
Delay
Manual
Reset
Reset
Delay
Voltage
Divider
SENSE2
GND
CTR2 / MR
CTS2
图8-1. Functional Block Diagram
Refer to 节5 for complete list of topologies and output logic combinations.
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8.3 Feature Description
8.3.1 Input Voltage (VDD)
VDD operating voltage ranges from 2.7 V to 65 V. An input supply capacitor is not required for this device;
however, if the input supply is noisy good analog practice is to place a 0.1 µF capacitor between the VDD and
GND.
VDD needs to be at or above VDD(MIN) for at least the start-up time delay (tSD) for the device to be fully functional.
VDD voltage is independent of VSENSE and VRESET, meaning that VDD can be higher or lower than the other
pins.
8.3.1.1 Undervoltage Lockout (VPOR < VDD < UVLO)
When the voltage on VDD is less than the UVLO voltage, but greater than the power-on reset voltage (VPOR),
the output pins will be in reset, regardless of the voltage at SENSE pins.
8.3.1.2 Power-On Reset (VDD < VPOR
)
When the voltage on VDD is lower than the power on reset voltage (VPOR), the output signal is undefined and is
not to be relied upon for proper device function.
SENSE VOLTAGE OUTSIDE OF THRESHOLD
VSENSEx
VITN > VSENSEx > VITP
VDD(MIN)
VDD
UVLO(MIN)
VPOR
RESETx
Active Low
Output stays low since VSENSEx
is outside of threshold
VOL
RESETx
Active High
VOL
Undefined
Undefined
tSD+ CTRx
t
图8-2. Power Cycle (SENSE Outside of Nominal Voltage)
图8-2 assumes an external pull-up resistor is connected to the reset pin via VDD.
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SENSE VOLTAGE WITH IN THRESHOLD
VITN < VSENSEx < VITP
VSENSEx
VDD(MIN)
VDD
UVLO(MIN)
VPOR
RESETx
Active Low
VOL
RESETx
Active High
VOL
Undefined
Undefined
tSD+ CTRx
t
图8-3. Power Cycle (SENSE Within Nominal Voltage)
图8-3 assumes an external pull-up resistor is connected to the reset pin via VDD.
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8.3.2 SENSE
The TPS38-Q1 high voltage family integrates two voltage comparators, a precision reference voltage and
trimmed resistor divider. This configuration optimizes device accuracy because all resistor tolerances are
accounted for in the accuracy and performance specifications. Device also has built-in hysteresis that provides
noise immunity and ensures stable operation.
Channels are independent of each other, meaning that SENSE1 and SENSE2 and respective outputs can be
connected to different voltage rails.
Although not required in most cases, for noisy applications good analog design practice is to place a 1 nF to
10 nF bypass capacitor at the SENSEx inputs in order to reduce sensitivity to transient voltages on the
monitored signal. SENSE1 and SENSE2 pins can be connected directly to VDD pin.
8.3.2.1 SENSE Hysteresis
The TPS38-Q1 has built-in hysteresis to avoid erroneous output reset release. The hysteresis is opposite to the
threshold voltage; for overvoltage options the hysteresis is subtracted from the positive threshold (VITP), for
undervoltage options hysteresis is added to the negative threshold (VITN).
VRESETx
VRESETx
VSENSEx
VSENSEx
VITP - VHYS
VITP
VITP - VHYS
VITP
图8-4. Hysteresis (Overvoltage Active-Low)
图8-5. Hysteresis (Overvoltage Active-High)
VRESETx
VRESETx
VSENSEx
VSENSEx
VITN
VITN
VITN+VHYS
VITN+VHYS
图8-6. Hysteresis (Undervoltage Active-High)
图8-7. Hysteresis (Undervoltage Active-Low)
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表8-1. Common Hysteresis Lookup Table
TARGET
DEVICE ACTUAL HYSTERESIS OPTION
DETECT THRESHOLD
TOPOLOGY
Overvoltage
Overvoltage
Overvoltage
Overvoltage
Overvoltage
Undervoltage
Undervoltage
Undervoltage
Undervoltage
RELEASE VOLTAGE (V)
18.0 V
18.0 V
17.0 V
16.0 V
15.0 V
6.0 V
5.5 V
8 V
17.5 V
16.0 V
16.5 V
15.0 V
14.0 V
6.5 V
6 V
-3%
-11%
-3%
-6%
-7%
0.5 V
0.5 V
1 V
9 V
5 V
7.5 V
2.5 V
表 8-1 shows a sample of hysteresis and voltage options for the TPS38-Q1. For threshold voltages ranging from
2.7 V to 8 V, one option is to select a fixed hysteresis value ranging from 0.5 V to 2.5 V in increments of 0.5 V.
Additionally, a second option can be selected where the hysteresis value is a percentage of the threshold
voltage. The percentage of voltage hysteresis ranges from 2% to 13%.
Knowing the amount of hysteresis voltage, the release voltage for the undervoltage (UV) channel is
(VITN(UV) + VHYS) and for the overvoltage (OV) channel is (VITP(OV) - VHYS). For a visual understanding of the UV
and OV release voltage, see 图 7-1 and 图 7-2 . The accuracy of the release voltage, or stated in the 节 7.5 as
Hysteresis Accuracy is ±1.5%. Expanding what is shown in 表 8-1, below are a few voltage hysteresis examples
that include the hysteresis accuracy:
Undervoltage (UV) Channel
VITN = 0.8 V
Voltage Hysteresis (VHYS) = 5% = 40 mV
Hysteresis Accuracy = ±1.5% = 39.4 mV or 40.6 mV
Release Voltage = VITN + VHYS = 839.4 mV to 840.6 mV
Overvoltage (OV) Channel
VITP = 8 V
Voltage Hysteresis (VHYS) = 2 V
Hysteresis Accuracy = ±1.5% = 1.97 V or 2.03 V
Release Voltage = VITP − VHYS = 5.97 V to 6.03V
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8.3.3 Output Logic Configurations
TPS38-Q1 has two channels with separate sense pins and reset pins that can be configured independently of
each other. Channel 1 is available as Open-Drain and Push-Pull while channel 2 is only available as Open-Drain
topology.
The available output logic configuration combinations are shown in Table 表8-2.
表8-2. TPS38-Q1 Output Logic
DESCRIPTION
GPN
NOMENCLATURE
TPS38-Q1 (+ topology)
TPS38A-Q1
VALUE
CHANNEL 1
UV OD L
UV PP L
UV PP L
UV PP H
UV PP H
UV OD H
UV OD H
OV OD L
OV OD H
OV OD H
OV PP L
OV PP L
OV PP H
OV PP H
CHANNEL 2
UV OD L
UV OD L
UV OD H
UV OD H
UV OD L
UV OD H
UV OD L
OV OD L
OV OD H
OV OD L
OV OD L
OV OD H
OV OD H
OV OD L
Topology (OV and UV only)
both channels are either OV or
UV
TPS38B-Q1
TPS38D-Q1
•
•
•
•
•
•
UV = Undervoltage
OV = Overvoltage
PP = Push-Pull
OD = Open-Drain
L = Active low
TPS38E-Q1
TPS38F-Q1
TPS38G-Q1
TPS38H-Q1
H = Active high
TPS38J-Q1
TPS38K-Q1
TPS38L-Q1
TPS38M-Q1
TPS38N-Q1
TPS38O-Q1
TPS38P-Q1
8.3.3.1 Open-Drain
Open-drain output requires an external pull-up resistor to hold the voltage high to the required voltage logic.
Connect the pull-up resistor to the proper voltage rail to enable the output to be connected to other devices at
the correct interface voltage levels.
To select the right pull-up resistor consider system VOH and the (Ilkg) current provided in the electrical
characteristics, high resistors values will have a higher voltage drop affecting the output voltage high. The open-
drain output can be connected as a wired-AND logic with other open-drain signals such as another TPS38-Q1
open-drain output pin.
8.3.3.2 Push-Pull
Push-Pull output does not require an external resistor since is the output is internally pulled-up to VDD during
VOH condition and output will be connected to GND during VOH condition.
8.3.3.3 Active-High (RESET)
RESET (active-high), denoted with no bar above the pin label. RESET remains low (VOL, deasserted) as long as
sense voltage is in normal operation within the threshold boundaries and VDD voltage is above UVLO. To assert
a reset sense pins needs to meet the condition below:
• For undervoltage variant the SENSE voltage need to cross the lower boundary (VITN).
• For overvoltage variant the SENSE voltage needs to cross the upper boundary (VITP).
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8.3.3.4 Active-Low (RESET)
RESET (active low) denoted with a bar above the pin label. RESET remains high voltage (VOH, deasserted)
(open drain variant VOH is measured against the pullup voltage) as long as sense voltage is in normal operation
within the threshold boundaries and VDD voltage is above UVLO. To assert a reset sense pins needs to meet
the condition below:
• For undervoltage variant the SENSE voltage need to cross the lower boundary (VITN).
• For overvoltage variant the SENSE voltage needs to cross the upper boundary (VITP).
8.3.4 User-Programmable Reset Time Delay
The TPS38-Q1 has an adjustable reset release time delay with external capacitors. Channel timing is
independent of each other.
• A capacitor in CTR1 / MR program the reset time delay of Output 1.
• A capacitor in CTR2 / MR program the reset time delay of Output 2.
• No capacitor on these pins gives the fastest reset delay time indicated in the 节7.6.
8.3.4.1 Reset Time Delay Configuration
The time delay (tCTR) can be programmed by connecting a capacitor between CTR1 pin and GND, CTR2 for
channel 2. In this section CTRx represent either channel 1 or channel 2.
The relationship between external capacitor CCTRx_EXT (typ) and the time delay tCTRx (typ) is given by 方程式1.
tCTRx (typ) = -ln (0.28) x RCTRx (typ) x CCTRx_EXT (typ) + tCTRx (no cap)
(1)
RCTRx (typ) = is in kilo ohms (kOhms)
CCTRx_EXT (typ) = is given in microfarads (μF)
tCTRx (typ) = is the reset time delay in (ms)
The reset delay varies according to three variables: the external capacitor (CCTRx_EXT), CTR pin internal
resistance (RCTRx) provided in 节 7.5, and a constant. The minimum and maximum variance due to the constant
is show in 方程式2 and 方程式3:
tCTRx (min) = -ln (0.31) x RCTRx (min) x CCTRx_EXT (min) + tCTRx (no cap (min))
tCTRx (max) = -ln (0.25) x RCTRx (max) x CCTRx_EXT (max) + tCTRx (no cap (max))
(2)
(3)
The recommended maximum reset delay capacitor for the TPS38-Q1 is limited to 10 μF as this ensures enough
time for the capacitor to fully discharge when a voltage fault occurs. Also, having a too large of a capacitor value
can cause very slow charge up (rise times) and system noise can cause the the internal circuit to trip earlier or
later near the threshold. This leads to variation in time delay where it can make the delay accuracy worse in the
presence of system noise.
When a voltage fault occurs, the previously charged up capacitor discharges and if the monitored voltage returns
from the fault condition before the delay capacitor discharges completely, the delay will be shorter than
expected. The capacitor will begin charging from a voltage above zero and resulting in shorter than expected
time delay. A larger delay capacitor can be used so long as the capacitor has enough time to fully discharge
during the duration of the voltage fault. To ensure the capacitor is fully discharged, the time period or duration of
the voltage fault needs to be greater than 5% of the programmed reset time delay.
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8.3.5 User-Programmable Sense Delay
TPS38-Q1 has adjustable sense release time delay with external capacitors. Channel timing are independent of
each other. Sense delay is used as a de-glitcher or ignoring known transients.
• A capacitor in CTS1 program the excursion detection on SENSE1.
• A capacitor in CTS2 program the excursion detection on SENSE2.
• No capacitor on these pins gives the fastest detection time indicated in the 节7.6.
8.3.5.1 Sense Time Delay Configuration
The time delay (tCTS) can be programmed by connecting a capacitor between CTS1 pin and GND, CTS2 for
channel 2. In this section CTSx represent either channel 1 or channel 2.
The relationship between external capacitor CCTSx_EXT (typ) and the time delay tCTSx (typ) is given by 方程式4.
tCTSx (typ) = -In (0.28) x RCTSx (typ) x CCTSx_EXT (typ) + tCTSx (no cap)
(4)
RCTSx = is in kilo ohms (kOhms)
CCTSX_EXT = is given in microfarads (μF)
tCTSx = is the sense time delay (ms)
The sense delay varies according to three variables: the external capacitor (CCTSx_EXT), CTS pin internal
resistance (RCTSx) provided in 节 7.5, and a constant. The minimum and maximum variance due to the constant
is show in 方程式5 and 方程式6:
tCTSx (min) = -ln (0.31) x RCTSx (min) x CCTSx_EXT (min) + tCTSx (no cap (min))
tCTRx (max) = -ln (0.25) x RCTSx (max) x CCTSx_EXT (max) + tCTSx (no cap (max))
(5)
(6)
The recommended maximum sense delay capacitor for the TPS38-Q1 is limited to 10 μF as this ensures
enough time for the capacitor to fully discharge when a voltage fault occurs. Also, having a too large of a
capacitor value can cause very slow charge up (rise times) and system noise can cause the the internal circuit to
trip earlier or later near the threshold. This leads to variation in time delay where it can make the delay accuracy
worse in the presence of system noise.
When a voltage fault occurs, the previously charged up capacitor discharges and if the monitored voltage returns
from the fault condition before the delay capacitor discharges completely, the delay will be shorter than
expected. The capacitor will begin charging from a voltage above zero and resulting in shorter than expected
time delay. A larger delay capacitor can be used so long as the capacitor has enough time between fault events
to fully discharge during the duration of the voltage fault. To ensure the capacitor is fully discharged, the time
period or time duration between fault events needs to be greater than 10% of the programmed sense time delay.
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8.3.6 Manual RESET (CTR1 / MR) and (CTR2 / MR) Input
The manual reset input allows a processor or other logic circuits to initiate a reset. In this section MR is a generic
reference to (CTR1 / MR) and (CTR2 / MR). A logic low on MR causes RESET1 to assert on reset output. After
MR is left floating, RESET1 will release the reset if the voltage at SENSE1 pin is at nominal voltage. MR should
not be driven high, this pin should be left floating or connected to a capacitor to GND, this pin can be left
unconnected if is not used.
If the logic driving the MR cannot tri-state (floating and GND) then a logic-level FET should be used as illustrated
in 图8-8.
Low Voltage
High Voltage
VDD
MCU
CTRx
Active low
Logic
Reset
Delay
GPIO
Low or Floating
图8-8. Manual Reset Implementation
SENSE VOLTAGE WITH IN THRESHOLD
VITN < VSENSEx < VITP
VSENSEx
CTRx/MR
< VMR
MR floating or
connected to capacitor
MR floating or
connected to capacitor
RESETx
Active-High
RESETx
Active-Low
图8-9. Manual Rest Timing Diagram
表8-3. MR Functional Table
SENSE ON NOMINAL VOLTAGE
Yes
MR
RESET STATUS
Low
Reset asserted
Fast reset release when SENSE
voltage goes back to nominal
voltage
Floating
Yes
Capacitor
High
Yes
Yes
Programmable reset time delay
NOT Recommended
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8.3.7 Adjustable Voltage Thresholds
方程式 7 illustrates an example of how to adjust the voltage threshold with external resistor dividers. The
resistors can be calculated depending on the desired voltage threshold and device part number. TI recommends
using the 0.8 V voltage threshold device when using an adjustable voltage variant. This variant bypasses the
internal resistor ladder.
For example, consider a 12 V rail being monitored VMON for undervoltage (UV) using channel 1 of the
TPS38A010122DSKRQ1 variant. Using 方程式 7 and shown in 图 8-10, R1 is the top resistor of the resistor
divider that is between VMON and VSENSE2, R2 is the bottom resistor that is between VSENSE2 and GND, VMON is
the voltage rail that is being monitored and VSENSE2 is the input threshold voltage. The monitored UV threshold,
denoted as VMON-, where the device will assert a reset signal occurs when VSENSE2 = VIT-(UV) or, for this
example, VMON- = 10.8V which is 90% from 12 V. Using 方程式 7 and assuming R2 = 10kΩ, R1 can be
calculated shown in 方程式8 where IR1 is represented in 方程式9:
VSENSE2 = VMON- × (R2 ÷ (R1 + R2))
R1 = (VMON- - VSENSE2) ÷ IR1
IR1 = IR2 = VSENSE2 ÷ R2
(7)
(8)
(9)
Substituting 方程式 9 into 方程式 8 and solving for R1 in 方程式 7, R1 = 125kΩ. The TPS38A010122DSKRQ1 is
typically meant to monitor a 0.8 V rail with ±2% voltage threshold hysteresis. For the reset signal to become
deasserted, VMON would need to go above VIT- + VHYS. For this example,
VMON = 11.016 V when the reset signal becomes deasserted.
There are inaccuracies that must be taken into consideration while adjusting voltage thresholds. Aside from the
tolerance of the resistor divider, there is an internal resistance of the SENSE pin that may affect the accuracy of
the resistor divider. Although expected to be very high impedance, users are recommended to calculate the
values for the design specifications. The internal SENSE resistance RSENSE can be calculated by the SENSE
voltage VSENSE divided by the SENSE current ISENSE as shown in 方程式 11. VSENSE can be calculated using 方
程式7 depending on the resistor divider and monitored voltage. ISENSE can be calculated using 方程式10.
ISENSE = [(VMON - VSENSE) ÷ R1] - (VSENSE ÷ R2)
(10)
(11)
RSENSE = VSENSE ÷ ISENSE
VMON
VMON
VDD
10 k
VDD
VDD
VDD
R3
R1
10 k
VSENSE1
SENSE1
SENSE2
RESET1
RESET2
VSENSE2
TPS38A-Q1
CTR1
CTR2
CTS1
CTS2
R2
R4
GND
图8-10. Adjustable Voltage Threshold with External Resistor Dividers
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8.4 Device Functional Modes
表8-4. Undervoltage Detect Functional Mode Truth Table
SENSE
OUTPUT (2)
(RESET PIN)
DESCRIPTION
CTR (1) / MR PIN
VDD PIN
PREVIOUS
CONDITION
CURRENT CONDITION
Open or capacitor
connected
Normal Operation
SENSE > VITN(UV)
SENSE > VITN(UV)
SENSE < VITN(UV)
SENSE > VITN(UV)
SENSE < VITN(UV)
SENSE > VITN(UV)
VDD > VDD(MIN)
VDD > VDD(MIN)
VDD > VDD(MIN)
High
Low
Low
Undervoltage
Detection
Open or capacitor
connected
Undervoltage
Detection
Open or capacitor
connected
Open or capacitor
connected
Normal Operation
Manual Reset
SENSE < VITN(UV) SENSE > VITN(UV) + HYS
VDD > VDD(MIN)
VDD > VDD(MIN)
High
Low
Low
SENSE > VITN(UV)
SENSE > VITN(UV)
SENSE > VITN(UV)
SENSE > VITN(UV)
Low
Open or capacitor
connected
UVLO Engaged
VPOR < VDD < VDD(MIN)
Below VPOR
Undefined Output
,
Open or capacitor
connected
SENSE > VITN(UV)
SENSE > VITN(UV)
VDD < VPOR
Undefined
(1) Reset time delay is ignored in the truth table
(2) Open-drain active low output. External pull-up resistor to high voltage
表8-5. Overvoltage Detect Functional Mode Truth Table
SENSE
OUTPUT (2)
(RESET PIN)
DESCRIPTION
CTR (1) / MR PIN
VDD PIN
PREVIOUS
CONDITION
CURRENT CONDITION
Open or capacitor
connected
Normal Operation
SENSE < VITN(OV)
SENSE < VITN(OV)
SENSE > VITN(OV)
SENSE < VITN(OV)
SENSE > VITN(OV)
SENSE < VITN(OV)
VDD > VDD(MIN)
VDD > VDD(MIN)
VDD > VDD(MIN)
High
Low
Low
Overvoltage
Detection
Open or capacitor
connected
Overvoltage
Detection
Open or capacitor
connected
Open or capacitor
connected
Normal Operation
Manual Reset
SENSE > VITN(OV)
SENSE < VITN(OV)
SENSE < VITN(OV)
SENSE < VITN(OV) - HYS
SENSE < VITN(OV)
VDD > VDD(MIN)
VDD > VDD(MIN)
High
Low
Low
Low
Open or capacitor
connected
UVLO Engaged
SENSE < VITN(OV)
VPOR < VDD < UVLO
Below VPOR
Undefined Output
,
Open or capacitor
connected
SENSE < VITN(OV)
SENSE < VITN(OV)
VDD < VPOR
Undefined
(1) Reset time delay is ignored in the truth table
(2) Open-drain active low output. External pull-up resistor to high voltage
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9 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围,TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计,以确保系统功能。
9.1 Adjustable Voltage Thresholds
方程式 12 illustrates an example of how to adjust the voltage threshold with external resistor dividers. The
resistors can be calculated depending on the desired voltage threshold and device part number. TI recommends
using the 0.8 V voltage threshold device when using an adjustable voltage variant. This variant bypasses the
internal resistor ladder.
For example, consider a 12 V rail being monitored VMON for undervoltage (UV) using channel 1 of the
TPS38A010122DSKRQ1 variant. Using 方程式 12 and shown in 图 9-1, R1 is the top resistor of the resistor
divider that is between VMON and VSENSE2, R2 is the bottom resistor that is between VSENSE2 and GND, VMON is
the voltage rail that is being monitored and VSENSE2 is the input threshold voltage. The monitored UV threshold,
denoted as VMON-, where the device will assert a reset signal occurs when VSENSE2 = VIT-(UV) or, for this
example, VMON- = 10.8V which is 90% from 12 V. Using 方程式 12 and assuming R2 = 10kΩ, R1 can be
calculated shown in 方程式13 where IR1 is represented in 方程式14:
VSENSE2 = VMON- × (R2 ÷ (R1 + R2))
R1 = (VMON- - VSENSE2) ÷ IR1
IR1 = IR2 = VSENSE2 ÷ R2
(12)
(13)
(14)
Substituting 方程式 14 into 方程式 13 and solving for R1 in 方程式 12, R1 = 125kΩ. The
TPS38A010122DSKRQ1 is typically meant to monitor a 0.8 V rail with ±2% voltage threshold hysteresis. For the
reset signal to become deasserted, VMON would need to go above VIT- + VHYS. For this example,
VMON = 11.016 V when the reset signal becomes deasserted.
There are inaccuracies that must be taken into consideration while adjusting voltage thresholds. Aside from the
tolerance of the resistor divider, there is an internal resistance of the SENSE pin that may affect the accuracy of
the resistor divider. Although expected to be very high impedance, users are recommended to calculate the
values for the design specifications. The internal SENSE resistance RSENSE can be calculated by the SENSE
voltage VSENSE divided by the SENSE current ISENSE as shown in 方程式 16. VSENSE can be calculated using 方
程式12 depending on the resistor divider and monitored voltage. ISENSE can be calculated using 方程式15.
ISENSE = [(VMON - VSENSE) ÷ R1] - (VSENSE ÷ R2)
(15)
(16)
RSENSE = VSENSE ÷ ISENSE
VMON
VMON
VDD
10 k
VDD
VDD
VDD
R3
R1
10 k
VSENSE1
SENSE1
SENSE2
RESET1
RESET2
VSENSE2
TPS38A-Q1
CTR1
CTR2
CTS1
CTS2
R2
R4
GND
图9-1. Adjustable Voltage Threshold with External Resistor Dividers
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9.2 Application Information
The following sections describe in detail how to properly use this device, depending on the requirements of the
final application.
9.3 Typical Application
9.3.1 Design 1: Automotive Off-Battery Monitoring
The initial power stage in automotive applications starts with the 12 V battery. Variation of the battery voltage is
common between 9 V and 16 V. Furthermore, if cold-cranking and load dump conditions are considered, voltage
transients can occur as low as 3 V and as high as 42 V. In this design example, we are highlighting the ability for
low power, direct off-battery voltage supervision. 图 9-2 illustrates an example of how the TPS38-Q1 is
monitoring the battery voltage while being powered by it as well. For more information, read this application
report on how to achieve low IQ voltage supervision in automotive, wide-VIN applications.
Low Iq, No external
resistors needed
DC/DC
MCU
VDD
VDD
GPIO
MCU Flag
RESET1
TPS38-Q1
RESET2
SENSE1
GND
SENSE2
GND
Enable
Boost
Backup
Vba
Boost
Converter
图9-2. Fast Start Supervisor with Direct Off-Battery Monitoring
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9.3.1.1 Design Requirements
This design requires voltage supervision on a 12-V power supply voltage rail with possibility of the 12-V rail rising
up as high as 42 V. The undervoltage fault occurs when the power supply voltage drops below 7.7 V.
PARAMETER
Power Rail Voltage Supervision
Maximum Input Power
Output logic voltage
DESIGN REQUIREMENT
DESIGN RESULT
TPS38-Q1 provides voltage monitoring with 1.5%
max accuracy with adjustable/non-adjustable
variations.
Monitor 12 V power supply for undervoltage
condition, trigger a undervoltage fault at 7.7 V.
Operate with power supply input up to 42 V.
Open-Drain Output Topology
The TPS38-Q1 can support a VDD of up to 65 V.
An open-drain output is recommended to provide
the correct reset signal, but a push-pull can also be
used.
TPS38-Q1 allows for IQ to remain low with support
of up to 65 V. This allows for no external resistor
divider to be required.
Maximum system current
consumption
2 µA max when power supply is at 12 V typical
Maximum voltage monitor accuracy of 1.5%.
The TPS38-Q1 has 1.5% maximum voltage
monitor accuracy.
Voltage Monitor Accuracy
Delay when returning from fault
condition
RESET delay of at least 420 ms when returning
from a undervoltage fault.
CCTR = 0.33 µF sets 422 ms delay
9.3.1.2 Detailed Design Procedure
The primary advantage of this application is being able to directly monitor a voltage on an automotive battery
without needing external resistor dividers on the SENSEx inputs. This keeps the overall IQ of the design low
while still achieving the desired rail monitoring.
As shown in 图9-2, rail monitoring is done by connecting SENSE1 and SENSE2 inputs directly to the battery rail
after the TVS protection diodes. The TPS38-Q1 that is being used in this example is a fixed voltage variant
where SENSE1 and SENSE 2 threshold voltages have been set internally by the factory. Word of caution, the
TVS protection diodes must be chosen such that the transient voltages on the monitored rails do not exceed the
absolute max limit listed in 节7.1.
To use this configuration, the specific voltage threshold variation of the device must be chosen according to the
application. In this configuration, the '77' variation must be chosen for 7.7 V as shown in 表12-1.
The device being able to handle 65 V on VDD means the monitored voltage rail can go as high as 42 V for the
application transients and not violate the recommended maximum for the supervisor as it usually would. This is
useful when monitoring a voltage rail that has a wide range that may go much higher than the nominal rail
voltage such as in this case. Good design practice recommends using a 0.1 µF capacitor on the VDD pin and
this capacitance may need to increase if using an adjustable version with a resistor divider.
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9.3.1.3 Application Curves
V_SENSE
RESET_B
图9-3. Undervoltage Reset Waveform
V_SENSE
RESET_B
图9-4. Undervoltage Recovery Waveform
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10 Power Supply Recommendations
These devices are designed to operate from an input supply with a voltage range between 1.4 V (VPOR) to 65 V
(max operation). Good analog design practice recommends placing a minimum 0.1 µF ceramic capacitor as near
as possible to the VDD pin.
10.1 Power Dissipation and Device Operation
The permissible power dissipation for any package is a measure of the capability of the device to pass heat from
the power source, the junctions of the IC, to the ultimate heat sink, the ambient environment. Thus, the power
dissipation is dependent on the ambient temperature and the thermal resistance across the various interfaces
between the die junction and ambient air.
The maximum continuous allowable power dissipation for the device in a given package can be calculated using
方程式17:
PD-MAX = ((TJ-MAX –TA) / RθJA
)
(17)
(18)
The actual power being dissipated in the device can be represented by 方程式18:
PD = VDD × IDD+pRESET
pRESET is calculated by 方程式19 or 方程式20
pRESET (PUSHPULL) = VDD - VRESET x IRESET
pRESET (OPEN-DRAIN) = VRESET x IRESET
(19)
(20)
方程式 17 and 方程式 18 establish the relationship between the maximum power dissipation allowed due to
thermal consideration, the voltage drop across the device, and the continuous current capability of the device.
These two equations should be used to determine the optimum operating conditions for the device in the
application.
In applications where lower power dissipation (PD) and/or excellent package thermal resistance (RθJA) is
present, the maximum ambient temperature (TA-MAX) may be increased.
In applications where high power dissipation and/or poor package thermal resistance is present, the maximum
ambient temperature (TA-MAX) may have to be de-rated. TA-MAX is dependent on the maximum operating junction
temperature (TJ-MAX-OP = 125°C), the maximum allowable power dissipation in the device package in the
application (PD-MAX), and the junction-to ambient thermal resistance of the part/package in the application
(RθJA), as given by 方程式21:
TA-MAX = (TJ-MAX-OP –(RθJA × PD-MAX))
(21)
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11 Layout
11.1 Layout Guidelines
• Make sure that the connection to the VDD pin is low impedance. Good analog design practice is to place a
greater than 0.1 µF ceramic capacitor as near as possible to the VDD pin.
• To further improve the noise immunity on the SENSEx pins, placing a 1 nF to 10 nF capacitor between the
SENSEx pins and GND can reduce the sensitivity to transient voltages on the monitored signal.
• If a capacitor is used on CTS1, CTS2, CTR1, or CTR2, place these components as close as possible to the
respective pins. If the capacitor adjustable pins are left unconnected, make sure to minimize the amount of
parasitic capacitance on the pins to less than 5 pF.
• For open-drain variants, place the pull-up resistors on RESET1 and RESET2 pins as close to the pins as
possible.
• When laying out metal traces, separate high voltage traces from low voltage traces as much as possible. If
high and low voltage traces need to run close by, spacing between traces should be greater than 20 mils
(0.5 mm).
• Do not have high voltage metal pads or traces closer than 20 mils (0.5 mm) to the low voltage metal pads or
traces.
11.2 Layout Example
The DSK layout example in 图 11-1 shows how the TPS38-Q1 is laid out on a printed circuit board (PCB) with
user-defined delays.
CVDD
VDD
1
2
3
10
9
GND
Monitored Voltage
Monitored Voltage
CSENSE1
TPS38-Q1
8
CSENSE2
DSK Package
GND
4
5
7
6
Overvoltage Flag
Undervoltage Flag
RPU1
RPU2
VPULL-UP
VPULL-UP
Vias used to connect pins for application-specific connections
图11-1. TPS38-Q1 DSK Package Recommended Layout
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The DYY layout example in 图 11-2 shows how the TPS38-Q1 is laid out on a printed circuit board (PCB) with
user-defined delays.
CVDD
VDD
1
2
3
14
13
12
NC
NC
NC
GND
TPS38-Q1
Monitored Voltage
Monitored Voltage
DYY Package
4
5
6
7
11
10
9
CSENSE1
CSENSE2
GND
Overvoltage Flag
Undervoltage Flag
8
GND
RPU1
RPU2
VPULL-UP
VPULL-UP
Vias used to connect pins for application-specific connections
图11-2. TPS38-Q1 DYY Package Recommended Layout
11.3 Creepage Distance
Per IEC 60664 Creepage is the shortest distance between two conductive parts or as shown in 图 11-3 the
distance between high voltage conductive parts and grounded parts, the floating conductive part is ignored and
subtracted from the total distance.
a
b
A
C
B
图11-3. Creepage Distance
图11-3 details:
• A = Left pins (high voltage)
• B = Central pad (not internally connected, can be left floating or connected to GND)
• C = Right pins (low voltage)
• Creepage distance = a + b
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12 Device and Documentation Support
12.1 Device Nomenclature
节5 shows how to decode the function of the device based on its part number
表 12-1 shows TPS38-Q1 possible voltage options per channel. Contact TI sales representatives or on TI's E2E
forum for details and availability of other options; minimum order quantities apply.
表12-1. Voltage Options
100 mV STEPS
400 mV STEPS
500 mV STEPS
1 V STEPS
NOMEN-
CLATURE
VOLTAGE
OPTIONS
NOMEN-
CLATURE
VOLTAGE
OPTIONS
NOMEN-
CLATURE
VOLTAGE
OPTIONS
NOMEN-
CLATURE
VOLTAGE
OPTIONS
NOMEN-
CLATURE
VOLTAGE
OPTIONS
08
800 mV
(divider
bypass)
70
7.0 V
A0
10.4 V
D0
20.5 V
F0
31.0 V
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
2.7 V
2.8 V
2.9 V
3.0 V
3.1 V
3.2 V
3.3 V
3.4 V
3.5 V
3.6 V
3.7 V
3.8 V
3.9 V
4.0 V
4.1 V
4.2 V
4.3 V
4.4 V
4.5 V
4.6 V
4.7 V
4.8 V
4.9 V
5.0 V
5.1 V
5.2 V
5.3 V
5.4 V
5.5 V
5.6 V
5.7 V
5.8 V
5.9 V
6.0 V
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
00
7.1 V
7.2 V
7.3 V
7.4 V
7.5 V
7.6 V
7.7 V
7.8 V
7.9 V
8.0 V
8.1 V
8.2 V
8.3 V
8.4 V
8.5 V
8.6 V
8.7 V
8.8 V
8.9 V
9.0 V
9.1 V
9.2 V
9.3 V
9.4 V
9.5 V
9.6 V
9.7 V
9.8 V
9.9 V
10.0 V
A1
A2
A3
A4
A5
A6
A7
A8
A9
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
C0
C1
C2
C3
C4
10.8 V
11.2 V
11.6 V
12.0 V
12.4 V
12.8 V
13.2 V
13.6 V
14.0 V
14.4 V
14.8 V
15.2 V
15.6 V
16.0 V
16.4 V
16.8 V
17.2 V
17.6 V
18.0 V
18.4 V
18.8 V
19.2 V
19.6 V
20.0 V
D1
D2
D3
D4
D5
D6
D7
D8
D9
E0
E1
E2
E3
E4
E5
E6
E7
E8
E9
21.0 V
21.5 V
22.0 V
22.5 V
23.0 V
23.5 V
24.0 V
24.5 V
25.0 V
25.5 V
26.0 V
26.5 V
27.0 V
27.5 V
28.0 V
28.5 V
29.0 V
29.5 V
30.0 V
F1
F2
F3
F4
F5
32.0 V
33.0 V
34.0 V
35.0 V
36.0 V
Copyright © 2023 Texas Instruments Incorporated
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表12-1. Voltage Options (continued)
100 mV STEPS
400 mV STEPS
500 mV STEPS
1 V STEPS
NOMEN-
CLATURE
VOLTAGE
OPTIONS
NOMEN-
CLATURE
VOLTAGE
OPTIONS
NOMEN-
CLATURE
VOLTAGE
OPTIONS
NOMEN-
CLATURE
VOLTAGE
OPTIONS
NOMEN-
CLATURE
VOLTAGE
OPTIONS
61
62
63
64
65
66
67
68
69
6.1 V
6.2 V
6.3 V
6.4 V
6.5 V
6.6 V
6.7 V
6.8 V
6.9 V
12.2 接收文档更新通知
要接收文档更新通知,请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册,即可每周接收产品信息更
改摘要。有关更改的详细信息,请查看任何已修订文档中包含的修订历史记录。
12.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料,可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范,并且不一定反映 TI 的观点;请参阅
TI 的《使用条款》。
12.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
12.5 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序,可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级,大至整个器件故障。精密的集成电路可能更容易受到损坏,这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
12.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2023 Texas Instruments Incorporated
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13.1 Package Option Addendum
Packaging Information
Device
Package
Drawing
Package
Qty
Lead/Ball
Finish(6)
Op Temp
(°C)
Orderable Device
Status (1)
Package Type
Pins
Eco Plan (2)
MSL Peak Temp(3)
Marking(4)
(5)
TPS38B4848EEDSKRQ1
TPS38B5858FFDSKRQ1
RoHS & Green
RoHS & Green
2KCL
2KBL
PREVIEW
PREVIEW
SON
SON
DSK
DSK
10
10
3000
3000
NIPDAU
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PRE_PROD Unannounced device, not in production, not available for mass market, nor on the web, samples not available.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check www.ti.com/productcontent for the latest
availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the
requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified
lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used
between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by
weight in homogeneous material).
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the
finish value exceeds the maximum column width.
Important Information and Disclaimer: The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on
information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI
has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming
materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Copyright © 2023 Texas Instruments Incorporated
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Product Folder Links: TPS38-Q1
English Data Sheet: SNVSBI8
TPS38-Q1
www.ti.com.cn
ZHCSMU7D –AUGUST 2020 –REVISED JULY 2023
13.2 Tape and Reel Information
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
Reel
Diameter
(mm)
Reel
Width W1
(mm)
Package Package
A0
(mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
(mm)
Pin1
Quadrant
Device
Pins
SPQ
Type
Drawing
TPS38B4848EEDSKRQ1
TPS38B5858FFDSKRQ1
SON
SON
DSK
DSK
10
10
3000
3000
180.0
180.0
8.4
8.4
2.8
2.8
2.8
2.8
1.0
1.0
4.0
4.0
8.0
8.0
Q2
Q2
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TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
Device
Package Type
Package Drawing Pins
SPQ
Length (mm) Width (mm)
Height (mm)
TPS38B4848EEDSKRQ1
TPS38B5858FFDSKRQ1
SON
DSK
DSK
10
10
3000
210.0
210.0
185.0
185.0
35.0
SON
3000
35.0
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TPS38-Q1
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ZHCSMU7D –AUGUST 2020 –REVISED JULY 2023
13.3 Tray Information
L - Outer tray length without tabs
KO -
Outer
tray
height
W -
Outer
tray
width
Text
P1 - Tray unit pocket pitch
CW - Measurement for tray edge (Y direction) to corner pocket center
CL - Measurement for tray edge (X direction) to corner pocket center
Chamfer on Tray corner indicates Pin 1 orientation of packed units.
Max
Temp.
(Deg C)
Package Package
Type Name
Configurati Unit Array
on Matrix
CL
(mm)
Device
Pins
SPQ
L (mm)
W (mm) K0 (mm) P1 (mm)
CW (mm)
Copyright © 2023 Texas Instruments Incorporated
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PACKAGE OPTION ADDENDUM
www.ti.com
14-Jul-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS38A010122DSKRQ1
TPS38B4848EEDSKRQ1
TPS38B5858FFDSKRQ1
TPS38J010155DSKRQ1
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SON
SON
SON
SON
DSK
DSK
DSK
DSK
10
10
10
10
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
-40 to 125
2KJL
2KCL
2KBL
2KEL
Samples
Samples
Samples
Samples
NIPDAU
NIPDAU
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
14-Jul-2023
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TPS38-Q1 :
Catalog : TPS38
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS38A010122DSKRQ1
TPS38B4848EEDSKRQ1
TPS38B5858FFDSKRQ1
TPS38J010155DSKRQ1
SON
SON
SON
SON
DSK
DSK
DSK
DSK
10
10
10
10
3000
3000
3000
3000
180.0
180.0
180.0
180.0
8.4
8.4
8.4
8.4
2.8
2.8
2.8
2.8
2.8
2.8
2.8
2.8
1.0
1.0
1.0
1.0
4.0
4.0
4.0
4.0
8.0
8.0
8.0
8.0
Q2
Q2
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS38A010122DSKRQ1
TPS38B4848EEDSKRQ1
TPS38B5858FFDSKRQ1
TPS38J010155DSKRQ1
SON
SON
SON
SON
DSK
DSK
DSK
DSK
10
10
10
10
3000
3000
3000
3000
210.0
210.0
210.0
210.0
185.0
185.0
185.0
185.0
35.0
35.0
35.0
35.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
DSK 10
2.5 x 2.5 mm, 0.5 mm pitch
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4225304/A
PACKAGE OUTLINE
WSON - 0.8 mm max height
PLASTIC QUAD FLAT PACK- NO LEAD
DSK0010C
2.6
2.4
A
B
2.6
2.4
PIN 1 INDEX AREA
0.100 MIN
(0.13)
SECTION A-A
TYPICAL
0.8
0.7
C
SEATING PLANE
0.08 C
0.05
0.00
1.3
1.1
SYMM
(0.25) TYP
(0.2) TYP
8X 0.5
5
6
SYMM
A
A
2X
2
2.1
1.9
11
10
1
0.3
0.2
PIN 1 ID
(OPTIONAL)
10X
0.5
0.3
10X
0.1
C A B
C
0.05
4225178/A 09/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
WSON - 0.8 mm max height
DSK0010C
PLASTIC QUAD FLAT PACK- NO LEAD
(2.3)
(1.2)
10X (0.6)
10X (0.25)
10
1
8X
(0.5)
SYMM
(2)
11
2X
(2)
2X
(0.75)
(R0.05)
TYP
5
6
SYMM
(Ø0.2) VIA
TYP
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 20X
0.07 MAX
0.07 MIN
ALL AROUND
ALL AROUND
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4225178/A 09/2019
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
WSON - 0.8 mm max height
DSK0010C
PLASTIC QUAD FLAT PACK- NO LEAD
(2.3)
10X (0.6)
10X (0.25)
(1.13)
11
1
10
8X
(0.5)
SYMM
(1.79)
2X
(2)
(R0.05)
TYP
6
5
SYMM
METAL TYP
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
84% PRINTED COVERAGE BY AREA
SCALE: 20X
4225178/A 09/2019
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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