TPS3808E-Q1 [TI]
汽车类 600nA 超低静态电流可编程延迟监控电路;
| 型号： | TPS3808E-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 汽车类 600nA 超低静态电流可编程延迟监控电路 监控 |
| 文件： | 总21页 (文件大小：1218K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS3808E-Q1
ZHCSPW0 –APRIL 2023
TPS3808E-Q1 汽车级低静态电流、可编程延迟监控电路
1 特性
3 说明
• 上电复位发生器具有可调节延迟时间：1.25ms 至
10s
• 极低静态电流：0.6μA（典型值）
• 高阈值精度：1%（典型值）
• 提供适用于标准电压轨的0.9V 至5V 固定阈值电压
且可调节电压低至0.405 V
TPS3808E-Q1 系列微处理器监控电路可以监视 0.4V
至 5V 的系统电压，在 SENSE 电压降至低于预设阈值
时或手动复位 (MR) 引脚降为逻辑低电平时，发出开漏
RESET 信号。在 SENSE 电压和手动复位 (MR) 返回
至相应阈值以上之后，RESET 输出会在用户可调节延
迟时间内保持低电平。
• 手动复位(MR) 输入
• 漏极开路复位输出
• 温度范围：–40°C 至125°C
• 小型SOT-23-6
TPS3808E-Q1 器件采用精密基准，可实现 0.5% 的阈
值精度。通过断开 CT 引脚，可将复位延迟时间设置为
20ms；通过使用电阻将 CT 引脚连接至 VDD，可将复
位延迟时间设置为300ms，或通过将CT 引脚连接到外
部电容器，用户可在1.25ms 至10s 之间调整复位延迟
时间。TPS3808E 器件具有超低的典型静态电流，为
0.6μA，因此非常适合电池供电应用。TPS3808E-Q1
采用 SOT-23-6 封装，额定工作温度范围为 –40°C 至
125°C (TJ)。
2 应用
• ADAS 域控制器
• 汽车网关
• 汽车音响主机
• 数字驾驶舱处理单元
• 远程信息处理控制单元
• 驾驶员监控
器件信息
封装(1)
封装尺寸（标称值）
器件型号
TPS3808E
SOT-23 (6)
2.90mm x 1.60mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
1.2 V
3.3 V
VCORE
SENSE
SENSE
VDD
VIO
VDD
MCU
TPS3808EG33-Q1
MR
CT
TPS3808EG12-Q1
RESET
RESET
GPIO
CT
GND
GND
GND
GND
典型应用电路
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SBVS430
TPS3808E-Q1
ZHCSPW0 –APRIL 2023
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Table of Contents
9.4 Device Functional Modes..........................................12
10 Application and Implementation................................13
10.1 Application Information........................................... 13
10.2 Typical Application.................................................. 13
11 Power Supply Recommendations..............................14
12 Layout...........................................................................14
12.1 Layout Guidelines................................................... 14
12.2 Layout Example...................................................... 14
13 Device and Documentation Support..........................16
13.1 Device Support....................................................... 16
13.2 Documentation Support.......................................... 16
13.3 支持资源..................................................................16
13.4 Trademarks.............................................................16
13.5 静电放电警告.......................................................... 16
13.6 术语表..................................................................... 16
14 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Device Voltage Thresholds.............................................3
6 Pin Configuration and Functions...................................4
7 Specification.................................................................... 5
7.1 Absolute Maximum Ratings........................................ 5
7.2 ESD Ratings .............................................................. 5
7.3 Recommended Operating Conditions.........................5
7.4 Thermal Information....................................................5
7.5 Electrical Characteristics.............................................6
7.6 Timing Requirements..................................................7
8 Typical Characteristics................................................... 8
9 Detailed Description........................................................9
9.1 Overview.....................................................................9
9.2 Functional Block Diagram...........................................9
9.3 Feature Description.....................................................9
Information.................................................................... 16
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
DATE
REVISION
NOTES
April 2023
*
Initial Release
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5 Device Voltage Thresholds
The following table shows the nominal rail to be monitored and the corresponding threshold voltage of the
device.
PART NUMBER
TPS3808EG01
TPS3808EG09
TPS3808EG12
TPS3808EG125
TPS3808EG15
TPS3808EG18
TPS3808EG19
TPS3808EG25
TPS3808EG30
TPS3808EG33
TPS3808EG50
NOMINAL SUPPLY VOLTAGE
THRESHOLD VOLTAGE (VIT)
Adjustable
0.9 V
1.2 V
1.25 V
1.5 V
1.8 V
1.9 V
2.5 V
3 V
0.405 V
0.84 V
1.12 V
1.16 V
1.40 V
1.67 V
1.77 V
2.33 V
2.79 V
3.07 V
4.65 V
3.3 V
5 V
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6 Pin Configuration and Functions
VDD
1
2
3
6
5
4
RESET
GND
MR
SENSE
CT
图6-1. DBV Package
6-Pin SOT-23
Top View
表6-1. Pin Functions
PIN
I/O
DESCRIPTION
NAME
SOT-23
Reset period programming pin. Connecting this pin to VDD through a 40-kΩ to 200-kΩ resistor or
leaving it open results in fixed delay times. Connecting this pin to a ground referenced capacitor ≥
130 pF gives a user-programmable delay time.
CT
4
I
GND
MR
2
3
Ground
—
Driving the manual reset pin ( MR) low asserts RESET. MR is internally tied to VDD by a 90-kΩ
pull-up resistor.
I
RESET is an open-drain output that is driven to a low-impedance state when RESET is asserted
(either the SENSE input is lower than the threshold voltage (VIT) or the MR pin is set to a logic
low). RESET remains low (asserted) for the reset period after both SENSE is above VIT and MR is
set to a logic high. A pull-up resistor from 10 kΩ to 1 MΩ should be used on this pin, and allows the
RESET
1
O
reset pin to attain voltages higher than VDD
.
This pin is connected to the voltage to be monitored. If the voltage at this terminal drops below the
threshold voltage VIT, then RESET is asserted.
SENSE
VDD
5
6
I
I
Supply voltage. For good analog design, place a 0.1-μF ceramic capacitor close to this pin.
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7 Specification
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX UNIT
Voltage
Current
VDD, VCT, VRESET, VMR, VSENSE
IRESET
6.5
±40
150
150
150
V
mA
°C
°C
°C
–0.3
Operating junction temperature, TJ
Operating free-air temperature, TA
Storage temperature, Tstg
-40
-40
-65
Temperature (2)
(1) Stresses beyond values listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) As a result of the low dissipated power in this device, it is assumed that TJ = TA.
7.2 ESD Ratings
VALUE UNIT
Human body model (HBM), per AEC Q100-002(1)
Charged device model (CDM), per AEC Q100-011
±2000
V
±1000
V(ESD) Electrostatic discharge
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
7.3 Recommended Operating Conditions
MIN
1.7
0
NOM
MAX
6
UNIT
V
VDD
Supply pin voltage
VSENSE
VCT
Input pin voltage
6
V
CT pin voltage ((1))
VDD
6
V
VMR
MR pin Voltage (2)
0
0
V
VRESET
IRESET
TJ
Output pin voltage
6
V
Output pin current
0
10
125
mA
℃
Junction temperature (free-air temperature)
-40
(1) CT pin connected to VDD pin requires a pullup resistor; 40 kΩ is recommended.
(2) If the logic signal driving MR is less than VDD, then additional current flows into VDD and out of MR.
7.4 Thermal Information
TPS3808-Q1
DBV (SOT23-6)
THERMAL METRIC(1)
UNIT
6 PINS
180.9
117.8
27.8
RθJA
RθJC(top)
RθJB
ΨJT
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
Junction-to-top characterization parameter
Junction-to-board characterization parameter
18.9
27.3
ΨJB
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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7.5 Electrical Characteristics
At 1.7 V ≤VDD ≤6 V,CT = MR = Open, RESET Voltage (VRESET) = 100 kΩto VDD, RESET load = 50 pF, and over the
operating free-air temperature range of –40°C to 125°C, unless otherwise noted. Typical values are at TJ = 25°C.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VDD
Supply Voltage
1.7
6
V
VPOR
VIT-(UV)
VIT-(UV)
VHYS
Power on reset voltage(2)
Negative-going threshold accuracy
Negative-going threshold accuracy
Hysteresis Voltage(1)
VOL(max) = 0.25 V, IOUT = 15 µA
Fixed threshold TPS3808EG01
1
V
-2
±1
±0.5
1
2
%
-1.5
1.5
2.5
2.5
%
Fixed Vth
%
VHYS
Hysteresis Voltage((1))
Adjustable Vth
VDD = 3.3 V
1
%
IDD
IDD
Supply current
Supply current
0.6
0.6
1.5
1.5
µA
µA
VDD = 6 V
ISENSE
ISENSE
VOL
Input current, SENSE pin
Input current, SENSE pin
Low level output voltage
Open drain output leakage current
MR logic low input
VSENSE = VIT, TPS3808EG01
VSENSE = 6 V, Fixed Versions
1.7 V ≤VDD < 6 V, IOUT = 1 mA
VDD = VRESET = 6 V
-25
25
1.25
nA
µA
mV
nA
V
0.75
400
ILKG
300
VMR_L
VMR_H
RMR
0.3 VDD
MR logic high input
0.7 VDD
TBD
V
Manual reset Internal pullup resistance
90
TBD
KΩ
(1) Hysteresis is with respect of the tripoint (VIT-(UV), VIT+(OV)).
(2) VPOR is the minimum VDD voltage level for a controlled output state.
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7.6 Timing Requirements
At 1.7 V ≤VDD ≤6 V, CT = MR = Open, RESET Voltage (VRESET) = 100 kΩto VDD, RESET load = 50 pF, and over the
operating free-air temperature range of –40°C to 125°C, unless otherwise noted. Typical values are at TJ = 25°C.
MIN
NOM
MAX UNIT
tD
Reset time delay
CT = Open
CT = VDD
12
20
28
420
ms
ms
ms
s
tD
Reset time delay
180
0.75
300
1.25
0.83
30
tD
Reset time delay
CT = 130 pF
CT = 150 nF
1.75
tD
Reset time delay
tPD
Propagation detect delay(1) (2)
Startup delay(3)
50
µs
µs
µs
ns
ns
tSD
300
5
tGI (VIT-)
tGI (MR)
tPD (MR)
Glitch Immunity undervoltage VIT-(UV), 5% Overdrive(1)
Glitch Immunity MR pin
50
Propagation delay from MR low to assert RESET
500
(1) 5% Overdrive from threshold. Overdrive % = [VSENSE - VIT] / VIT; Where VIT stands for VIT-(UV) or VIT+(OV)
(2) tPD measured from threhold trip point (VIT-(UV) or VIT+(OV)) to RESET VOL voltage
(3) During the power-on sequence, VDD must be at or above VDD (MIN) for at least tSD + tD before the output is in the correct state.
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8 Typical Characteristics
At TJ = 25°C, VDD = 3.3 V, RLRESET = 100 kΩ, and CLRESET = 50 pF, unless otherwise noted.
100
10
−40°C, +25°C, +125°C
1
0.1
0.01
0.001
0.0001
0.001
0.01
0.1
1
10
m
CT ( F)
图8-1. RESET Time-Out Period vs CT
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9 Detailed Description
9.1 Overview
The TPS3808E-Q1 microprocessor supervisory product family is designed to assert a RESET signal when either
the SENSE pin voltage drops below VIT or the manual reset ( MR) is driven low. The RESET output remains
asserted for a user-adjustable time after both the manual reset ( MR) and SENSE voltages return above their
respective thresholds.
9.2 Functional Block Diagram
VDD
VDD
RESET
90 k
MR
Reset
Logic
Timer
GND
CT
SENSE
–
+
0.4 V
VREF
GND
Adjustable-Voltage Version
VDD
VDD
90 k
RESET
MR
SENSE
Reset
Logic
Timer
R1
R2
CT
–
+
0.4 V
VREF
GND
Fixed-Voltage Version
9.3 Feature Description
A broad range of voltage threshold and reset delay time adjustments are available for the TPS3808E-Q1 device,
allowing these devices to be used in a wide array of applications. Reset threshold voltages can be factory-set
from 0.82 V to 3.3 V or from 4.4 V to 5 V, while the adjustable variant can be set to any voltage above 0.405 V
using an external resistor divider. Two preset delay times are also user-selectable: connecting the CT pin to VDD
results in a 300-ms reset delay, whereas leaving the CT pin open yields a 20-ms reset delay. In addition,
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connecting a capacitor between CT and GND allows the designer to select any reset delay period from 1.25 ms
to 10 s.
9.3.1 SENSE Input
The SENSE input provides a pin at which any system voltage can be monitored. If the voltage on this pin drops
below VIT, then RESET is asserted. The comparator has a built-in hysteresis to ensure smooth RESET
assertions and de-assertions. It is good analog design practice to put a 1-nF to 10-nF bypass capacitor on the
SENSE input to reduce sensitivity to transients and layout parasitics.
The TPS3808E-Q1 device is relatively immune to short negative transients on the SENSE pin. Sensitivity to
transients is dependent on threshold overdrive.
The adjustable variant can be used to monitor any voltage rail down to 0.405 V using the circuit shown in 图9-1.
VOUT
VIN
VDD
R1
R2
VIT’
V
R1
R2
TPS3808EG01-Q1
SENSE
RESET
1 nF
GND
图9-1. Using the TPS3808EG01-Q1 to Monitor a User-Defined Threshold Voltage
9.3.2 Selecting the RESET Delay Time
The TPS3808E-Q1 has three options for setting the RESET delay time as shown in 图 9-2. 图 9-2 (a) shows the
configuration for a fixed 300-ms typical delay time by tying CT to VDD; a resistor from 40 kΩ to 200 kΩ must be
used. Supply current is not affected by the choice of resistor. 图 9-2 (b) shows a fixed 20-ms delay time by
leaving the CT pin open. 图 9-2 (c) shows a ground referenced capacitor connected to CT for a user-defined
program time between 1.25 ms and 10 s.
3.3 V
3.3 V
3.3 V
VDD
VDD
VDD
SENSE
SENSE
SENSE
50 k
TPS3808E-Q1
TPS3808E-Q1
TPS3808E-Q1
CT
CT
RESET
RESET
CT
RESET
CT
GND
GND
GND
CT (nF)
175
20 ms Delay
Delay (s) =
+ 0.5 x 10-3 (s)
300 ms Delay
(a)
(b)
(C)
图9-2. Configuration Used to Set the RESET Delay Time
The capacitor CT should be ≥ 100 pF nominal value in order for the TPS3808Exxx to recognize that the
capacitor is present. The capacitor value for a given delay time can be calculated using 方程式1.
t (s) 0.5 × 10 3 (s) × 175
–
D
-
CT (nF)
=
[
]
(1)
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The reset delay time is determined by the time it takes an on-chip precision 220-nA current source to charge the
external capacitor to the internal threshold. When a RESET is asserted, the capacitor is discharged. When the
RESET conditions are cleared, the internal current source is enabled and begins to charge the external
capacitor. When the voltage on this capacitor reaches higher than the internal threshold, RESET is deasserted.
Note that a low-leakage type capacitor such as a ceramic should be used, and that stray capacitance around
this pin may cause errors in the reset delay time.
9.3.3 Manual RESET ( MR) Input
The manual reset ( MR) input allows a processor or other logic circuits to initiate a reset. A logic low (0.3 VDD) on
MR causes RESET to assert. After MR returns to a logic high and SENSE is above its reset threshold, RESET is
de-asserted after the user-defined reset delay expires. Note that MR is internally tied to VDD using a 90-kΩ
resistor, so this pin can be left unconnected if MR is not used.
See 图 9-3 for how MR can be used to monitor multiple system voltages. Note that if the logic signal driving MR
does not go fully to VDD, there is some additional current draw into VDD as a result of the internal pullup resistor
on MR. To minimize current draw, a logic-level FET can be used as illustrated in 图9-4.
1.2 V
3.3 V
VCORE
SENSE
SENSE
VDD
VIO
VDD
MCU
TPS3808EG33-Q1
MR
CT
TPS3808EG12-Q1
RESET
RESET
GPIO
CT
GND
GND
GND
GND
图9-3. Using MR to Monitor Multiple System Voltages
VDD
SENSE
90 kΩ
MR
RESET
TPS3808E-Q1
图9-4. Using an External MOSFET to Minimize IDD When MR Signal Does Not Go to VDD
9.3.4 RESET Output
RESET remains high (unasserted) as long as SENSE is above its threshold (VIT) and the manual reset ( MR) is
logic high. If either SENSE falls below VIT or MR is driven low, RESET is asserted, driving the RESET pin to a
low impedance.
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Once MR is again logic high and SENSE is above VIT + VHYS (the threshold hysteresis), a delay circuit is
enabled that holds RESET low for a specified reset delay period. Once the reset delay has expired, the RESET
pin goes to a high impedance state. The pullup resistor from the open-drain RESET to the supply line can be
used to allow the reset signal for the microprocessor to have a voltage higher than VDD (up to 6 V). The pullup
resistor should be no smaller than 10 kΩ as a result of the finite impedance of the RESET line.
9.4 Device Functional Modes
表9-1. Truth Table
MR
L
SENSE > VIT
RESET
0
1
0
1
L
L
L
H
L
H
H
9.4.1 Normal Operation (VDD > VDD(min)
)
When VDD is greater than VDD(min), the RESET signal is determined by the voltage on the SENSE pin and the
logic state of MR.
• MR high: When the voltage on VDD is greater than 1.7 V for a time of the selected tD, the RESET signal
corresponds to the voltage on SENSE relative to VIT.
• MR low: in this mode, RESET is held low regardless of the value of the SENSE pin.
9.4.2 Above Power-On Reset but Less Than VDD(min) (VPOR < VDD < VDD(min)
)
When the voltage on VDD is less than the device VDD(min) voltage, and greater than the power-on reset voltage
(VPOR), the RESET signal is asserted and low impedance, respectively, regardless of the voltage on the SENSE
pin.
9.4.3 Below Power-On Reset (VDD < VPOR
)
When the voltage on VDD is lower than the required voltage (VPOR) needed to internally pull the asserted output
to GND, RESET is undefined and should not be relied upon for proper device function.
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10 Application and Implementation
备注
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
10.1 Application Information
The following sections describe in detail how to properly use this device, depending on the requirements of the
final application.
10.2 Typical Application
A typical application of the TPS3808E-Q1 used with a 3.3-V processor is shown in 图 10-1. The open-drain
RESET output is typically connected to the RESET input of a microprocessor. A pullup resistor must be used to
hold this line high when RESET is not asserted. The RESET output is undefined for voltage below 0.8 V, but this
characteristic is normally not a problem because most microprocessors do not function below this voltage.
3.3V
VDD
SENSE
VDD
VIO
MCU
TPS3808EG33-Q1
MR
CT
RESET
GPIO
GND
GND
GND
图10-1. Typical Application of the TPS3808E-Q1 With an C2000 Processor
10.2.1 Design Requirements
The TPS3808E-Q1 is intended to drive the RESET input of a microprocessor. The RESET pin is pulled high with
a 100-kΩ resistor and the reset delay time is controlled by CT depending on the reset requirement times of the
microprocessor. In this case, CT is left open for a typical reset delay time of 20 ms.
10.2.2 Detailed Design Procedure
The primary constraint for this application is the reset delay time. In this case, because CT is open, it is set to
20 ms. A 0.1-µF decoupling capacitor is connected to the VDD pin and a 100-kΩ resistor is used to pull up the
RESET pin high. The MR pin can be connected to an external signal if desired.
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10.2.2.1 Immunity to SENSE Pin Voltage Transients
The TPS3808E-Q1 is relatively immune to short negative transients on the SENSE pin. Sensitivity to transients
depends on threshold overdrive. Threshold overdrive is defined by how much the VSENSE exceeds the specified
threshold, and is important to know because the smaller the overdrive, the slower the RESET response.
Threshold overdrive is calculated as a percent of the threshold in question, as shown in 方程式2:
Overdrive = | (VSENSE / VIT –1) × 100% |
(2)
where:
• VIT is the threshold voltage.
11 Power Supply Recommendations
These devices are designed to operate from an input supply with a voltage range between 1.7 V and 6. V. Use a
low-impedance power supply to eliminate inaccuracies caused by current changes during the voltage reference
refresh.
12 Layout
12.1 Layout Guidelines
Make sure the connection to the VDD pin is low impedance. Place a 0.1-µF ceramic capacitor near the VDD pin. If
no capacitor is connected to the CT pin, parasitic capacitance on this pin should be minimized so the RESET
delay time is not adversely affected.
12.2 Layout Example
The layout example in 图12-1 shows how the TPS3808E-Q1 is laid out on a printed circuit board (PCB) for a 20-
ms delay.
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SBVS430
14
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TPS3808E-Q1
ZHCSPW0 –APRIL 2023
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VDD
RESET
GND
VDD
SENSE
CT
CIN
MR
GND
Vias used to connect pins for application-specific connections
图12-1. Layout Example for a 20-ms Delay
Copyright © 2023 Texas Instruments Incorporated
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English Data Sheet: SBVS430
TPS3808E-Q1
ZHCSPW0 –APRIL 2023
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13 Device and Documentation Support
13.1 Device Support
13.1.1 Development Support
13.1.1.1 Evaluation Modules
An evaluation module (EVM) is available to assist in the initial circuit performance evaluation using the
TPS3808E-Q1. The TPS3808EG01DBVEVM evaluation module can be requested at the Texas Instruments
website through the product folders or purchased directly from the TI eStore and is compatable with the
TPS3808E-Q1. TPS3808E-Q1 sampled should be ordered and used to replace the existing TPS3808 device for
testing.
13.2 Documentation Support
13.2.1 Related Documentation
The following related documents are available for download at www.ti.com:
• Application note. Optimizing Resistor Dividers at a Comparator Input. Literature number SLVA450.
• Application note. Sensitivity Analysis for Power Supply Design. Literature number SLVA481.
• TPS3808EG01DBVEVM Evaluation Module User Guide. Literature number SBVU015.
13.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
13.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
13.5 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
13.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most-
current data available for the designated devices. This data is subject to change without notice and without
revision of this document. For browser-based versions of this data sheet, see the left-hand navigation pane.
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SBVS430
16
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PACKAGE OPTION ADDENDUM
www.ti.com
23-Apr-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
PTPS3808EG01DBVQ1
ACTIVE
SOT-23
DBV
6
3000
TBD
Call TI
Call TI
-40 to 125
Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OUTLINE
DBV0006A
SOT-23 - 1.45 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
0.1 C
1.75
1.45
B
1.45 MAX
A
PIN 1
INDEX AREA
1
2
6
5
2X 0.95
1.9
3.05
2.75
4
3
0.50
6X
0.25
C A B
0.15
0.00
0.2
(1.1)
TYP
0.25
GAGE PLANE
0.22
0.08
TYP
8
TYP
0
0.6
0.3
TYP
SEATING PLANE
4214840/C 06/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Body dimensions do not include mold flash or protrusion. Mold flash and protrusion shall not exceed 0.25 per side.
4. Leads 1,2,3 may be wider than leads 4,5,6 for package orientation.
5. Refernce JEDEC MO-178.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0006A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
6X (1.1)
1
6X (0.6)
6
SYMM
5
2
3
2X (0.95)
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214840/C 06/2021
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0006A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
6X (1.1)
1
6X (0.6)
6
SYMM
5
2
3
2X(0.95)
4
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214840/C 06/2021
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
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Copyright © 2023，德州仪器 (TI) 公司
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