TPS3850_技术文档

TPS3850

ZHCSFP2B –OCTOBER 2016 –REVISED SEPTEMBER 2021

TPS3850 具备可编程窗口看门狗定时器的高精度电压监控器

1 特性

3 说明

• 输入电压范围：VDD = 1.6V 至6.5V

• 0.8% 电压阈值精度

• 低电源电流：I_DD= 10µA（典型值）

• 用户可编程看门狗超时

• 用户可编程复位延迟

• 出厂编程的精密看门狗和复位计时器

• 开漏输出

• 精密过压和欠压监测：

TPS3850 将精密监控器与一个可编程窗口看门狗定时

器相结合。TPS3850 窗口比较器在 SENSE 引脚上可

针对过压 (V_IT+(OV)) 和欠压 (V_IT–(UV)) 阈值实现 0.8%

的精度（–40°C 至 +125°C）。此外，TPS3850 针对

两阈值施加精确迟滞，使得该器件非常适用于容差要求

严格的系统。该监控器的 RESET 延迟可通过经出厂编

程的默认延迟设置进行设定，也可以通过外部电容以编

程方式设定。出厂编程的 RESET 延迟具备 9.5% 精

度、高精密延迟时间。

– 支持0.9V 到5.0V 常见电压轨

– 提供±4% 和±7% 故障窗口

– 0.5% 迟滞

TPS3850 具备适用于多种应用的可编程窗口看门狗计

时器。专用看门狗输出 (WDO) 有助于提高分辨率，从

而帮助确定出现故障情况的根本原因。窗口看门狗超时

可通过经出厂编程的默认延迟设置进行设定，也可以通

过外部电容以编程方式设定。可通过逻辑引脚禁用看门

狗，避免在开发过程中出现意外的看门狗超时。

• 看门狗禁用功能

• 采用小型3mm × 3mm 10 引脚VSON 封装

• 结工作温度范围：

–40°C 至+125°C

2 应用

TPS3850 采用小型3.00mm ×

3.00mm 10 引脚VSON 封装。

• 超声波扫描仪

• 存储区域网络

• 有源天线系统mMIMO (AAS)

• 机器人伺服驱动器

• 输液泵

器件信息

封装⁽¹⁾

封装尺寸（标称值）

器件型号

TPS3850

VSON (10)

3.00mm × 3.00mm

• HVAC 控制器

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

0.5

1.8V

1.2V

Unit 1

Unit 2

Unit 3

Unit 4

Unit 5

Average

0.3

0.1

TPS3850

V_CORE

Microcontroller

RESET

V_I/O

SENSE

SET1

VDD

RESET

WDO

NMI

SET0

-0.1

-0.3

-0.5

CRST

CWD

WDI

GND

GPIO

GND

-50

-25

0

25

50

75

100

125

全集成微控制器监控电路

Temperature (èC)

过压阈值(V_IT+(OV)) 精度与温度间的关系

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SBVS301

TPS3850

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ZHCSFP2B –OCTOBER 2016 –REVISED SEPTEMBER 2021

Table of Contents

7.4 Device Functional Modes..........................................22

8 Application and Implementation..................................23

8.1 Application Information............................................. 23

8.2 Typical Applications.................................................. 29

9 Power Supply Recommendations................................35

10 Layout...........................................................................36

10.1 Layout Guidelines................................................... 36

10.2 Layout Example...................................................... 36

11 Device and Documentation Support..........................37

11.1 Device Support........................................................37

11.2 Documentation Support.......................................... 37

11.3 接收文档更新通知................................................... 37

11.4 支持资源..................................................................37

11.5 Trademarks............................................................. 37

11.6 Electrostatic Discharge Caution..............................37

11.7 术语表..................................................................... 37

12 Mechanical, Packaging, and Orderable

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................4

6 Specifications.................................................................. 5

6.1 Absolute Maximum Ratings........................................ 5

6.2 ESD Ratings............................................................... 5

6.3 Recommended Operating Conditions.........................5

6.4 Thermal Information....................................................6

6.5 Electrical Characteristics.............................................6

6.6 Timing Requirements..................................................7

6.7 Timing Diagrams.........................................................8

6.8 Typical Characteristics.............................................. 11

7 Detailed Description......................................................14

7.1 Overview...................................................................14

7.2 Functional Block Diagrams....................................... 14

7.3 Feature Description...................................................15

Information.................................................................... 38

4 Revision History

注：以前版本的页码可能与当前版本的页码不同

Changes from Revision A (November 2016) to Revision B (September 2021)

Page

• 更新了整个文档中的表格、图和交叉参考的编号格式.........................................................................................1

• 删除了“±15% 的WDT 和RST 延迟”..............................................................................................................1

• 更新了“应用”以包括网站链接......................................................................................................................... 1

• 添加了“在SENSE 引脚上”............................................................................................................................. 1

• Changed V_ESDvalues to ±4000 V and ±1000 V................................................................................................. 5

• Changed I_CWDmin and max spec ......................................................................................................................6

• Changed V_CWDmin and max spec .................................................................................................................... 6

• Added a footnote to for t_INIT............................................................................................................................... 7

• Changed minimum and maximum specifications of 2nd, 5th, 6th, and 8th rows of t_WDLparameter ................. 7

• Changed minimum and maximum specifications of 2nd and last rows of t_WDUparameter ............................... 7

• Added new section "Disabling the Watchdog Timer When Using the CRST Capacitor".................................. 18

• Changed 0.000381 to 0.000324 and 0.000438 in Equation 4 and Equation 5, respectively............................24

• Changed minimum and maximum specifications in 100 pF and 1 nF rows of Reset Delay Time for Common

Ideal Capacitor Values table.............................................................................................................................24

• Changed minimum and maximum specifications for NC SETx 01 setting for both upper and lower watchdog

boundaries, 10 kΩto VDD SETx 00 and 01 settings for lower watchdog boundary, and 10 kΩto VDD SETx

11 setting for both upper and lower watchdog boundaries in Factory-Programmed Watchdog Timing table...25

• Changed minimum and maximum limits on t_WDUand added explanation. ......................................................25

• Changed 0.000381 to 0.000324 in Equation 11............................................................................................... 30

• Changed description of factory-programmed timing options and values of t_WDL(max)and t_WDU(min)in Setting

the Watchdog Window section..........................................................................................................................30

• Changed 0.85 to 0.905 in Equation 14............................................................................................................. 33

• Changed Equation 17 and Equation 18 so that I_SENSEis no longer in the denominator.................................. 34

Changes from Revision * (October 2016) to Revision A (November 2016)

Page

• Changed units in I_SENSEparameter and footnote 1 in Electrical Characteristics table ...................................... 6

• Added correct operation state to Figure 2 ......................................................................................................... 7

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• Changed Figure 3 so the SET pins do not bring the watchdog into the disabled state before going to the 1:2

ratio.....................................................................................................................................................................7

• Changed Figure 11 so it no longer has VDD and V_SENSEtied together ...........................................................11

• Changed Figure 26 so it no longer goes through watchdog disabled...............................................................18

• Added correct operation state to Figure 27 ..................................................................................................... 20

• Changed RESET to WDO in description of WDO assertion in WDO Functionality section .............................21

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5 Pin Configuration and Functions

VDD

CWD

SET0

CRST

GND

1

2

3

4

5

10

9

SENSE

RESET

WDO

Thermal

Pad

8

7

WDI

6

SET1

Not to scale

图5-1. DRC Package: TPS3850

3-mm × 3-mm VSON-10

Top View

表5-1. Pin Functions

NO.

DESCRIPTION

NAME

I/O

Programmable reset timeout pin. Connect a capacitor between this pin and GND to program the reset timeout

period. This pin can also be connected by a 10-kΩpullup resistor to VDD, or left unconnected (NC) for various

factory programmed reset timeout options; see the 节8.1.1 section.

CRST

4

I

When using an external capacitor, use 方程式3 to determine the reset timeout.

Programmable watchdog timeout input. Watchdog timeout is set by connecting a capacitor between this pin

and ground. Furthermore, this pin can also be connected by a 10-kΩresistor to VDD, or leaving unconnected

(NC) further enables the selection of the preset watchdog timeouts; see the 节6.6 table.

When using a capacitor, the TPS3850 determines the window watchdog upper boundary with 方程式6. The

lower watchdog boundary is set by the SET pins, see 表8-5 and the 节8.1.2 section for additional information.

CWD

GND

2

5

I

Ground pin

—

Reset output. Connect RESET using a 1-kΩto 100-kΩresistor to VDD. RESET goes low when the voltage at

the SENSE pin goes below the undervoltage threshold (V_IT-(UV)) or above the overvoltage threshold (V_IT+(OV)).

When the voltage level at the SENSE pin is within the normal operating range, the RESET timeout counter

starts. At timer completion, RESET goes high. During startup, the state of RESET is undefined below the

specified power-on reset voltage (V_POR). Above V_POR, RESET goes low and remains low until the monitored

voltage is within the correct operating range (between V_IT-(UV)and V_IT(+OV)) and the RESET timeout is

complete.

RESET

9

O

SENSE

SET0

10

3

I

SENSE input to monitor voltage rail. Connect this pin to the supply rail that must be monitored.

Logic input. SET0, SET1, and CWD select the watchdog window ratios, timeouts, and disable the watchdog;

see the 节6.6 table.

Logic input. SET0, SET1, and CWD select the watchdog window ratios, timeouts, and disable the watchdog;

see the 节6.6 table.

SET1

VDD

6

1

I

Supply voltage pin. For noisy systems, connecting a 0.1-µF bypass capacitor is recommended.

Watchdog input. A falling transition (edge) must occur at this pin between the lower (t_WDL(max)) and upper

(t_WDU(min)) window boundaries in order for WDO to not assert.

WDI

7

8

I

When the watchdog is not in use, the SET pins can be used to disable the watchdog. The input at WDI is

ignored when RESET or WDO are low (asserted) and also when the watchdog is disabled. If the watchdog is

disabled, then WDI cannot be left unconnected and must be driven to either VDD or GND.

Watchdog output. Connect WDO with a 1-kΩto 100-kΩresistor to VDD. WDO goes low (asserts) when a

watchdog timeout occurs. WDO only asserts when RESET is high. When a watchdog timeout occurs, WDO

goes low (asserts) for the set RESET timeout delay (t_RST). When RESET goes low, WDO is in a high-

impedance state.

WDO

O

Thermal pad

Connect the thermal pad to a large-area ground plane. The thermal pad is internally connected to GND.

—

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6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

MAX

UNIT

V

Supply voltage range

Output voltage range

VDD

7

–0.3

RESET, WDO

SET0, SET1, WDI, SENSE

CWD, CRST

7

V

7

VDD + 0.3⁽³⁾

±20

Voltage ranges

V

Output pin current

RESET, WDO

mA

Input current (all pins)

±20

Continuous total power dissipation

See 节6.4

(2)

Operating junction, T_J

150

–40

–65

(2)

Temperature

Operating free-air temperature, T_A

Storage, T_stg

°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under

Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device

reliability.

(2) T_J= T_Aas a result of the low dissipated power in this device.

(3) The absolute maximum rating is V_DD+ 0.3 V or 7.0 V, whichever is smaller.

6.2 ESD Ratings

VALUE

±4000

±1000

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

V_(ESD)

Electrostatic discharge

V

Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with

less than 500-V HBM is possible with the necessary precautions.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with

less than 250-V CDM is possible with the necessary precautions.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

NOM

MAX

6.5

UNIT

V

VDD

V_SENSE

V_SET0

V_SET1

C_CRST

CRST

C_CWD

CWD

R_PU

Supply pin voltage

1.6

Input pin voltage

0

6.5

V

SET0 pin voltage

0

6.5

V

SET1 pin voltage

0

0.1⁽¹⁾

9

6.5

V

RESET delay capacitor

Pullup resistor to VDD

Watchdog timing capacitor

Pullup resistor to VDD

Pullup resistor, RESET and WDO

RESET pin current

1000⁽¹⁾

nF

kΩ

nF

kΩ

mA

°C

10

11

0.1⁽²⁾

9

1000⁽²⁾

11

10

1

100

10

I_RST

I_WDO

T_J

Watchdog output current

Junction Temperature

10

125

–40

(1) Using a C_CRSTcapacitor of 0.1 nF or 1000 nF gives a reset delay of 703 µs or 3.22 seconds, respectively.

(2) Using a C_CWDcapacitor of 0.1 nF or 1000 nF gives a t_WDU(typ)of 62.74 ms or 77.45 seconds, respectively.

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6.4 Thermal Information

TPS3850

DRC (VSON)

10 PINS

52.3

THERMAL METRIC⁽¹⁾

UNIT

R_θJA

Junction-to-ambient thermal resistance

°C/W

R_θJC(top)

R_θJB

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

59.7

26.1

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

1.7

ψ_JT

26.0

ψ_JB

R_θJC(bot)

9.7

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

6.5 Electrical Characteristics

at 1.6 V ≤V_DD≤6.5 V over the operating temperature range of –40°C ≤T_J≤+125°C (unless otherwise noted); the

open-drain pullup resistors are 10 kΩfor each output; typical values are at T_J= 25°C

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

GENERAL CHARACTERISTICS

(1) (2) (3)

V_DD

I_DD

Supply voltage

Supply current

1.6

6.5

19

V

10

µA

RESET FUNCTION

(2)

V_POR

Power-on reset voltage

I_RESET= 15 µA, V_OL(MAX)= 0.25 V

0.8

V

(1)

V_UVLO

Undervoltage lockout voltage

1.35

Overvoltage SENSE threshold accuracy,

entering RESET

V_IT+(OV)

V_IT-(UV)

V_IT(ADJ)

V_IT+(nom)+0.8%

V_IT-(nom)+0.8%

0.4032

V

_IT+(nom)–0.8%

Undervoltage SENSE threshold accuracy,

entering RESET

V

_IT-(nom)–0.8%

Falling SENSE threshold voltage,

adjustable version only

0.3968

0.4

V

V_HYST

I_CRST

Hysteresis voltage

0.2%

347

0.5%

375

0.8%

403

CRST pin charge current

CRST pin threshold voltage

CRST = 0.5 V

CWD = 0.5 V

nA

V

V_CRST

1.196

1.21

1.224

WINDOW WATCHDOG FUNCTION

I_CWD

V_CWD

V_OL

CWD pin charge current

347

375

403

1.224

0.4

nA

V

CWD pin threshold voltage

1.196

1.21

RESET, WDO output low

VDD = 5 V, I_SINK= 3 mA

V

I_D

RESET, WDO output leakage current

Low-level input voltage (SET0, SET1)

High-level input voltage (SET0, SET1)

Low-level input voltage (WDI)

High-level input voltage (WDI)

VDD = 1.6 V, V_RESET,= V_WDO= 6.5 V

1

µA

V

V_IL

0.25

V_IH

0.8

V

V_IL(WDI)

V_IH(WDI)

0.3 × V_DD

V

0.8 × V_DD

V

TPS3850Xyy(y), V_SENSE= 5.0 V,

VDD = 3.3 V

2.1

2.5

50

µA

nA

I_SENSE

SENSE pin idle current

TPS3850H01 only, V_SENSE= 5.0 V,

VDD = 3.3 V

–50

(1) When V_DDfalls below V_UVLO, RESET is driven low.

(2) When V_DDfalls below V_POR, RESET and WDO are undefined.

(3) During power-on, V_DDmust be a minimum 1.6 V for at least 300 µs before the output corresponds to the SENSE voltage.

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6.6 Timing Requirements

MIN

TYP

MAX

UNIT

GENERAL

t_INIT

t_SET

CWD, CRST pin evaluation period⁽¹⁾

381

500

1

µs

Time required between changing SET0 and SET1 pins

SET0, SET1 pin setup time

Startup delay⁽²⁾

300

RESET FUNCTION

CRST = NC

170

8.5

200

10

230

ms

t_RST

Reset timeout period

11.5

CRST = 10 kΩto VDD

VDD = 5 V, V_SENSE= V_IT+(OV)+ 2.5%

VDD = 5 V, V_SENSE= V_IT-(UV)–2.5%

35

t_RST-DEL

V_SENSEto RESET delay

µs

17

WINDOW WATCHDOG FUNCTION

CWD = programmable, SET0 = 0, SET1 = 0⁽³⁾

CWD = programmable, SET0 = 1, SET1 = 1⁽³⁾

CWD = programmable, SET0 = 0, SET1 = 1^{(3) (4)}

CWD = NC, SET0 = 0, SET1 = 0

1/8

1/2

Window watchdog ratio of

WD ratio lower boundary to upper

boundary

3/4

19.1

1.48

22.5

1.85

25.9

2.22

ms

CWD = NC, SET0 = 0, SET1 = 1

CWD = NC, SET0 = 1, SET1 = 0

Watchdog disabled

CWD = NC, SET0 = 1, SET1 = 1

680

7.65

800

9.0

920

10.35

ms

Window watchdog lower

boundary

t_WDL

CWD = 10 kΩto VDD, SET0 = 0, SET1 = 0

CWD = 10 kΩto VDD, SET0 = 0, SET1 = 1

CWD = 10 kΩto VDD, SET0 = 1, SET1 = 0

CWD = 10 kΩto VDD, SET0 = 1, SET1 = 1

CWD = NC, SET0 = 0, SET1 = 0

Watchdog disabled

1.48

1.85

55.0

27.5

2.22

63.3

ms

46.8

CWD = NC, SET0 = 0, SET1 = 1

23.375

31.625

CWD = NC, SET0 = 1, SET1 = 0

Watchdog disabled

CWD = NC, SET0 = 1, SET1 = 1

1360

1600

109.0

195.0

1840

125.4

224.3

ms

Window watchdog upper

boundary

t_WDU

92.7

CWD = 10 kΩto VDD, SET0 = 0, SET1 = 0

CWD = 10 kΩto VDD, SET0 = 0, SET1 = 1

CWD = 10 kΩto VDD, SET0 = 1, SET1 = 0

CWD = 10 kΩto VDD, SET0 = 1, SET1 = 1

165.8

Watchdog disabled

9.35

11.0

150

50

12.65

ms

µs

ns

t_WD-setupSetup time required for device to respond to changes on WDI after being enabled

Minimum WDI pulse duration

t_WD-del

WDI to WDO delay

50

(1) Please refer to 节8.1.1.2

(2) During power-on, V_DDmust be a minimum 1.6 V for at least 300 µs before the output corresponds to the SENSE voltage.

(3) 0 refers to V_SET≤V_IL, 1 refers to V_SET≥V_IH.

(4) If this watchdog ratio is used, then t_WDL(max)can overlap t_WDU(min)

.

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6.7 Timing Diagrams

VDD

V_POR

V_UVLO

V_IT-(UV)+ V_HYST

V_IT-(UV)

t_RST-DEL

SENSE

t_RST

(1)

RESET

WDI

t_WDL< t < t_WDU

t < t_WDU

X

t < t_WDL

WDO

t_RST

图6-1. Timing Diagram

A. See 图6-2 for WDI timing requirements.

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WDI

Early Fault

WDO

Correct Operation

WDI

WDO

Late Fault

WDI

WDO

Valid

Window

Timing

t_WDL(min)

t_WDL(typ)

t_WDL(max)

t_WDU(min)

t_WDU(typ)

t_WDU(max)

= Tolerance Window

图6-2. TPS3850 Window Watchdog Timing

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VDD/

SENSE

RESET

t_RST-DEL

t_RST

SET0

t_SET

t_WD-setup

SET1

RATIO

1:8

1:2

1:8

Disabled

图6-3. Changing SET0 and SET1 Pins

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6.8 Typical Characteristics

all curves are taken at T_A= 25°C with 1.6 V ≤V_DD≤6.5 V (unless otherwise noted)

0.5

0.3

0.5

Unit 1

Unit 2

Unit 3

Unit 4

Unit 5

Average

Unit 1

Unit 2

Unit 3

Unit 4

Unit 5

Average

0.3

0.1

-0.1

-0.3

-0.5

-0.1

-0.3

-0.5

-50

-25

0

25

50

75

100

125

-50

-25

0

25

50

75

100

125

Temperature (èC)

图6-4. V_IT+(OV)Accuracy vs Temperature

图6-5. V_IT-(UV)Accuracy vs Temperature

0.5

0.3

0.5

0.3

Unit 1

Unit 2

Unit 3

Unit 4

Unit 5

Average

Unit 1

Unit 2

Unit 3

Unit 4

Unit 5

Average

0.1

-0.1

-0.3

-0.5

-0.1

-0.3

-0.5

-50

-25

0

25

50

75

100

125

-50

-25

0

25

50

75

100

125

Temperature (èC)

图6-6. V_IT-(OV)Accuracy vs Temperature

图6-7. V_IT+(UV)Accuracy vs Temperature

25

20

15

10

5

25

20

15

10

5

0

-0.5 -0.4 -0.3 -0.2 -0.1

0

V_IT+(OV)Accuracy (%)

0.1 0.2 0.3 0.4 0.5

-0.5 -0.4 -0.3 -0.2 -0.1

0

V_IT-(UV)Accuracy (%)

0.1 0.2 0.3 0.4 0.5

Includes G and H versions; with 1.2-V, 1.8-V, 3.0-V, 3.3-V, and

5-V thresholds; total units = 41,111

Includes G and H versions; with 1.2-V, 1.8-V, 3.0-V, 3.3-V, and

5-V thresholds; total units = 41,111

图6-8. V_IT+(OV)Accuracy Histogram

图6-9. V_IT-(UV)Accuracy Histogram

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6.8 Typical Characteristics (continued)

all curves are taken at T_A= 25°C with 1.6 V ≤V_DD≤6.5 V (unless otherwise noted)

380

376

372

368

364

16

12

8

-40èC

0èC

25èC

105èC

125èC

4

1.6 V

6.5 V

0

-50

-25

0

25

50

75

100

125

0

1

2

3

4

5

6

7

Temperature (èC)

VDD (V)

图6-11. Supply Current vs Power-Supply Voltage

1.6

图6-10. CWD Charging Current vs Temperature

1.6

1.4

1.2

1

-40èC

0èC

25èC

105èC

125èC

-40èC

0èC

25èC

105èC

125èC

1.4

1.2

1

0.8

0.6

0.4

0.2

0

0.8

0.6

0.4

0.2

0

1

2

3

I_RESET(mA)

4

5

6

0

1

2

3

I_RESET(mA)

4

5

6

VDD = 1.6 V

VDD = 6.5 V

图6-12. Low-Level RESET Voltage vs RESET Current

图6-13. Low-Level RESET Voltage vs RESET Current

90

-40èC

0èC

25èC

105èC

125èC

-40èC

0èC

25èC

105èC

125èC

70

50

30

10

70

50

30

10

1

2

3

4

Overdrive (%)

5

6

7

1

2

3

4

Overdrive (%)

5

6

7

VDD = 1.6 V, V_IT+(OV)= 0.936 V

图6-14. Propagation Delay vs Overdrive

VDD = 6.5 V, V_IT+(OV)= 0.936 V

图6-15. Propagation Delay vs Overdrive

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6.8 Typical Characteristics (continued)

all curves are taken at T_A= 25°C with 1.6 V ≤V_DD≤6.5 V (unless otherwise noted)

40

30

20

10

0

40

30

20

10

0

-40èC

0èC

25èC

105èC

125èC

-40èC

0èC

25èC

105èC

125èC

1

2

3

4

Overdrive (%)

5

6

7

1

2

3

4

Overdrive (%)

5

6

7

VDD = 1.6 V, V_IT-(UV)= 0.864 V

图6-16. Propagation Delay vs Overdrive

VDD = 6.5 V, V_IT-(UV)= 0.864 V

图6-17. Propagation Delay vs Overdrive

40

35

30

25

20

15

10

5

40

35

30

25

20

15

10

5

Overdrive = 3%

Overdrive = 4%

Overdrive = 5%

Overdrive = 6%

Overdrive = 7%

Overdrive = 3%

Overdrive = 4%

Overdrive = 5%

Overdrive = 6%

Overdrive = 7%

-50

-25

0

25

50

75

100

125

-50

-25

0

25

50

75

100

125

Temperature (èC)

VDD = 1.6 V, V_IT+(OV)= 0.936 V

图6-18. SENSE Glitch Immunity vs Temperature

VDD = 6.5 V, V_IT+(OV)= 0.936 V

图6-19. SENSE Glitch Immunity vs Temperature

40

35

30

25

20

15

10

5

40

35

30

25

20

15

10

5

Overdrive = 3%

Overdrive = 4%

Overdrive = 5%

Overdrive = 6%

Overdrive = 7%

Overdrive = 3%

Overdrive = 4%

Overdrive = 5%

Overdrive = 6%

Overdrive = 7%

-50

-25

0

25

50

75

100

125

-50

-25

0

25

50

75

100

125

Temperature (èC)

VDD = 1.6 V, V_IT-(UV)= 0.864 V

图6-20. SENSE Glitch Immunity vs Temperature

VDD = 6.5 V, V_IT-(UV)= 0.864 V

图6-21. SENSE Glitch Immunity vs Temperature

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7 Detailed Description

7.1 Overview

The TPS3850 is a high-accuracy voltage supervisor with an integrated watchdog timer. This device includes a

precision voltage supervisor with both overvoltage (V_IT+(OV)) and undervoltage (V_IT-(UV)) thresholds that achieve

0.8% accuracy over the specified temperature range of –40°C to +125°C. In addition, the TPS3850 includes

accurate hysteresis on both thresholds, making the device ideal for use with tight tolerance systems where

voltage supervisors must ensure a RESET before the minimum and maximum supply tolerance of the

microprocessor or system-on-a-chip (SoC) is reached.

7.2 Functional Block Diagrams

VDD

SENSE

R₁

RESET

R₂

Precision

Clock

R₃

Reference

0.4 V

VDD

WDO

State

Machine

Cap

Control

CWD

VDD

Cap

Control

CRST

WDI SET0 SET1

GND

图7-1. Fixed Version Block Diagram

R_TOTAL= R₁+ R₂+ R₃= 4.5 MΩ.

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VDD

SENSE

RESET

Reference

Precision

Clock

0.4 V

VDD

WDO

State

Machine

Cap

Control

CWD

VDD

Cap

Control

CRST

WDI SET0 SET1

GND

图7-2. Adjustable Version Block Diagram

7.3 Feature Description

7.3.1 CRST

The CRST pin provides the user the functionality of both high-precision, factory-programmed, reset delay timing

options and user-programmable, reset delay timing. The CRST pin can be pulled up to VDD through a resistor,

have an external capacitor to ground, or can be left unconnected. The configuration of the CRST pin is re-

evaluated by the device every time the voltage on the SENSE line enters the valid window (V_IT+(UV)< V_SENSE

<

V_IT-(OV)). The pin evaluation is controlled by an internal state machine that determines which option is connected

to the CRST pin. The sequence of events takes 381 μs (t_INIT) to determine if the CRST pin is left unconnected,

pulled up through a resistor, or connected to a capacitor. If the CRST pin is being pulled up to VDD, then a 10-

kΩpullup resistor is required.

7.3.2 RESET

The RESET pin features a programmable reset delay time that can be adjusted from 703 µs to 3.22 seconds

when using adjustable capacitor timing. RESET is an open-drain output that should be pulled up through a 1-kΩ

to 100-kΩ pullup resistor. When V_DDis above V_{DD (min)}, RESET remains high (not asserted) when the SENSE

voltage is between the positive threshold (V_IT+(OV)) and the negative threshold (V_IT-(UV)). If SENSE falls below

V_IT-(UV)or rises above V_IT+(OV), then RESET is asserted, driving the RESET pin to a low-impedance state. When

SENSE comes back into the valid window, a RESET delay circuit is enabled that holds RESET low for a

specified reset delay period (t_RST). This t_RSTperiod is determined by what is connected to the CRST pin; see 图

8-1. When the reset delay has elapsed, the RESET pin goes to a high-impedance state and uses a pullup

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resistor to hold RESET high. The pullup resistor must be connected to the proper voltage rail to allow other

devices to be connected at the correct interface voltage. To ensure proper voltage levels, give some

consideration when choosing the pullup resistor values. The pullup resistor value is determined by output logic

low voltage (V_OL), capacitive loading, and leakage current (I_D); see the 节8.1.1 section for more information.

7.3.3 Over- and Undervoltage Fault Detection

The TPS3850 features both overvoltage detection and undervoltage detection. This detection is achieved

through the combination of two comparators with a precision voltage reference and a trimmed resistor divider

(fixed versions only). The SENSE pin is used to monitor the critical voltage rail; this configuration optimizes

device accuracy because all resistor tolerances are accounted for in the accuracy and performance

specifications. Both comparators also include built-in hysteresis that provides some noise immunity and ensures

stable operation. If the voltage on the SENSE pin drops below V_IT-(UV), then RESET is asserted (driven low).

When the voltage on the SENSE pin is between the positive and negative threshold voltages, RESET deasserts

after the user-defined RESET delay time, as shown in 图7-3.

The SENSE input can vary from GND to 6.5 V, regardless of the device supply voltage used. Although not

required in most cases, for noisy applications, good analog-design practice is to place a 1-nF to 10-nF bypass

capacitor at the SENSE pin to reduce sensitivity to transient voltages on the monitored signal.

V_IT+(OV)

Overvoltage Limit

V_IT-(OV)= V_IT+(OV)- V_HYST

V_SENSE

V_IT+(UV)= V_IT-(UV)+ V_HYST

V_IT-(UV)

Undervoltage Limit

t_RST

RESET

图7-3. Window Comparator Timing Diagram

7.3.4 Adjustable Operation Using the TPS3850H01

The adjustable version (TPS3850H01) can be used to monitor any voltage rail down to 0.4 V using the circuit

illustrated in 图 7-4. When using the TPS3850H01, the device does not function as a window comparator;

instead, the device only monitors the undervoltage threshold. To monitor a user-defined voltage, the target

threshold voltage for the monitored supply (V_MON) and the resistor divider values can be calculated by using 方

程式1 and 方程式2, respectively:

≈

’

÷

R₁

V_MON= V

ì 1+

∆

IT(ADJ)

R_{2 ◊}

«

(1)

方程式 1 can be used to calculate either the negative threshold or the positive threshold by replacing V_ITxwith

either V_ITNor V_ITN+ V_HYST, respectively.

R_TOTAL= R₁+ R₂

(2)

Large resistor values minimize current consumption; however, the input bias current of the device degrades

accuracy if the current through the resistors is too low. Therefore, choosing an R_TOTALvalue so that the current

through the resistor divider is at least 100 times larger than the maximum SENSE pin current (I_SENSE) ensures a

good degree of accuracy; see the I_Qvs Accuracy Tradeoff In Designing Resistor Divider Input To A Voltage

Supervisor (SLVA450) application report for more details on sizing input resistors.

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V_MON

VDD

R₁

TPS3850

SENSE

SET1

SET0

CRST

CWD

VDD

RESET

WDO

R₂

WDI

GND

图7-4. Adjustable Voltage Monitor

7.3.5 Window Watchdog

7.3.5.1 SET0 and SET1

When changing the SET0 or SET1 pins, there are two cases to consider: enabling and disabling the watchdog,

and changing the SET0 or SET1 pins when the watchdog is enabled. In case 1 where the watchdog is being

enabled or disabled, the changes take effect immediately. However, in case 2, a RESET event must occur in

order for the changes to take place.

7.3.5.1.1 Enabling the Window Watchdog

The TPS3850 features the ability to enable and disable the watchdog timer. This feature allows the user to start

with the watchdog timer disabled and then enable the watchdog timer using the SET0 and SET1 pins. The ability

to enable and disable the watchdog is useful to avoid undesired watchdog trips during initialization and

shutdown. When the SETx pins are changed to disable the watchdog timer, changes on the pins are responded

to immediately (as shown in 图 7-5). When the watchdog goes from disabled to enabled, there is a 150 μs

(t_WD-setup) transition period where the device does not respond to changes on WDI. After this 150-μs period, the

device begins to respond to changes on WDI again.

VDD/

SENSE

RESET

SET0

t_WD-setup

SET1

RATIO

1:8

Disabled

1:8

图7-5. Enabling the Watchdog Timer

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7.3.5.1.2 Disabling the Watchdog Timer When Using the CRST Capacitor

When using the TPS3850-Q1 with fixed timing options, if the watchdog is disabled and reenabled while WDO is

asserted (logic low) the watchdog performs as described in the 节 7.3.5.1.1 section. However, if there is a

capacitor on the CRST pin, and the watchdog is disabled and reenabled when WDO is asserted (logic low), then

the watchdog behaves as shown in 图 7-6. When the watchdog is disabled, WDO goes high impedance (logic

high). However, when the watchdog is enabled again, the t_RSTperiod must expire before the watchdog resumes

normal operation.

VDD/

SENSE

RESET

t_WDU

WDO

t_RST

Disabling and

Enabling

watchdog

SET1

SET0

There is no WDI signal in this figure, WDI is always at GND.

图7-6. Enabling and Disabling the Watchdog Timer During a WDO Reset Event

7.3.5.1.3 SET0 and SET1 During Normal Watchdog Operation

The SET0 and SET1 pins can be used to control the window watchdog ratio of the lower boundary to the upper

boundary. There are four possible modes for the watchdog (see 表 8-5): disabled, 1:8 ratio, 3:4 ratio, and 1:2

ratio. If SET0 = 1 and SET1 = 0, then the watchdog is disabled. When the watchdog is disabled WDO does not

assert, and the TPS3850 functions as a normal supervisor. The SET0 and SET1 pins can be changed when the

device is operational, but cannot be changed at the same time. If these pins are changed when the device is

operational, then there must be a 500-µs (t_SET) delay between switching the two pins. If the SET0 and SET1 are

used to change the reset timing, then a reset event must occur before the new timing condition is latched. This

reset can be triggered by SENSE rising above V_IT+(OV)or below V_IT-(UV), or by bringing V_DDbelow V_UVLO. 图 7-7

shows how the SET0 and SET1 pins do not change the watchdog timing option until a reset event has occurred.

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VDD/

SENSE

RESET

t_RST-DEL

t_RST

SET0

t_SET

SET1

RATIO

1:2

1:8

图7-7. Changing SET0 and SET1 Pins

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7.3.6 Window Watchdog Timer

This section provides information for the window watchdog modes of operation. A window watchdog is typically

employed in safety critical applications where a traditional watchdog timer is inadequate. In a traditional

watchdog, there is a maximum time in which a pulse must be issued to prevent the reset from occurring.

However, in a window watchdog the pulse must be issued between a maximum lower window time (t_WDL(max)

)

and the minimum upper window time (t_WDU(min)) set by the CWD pin and the SET0 and SET1 pins. 表 8-5

describes how t_WDUcan be used to calculate the timing of t_WDL. The t_WDLtiming can also be changed by

adjusting the SET0 and SET1 pins. 图 7-8 shows the valid region for a WDI pulse to be issued to prevent the

WDO from being triggered and being pulled low.

WDI

Early Fault

WDO

Correct Operation

WDI

WDO

Late Fault

WDI

WDO

Valid

Window

Timing

t_WDL(min)

t_WDL(typ)

t_WDL(max)

t_WDU(min)

t_WDU(typ)

t_WDU(max)

= Tolerance Window

图7-8. TPS3850 Window Watchdog Timing

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7.3.6.1 CWD

The CWD pin provides the user the functionality of both high-precision, factory-programmed watchdog timing

options and user-programmable watchdog timing. The TPS3850 features three options for setting the watchdog

window: connecting a capacitor to the CWD pin, connecting a pullup resistor to VDD, and leaving the CWD pin

unconnected. The configuration of the CWD pin is evaluated by the device every time V_SENSEenters the valid

window (V_IT+(UV)< V_SENSE< V_IT-(OV)). The pin evaluation is controlled by an internal state machine that

determines which option is connected to the CWD pin. The sequence of events takes 381 μs (t_INIT) to determine

if the CWD pin is left unconnected, pulled up through a resistor, or connected to a capacitor. If the CWD pin is

being pulled up to VDD using a pullup resistor, then a 10-kΩresistor is required.

7.3.6.2 WDI Functionality

WDI is the watchdog timer input that controls the WDO output. The WDI input is triggered by the falling edge of

the input signal. For the first pulse, the watchdog acts as a traditional watchdog timer; thus, the first pulse must

be issued before t_WDU(min). After the first pulse, to ensure proper functionality of the watchdog timer, always issue

the WDI pulse within the window of t_WDL(max)and t_WDU(min). If the pulse is issued in this region, then WDO

remains unasserted. Otherwise, the device asserts WDO, putting the WDO pin into a low-impedance state.

The watchdog input (WDI) is a digital pin. To ensure there is no increase in I_DD, drive the WDI pin to either VDD

or GND at all times. Putting the pin to an intermediate voltage can cause an increase in supply current (I_DD

)

because of the architecture of the digital logic gates. When RESET is asserted, the watchdog is disabled and all

signals input to WDI are ignored. When RESET is no longer asserted, the device resumes normal operation and

no longer ignores the signal on WDI. If the watchdog is disabled, drive the WDI pin to either VDD or GND.

7.3.6.3 WDO Functionality

The TPS3850 features a window watchdog timer with an independent watchdog output ( WDO). The

independent watchdog output provides the flexibility to flag a fault in the watchdog timing without performing an

entire system reset. When RESET is not asserted (high), the WDO signal maintains normal operation. When

asserted, WDO remains down for t_RST. When the RESET signal is asserted (low), the WDO pin goes to a high-

impedance state. When RESET is unasserted, the window watchdog timer resumes normal operation and WDO

can be used again.

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7.4 Device Functional Modes

表7-1 summarizes the functional modes of the TPS3850.

表7-1. Device Functional Modes

VDD

WDI

WDO

SENSE

RESET

Undefined

Low

V_DD< V_POR

—

High

Ignored

V

_POR≤V_DD< V_UVLO

(1)

High

V_SENSE< V_IT+(UV)

V_SENSE> V_IT-(OV)

Low

(2)

(3)

V_IT-(UV)< V_SENSE< V_IT+(OV)

High

t

_WDL(max)≤t_pulse

≤

V_DD≥V_{DD (min)}

t_WDU(min)

(3)

(2)

t_WDL(max)> t_pulse

Low

V_IT-(UV)< V_SENSE< V_IT+(OV)

High

(3)

t_WDU(min)< t_pulse

(1) When V_SENSEhas not entered the valid window.

(2) When V_SENSEis in the valid window.

(3) Where t_pulseis the time between falling edges on WDI.

7.4.1 V_DDis Below V_POR( V_DD< V_POR

)

When V_DDis less than V_POR, RESET is undefined and can be either high or low. The state of RESET largely

depends on the load that the RESET pin is experiencing.

7.4.2 Above Power-On-Reset But Less Than UVLO (V_POR≤V_DD< V_UVLO

)

When V_DDis less than V_UVLO, and greater than or equal to V_POR, the RESET signal is asserted (logic low)

regardless of the voltage on the SENSE pin. When RESET is asserted, the watchdog output WDO is in a high-

impedance state regardless of the WDI signal that is input to the device.

7.4.3 Above UVLO But Less Than V_{DD (min)}(V_UVLO≤V_DD< V_{DD (min)}

)

When V_DDis less than V_{DD (min)}and greater than or equal to V_UVLO, the RESET signal responds to changes on

the SENSE pin, but the accuracy can be degraded.

7.4.4 Normal Operation (V_DD≥V_{DD (min)}

)

When V_DDis greater than or equal to V_{DD (min)}, the RESET signal is determined by V_SENSE. When RESET is

asserted, WDO goes to a high-impedance state. WDO is then pulled high through the pullup resistor.

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8 Application and Implementation

Note

以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客户应负责确定

器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。

8.1 Application Information

The following sections describe in detail proper device implementation, depending on the final application

requirements.

8.1.1 CRST Delay

The TPS3850 features three options for setting the reset delay (t_RST): connecting a capacitor to the CRST pin,

connecting a pullup resistor to VDD, and leaving the CRST pin unconnected. 图 8-1 shows a schematic drawing

of all three options. To determine which option is connected to the CRST pin, an internal state machine controls

the internal pulldown device and measures the pin voltage. This sequence of events takes 381 μs (t_INIT) to

determine which timing option is used. Every time RESET is asserted, the state machine determines what is

connected to the pin.

VDD

TPS3850

VDD

375 nA

CRST

C_CRST

CRST

Cap

Control

Cap

Control

Cap

Control

User Programmable

Capacitor to GND

CRST

Unconnected

10 kΩ Resistor

to VDD

图8-1. CRST Charging Circuit

8.1.1.1 Factory-Programmed Reset Delay Timing

To use the factory-programmed timing options, the CRST pin must either be left unconnected or pulled up to

VDD through a 10-kΩ pullup resistor. Using these options enables a high-precision, 15% accurate reset delay

timing, as shown in 表8-1.

表8-1. Reset Delay Time for Factory-Programmed Reset Delay Timing

RESET DELAY TIME (t_RST

)

CRST

UNIT

MIN

TYP

200

10

MAX

230

NC

170

8.5

ms

11.5

10 kΩto VDD

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8.1.1.2 Programmable Reset Delay-Timing

The TPS3850 uses a CRST pin charging current (I_CRST) of 375 nA. When using an external capacitor, the rising

RESET delay time can be set to any value between 700 µs (C_CRST= 100 pF) and 3.2 seconds (C_CRST= 1 µF).

The typical ideal capacitor value needed for a given delay time can be calculated using 方程式3, where C_CRSTis

in microfarads and t_RSTis in seconds:

t_RST= 3.22 × C_CRST+ 0.000381

(3)

To calculate the minimum and maximum-reset delay time use 方程式4 and 方程式5, respectively.

t_RST(min)= 2.8862 × C_CRST+ 0.000324

t_RST(max)= 3.64392 × C_CRST+ 0.000438

(4)

(5)

The slope of 方程式 3 is determined by the time the CRST charging current (I_CRST) takes to charge the external

capacitor up to the CRST comparator threshold voltage (V_CRST). When RESET is asserted, the capacitor is

discharged through the internal CRST pulldown resistor. When the RESET conditions are cleared, the internal

precision current source is enabled and begins to charge the external capacitor; when V_CRST= 1.21 V, RESET is

unasserted. Note that to minimize the difference between the calculated RESET delay time and the actual

RESET delay time, use a use a high-quality ceramic dielectric COG, X5R, or X7R capacitor and minimize

parasitic board capacitance around this pin. 表8-2 lists the reset delay time ideal capacitor values for C_CRST

.

表8-2. Reset Delay Time for Common Ideal Capacitor Values

RESET DELAY TIME (t_RST

)

C_CRST

UNIT

MIN⁽¹⁾

TYP

0.70

3.61

32.6

323

MAX⁽¹⁾

0.8

100 pF

1 nF

0.61

3.21

29.2

289

ms

4.08

36.8

364

10 nF

100 nF

1 μF

2886

3227

3644

(1) Minimum and maximum values are calculated using ideal capacitors.

8.1.2 CWD Functionality

The TPS3850 features three options for setting the watchdog window: connecting a capacitor to the CWD pin,

connecting a pullup resistor to VDD, and leaving the CWD pin unconnected. 图 8-2 shows a schematic drawing

of all three options. If this pin is connected to VDD through a 10-kΩ pullup resistor or left unconnected (high

impedance), then the factory-programmed watchdog timeouts are enabled; see the 节 6.6 table. Otherwise, the

watchdog timeout can be adjusted by placing a capacitor from the CWD pin to ground.

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VDD

TPS3850

VDD

375 nA

CWD

C_CWD

CWD

Cap

Control

Cap

Control

Cap

Control

User Programmable

Capacitor to GND

CWD

Unconnected

10 kΩ Resistor

to VDD

图8-2. CWD Charging Circuit

8.1.2.1 Factory-Programmed Timing Options

If using the factory-programmed timing options (listed in 表 8-3), the CWD pin must either be unconnected or

pulled up to VDD through a 10-kΩ pullup resistor. Using these options enables high-precision, factory-

programmed watchdog timing.

表8-3. Factory-Programmed Watchdog Timing

INPUT

WATCHDOG LOWER BOUNDARY (t_WDL

)

WATCHDOG UPPER BOUNDARY (t_WDU)

UNIT

CWD

SET0 SET1

MIN

19.1

1.48

TYP

22.5

1.85

MAX

25.9

2.22

MIN

46.8

TYP

55.0

27.5

MAX

63.3

0

1

0

1

0

1

0

1

0

1

0

1

ms

23.375

31.625

NC

Watchdog disabled

680

800

9.0

920

10.35

1360

1600

109.0

195.0

1840

125.4

224.3

ms

7.65

92.7

165.8

10 kΩto VDD

Watchdog disabled

1.48 1.85

Watchdog disabled

9.35 11.0

2.22

12.65

ms

8.1.2.2 Adjustable Capacitor Timing

Adjustable capacitor timing is achievable by connecting a capacitor to the CWD pin. If a capacitor is connected

to CWD, then a 375-nA constant-current source charges C_CWDuntil V_CWD= 1.21 V. The TPS3850 determines

the window watchdog upper boundary with the formula given in 方程式 6, where C_CWDis in microfarads and

t_WDUis in seconds.

t_WDU(typ)= 77.4 × C_CWD+ 0.055

(6)

The TPS3850 is designed and tested using C_CWDcapacitors between 100 pF and 1 µF. Note that 方程式 6 is for

ideal capacitors. Capacitor tolerances cause the actual device timing to vary such that the minimum of t_WDUcan

decrease and the maximum of t_WDUcan increase by the capacitor tolerance. To allow for a valid watchdog

window, choose a capacitor with tolerance such that t_WDU(min)and t_WDL(max)do not overlap. For the most

accurate timing, use ceramic capacitors with COG dielectric material. As shown in 表 8-4, when using the

minimum capacitor of 100 pF, the watchdog upper boundary is 62.74 ms; whereas with a 1-µF capacitor, the

watchdog upper boundary is 77.455 seconds. If a C_CWDcapacitor is used, 方程式 6 can be used to set t_WDUthe

window watchdog upper boundary. The window watchdog lower boundary is dependent on the SET0 and SET1

pins because these pins set the window watchdog ratio of the lower boundary to upper boundary; 表 8-5 shows

how t_WDUcan be used to calculate t_WDLbased on the SET0 and SET1 pins.

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表8-4. t_WDUValues for Common Ideal Capacitor Values

WATCHDOG UPPER BOUNDARY (t_WDU

)

C_CWD

MIN⁽¹⁾

56.77

119.82

750

TYP

62.74

132.4

829

MAX⁽¹⁾

68.7

100 pF

1 nF

ms

144.98

908

10 nF

100 nF

1 µF

7054

7795

77455

8536

70096

84814

(1) Minimum and maximum values are calculated using ideal capacitors.

表8-5. Programmable CWD Timing

INPUT

SET0 SET1

WATCHDOG LOWER BOUNDARY (t_WDL

)

WATCHDOG UPPER BOUNDARY (t_WDU

MIN⁽²⁾TYP⁽¹⁾MAX⁽²⁾

t_WDUx 0.125 t_WDU(max)x 0.125 0.905 x t_WDU(typ)

)

UNIT

CWD

MIN

t_WDU(min)x 0.125

t_WDU(min)x 0.75

TYP

MAX

0

1

0

1

0

1

t_WDU(typ)1.095 x t_WDU(typ)

s

t_WDUx 0.75

Watchdog disabled

t_WDUx 0.5

t_WDU(max)x 0.75 0.905 x t_WDU(typ)

C_CWD

Watchdog disabled

t_WDU(max)x 0.5 0.905 x t_WDU(typ)t_WDU(typ)1.095 x t_WDU(typ)

t_WDU(min)x 0.5

s

(1) Calculated from 方程式6 using ideal capacitors.

(2) The t_WDU(min)and t_WDU(max)include I_CWDand V_CWDminimum to maximum variation

8.1.3 Adjustable SENSE Configuration

The TPS3850H01 has an undervoltage supervisor that can monitor voltage rails greater than 0.4 V. 表 8-6

contains 1% resistor values for creating a voltage divider to monitor common rails from 0.5 V to 12 V with a

threshold of 4% and 10%. These resistor values can be scaled to decrease the amount of current flowing

through the resistor divider, but increasing the resistor values also decreases the accuracy of the resistor divider.

General practice is for the current flowing through the resistor divider to be 100 times greater than the current

going into the SENSE pin. This practice ensures the highest possible accuracy. 方程式 7 can be used to

calculate the resistors required in the resistor divider. 图8-3 shows the block diagram for adjustable operation.

≈

’

÷

R₁

V_MON= V

ì 1+

∆

IT(ADJ)

R_{2 ◊}

«

(7)

表8-6. SENSE Resistor Divider Values

4% THRESHOLD

10% THRESHOLD

INPUT VOLTAGE (V)

THRESHOLD

VOLTAGE (V)

THRESHOLD

VOLTAGE (V)

R₁(kΩ)

R₂(kΩ)

R₁(kΩ)

R₂(kΩ)

0.5

16.2

75

80.6

0.48

10

64.9

82.5

137

249

374

464

523

825

2100

80.6

0.45

0.72

0.81

1.08

1.64

2.26

2.70

2.99

4.49

10.82

0.8

0.9

1.2

1.8

2.5

3

0.77

93.1

150

267

402

499

562

887

2260

0.86

1.14

1.73

2.40

2.88

3.3

5

3.19

4.80

12

11.62

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V_DD

Reference

0.4 V

V_MON

RESET

R₁

RESET

TIMING

SENSE

R₂

图8-3. Adjustable Voltage Divider

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8.1.4 Overdrive on the SENSE Pin

The propagation delay from exceeding the threshold to RESET being asserted is dependent on two conditions:

the amplitude of the voltage on the SENSE pin relative to the threshold, (ΔV₁and ΔV₂), and the length of time

that the voltage is above or below the trip point (t₁and t₂). If the voltage is just over the trip point for a long

period of time, then RESET asserts and the output is pulled low. However, if the SENSE voltage is just over the

trip point for a few nanoseconds, then the RESET does not assert and the output remains high. The time

required for RESET to assert can be changed by increasing the time that the SENSE voltage goes over the trip

point. 方程式8 shows how to calculate the percentage overdrive.

Overdrive = | ( V_SENSE/ V_ITx–1) × 100% |

(8)

In 方程式 8, V_ITxcorresponds to the SENSE threshold trip point. If V_SENSEexceeds the positive threshold, then

V_IT+(OV)is used. V_IT-(UV)is used when V_SENSEfalls below the negative threshold. In 图 8-4, t₁and t₂correspond

to the amount of time that the SENSE voltage is over the threshold. The response time versus overdrive for

V

_IT+(OV)and V_IT-(UV)is illustrated in 图6-14 and 图6-17, respectively.

The TPS3850 is relatively immune to short positive and negative transients on the SENSE pin because of the

overdrive voltage curve; see 图6-20 and 图6-21.

ûV₁

t₁

V_IT+(OV)

V_SENSE

V_IT-(UV)

ûV₂

t₂

Time

图8-4. Overdrive Voltage on the SENSE Pin

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8.2 Typical Applications

8.2.1 Design 1: Monitoring a 1.2-V Rail with Factory-Programmable Watchdog Timing

A typical application for the TPS3850 is shown in 图 8-5. The TPS3850G12 is used to monitor the 1.2-V, V_CORE

rail powering the microcontroller.

1.8V

1.2V

TPS3850

V_CORE

Microcontroller

RESET

V_I/O

SENSE

SET1

SET0

CRST

CWD

VDD

RESET

WDO

NMI

WDI

GND

GPIO

0.1 µF

GND

图8-5. Monitoring Supply Voltage and Watchdog Supervision of a Microcontroller

8.2.1.1 Design Requirements

PARAMETER

Reset delay

DESIGN REQUIREMENT

Minimum reset delay of 250 ms

DESIGN RESULT

Minimum reset delay of 260 ms, reset delay of 322

ms (typical)

Leaving the CWD pin unconnected with SET0 = 0

and SET1 = 1 produces a window with a t_WDL(max)

of 2.2 ms and a t_WDU(min)of 22 ms

Functions with a 200-Hz pulse-width modulation

(PWM) signal with a 50% duty cycle

Watchdog window

Output logic voltage

Monitored rail

1.8-V CMOS

Worst-case V_IT+(OV)1.257 V (4.8%)

Worst-case V_IT-(UV)1.142 V (4.7%)

1.2 V within ±5%

Maximum device current

consumption

10 µA of current consumption, typical worst-case of

199 µA when WDO or RESET is asserted

200 µA

8.2.1.2 Detailed Design Procedure

8.2.1.2.1 Monitoring the 1.2-V Rail

The window comparator allows for precise voltage supervision of common rails between 0.9 V and 5.0 V. This

application calls for very tight monitoring of the rail with only ±5% of variation allowed on the rail. To ensure this

requirement is met, the TPS3850G12 was chosen for its ±4% thresholds. To calculate the worst-case for V_IT+(OV)

and V_IT-(UV), the accuracy must also be taken into account. The worst-case for V_IT+(OV)can be calculated by 方程

式9:

V_{IT+(OV)(Worst-Case)}= V_IT+(OV)typ× 1.048 = 1.2 × 1.048 = 1.257 V

(9)

The worst case for V_IT-(UV)can be calculated using 方程式10:

V_{IT–(UV)(Worst-Case)}= V_IT–(UV)typ× 0.952 = 1.2 × 0.952 = 1.142 V

(10)

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8.2.1.2.2 Meeting the Minimum Reset Delay

The TPS3850 features three options for setting the reset delay: connecting a capacitor to the CRST pin,

connecting a pullup resistor, and leaving the CRST pin unconnected. If the CRST pin is either unconnected or

pulled up the minimum timing requirement cannot be met, thus an external capacitor must be connected to the

CRST pin. Because a minimum time is required, the worst-case scenario is a supervisor with a high CRST

charging current (I_CRST) and a low CRST comparator threshold (V_CRST). For applications with ambient

temperatures ranging from –40°C to +125°C, C_CRSTcan be calculated using I_CRST(MAX), V_CRST(MIN), and solving

for C_CRSTin 方程式11:

t_RST(min)- 0.000324

0.25 - 0.000324

2.8862

C_{RST(min)_ideal}

=

2.8862

(11)

When solving 方程式 11, the minimum capacitance required at the CRST pin is 0.086 μF. If standard capacitors

with ±10% tolerances are used, then the minimum CRST capacitor required can be found in 方程式12:

C_{RST(min)_ideal}

0.086 mF

1- 0.1

C_RST(min)

=

1- C_tolerance

(12)

Solving 方程式 12 where C_toleranceis 0.1 or 10%, the minimum C_CRSTcapacitor is 0.096 μF. This value is then

rounded up to the nearest standard capacitor value, so a 0.1-μF capacitor must be used to achieve this reset

delay timing. If voltage and temperature derating are being considered, then also include these values in

C_tolerance

.

8.2.1.2.3 Setting the Watchdog Window

In this application, the window watchdog timing options are based on the PWM signal that is provided to the

TPS3850. A window watchdog setting must be chosen such that the falling edge of the PWM signal always falls

within the window. A nominal window must be designed with t_WDL(max)less than 5 ms and t_WDU(min)greater than

5 ms. There are several options that satisfy this window option. An external capacitor can be placed on the CWD

pin and calculated to have a sufficient window. Another option is to use one of the factory-programmed timing

options. An additional advantage of choosing one of the factory-programmed options is the ability to reduce the

number of components required, thus reducing overall BOM cost. Leaving the CWD pin unconnected (NC) with

SET0 = 0 and SET1 = 1 produces a t_WDL(max)of 2.22 ms and a t_WDU(min)of 23.375 ms; see 图8-10.

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8.2.1.2.4 Calculating the RESET and WDO Pullup Resistor

The TPS3850 uses an open-drain configuration for the RESET circuit, as shown in 图 8-6. When the FET is off,

the resistor pulls the drain of the transistor to VDD and when the FET is turned on, the FET attempts to pull the

drain to ground, thus creating an effective resistor divider. The resistors in this divider must be chosen to ensure

that V_OLis below its maximum value. To choose the proper pullup resistor, there are three key specifications to

keep in mind: the pullup voltage (V_PU), the recommended maximum RESET pin current (I_RST), and V_OL. The

maximum V_OLis 0.4 V, meaning that the effective resistor divider created must be able to bring the voltage on

the reset pin below 0.4 V with I_RSTkept below 10 mA. For this example, with a V_PUof 1.8 V, a resistor must be

chosen to keep I_RSTbelow 200 μA because this value is the maximum consumption current allowed. To ensure

this specification is met, a pullup resistor value of 10 kΩwas selected, which sinks a maximum of 180 μA when

RESET or WDO is asserted. As illustrated in 图 6-12, the RESET current is at 180 μA and the low-level output

voltage is approximately zero.

VDD

RESET

CONTROL

图8-6. Open-Drain RESET Configuration

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8.2.1.3 Application Curves

Unless otherwise stated, application curves were taken at T_A= 25°C.

V_DD

500mV/div

SENSE

1.2578 V

200mV/div

1.1576 V

WDO

RESET

500mV/div

V_UVLO= 1.4 V

VDD

RESET

500mV/div

V_POR= .404V

100ms/div

50ms/div

图8-8. Window Comparator Thresholds Entering a

Valid Window

图8-7. Startup Waveform

V_DD

2V/div

SENSE

2V/div

SENSE

2V/div

WDO

2V/div

WDO

2V/div

WDI

2V/div

WDI

2V/div

22 ms

2.2 ms

5ms

10ms/div

5ms/div

图8-10. Window Watchdog Timing

图8-9. 200-Hz WDI Pulse

V_DD

SENSE

500mV/div

200mV/div

RESET

500mV/div

50ms/div

图8-11. Typical RESET Delay Timing

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8.2.2 Design 2: Using TPS3850H01 to monitor a 0.7-V Rail With an Adjustable Window Watchdog Timing

A typical application for the TPS3850H01 is shown in 图8-12.

3.3 V

0.7 V

TPS3850

V_CORE

V_I/O

TPS3890

SENSE

VDD

RESET

WDO

Microcontroller

VDD

SENSE

RESET

NMI

SET1

SET0

CRST

CWD

MR

3.3 V

WDI

GND

GPIO

CT

6.8 µF

GND

2.2 nF

图8-12. Monitoring Supply Voltage and Watchdog Supervision of a Microcontroller

8.2.2.1 Design Requirements

PARAMETER

Reset delay

DESIGN REQUIREMENT

DESIGN RESULT

Minimum RESET delay of 150 ms

Minimum RESET delay of 170 ms

Watchdog disable for initialization Watchdog must remain disabled for 7 seconds until

7.21 seconds (typ)

period

logic enables the watchdog timer

Watchdog window

Output logic voltage

250 ms, maximum

t_WDL(max)= 135 ms, t_WDU(min)= 181 ms

3.3-V CMOS

V_{ITN (max)}0.667 V (–4.7%)

V_{ITN (typ)}0.65 V (–6.6%)

V_{ITN (min)}0.641 V (–8.5%)

Monitored rail

0.7 V, with 7% threshold

50 µA

10 µA of current consumption typical, worst-case of

52 μA when WDO or RESET is asserted⁽¹⁾

Maximum device current

consumption

(1) Only includes the current consumption of the TPS3850.

8.2.2.2 Detailed Design Procedure

8.2.2.2.1 Meeting the Minimum Reset Delay

The design goal for the RESET delay time can be achieved by either using an external capacitor or the CRST

pin can be left unconnected. To minimize component count, the CRST pin is left unconnected. For CRST = NC,

the minimum delay is 170 ms, which is greater than the minimum required RESET delay of 150 ms.

8.2.2.2.2 Setting the Window Watchdog

As illustrated in 图8-2, there are three options for setting the window watchdog. The design specifications in this

application require the programmable timing option (external capacitor connected to CWD). When a capacitor is

connected to the CWD pin, the window is governed by 方程式 13. 方程式 13 is only valid for ideal capacitors,

any temperature or voltage derating must be accounted for separately.

t_WDU- 0.055

77.4

0.25 - 0.055

77.4

C_CWDmF =

=

= 0.0025 mF

(

)

(13)

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The nearest standard capacitor value to 2.5 nF is 2.2 nF. Selecting 2.2 nF for the C_CWDcapacitor gives the

following minimum and maximum timing parameters:

t_WDU(MIN)= 0.905ì t_WDU(TYP)= 0.905ì 77.4ì 2.2ì10^-3+ 0.055 = 203.88 ms

(

)

(14)

(15)

t_WDL(MAX)= 0.5ì t_WDU(MAX)= 0.5ì 1.05ì 77.4ì 2.2ì10^-3+ 0.055 = 118 ms

»

ÿ

(

)

⁄

Capacitor tolerance also influence t_WDU(MIN)and t_WDL(MAX). Select a ceramic COG dielectric capacitor for high

accuracy. For 2.2 nF, COG capacitors are readily available with a 5% tolerance, which results in a 5% decrease

in t_WDU(MIN)and a 5% increase in t_WDL(MAX), giving 181 ms and 135 ms, respectively. A falling edge must be

issued within this window.

8.2.2.2.3 Watchdog Disabled During the Initialization Period

The watchdog is often needed to be disabled during startup to allow for an initialization period. When the

initialization period is over, the watchdog timer is turned back on to allow the microcontroller to be monitored by

the TPS3850. To achieve this setup, SET0 must start at VDD and SET1 must start at GND. In this design, SET0

is simply tied to VDD and SET1 is controlled by a TPS3890 supervisor. In this application, the TPS3890 was

chosen to monitor V_DDas well, which means that RESET on the TPS3890 stays low until V_DDrises above V_ITN

.

When V_DDcomes up, the delay time can be adjusted through the CT capacitor on the TPS3890. With this

approach, the RESET delay can be adjusted from a minimum of 25 µs to a maximum of 30 seconds. For this

design, a minimum delay of 7 seconds is needed until the watchdog timer is enabled. The CT capacitor

calculation (see the TPS3890 data sheet) yields an ideal capacitance of 6.59 µF, giving a closest standard

ceramic capacitor value of 6.8 µF. When connecting a 6.8-µF capacitor from CT to GND, the typical delay time is

7.21 seconds. 图 8-13 illustrates the typical startup waveform for this circuit when the watchdog input is off. 图

8-13 illustrates that when the watchdog is disabled, the WDO output remains high. See the TPS3890 data sheet

for detailed information on the TPS3890.

8.2.2.2.4 Calculating the Sense Resistor

There are three key specifications to keep in mind when calculating the resistor divider values (R₁and R₂, see

图 7-4 or 图 8-3): voltage threshold (V_IT(ADJ)), resistor tolerance, and the SENSE pin current (I_SENSE). To ensure

that no accuracy is lost because of I_SENSE, the current through the resistor divider must be 100 times greater

than I_SENSE. Starting with R₂= 80.6 kΩ provides a 5-µA resistor divider current when V_SENSE= 0.4 V. To

calculate the nominal resistor values, use 方程式16:

V

IT(ADJ)

V

= V

+ R₁

ITN

IT(ADJ)

R₂

(16)

where

• V_ITNis the monitored falling threshold voltage and

• V_IT(ADJ)is the threshold voltage on the SENSE pin

Solving 方程式 16 for R₁gives the nearest 1% resistor of 51.1 kΩ. Now, plug R₁back into 方程式 16 to get the

monitored threshold. With these resistor values, the nominal threshold is 0.65 V or 6.6%.

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To calculate the minimum and maximum threshold variation including the tolerances of the resistors, threshold

voltage, and sense current, use 方程式17 and 方程式18.

≈

’

÷

◊

V

IT(ADJ)min

V

= V

+ R_1(min)

+I_SENSE(min)= 0.641V

∆

«

÷

ITN(min)

IT(ADJ)min

R_2(max)

(17)

(18)

≈

’

÷

◊

V

IT(ADJ)max

V

= V

+ R_1(max)

+I_SENSE(max)= 0.667 V

∆

«

÷

ITN(max)

IT(ADJ)max

R_2(min)

where

• V_ITNis the falling monitored threshold voltage

• V_IT(ADJ)is the sense voltage threshold and

• I_SENSEis the sense pin current

The calculated tolerance on R₁and R₂is 1%.

8.2.2.3 Application Curves

VDD

2V/div

158 ms

2V/div

WDI

RESET

2V/div

7.6 seconds

WDO

2V/div

SET1

2V/div

RESET

2V/div

WDO

50ms/div

2V/div

1s/div

图8-14. Typical WDI Signal

图8-13. Startup Without a WDI Signal

9 Power Supply Recommendations

This device is designed to operate from an input supply with a voltage range between 1.6 V and 6.5 V. An input

supply capacitor is not required for this device; however, if the input supply is noisy, then good analog practice is

to place a 0.1-µF capacitor between the VDD pin and the GND pin.

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10 Layout

10.1 Layout Guidelines

Make sure that the connection to the VDD pin is low impedance. Good analog design practice recommends

placing a 0.1-µF ceramic capacitor as near as possible to the VDD pin. If a capacitor is not connected to the

CRST pin, then minimize parasitic capacitance on this pin so the RESET delay time is not adversely affected.

• Make sure that the connection to the VDD pin is low impedance. Good analog design practice is to place a

0.1-µF ceramic capacitor as near as possible to the VDD pin.

• If a C_CRSTcapacitor or pullup resistor is used, place these components as close as possible to the CRST pin.

If the CRST pin is left unconnected, make sure to minimize the amount of parasitic capacitance on the pin.

• If a C_CWDcapacitor or pullup resistor is used, place these components as close as possible to the CWD pin. If

the CWD pin is left unconnected, make sure to minimize the amount of parasitic capacitance on the pin.

• Place the pullup resistors on RESET and WDO as close to the pin as possible.

10.2 Layout Example

C_VDD

GND Plane

Vin

R_PU1

1

2

3

4

5

10

9

SENSE

RESET

WDO

Vin

C_CWD

VDD

CWD

SET0

CRST

GND

8

R_PU2

C_CRST

7

WDI

6

SET1

Vin

Denotes a via.

图10-1. Typical Layout for the TPS3850

36

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Product Folder Links: TPS3850

TPS3850

www.ti.com.cn

ZHCSFP2B –OCTOBER 2016 –REVISED SEPTEMBER 2021

11 Device and Documentation Support

11.1 Device Support

11.1.1 Device Nomenclature

表11-1. Device Nomenclature

DESCRIPTION

NOMENCLATURE

VALUE

TPS3850

—

(high-accuracy supervisor with window watchdog)

X

G

H

V_IT+(OV)= 4%; V_IT–(UV)= –4%

V_IT+(OV)= 7%; V_IT–(UV)= –7%

(nominal thresholds as a percent of the nominal

monitored voltage)

01

09

115

12

18

25

30

33

50

0.4 V

0.9 V

1.15 V

1.2 V

1.8 V

2.5 V

3.0 V

3.3 V

5.0 V

yy(y)

(nominal monitored voltage option)

11.2 Documentation Support

11.2.1 Related Documentation

For related documentation see the following:

• TPS3890 Low Quiescent Current, 1% Accurate Supervisor with Programmable Delay

• Optimizing Resistor Dividers at a Comparator Input

• TPS3850EVM-781 Evaluation Module

11.3 接收文档更新通知

要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新进行注册，即可每周接收产品信息更

改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

11.4 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的《使用条款》。

11.5 Trademarks

TI E2E^™is a trademark of Texas Instruments.

所有商标均为其各自所有者的财产。

11.6 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

11.7 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

Submit Document Feedback

37

Product Folder Links: TPS3850

TPS3850

www.ti.com.cn

ZHCSFP2B –OCTOBER 2016 –REVISED SEPTEMBER 2021

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

38

Submit Document Feedback

Product Folder Links: TPS3850

重要声明和免责声明

TI 提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，不保证没

有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担保。

这些资源可供使用TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的TI 产品，(2) 设计、验

证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。这些资源如有变更，恕不另行通知。TI 授权您仅可

将这些资源用于研发本资源所述的TI 产品的应用。严禁对这些资源进行其他复制或展示。您无权使用任何其他TI 知识产权或任何第三方知

识产权。您应全额赔偿因在这些资源的使用中对TI 及其代表造成的任何索赔、损害、成本、损失和债务，TI 对此概不负责。

TI 提供的产品受TI 的销售条款(https:www.ti.com/legal/termsofsale.html) 或ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI

提供这些资源并不会扩展或以其他方式更改TI 针对TI 产品发布的适用的担保或担保免责声明。重要声明

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

PACKAGE MATERIALS INFORMATION

www.ti.com

7-Nov-2021

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TPS3850G12DRCR

TPS3850G12DRCT

TPS3850G18DRCR

TPS3850G18DRCT

TPS3850G30DRCR

TPS3850G30DRCT

TPS3850G33DRCR

TPS3850G33DRCT

TPS3850G50DRCR

TPS3850G50DRCT

TPS3850H01DRCR

TPS3850H01DRCT

TPS3850H12DRCR

TPS3850H12DRCT

TPS3850H18DRCR

TPS3850H18DRCT

TPS3850H30DRCR

TPS3850H30DRCT

VSON

DRC

10

3000

250

330.0

180.0

330.0

180.0

330.0

180.0

330.0

180.0

330.0

180.0

330.0

180.0

330.0

180.0

330.0

180.0

330.0

180.0

12.4

3.3

1.1

8.0

12.0

Q2

3000

250

3000

250

3000

250

3000

250

3000

250

3000

250

3000

250

3000

250

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

7-Nov-2021

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TPS3850H33DRCR

TPS3850H33DRCT

TPS3850H50DRCR

TPS3850H50DRCT

VSON

DRC

10

3000

250

330.0

180.0

330.0

180.0

12.4

3.3

1.1

8.0

12.0

Q2

3000

250

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

TPS3850G12DRCR

TPS3850G12DRCT

TPS3850G18DRCR

TPS3850G18DRCT

TPS3850G30DRCR

TPS3850G30DRCT

TPS3850G33DRCR

TPS3850G33DRCT

TPS3850G50DRCR

TPS3850G50DRCT

TPS3850H01DRCR

TPS3850H01DRCT

TPS3850H12DRCR

VSON

DRC

10

3000

250

367.0

210.0

367.0

210.0

367.0

210.0

367.0

210.0

367.0

210.0

367.0

210.0

367.0

185.0

367.0

185.0

367.0

185.0

367.0

185.0

367.0

185.0

367.0

185.0

367.0

35.0

3000

250

3000

250

3000

250

3000

250

3000

250

3000

Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

7-Nov-2021

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

TPS3850H12DRCT

TPS3850H18DRCR

TPS3850H18DRCT

TPS3850H30DRCR

TPS3850H30DRCT

TPS3850H33DRCR

TPS3850H33DRCT

TPS3850H50DRCR

TPS3850H50DRCT

VSON

DRC

10

250

3000

250

210.0

367.0

210.0

367.0

210.0

367.0

210.0

367.0

210.0

185.0

367.0

185.0

367.0

185.0

367.0

185.0

367.0

185.0

35.0

3000

250

3000

250

3000

250

Pack Materials-Page 3

GENERIC PACKAGE VIEW

DRC 10

3 x 3, 0.5 mm pitch

VSON - 1 mm max height

PLASTIC SMALL OUTLINE - NO LEAD

This image is a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4226193/A

www.ti.com

PACKAGE OUTLINE

DRC0010J

VSON - 1 mm max height

SCALE 4.000

PLASTIC SMALL OUTLINE - NO LEAD

3.1

2.9

B

A

PIN 1 INDEX AREA

3.1

2.9

1.0

0.8

C

SEATING PLANE

0.08 C

0.05

0.00

1.65 0.1

2X (0.5)

(0.2) TYP

EXPOSED

THERMAL PAD

4X (0.25)

5

6

2X

2

11

SYMM

2.4 0.1

10

1

8X 0.5

0.30

0.18

10X

SYMM

PIN 1 ID

0.1

C A B

C

(OPTIONAL)

0.05

0.5

0.3

10X

4218878/B 07/2018

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT

DRC0010J

VSON - 1 mm max height

PLASTIC SMALL OUTLINE - NO LEAD

(1.65)

(0.5)

10X (0.6)

1

10

10X (0.24)

11

(2.4)

(3.4)

SYMM

(0.95)

8X (0.5)

6

5

(R0.05) TYP

(

0.2) VIA

TYP

(0.25)

(0.575)

SYMM

(2.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:20X

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

EXPOSED METAL

SOLDER MASK

OPENING

METAL

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

NON SOLDER MASK

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4218878/B 07/2018

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com

EXAMPLE STENCIL DESIGN

DRC0010J

VSON - 1 mm max height

PLASTIC SMALL OUTLINE - NO LEAD

2X (1.5)

(0.5)

SYMM

EXPOSED METAL

TYP

11

10X (0.6)

1

10

(1.53)

10X (0.24)

2X

(1.06)

SYMM

(0.63)

8X (0.5)

6

5

(R0.05) TYP

4X (0.34)

4X (0.25)

(2.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD 11:

80% PRINTED SOLDER COVERAGE BY AREA

SCALE:25X

4218878/B 07/2018

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担

保。

这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验

证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。

这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。

您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成

本、损失和债务，TI 对此概不负责。

TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改

TI 针对 TI 产品发布的适用的担保或担保免责声明。

TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	TPS3850
厂家：	TEXAS INSTRUMENTS
描述：	用于进行 OV 和 UV 监控的精密窗口监控器，具有窗口看门狗计时器和可编程延迟监控
文件：	总50页 (文件大小：3250K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TPS3850 [TI]

相关型号：

TPS3850-Q1

TPS3850G09QDRCRQ1

TPS3850G12DRCR

TPS3850G12DRCT

TPS3850G12QDRCRQ1

TPS3850G18DRCR

TPS3850G18DRCT

TPS3850G18QDRCRQ1

TPS3850G25QDRCRQ1

TPS3850G30DRCR

TPS3850G30DRCT

TPS3850G30QDRCRQ1