TPS3851G18EDRBR [TI]
具有集成看门狗计时器的高精度电压监控器 | DRB | 8 | -40 to 125;型号: | TPS3851G18EDRBR |
厂家: | TEXAS INSTRUMENTS |
描述: | 具有集成看门狗计时器的高精度电压监控器 | DRB | 8 | -40 to 125 监控 |
文件: | 总37页 (文件大小:1942K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
TPS3851
ZHCSFP1A –NOVEMBER 2016 –REVISED SEPTEMBER 2021
TPS3851 集成有看门狗定时器的高精度电压监控器
1 特性
3 说明
• 输入电压范围:VDD = 1.6 V 至6.5 V
• 0.8% 电压阈值精度
• 低静态电流:IDD = 10µA(典型值)
• 用户可编程看门狗超时
• 开漏输出
TPS3851 完美结合了高精度电压监控器和可编程看门
狗定时器。TPS3851 比较器在 VDD 引脚上可实现
0.8% 的精度
(–40°C 至 +125°C),针对欠压 (VITN) 阈值。
TPS3851 还包含与欠压阈值相关的高精度迟滞,因此
成为了紧容差系统的理想之选。该监控器的 RESET 延
迟具备15% 精度、高精密延迟时间。
• 高精度欠压监控:
– 支持1.8 V 到5.0V 常见电压轨
– 支持4% 和7% 欠压阈值
– 0.5% 迟滞
TPS3851 包含可编程窗口看门狗计时器,广泛适用于
各种应用。专用看门狗输出 (WDO) 有助于提高分辨
率,从而帮助确定出现故障情况的根本原因。看门狗超
时可通过外部电容编程,也可以采用工厂编程的默认延
迟设置。可通过逻辑引脚禁用看门狗,避免在开发过程
中出现意外的看门狗超时。
• 看门狗禁用功能
• 出厂编程的精密看门狗和复位计时器
• 手动复位输入(MR)
• 采用小型3mm × 3mm 8 引脚VSON 封装
• 结工作温度范围:
–40°C 至+125°C
TPS3851 采用小型 3.00mm × 3.00mm 8 引脚 VSON
封装。
2 应用
器件信息
封装(1)
• WLAN/Wi-Fi 接入点
• 无线安防摄像头
• IP 网络摄像机
封装尺寸(标称值)
器件型号
TPS3851
VSON (8)
3.00mm × 3.00mm
• 串式逆变器
• 血压监护仪
• 电表
(1) 如需了解所有可用封装,请参阅数据表末尾的可订购产品附
录。
0.5
1.8 V
Unit 1
Unit 2
Unit 3
Unit 4
Unit 5
Average
0.3
0.1
TPS3851
VDD
Microcontroller
VDD
RESET
WDO
RESET
-0.1
-0.3
-0.5
SET1
NMI
MR
WDI
GPIO
CWD
GND
GND
-50
-25
0
25
50
75
100
125
Temperature (èC)
Copyright © 2016, Texas Instruments Incorporated
欠压阈值(VITN) 精度与温度间的关系
全集成微控制器监控电路
本文档旨在为方便起见,提供有关TI 产品中文版本的信息,以确认产品的概要。有关适用的官方英文版本的最新信息,请访问
www.ti.com,其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前,请务必参考最新版本的英文版本。
English Data Sheet: SBVS300
TPS3851
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ZHCSFP1A –NOVEMBER 2016 –REVISED SEPTEMBER 2021
Table of Contents
7.4 Device Functional Modes..........................................14
8 Application and Implementation..................................15
8.1 Application Information............................................. 15
8.2 Typical Application.................................................... 18
9 Power Supply Recommendations................................21
10 Layout...........................................................................22
10.1 Layout Guidelines................................................... 22
10.2 Layout Example...................................................... 22
11 Device and Documentation Support..........................23
11.1 Device Support........................................................23
11.2 Documentation Support.......................................... 23
11.3 接收文档更新通知................................................... 23
11.4 支持资源..................................................................23
11.5 Trademarks............................................................. 23
11.6 Electrostatic Discharge Caution..............................23
11.7 术语表..................................................................... 23
12 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................5
6.5 Electrical Characteristics.............................................5
6.6 Timing Requirements..................................................6
6.7 Timing Diagrams.........................................................7
6.8 Typical Characteristics................................................8
7 Detailed Description......................................................11
7.1 Overview................................................................... 11
7.2 Functional Block Diagram......................................... 11
7.3 Feature Description...................................................11
Information.................................................................... 24
4 Revision History
注:以前版本的页码可能与当前版本的页码不同
Changes from Revision * (November 2016) to Revision A (September 2021)
Page
• 更新了整个文档中的表格、图和交叉参考的编号格式.........................................................................................1
• 删除了“±15% 的WDT 和RST 延迟”..............................................................................................................1
• 添加了“在VDD 引脚上”..................................................................................................................................1
• Changed VESD values to ±4000 V and ±1000 V................................................................................................. 4
• Changed ICWD min and max spec ......................................................................................................................5
• Changed VCWD min and max spec .................................................................................................................... 5
• Added a footnote to for tINIT ............................................................................................................................... 6
• Updated tWDU min and max multipliers from 0.85 and 1.15 to 0.905 and 1.095 respectively...........................15
• Updated tWDU min and max values for all capacitors........................................................................................15
• Updated equation 6 and 7 to replace 0.85 and 1.15 with 0.905 and 1.095 respectively.................................. 19
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5 Pin Configuration and Functions
VDD
CWD
MR
1
2
3
4
8
7
6
5
RESET
WDO
WDI
Thermal
Pad
GND
SET1
Not to scale
图5-1. DRB Package: TPS3851
3-mm × 3-mm VSON-8
Top View
表5-1. Pin Functions
NAME
NO.
I/O
DESCRIPTION
Programmable watchdog timeout input. The watchdog timeout is set by connecting a capacitor between this pin and
ground. Connecting via a 10-kΩresistor to VDD or leaving unconnected further enables the selection of the preset
watchdog timeouts; see the CWD Functionality section.
CWD
2
I
The TPS3851 determines the watchdog timeout using either Equation 1 or Equation 2 with standard or extended
timing, respectively.
GND
MR
4
3
Ground pin
—
Manual reset pin. A logical low on this pin issues a RESET. This pin is internally pulled up to VDD. RESET remains
low for a fixed reset delay (tRST) time after MR is deasserted (high).
I
Reset output. Connect RESET using a 1-kΩto 100-kΩresistor to the correct pullup voltage rail (VPU). RESET goes
low when VDD goes below the undervoltage threshold (VITN). When VDD is within the normal operating range, the
RESET timeout-counter starts. At completion, RESET goes high. During startup, the state of RESET is undefined
below the specified power-on-reset (POR) voltage (VPOR). Above POR, RESET goes low and remains low until the
monitored voltage is within the correct operating range (above VITN+VHYST) and the RESET timeout is complete.
RESET
8
O
Logic input. Grounding the SET1 pin disables the watchdog timer. SET1 and CWD select the watchdog timeouts; see
the SET1 section.
SET1
VDD
5
1
I
I
Supply voltage pin. For noisy systems, connecting a 0.1-μF bypass capacitor is recommended.
Watchdog input. A falling edge must occur at WDI before the timeout (tWD) expires.
When the watchdog is not in use, the SET1 pin can be used to disable the watchdog. WDI is ignored when RESET or
WDO are low (asserted) and when the watchdog is disabled. If the watchdog is disabled, WDI cannot be left
unconnected and must be driven to either VDD or GND.
WDI
6
7
I
Watchdog output. Connect WDO with a 1-kΩto 100-kΩresistor to the correct pullup voltage rail (VPU). WDO goes
low (asserts) when a watchdog timeout occurs. WDO only asserts when RESET is high. When a watchdog timeout
occurs, WDO goes low (asserts) for the set RESET timeout delay (tRST). When RESET goes low, WDO is in a high-
impedance state.
WDO
O
Thermal pad
Connect the thermal pad to a large-area ground plane. The thermal pad is internally connected to GND.
—
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
V
Supply voltage range
Output voltage range
VDD
7
–0.3
–0.3
–0.3
–0.3
RESET, WDO
SET1, WDI, MR
CWD
7
V
7
VDD + 0.3 (3)
±20
Voltage ranges
V
Output pin current
RESET, WDO
mA
mA
Input current (all pins)
±20
Continuous total power dissipation
See 节6.4
(2)
(2)
Operating junction, TJ
Operating free-air, TA
Storage, Tstg
150
150
150
–40
–40
–65
Temperature
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) Assume that TJ = TA as a result of the low dissipated power in this device.
(3) The absolute maximum rating is VDD + 0.3 V or 7.0 V, whichever is smaller.
6.2 ESD Ratings
VALUE
±4000
±1000
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 500-V HBM is possible with the necessary precautions.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 250-V CDM is possible with the necessary precautions.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
TYP
MAX
UNIT
V
VDD
Supply pin voltage
1.6
6.5
VSET1
CCWD
CWD
RPU
SET1 pin voltage
0
6.5
V
Watchdog timing capacitor
Pullup resistor to VDD
Pullup resistor, RESET and WDO
RESET pin current
0.1 (1) (2)
1000 (1) (2)
nF
9
1
10
10
11
100
10
kΩ
kΩ
mA
mA
°C
IRESET
IWDO
TJ
Watchdog output current
Junction temperature
10
125
–40
(1) Using standard timing with a CCWD capacitor of 0.1 nF or 1000 nF gives a tWD(typ) of 0.704 ms or 3.23 seconds, respectively.
(2) Using extended timing with a CCWD capacitor of 0.1 nF or 1000 nF gives a tWD(typ) of 62.74 ms or 77.45 seconds, respectively.
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6.4 Thermal Information
TPS3851
THERMAL METRIC (1)
DRB (VSON)
8 PINS
50.7
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
51.6
25.8
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
1.3
ψJT
25.8
ψJB
RθJC(bot)
7.1
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report.
6.5 Electrical Characteristics
at VITN + VHYST ≤VDD ≤6.5 V over the operating temperature range of –40°C ≤TA, T A ≤125°C (unless otherwise
noted); the open-drain pullup resistors are 10 kΩfor each output; typical values are at TA = 25°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
GENERAL CHARACTERISTICS
(1) (2) (3)
VDD
IDD
Supply voltage
Supply current
1.6
6.5
19
V
10
µA
RESET FUNCTION
(2)
VPOR
Power-on reset voltage
IRESET = 15 µA, VOL(MAX) = 0.25 V
0.8
V
V
(1)
VUVLO
Undervoltage lockout voltage
1.35
Undervoltage threshold accuracy, entering
RESET
VITN
VDD falling
VITN + 0.8%
V
ITN –0.8%
VHYST
IMR
Hysteresis voltage
VDD rising
VMR = 0 V
0.2%
500
0.5%
620
0.8%
700
MR pin internal pullup current
nA
WATCHDOG FUNCTION
ICWD
VCWD
VOL
CWD pin charge current
CWD = 0.5 V
347
375
403
1.224
0.4
nA
V
CWD pin threshold voltage
RESET, WDO output low
1.196
1.21
VDD = 5 V, ISINK = 3 mA
V
RESET, WDO output leakage current,
open-drain
VDD = VITN + VHYST
VRESET = VWDO = 6.5 V
,
ID
1
µA
VIL
Low-level input voltage ( MR, SET1)
High-level input voltage ( MR, SET1)
Low-level input voltage (WDI)
0.25
V
V
V
V
VIH
0.8
VIL(WDI)
VIH(WDI)
0.3 × VDD
High-level input voltage (WDI)
0.8 × VDD
(1) When VDD falls below VUVLO, RESET is driven low.
(2) When VDD falls below VPOR, RESET and WDO are undefined.
(3) During power-on, VDD must be a minimum 1.6 V for at least 300 µs before RESET correlates with VDD
.
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6.6 Timing Requirements
at VITN + VHYST ≤VDD ≤6.5 V over the operating temperature range of –40°C ≤TA, T A ≤125°C (unless otherwise
noted); the open-drain pullup resistors are 10 kΩfor each output; typical values are at TA = 25°C
MIN
NOM
MAX UNIT
GENERAL
tINIT
CWD pin evaluation period (1)
381
1
µs
µs
µs
Minimum MR, SET1 pin pulse duration
Startup delay (2)
300
RESET FUNCTION
tRST
Reset timeout period
170
200
35
230 ms
VDD = VITN + VHYST + 2.5%
tRST-DEL VDD to RESET delay
µs
ns
17
VDD = VITN –2.5%
tMR-DEL MR to RESET delay
200
WATCHDOG FUNCTION
CWD = NC, SET1 = 0 (4)
CWD = NC, SET1 = 1 (4)
Watchdog disabled
1360
1600
1840 ms
Watchdog timeout (3)
CWD = 10 kΩto VDD,
tWD
Watchdog disabled
SET1 = 0 (4)
CWD = 10 kΩto VDD,
170
200
150
230 ms
µs
SET1 = 1 (4)
tWD-
Setup time required for device to respond to changes on WDI after
being enabled
setup
Minimum WDI pulse duration
50
50
ns
ns
tWD-del WDI to WDO delay
(1) Refer to 节8.1.1.2
(2) During power-on, VDD must be a minimum 1.6 V for at least 300 µs before RESET correlates with VDD
(3) The fixed watchdog timing covers both standard and extended versions.
(4) SET1 = 0 means VSET1 < VIL; SET1 = 1 means VSET1 > VIH.
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6.7 Timing Diagrams
VITN + VHYST
VITN
tRST-DEL
VDD
VITN
tRST
VPOR
tRST
RESET
WDI
(1)
t < tWD t = tWD
t < tWD
X
X
WDO
tRST
A. See 图6-2 for WDI timing requirements.
图6-1. Timing Diagram
Correct
Operation
WDI
WDO
Late Fault
WDI
WDO
Valid
Region
Timing
tWD(MIN)
tWD(TYP)
tWD(MAX)
= Tolerance Window
图6-2. Watchdog Timing Diagram
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6.8 Typical Characteristics
all typical characteristics curves are taken at 25°C with 1.6 V ≤VDD ≤6.5 V (unless other wise noted)
16
12
8
0.7
0.6
0.5
0.4
0.3
-40èC
0èC
25èC
105èC
125èC
4
VIL
VIH
0
0
-50
-25
25
50
75
100
125
0
1
2
3
4
5
6
7
Temperature (èC)
VDD (V)
VDD = 1.6 V
图6-3. Supply Current vs VDD
图6-4. MR Threshold vs Temperature
380
376
372
368
364
0.5
Unit 1
Unit 2
Unit 3
Unit 4
Unit 5
Average
0.3
0.1
-0.1
-0.3
-0.5
1.6 V
6.5 V
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Temperature (èC)
Temperature (èC)
图6-5. CWD Charging Current vs Temperature
TPS3851G18, VITN = 1.728 V
图6-6. VITN + VHYST Accuracy vs Temperature
0.5
0.3
0.5
0.3
Unit 1
Unit 2
Unit 3
Unit 4
Unit 5
Average
Unit 1
Unit 2
Unit 3
Unit 4
Unit 5
Average
0.1
0.1
-0.1
-0.3
-0.5
-0.1
-0.3
-0.5
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Temperature (èC)
Temperature (èC)
TPS3851G18, VITN = 1.728 V
图6-7. VITN Accuracy vs Temperature
TPS3851G50, VITN = 4.8 V
图6-8. VITN + VHYST Accuracy vs Temperature
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6.8 Typical Characteristics (continued)
all typical characteristics curves are taken at 25°C with 1.6 V ≤VDD ≤6.5 V (unless other wise noted)
0.5
0.3
50
45
40
35
30
25
20
15
10
5
Unit 1
Unit 2
Unit 3
Unit 4
Unit 5
Average
0.1
-0.1
-0.3
-0.5
0
-50
-25
0
25
50
75
100
125
-0.8 -0.6 -0.4 -0.2
0
VITN + VHYST Accuracy (%)
0.2
0.4
0.6
0.8
Temperature (èC)
TPS3851G50, VITN = 4.8 V
图6-9. VITN Accuracy vs Temperature
Includes G and H versions; 1.8-V, 2.5-V, 3.0-V, 3.3-V, and 5-V
thresholds; total units = 36,627
图6-10. VITN + VHYST Accuracy Histogram
50
45
40
35
30
25
20
15
10
5
80
60
40
20
0
0
-0.8 -0.6 -0.4 -0.2
0
VITN Accuracy (%)
0.2
0.4
0.6
0.8
0.2
0.35
0.5
Hysteresis (%)
0.8
Includes G and H versions; 1.8-V, 2.5-V, 3.0-V, 3.3-V, and 5-V
thresholds; total units = 36,627
Includes G and H versions; 1.8-V, 2.5-V, 3.0-V, 3.3-V, and 5-V
thresholds; total units = 36,627
图6-11. VITN Accuracy Histogram
图6-12. Hysteresis Histogram
1.6
1.6
-40èC
-40èC
0èC
0èC
1.4
1.2
1
1.4
1.2
1
25èC
105èC
125èC
25èC
105èC
125èC
0.8
0.6
0.4
0.2
0
0.8
0.6
0.4
0.2
0
0
1
2
3
IRESET (mA)
4
5
6
0
1
2
3
IRESET (mA)
4
5
6
VDD = 1.6 V
VDD = 6.5 V
图6-13. Low-Level RESET Voltage vs RESET Current
图6-14. Low-Level RESET Voltage vs RESET Current
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6.8 Typical Characteristics (continued)
all typical characteristics curves are taken at 25°C with 1.6 V ≤VDD ≤6.5 V (unless other wise noted)
100
90
80
70
60
50
40
30
20
10
0
50
45
40
35
30
25
20
15
10
5
-40èC
0èC
25èC
105èC
125èC
-40èC
0èC
25èC
105èC
125èC
0
0
2
4
6
Overdrive (%)
8
10
0
2
4
6
Overdrive (%)
8
10
TPS3851G18 entering undervoltage
TPS3851G50 entering undervoltage
图6-15. Propagation Delay vs Overdrive
图6-16. Propagation Delay vs Overdrive
210
205
200
195
190
210
205
200
195
190
-40èC
0èC
25èC
105èC
125èC
-40èC
0èC
25èC
105èC
125èC
0
2
4
6
8
10
0
2
4
6
8
10
Overdrive (%)
TPS3851G18 exiting undervoltage
图6-17. Propagation Delay (tRST) vs Overdrive
Overdrive (%)
TPS3851G50 exiting undervoltage
图6-18. Propagation Delay (tRST) vs Overdrive
25
20
15
10
5
25
20
15
10
5
Overdrive = 3%
Overdrive = 5%
Overdrive = 7%
Overdrive = 9%
Overdrive = 10%
Overdrive = 3%
Overdrive = 5%
Overdrive = 7%
Overdrive = 9%
Overdrive = 10%
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Temperature (èC)
Temperature (èC)
VITN = 1.728 V
VITN = 4.8 V
图6-19. High-to-Low Glitch Immunity vs Temperature
图6-20. High-to-Low Glitch Immunity vs Temperature
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7 Detailed Description
7.1 Overview
The TPS3851 is a high-accuracy voltage supervisor with an integrated watchdog timer. This device includes a
precision undervoltage supervisor with a threshold that achieves 0.8% accuracy over the specified temperature
range of –40°C to +125°C. In addition, the TPS3851 includes accurate hysteresis on the threshold, making the
device ideal for use with tight tolerance systems where voltage supervisors must ensure a RESET before the
minimum supply tolerance of the microprocessor or system-on-a-chip (SoC) is reached. There are two options
for the watchdog timing standard and extended timing. To get standard timing use the TPS3851Xyy(y)S, for
extended timing use the TPS3851Xyy(y)E.
7.2 Functional Block Diagram
VDD
R1
RESET
R2
Precision
Clock
Reference
VDD
WDO
State
Machine
Cap
Control
CWD
WDI
MR
SET1
GND
A. Note: R1 + R2 = 4.5 MΩ.
7.3 Feature Description
7.3.1 RESET
Connect RESET to VPU through a 1-kΩ to 100-kΩ pullup resistor. RESET remains high (deasserted) when VDD
is greater than the negative threshold voltage (VITN). If VDD falls below the negative threshold (VITN), then
RESET is asserted, driving the RESET pin to low impedance. When VDD rises above VITN + VHYST, a delay
circuit is enabled that holds RESET low for a specified reset delay period (tRST). When the reset delay has
elapsed, the RESET pin goes to a high-impedance state and uses a pullup resistor to hold RESET high. The
pullup resistor must be connected to the proper voltage rail to allow other devices to be connected at the correct
interface voltage. To ensure proper voltage levels, give some consideration when choosing the pullup resistor
values. The pullup resistor value is determined by output logic low voltage (VOL), capacitive loading, leakage
current (ID), and the current through the RESET pin IRESET
.
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7.3.2 Manual Reset MR
The manual reset ( MR) input allows a processor or other logic circuits to initiate a reset. A logic low on MR
causes RESET to assert. After MR returns to a logic high and VDD is above VITN + VHYST, RESET is deasserted
after the reset delay time (tRST). If MR is not controlled externally, then MR can either be connected to VDD or left
floating because the MR pin is internally pulled up.
7.3.3 UV Fault Detection
The TPS3851 features undervoltage detection for common rails between 1.8 V and 5 V. The voltage is
monitored on the input rail of the device. If VDD drops below VITN, then RESET is asserted (driven low). When
V
DD is above VITN + VHYST, RESET deasserts after tRST, as shown in 图7-1. The internal comparator has built-in
hysteresis that provides some noise immunity and ensures stable operation. Although not required in most
cases, for noisy applications, good analog design practice is to place a 1-nF to 100-nF bypass capacitor close to
the VDD pin to reduce sensitivity to transient voltages on the monitored signal.
VDD
VITN + VHYST
VITN
Undervoltage Limit
tRST
RESET
图7-1. Undervoltage Detection
7.3.4 Watchdog Mode
This section provides information for the watchdog mode of operation.
7.3.4.1 CWD
The CWD pin provides the user the functionality of both high-precision, factory-programmed watchdog timing
options and user-programmable watchdog timing. The TPS3851 features three options for setting the watchdog
timer: connecting a capacitor to the CWD pin, connecting a pullup resistor to VDD, and leaving the CWD pin
unconnected. The configuration of the CWD pin is evaluated by the device every time VDD enters the valid
region (VITN + VHYST < VDD). The pin evaluation is controlled by an internal state machine that determines which
option is connected to the CWD pin. The sequence of events typically takes 381 μs (tINIT) to determine if the
CWD pin is left unconnected, pulled-up through a resistor, or connected to a capacitor. If the CWD pin is being
pulled up to VDD, a 10-kΩresistor is required.
7.3.4.2 Watchdog Input WDI
WDI is the watchdog timer input that controls the WDO output. The WDI input is triggered by the falling edge of
the input signal. To ensure proper functionality of the watchdog timer, always issue the WDI pulse before
tWD(min). If the pulse is issued in this region, then WDO remains unasserted. Otherwise, the device asserts WDO,
putting the WDO pin into a low-impedance state.
The watchdog input (WDI) is a digital pin. To ensure there is no increase in IDD, drive the WDI pin to either VDD
or GND at all times. Putting the pin to an intermediate voltage can cause an increase in supply current (IDD
)
because of the architecture of the digital logic gates. When RESET is asserted, the watchdog is disabled and all
signals input to WDI are ignored. When RESET is no longer asserted, the device resumes normal operation and
no longer ignores the signal on WDI. If the watchdog is disabled, drive the WDI pin to either VDD or GND.
图7-2 shows the valid region for a WDI pulse to be issued to prevent WDO from being triggered and pulled low.
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Correct
Operation
WDI
WDO
Late Fault
WDI
WDO
Valid
Region
Timing
tWD(MIN)
tWD(TYP)
tWD(MAX)
= Tolerance Window
图7-2. Watchdog Timing Diagram
7.3.4.3 Watchdog Output WDO
The TPS3851 features a watchdog timer with an independent watchdog output (WDO). The independent
watchdog output provides the flexibility to flag a fault in the watchdog timing without performing an entire system
reset. When RESET is not asserted (high), the WDO signal maintains normal operation. When asserted, WDO
remains low for tRST. When the RESET signal is asserted (low), the WDO pin goes to a high-impedance state.
When RESET is unasserted, the watchdog timer resumes normal operation.
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7.3.4.4 SET1
The SET1 pin can enable and disable the watchdog timer. If SET1 is set to GND, the watchdog timer is disabled
and WDI is ignored. If the watchdog timer is disabled, drive the WDI pin to either GND or VDD to ensure that
there is no increase in IDD. When SET1 is logic high, the watchdog operates normally. The SET1 pin can be
changed dynamically; however, if the watchdog is going from disabled to enabled there is a 150-µs setup time
where the watchdog does not respond to changes on WDI, as shown in 图7-3.
VDD
RESET
SET1
150 µs
Watchdog
Enabled/Disabled
Enabled
Disabled
Enabled
图7-3. Enabling and Disabling the Watchdog
7.4 Device Functional Modes
表7-1 summarises the functional modes of the TPS3851.
表7-1. Device Functional Modes
VDD
WDI
---
WDO
---
RESET
Undefined
Low
VDD < VPOR
Ignored
Ignored
High
High
V
POR ≤VDD < VDD(min)
Low
V
DD(min) ≤VDD ≤VITN + VHYST
(1)
(2)
(3)
(3)
VDD > VITN
tPULSE < tWD(min)
tPULSE > tWD(min)
High
Low
High
High
(2)
VDD > VITN
(1) Only valid before VDD has gone above VITN + VHYST
(2) Only valid after VDD has gone above VITN + VHYST
(3) Where tpulse is the time between the falling edges on WDI.
.
.
7.4.1 VDD is Below VPOR ( VDD < VPOR
)
When VDD is less than VPOR, RESET is undefined and can be either high or low. The state of RESET largely
depends on the load that the RESET pin is experiencing.
7.4.2 Above Power-On-Reset, But Less Than VDD(min) (VPOR ≤VDD < VDD(min)
)
When the voltage on VDD is less than VDD(min), and greater than or equal to VPOR, the RESET signal is asserted
(logic low). When RESET is asserted, the watchdog output WDO is in a high-impedance state regardless of the
WDI signal that is input to the device.
7.4.3 Normal Operation (VDD ≥VDD(min)
)
When VDD is greater than or equal to VDD(min), the RESET signal is determined by VDD. When RESET is
asserted, WDO goes to a high-impedance state. WDO is then pulled high through the pullup resistor.
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8 Application and Implementation
Note
以下应用部分中的信息不属于TI 器件规格的范围,TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计,以确保系统功能。
8.1 Application Information
The following sections describe in detail proper device implementation, depending on the final application
requirements.
8.1.1 CWD Functionality
The TPS3851 features three options for setting the watchdog timer: connecting a capacitor to the CWD pin,
connecting a pullup resistor to VDD, and leaving the CWD pin unconnected. 图 8-1 shows a schematic drawing
of all three options. If this pin is connected to VDD through a 10-kΩ pullup resistor or left unconnected (high
impedance), then the factory-programmed watchdog timeouts are enabled; see the 节 8.1.1.1 section.
Otherwise, the watchdog timeout can be adjusted by placing a capacitor from the CWD pin to ground.
VDD
VDD
VDD
TPS3851
TPS3851
TPS3851
VDD
VDD
VDD
375 nA
375 nA
375 nA
CWD
CCWD
CWD
CWD
Cap
Control
Cap
Control
Cap
Control
User Programmable
Capacitor to GND
CWD
Unconnected
10 kΩ Resistor
to VDD
图8-1. CWD Charging Circuit
8.1.1.1 Factory-Programmed Timing Options
If using the factory-programmed timing options (listed in 表 8-1), the CWD pin must either be unconnected or
pulled up to VDD through a 10-kΩ pullup resistor. Using these options enables high-precision, 15% accurate
watchdog timing.
表8-1. Factory Programmed Watchdog Timing
INPUT
STANDARD AND EXTENDED TIMING WDT (tWD)
UNIT
CWD
NC
SET1
MIN
TYP
Watchdog disabled
1600
Watchdog disabled
200
MAX
0
1
0
1
NC
1360
1840
ms
ms
10 kΩto VDD
10 kΩto VDD
170
230
8.1.1.2 Adjustable Capacitor Timing
Adjustable capacitor timing is achievable by connecting a capacitor to the CWD pin. If a capacitor is connected
to CWD, then a 375-nA, constant-current source charges CCWD until VCWD = 1.21 V. 表 8-2 shows how to
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calculate tWD using 方程式 1 and 方程式 2 and the SET1 pin. The TPS3851 determines the watchdog timeout
with the formulas given in 方程式1 and 方程式2, where CCWD is in nanofarads and tWD is in milliseconds.
tWD(standard) (ms) = 3.23 x CCWD (nF) + 0.381 (ms)
tWD(extended) (ms) = 77.4 x CCWD (nF) + 55 (ms)
(1)
(2)
The TPS3851 is designed and tested using CCWD capacitors between 100 pF and 1 µF. Note that 方程式 1 and
方程式 2 are for ideal capacitors, capacitor tolerances vary the actual device timing. For the most accurate
timing, use ceramic capacitors with COG dielectric material. If a CCWD capacitor is used, 方程式 1 can be used
to set tWD for standard timing. Use 方程式 2 to calculate tWD for extended timing. 表8-3 shows the minimum and
maximum calculated tWD values using an ideal capacitor for both the standard and extended timing.
表8-2. Programmable CWD Timing
INPUT
STANDARD TIMING WDT (tWD
)
EXTENDED TIMING WDT (tWD)
UNIT
CWD
SET1
MIN
TYP
MAX
MIN
TYP
MAX
CCWD
CCWD
0
1
Watchdog disabled
Watchdog disabled
(1)
(2)
tWD(std) × 0.905
tWD(std)
tWD(std) × 1.095
tWD(ext) × 0.905
tWD(ext)
tWD(ext) × 1.095
ms
(1) Calculated from 方程式1 using an ideal capacitor.
(2) Calculated from 方程式2 using an ideal capacitor.
表8-3. tWD Values for Common Ideal Capacitor Values
STANDARD TIMING WDT (tWD
)
EXTENDED TIMING WDT (tWD)
CCWD
UNIT
MIN(1)
0.637
3.268
29.58
292.7
2923
TYP
0.704
3.611
32.68
323.4
3230
MAX(1)
0.771
3.954
35.79
354.1
3537
MIN(1)
56.77
119.82
750
TYP
62.74
132.4
829
MAX(1)
68.7
100 pF
1 nF
ms
ms
ms
ms
ms
144.98
908
10 nF
100 nF
1 μF
7054
7795
77455
8536
70096
84814
(1) The minimum and maximum values are calculated using an ideal capacitor.
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8.1.2 Overdrive Voltage
Forcing a RESET is dependent on two conditions: the amplitude VDD is beyond the trip point (ΔV1 and ΔV2),
and the length of time that the voltage is beyond the trip point (t1 and t2). If the voltage is just under the trip point
for a long period of time, RESET asserts and the output is pulled low. However, if VDD is just under the trip point
for a few nanoseconds, RESET does not assert and the output remains high. The length of time required for
RESET to assert can be changed by increasing the amount VDD goes under the trip point. If VDD is under the trip
point by 10%, the amount of time required for the comparator to respond is much faster and causes RESET to
assert much quicker than when barely under the trip point voltage. 方程式 3 shows how to calculate the
percentage overdrive.
Overdrive = |((VDD / VITX) –1) × 100% |
(3)
In 方程式3, VITX corresponds to the threshold trip point. If VDD is exceeding the positive threshold,
VITN + VHYST is used. VITN is used when VDD is falling below the negative threshold. In 图 8-2, t1 and t2
correspond to the amount of time that VDD is over the threshold; the propagation delay versus overdrive for VITN
and VITN + VHYST is illustrated in 图6-16 and 图6-18, respectively.
The TPS3851 is relatively immune to short positive and negative transients on VDD because of the overdrive
voltage curve.
ûV1
t1
VITN + VHYST
VDD
VITN
ûV2
t2
Time
图8-2. Overdrive Voltage
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8.2 Typical Application
1.8 V
VCORE
Microcontroller
RESET
TPS3851
VDD
TPS3890
RESET
WDO
WDI
VDD
MR
CT
SENSE
NMI
MR
RESET
SET1
GPIO
GND
4.7 µF
CWD
GND
GND
2.7 nF
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图8-3. Monitoring the Supply Voltage and Watchdog Supervision of a Microcontroller
8.2.1 Design Requirements
PARAMETER
DESIGN REQUIREMENT
DESIGN RESULT
Watchdog disable for initialization Watchdog must remain disabled for 5 seconds
5.02 seconds (typ)
1.8V CMOS
period
until logic enables the watchdog timer
1.8-V CMOS
Output logic voltage
Monitored rail
Watchdog timeout
1.8 V with a 5% threshold
10 ms typical
Worst-case VITN = 1.714 V –4.7%
tWD(min) = 7.3 ms, tWD(TYP) = 9.1 ms, tWD(max) = 11 ms
Maximum device current
consumption
50 µA
37 µA when RESET or WDO is asserted (1)
(1) Only includes the TPS3851G18S current consumption.
8.2.2 Detailed Design Procedure
8.2.2.1 Monitoring the 1.8-V Rail
The undervoltage comparator allows for precise voltage supervision of common rails between 1.8 V and 5.0 V.
This application calls for very tight monitoring of the rail with only 5% of variation allowed on the rail. To ensure
this requirement is met, the TPS3851G18S was chosen for its –4% threshold. To calculate the worst-case for
VITN, the accuracy must also be taken into account. The worst-case for VITN can be calculated by 方程式4:
VITN(Worst Case) = VITN(typ) x 0.992 = 1.8 x 0.96 x 0.992 = 1.714 V
(4)
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8.2.2.2 Calculating RESET and WDO Pullup Resistor
The TPS3851 uses an open-drain configuration for the RESET circuit, as shown in 图 8-4. When the FET is off,
the resistor pulls the drain of the transistor to VDD and when the FET is turned on, the FET attempts to pull the
drain to ground, thus creating an effective resistor divider. The resistors in this divider must be chosen to ensure
that VOL is below the maximum value. To choose the proper pullup resistor, there are three key specifications to
keep in mind: the pullup voltage (VPU), the recommended maximum RESET pin current (IRESET), and VOL. The
maximum VOL is 0.4 V, meaning that the effective resistor divider created must be able to bring the voltage on
the reset pin below 0.4 V with IRESET kept below 10 mA. For this example, with a VPU of 1.8 V, a resistor must be
chosen to keep IRESET below 50 μA because this value is the maximum consumption current allowed. To ensure
this specification is met, a pullup resistor value of 100 kΩwas selected, which sinks a maximum of 18 μA when
RESET or WDO is asserted. As illustrated in 图6-13, the RESET current is at
18 μA and the low-level output voltage is approximately zero.
VPU
RESET
RESET
CONTROL
图8-4. RESET Open-Drain Configuration
8.2.2.3 Setting the Watchdog
As illustrated in 图 8-1 there are three options for setting the watchdog timer. The design specifications in this
application require the programmable timing option (external capacitor connected to CWD). When a capacitor is
connected to the CWD pin, the watchdog timer is governed by 方程式 1 for the standard timing version. Note
that only the standard version is capable of meeting this timing requirement. 方程式 1 is only valid for ideal
capacitors, any temperature or voltage derating must be accounted for separately.
CCWD (nF) = (tWD(ms) –0.0381) / 3.23 = (10 –0.381) / 3.23 = 2.97 nF
(5)
The nearest standard capacitor value to 2.9 nF is 2.7 nF. Selecting 2.7 nF for the CCWD capacitor gives the
following minimum timing parameters:
tWD(MIN) = 0.905 x tWD(TYP) = 0.905 x (3.23 x 2.7 + 0.381) = 8.24 ms
tWD(MAX) = 1.095 x tWD(TYP) = 1.095 x (3.23 x 2.7 + 0.381) = 9.97 ms
(6)
(7)
Capacitor tolerance also influences tWD(MIN) and tWD(MAX). Select a ceramic COG dielectric capacitor for high
accuracy. For 2.7 nF, COG capacitors are readily available with 5% tolerances. This selection results in a 5%
decrease in tWD(MIN) and a 5% increase in tWD(MAX), giving 7.34 ms and 11 ms, respectively. To ensure proper
functionality, a falling edge must be issued before tWD(min). 图 8-6 illustrates that a WDI signal with a period of 5
ms keeps WDO from asserting.
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8.2.2.4 Watchdog Disabled During Initialization Period
The watchdog is often needed to be disabled during startup to allow for an initialization period. When the
initialization period is over, the watchdog timer is turned back on to allow the microcontroller to be monitored by
the TPS3851. To achieve this setup, SET1 must start at GND. In this design, SET1 is controlled by a TPS3890
supervisor. In this application, the TPS3890 was chosen to monitor VDD as well, which means that the RESET
on the TPS3890 stays low until VDD rises above VITN. When VDD comes up, the delay time can be adjusted
through the CT capacitor on the TPS3890. With this approach, the RESET delay can be adjusted from a
minimum of 25 μs to a maximum of 30 seconds. For this design, a typical delay of 5 seconds is needed before
the watchdog timer is enabled. The CT capacitor calculation (see the TPS3890 data sheet) yields an ideal
capacitance of 4.67 μF, giving a closest standard ceramic capacitor value of 4.7 μF. When connecting a 4.7-
μF capacitor from CT to GND, the typical delay time is 5 seconds. 图 8-5 shows that when the watchdog is
disabled, the WDO output remains high. However when SET1 goes high and there is no WDI signal, WDO
begins to assert. See the TPS3890 data sheet for detailed information on the TPS3890.
8.2.3 Glitch Immunity
图 8-8 shows the high-to-low glitch immunity for the TPS3851G18S with a 7% overdrive with VDD starting at 1.8
V. This curve shows that VDD can go below the threshold for at least 6 µs before RESET asserts.
8.2.4 Application Curves
Unless otherwise stated, application curves were taken at TA = 25°C.
VDD
2V/div
VDD
2V/div
6 seconds
SET1
5ms
2V/div
WDI
2V/div
WDO
2V/div
WDO
2V/div
RESET
2V/div
RESET
2V/div
1s/div
2ms/div
图8-5. Startup Without a WDI Signal
图8-6. Typical WDI Signal
VDD
VDD
500mV/div
500mV/div
6µs
WDO
WDO
2V/div
2V/div
195 ms
RESET
2V/div
RESET
2V/div
50ms/div
2µs/div
图8-7. Typical RESET Delay
图8-8. High-to-Low Glitch Immunity
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9 Power Supply Recommendations
This device is designed to operate from an input supply with a voltage range between 1.6 V and 6.5 V. An input
supply capacitor is not required for this device; however, if the input supply is noisy, then good analog practice is
to place a 0.1-µF capacitor between the VDD pin and the GND pin.
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10 Layout
10.1 Layout Guidelines
• Make sure that the connection to the VDD pin is low impedance. Good analog design practice is to place a
0.1-µF ceramic capacitor as near as possible to the VDD pin.
• If a CCWD capacitor or pullup resistor is used, place these components as close as possible to the CWD pin. If
the CWD pin is left unconnected, make sure to minimize the amount of parasitic capacitance on the pin.
• Place the pullup resistors on RESET and WDO as close to the pin as possible.
10.2 Layout Example
Vin
CVDD
RPU1
Vin
RPU2
1
2
3
4
8
7
6
5
Vin
CCWD
VDD
CWD
MR
RESET
WDO
WDI
GND
SET1
GND Plane
Denotes a via
图10-1. TPS3851 Recommended Layout
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Device Nomenclature
表11-1. Device Nomenclature
DESCRIPTION
NOMENCLATURE
VALUE
TPS3851
—
—
(high-accuracy supervisor with watchdog)
X
G
H
VITN = –4%
VITN = –7%
(nominal threshold as a percent of the nominal
monitored voltage)
18
25
30
33
50
S
1.8 V
2.5 V
yy(y)
3.0 V
(nominal monitored voltage option)
3.3 V
5.0 V
tWD (ms) = 3.23 x CWD (nF) + 0.381 (ms)
tWD (ms) = 77.4 x CWD (nF) + 55.2 (ms)
z
(nominal watchdog timeout period)
E
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation see the following:
• TPS3890 Low Quiescent Current, 1% Accurate Supervisor with Programmable Delay (SLVSD65)
• TPS3851EVM-780 Evaluation Module (SBVU033)
11.3 接收文档更新通知
要接收文档更新通知,请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册,即可每周接收产品信息更
改摘要。有关更改的详细信息,请查看任何已修订文档中包含的修订历史记录。
11.4 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料,可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范,并且不一定反映 TI 的观点;请参阅
TI 的《使用条款》。
11.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.7 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
Copyright © 2021 Texas Instruments Incorporated
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Product Folder Links: TPS3851
TPS3851
www.ti.com.cn
ZHCSFP1A –NOVEMBER 2016 –REVISED SEPTEMBER 2021
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2021 Texas Instruments Incorporated
24
Submit Document Feedback
Product Folder Links: TPS3851
重要声明和免责声明
TI 提供技术和可靠性数据(包括数据表)、设计资源(包括参考设计)、应用或其他设计建议、网络工具、安全信息和其他资源,不保证没
有瑕疵且不做出任何明示或暗示的担保,包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担保。
这些资源可供使用TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任:(1) 针对您的应用选择合适的TI 产品,(2) 设计、验
证并测试您的应用,(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。这些资源如有变更,恕不另行通知。TI 授权您仅可
将这些资源用于研发本资源所述的TI 产品的应用。严禁对这些资源进行其他复制或展示。您无权使用任何其他TI 知识产权或任何第三方知
识产权。您应全额赔偿因在这些资源的使用中对TI 及其代表造成的任何索赔、损害、成本、损失和债务,TI 对此概不负责。
TI 提供的产品受TI 的销售条款(https:www.ti.com/legal/termsofsale.html) 或ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI
提供这些资源并不会扩展或以其他方式更改TI 针对TI 产品发布的适用的担保或担保免责声明。重要声明
邮寄地址:Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2021,德州仪器(TI) 公司
PACKAGE OPTION ADDENDUM
www.ti.com
28-Sep-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS3851G18EDRBR
TPS3851G18EDRBT
TPS3851G18SDRBR
TPS3851G18SDRBT
TPS3851G25EDRBR
TPS3851G25EDRBT
TPS3851G30EDRBR
TPS3851G30EDRBT
TPS3851G33EDRBR
TPS3851G33EDRBT
TPS3851G33SDRBR
TPS3851G33SDRBT
TPS3851G50EDRBR
TPS3851G50EDRBT
TPS3851G50SDRBR
TPS3851G50SDRBT
TPS3851H18EDRBR
TPS3851H18EDRBT
TPS3851H25EDRBR
TPS3851H25EDRBT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SON
SON
SON
SON
SON
SON
SON
SON
SON
SON
SON
SON
SON
SON
SON
SON
SON
SON
SON
SON
DRB
DRB
DRB
DRB
DRB
DRB
DRB
DRB
DRB
DRB
DRB
DRB
DRB
DRB
DRB
DRB
DRB
DRB
DRB
DRB
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
851DD
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
851DD
851DC
851DC
851ED
851ED
851FD
851FD
851GD
851GD
851GC
851GC
851HD
851HD
851HC
851HC
851LD
851LD
851MD
851MD
250
RoHS & Green
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
28-Sep-2021
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS3851H30EDRBR
TPS3851H30EDRBT
TPS3851H33EDRBR
TPS3851H33EDRBT
TPS3851H50EDRBR
TPS3851H50EDRBT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SON
SON
SON
SON
SON
SON
DRB
DRB
DRB
DRB
DRB
DRB
8
8
8
8
8
8
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
851ND
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
851ND
851PD
851PD
851RD
851RD
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
28-Sep-2021
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TPS3851 :
Automotive : TPS3851-Q1
•
NOTE: Qualified Version Definitions:
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Jun-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS3851G18EDRBR
TPS3851G18EDRBT
TPS3851G18SDRBR
TPS3851G18SDRBT
TPS3851G25EDRBR
TPS3851G25EDRBT
TPS3851G30EDRBR
TPS3851G30EDRBT
TPS3851G33EDRBR
TPS3851G33EDRBT
TPS3851G33SDRBR
TPS3851G33SDRBT
TPS3851G50EDRBR
TPS3851G50EDRBT
TPS3851G50SDRBR
TPS3851G50SDRBT
SON
SON
SON
SON
SON
SON
SON
SON
SON
SON
SON
SON
SON
SON
SON
SON
DRB
DRB
DRB
DRB
DRB
DRB
DRB
DRB
DRB
DRB
DRB
DRB
DRB
DRB
DRB
DRB
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
3000
250
330.0
180.0
330.0
180.0
330.0
180.0
330.0
180.0
330.0
180.0
330.0
180.0
330.0
180.0
330.0
180.0
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.1
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
3000
250
3000
250
3000
250
3000
250
3000
250
3000
250
3000
250
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Jun-2023
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS3851H18EDRBR
TPS3851H18EDRBT
TPS3851H25EDRBR
TPS3851H25EDRBT
TPS3851H30EDRBR
TPS3851H30EDRBT
TPS3851H33EDRBR
TPS3851H33EDRBT
TPS3851H50EDRBR
TPS3851H50EDRBT
SON
SON
SON
SON
SON
SON
SON
SON
SON
SON
DRB
DRB
DRB
DRB
DRB
DRB
DRB
DRB
DRB
DRB
8
8
8
8
8
8
8
8
8
8
3000
250
330.0
180.0
330.0
180.0
330.0
180.0
330.0
180.0
330.0
180.0
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.1
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
3000
250
3000
250
3000
250
3000
250
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Jun-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS3851G18EDRBR
TPS3851G18EDRBT
TPS3851G18SDRBR
TPS3851G18SDRBT
TPS3851G25EDRBR
TPS3851G25EDRBT
TPS3851G30EDRBR
TPS3851G30EDRBT
TPS3851G33EDRBR
TPS3851G33EDRBT
TPS3851G33SDRBR
TPS3851G33SDRBT
TPS3851G50EDRBR
TPS3851G50EDRBT
TPS3851G50SDRBR
TPS3851G50SDRBT
TPS3851H18EDRBR
TPS3851H18EDRBT
SON
SON
SON
SON
SON
SON
SON
SON
SON
SON
SON
SON
SON
SON
SON
SON
SON
SON
DRB
DRB
DRB
DRB
DRB
DRB
DRB
DRB
DRB
DRB
DRB
DRB
DRB
DRB
DRB
DRB
DRB
DRB
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
3000
250
367.0
210.0
367.0
210.0
367.0
210.0
367.0
210.0
367.0
210.0
367.0
210.0
367.0
210.0
367.0
210.0
367.0
210.0
367.0
185.0
367.0
185.0
367.0
185.0
367.0
185.0
367.0
185.0
367.0
185.0
367.0
185.0
367.0
185.0
367.0
185.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
3000
250
3000
250
3000
250
3000
250
3000
250
3000
250
3000
250
3000
250
Pack Materials-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Jun-2023
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS3851H25EDRBR
TPS3851H25EDRBT
TPS3851H30EDRBR
TPS3851H30EDRBT
TPS3851H33EDRBR
TPS3851H33EDRBT
TPS3851H50EDRBR
TPS3851H50EDRBT
SON
SON
SON
SON
SON
SON
SON
SON
DRB
DRB
DRB
DRB
DRB
DRB
DRB
DRB
8
8
8
8
8
8
8
8
3000
250
367.0
210.0
367.0
210.0
367.0
210.0
367.0
210.0
367.0
185.0
367.0
185.0
367.0
185.0
367.0
185.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
3000
250
3000
250
3000
250
Pack Materials-Page 4
PACKAGE OUTLINE
DRB0008A
VSON - 1 mm max height
SCALE 4.000
PLASTIC SMALL OUTLINE - NO LEAD
3.1
2.9
B
A
PIN 1 INDEX AREA
3.1
2.9
C
1 MAX
SEATING PLANE
0.08 C
0.05
0.00
DIM A
OPT 1
(0.1)
OPT 2
(0.2)
1.5 0.1
4X (0.23)
EXPOSED
THERMAL PAD
(DIM A) TYP
4
5
2X
1.95
1.75 0.1
8
1
6X 0.65
0.37
0.25
8X
PIN 1 ID
0.1
C A B
C
(OPTIONAL)
(0.65)
0.05
0.5
0.3
8X
4218875/A 01/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
DRB0008A
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(1.5)
(0.65)
SYMM
8X (0.6)
(0.825)
8
8X (0.31)
1
SYMM
(1.75)
(0.625)
6X (0.65)
4
5
(R0.05) TYP
(
0.2) VIA
(0.23)
TYP
(0.5)
(2.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
EXPOSED
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4218875/A 01/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
DRB0008A
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(0.65)
4X (0.23)
SYMM
METAL
TYP
8X (0.6)
4X
(0.725)
8
1
8X (0.31)
(2.674)
(1.55)
SYMM
6X (0.65)
4
5
(R0.05) TYP
(1.34)
(2.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
84% PRINTED SOLDER COVERAGE BY AREA
SCALE:25X
4218875/A 01/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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