TPS3851H30EQDRBRQ1 [TI]

具有集成看门狗计时器的汽车类高精度电压监控器 | DRB | 8 | -40 to 125;


型号：	TPS3851H30EQDRBRQ1
厂家：	TEXAS INSTRUMENTS
描述：	具有集成看门狗计时器的汽车类高精度电压监控器 \| DRB \| 8 \| -40 to 125 监控
文件：	总39页 (文件大小：2131K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TPS3851-Q1

ZHCSO14A –MARCH 2017 –REVISED SEPTEMBER 2021

TPS3851-Q1 集成看门狗定时器的高精度电压监控器

1 特性

3 说明

• 具有符合AEC-Q100 标准的下列特性：

TPS3851-Q1 器件结合了精密电压监控器和可编程看

门狗计时器。TPS3851-Q1 比较器在 VDD 引脚上可针

对欠压 (V_ITN) 阈值实现 0.8% 的精度（–40°C 至

+125°C）。TPS3851-Q1 还包含与欠压阈值相关的高

精度迟滞，因此成为小容差系统的理想之选。该监控器

的RESET 延迟具备15% 精度、高精密延迟时间。

– 器件温度等级1：-40°C 至125°C 环境工作温度

范围

– 器件HBM ESD 分类等级2

– 器件CDM ESD 分类等级C4B

• 提供功能安全

– 可帮助进行功能安全系统设计的文档

• 输入电压范围：V_DD= 1.6 V 至6.5 V

• 0.8% 电压阈值精度

• 低电源电流：I_DD= 10µA（典型值）

• 用户可编程看门狗超时

• 出厂编程的精密看门狗和复位计时器：

• 手动复位输入(MR)

• 开漏输出

TPS3851-Q1 包含可编程窗口看门狗计时器，广泛适

用于各种应用。专用看门狗输出 (WDO) 有助于提高分

辨率，从而帮助确定出现故障情况的根本原因。看门狗

超时可通过外部电容编程，也可以采用工厂编程的默认

延迟设置。可通过逻辑引脚禁用看门狗，避免在开发过

程中出现意外的看门狗超时。

TPS3851-Q1 采用小型

• 高精度欠压监控：

3.00mm × 3.00mm、8 引脚 VSON 封装。TPS3851-

Q1 具有可湿性侧面，可轻松进行光学检查。

– 支持1.8 V 到5.0V 常见电压轨

– 支持4% 和7% 欠压阈值

– 0.5% 迟滞

器件信息

封装⁽¹⁾

封装尺寸（标称值）

器件型号

• 看门狗禁用功能

• 采用小型3mm × 3mm 8 引脚VSON 封装

TPS3851-Q1

VSON (8)

3.00mm × 3.00mm

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

2 应用

• 环视系统ECU

• 车辆乘员检测传感器

• ADAS 域控制器

• 汽车直流/直流转换器

• 汽车前置摄像机

• 汽车中心信息显示屏

1.8 V

TPS3851-Q1

V_DD

Microcontroller

VDD

RESET

WDO

RESET

SET1

NMI

WDI

GPIO

CWD

GND

全集成微控制器监控电路

欠压阈值(V_ITN) 精度与温度间的关系

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SBVS286

TPS3851-Q1

ZHCSO14A –MARCH 2017 –REVISED SEPTEMBER 2021

www.ti.com.cn

Table of Contents

7.4 Device Functional Modes..........................................14

8 Application and Implementation..................................15

8.1 Application Information............................................. 15

8.2 Typical Application.................................................... 18

9 Power Supply Recommendations................................21

10 Layout...........................................................................22

10.1 Layout Guidelines................................................... 22

10.2 Layout Example...................................................... 22

11 Device and Documentation Support..........................23

11.1 Device Support........................................................23

11.2 Documentation Support.......................................... 23

11.3 接收文档更新通知................................................... 23

11.4 支持资源..................................................................23

11.5 Trademarks............................................................. 23

11.6 Electrostatic Discharge Caution..............................23

11.7 术语表..................................................................... 23

12 Mechanical, Packaging, and Orderable

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................3

6 Specifications.................................................................. 4

6.1 Absolute Maximum Ratings........................................ 4

6.2 ESD Ratings............................................................... 4

6.3 Recommended Operating Conditions.........................4

6.4 Thermal Information....................................................5

6.5 Electrical Characteristics.............................................5

6.6 Timing Requirements..................................................6

6.7 Timing Diagrams.........................................................7

6.8 Typical Characteristics................................................8

7 Detailed Description......................................................11

7.1 Overview................................................................... 11

7.2 Functional Block Diagram......................................... 11

7.3 Feature Description...................................................11

Information.................................................................... 24

4 Revision History

注：以前版本的页码可能与当前版本的页码不同

Changes from Revision * (March 2017) to Revision A (September 2021)

Page

• 更新了整个文档中的表格、图和交叉参考的编号格式.........................................................................................1

• 删除了“可在工作温度范围内实现±15% 的看门狗超时和看门狗复位延迟精度”..............................................1

• 添加了“在VDD 引脚上”以进行阐释................................................................................................................1

• Updated ESD Ratings.........................................................................................................................................4

• Updated I_CWDmin and max spec........................................................................................................................5

• Updated V_CWDmin and max spec...................................................................................................................... 5

• Added a footnote to for t_INIT............................................................................................................................... 6

• Updated t_WDUmin and max boundry values from 0.85 and 1.15 to 0.905 and 1.095 respectively...................16

• Updated t_WDUmin and max values for all capacitors........................................................................................16

• Updated the equations 6 and 7 to replace 0.85 and 1.15 to 0.905 and 1.095 respectively..............................19

Submit Document Feedback

Product Folder Links: TPS3851-Q1

TPS3851-Q1

ZHCSO14A –MARCH 2017 –REVISED SEPTEMBER 2021

www.ti.com.cn

5 Pin Configuration and Functions

VDD

CWD

RESET

WDO

WDI

Thermal

Pad

GND

SET1

Not to scale

图5-1. DRB Package

3-mm × 3-mm, 8-Pin VSON

Top View

表5-1. Pin Functions

NAME

NO.

I/O

DESCRIPTION

Programmable watchdog timeout input. The watchdog timeout is set by connecting a capacitor between this

pin and ground. Connecting via a 10-kΩresistor to V_DDor leaving unconnected further enables the

selection of the preset watchdog timeouts; see the CWD Functionality section.

The TPS3851-Q1 determines the watchdog timeout using either Equation 1 or Equation 2 with standard or

extended timing, respectively.

CWD

GND

Ground pin

—

Manual reset pin. A logical low on this pin issues a RESET. This pin is internally pulled up to V_DD. RESET

remains low for a fixed reset delay (t_RST) time after MR is deasserted (high).

Reset output. Connect RESET using a 1-kΩto 100-kΩresistor to the correct pullup voltage rail (V_PU).

RESET goes low when V_DDgoes below the undervoltage threshold (V_ITN). When V_DDis within the normal

operating range, the RESET timeout-counter starts. At completion, RESET goes high. During startup, the

state of RESET is undefined below the specified power-on-reset (POR) voltage (V_POR). Above POR, RESET

RESET

goes low and remains low until the monitored voltage is within the correct operating range (above V_ITN

V_HYST) and the RESET timeout is complete.

Logic input. Grounding the SET1 pin disables the watchdog timer. SET1 and CWD select the watchdog

timeouts; see the SET1 section.

SET1

VDD

Supply voltage pin. For noisy systems, connecting a 0.1-μF bypass capacitor is recommended.

Watchdog input. A falling edge must occur at WDI before the timeout (t_WD) expires.

When the watchdog is not in use, the SET1 pin can be used to disable the watchdog. WDI is ignored when

RESET or WDO are low (asserted) and when the watchdog is disabled. If the watchdog is disabled, WDI

cannot be left unconnected and must be driven to either VDD or GND.

WDI

Watchdog output. Connect WDO with a 1-kΩto 100-kΩresistor to the correct pullup voltage rail (V_PU).

WDO goes low (asserts) when a watchdog timeout occurs. WDO only asserts when RESET is high. When a

watchdog timeout occurs, WDO goes low (asserts) for the set RESET timeout delay (t_RST). When RESET

goes low, WDO is in a high-impedance state.

WDO

Thermal pad

Connect the thermal pad to a large-area ground plane. The thermal pad is internally connected to GND.

—

Submit Document Feedback

Product Folder Links: TPS3851-Q1

TPS3851-Q1

ZHCSO14A –MARCH 2017 –REVISED SEPTEMBER 2021

www.ti.com.cn

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) ⁽¹⁾

MIN

MAX

UNIT

Supply voltage range

Output voltage range

VDD

–0.3

RESET, WDO

SET1, WDI, MR

CWD

V_DD+ 0.3 ⁽³⁾

±20

Voltage ranges

Output pin current

RESET, WDO

Input current (all pins)

±20

Continuous total power dissipation

See 节6.4

(2)

Operating junction, T_J

Operating free-air, T_A

Storage, T_stg

150

–40

–65

Temperature

°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under

Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device

reliability.

(2) Assume that T_J= T_Aas a result of the low dissipated power in this device.

(3) The absolute maximum rating is V_DD+ 0.3 V or 7.0 V, whichever is smaller.

6.2 ESD Ratings

VALUE

±4000

±1000

UNIT

Human-body model (HBM), per AEC Q100-002 ⁽¹⁾

Charged-device model (CDM), per AEC Q100-011

V_(ESD)

Electrostatic discharge

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

TYP

MAX

UNIT

V_DD

Supply pin voltage

1.6

6.5

V_SET1

C_CWD

CWD

R_PU

SET1 pin voltage

6.5

Watchdog timing capacitor

Pullup resistor to VDD

Pullup resistor, RESET and WDO

RESET pin current

0.1 ^{(1) (2)}

1000 ^{(1) (2)}

kΩ

°C

100

I_RESET

I_WDO

T_J

Watchdog output current

Junction temperature

125

–40

(1) Using standard timing with a C_CWDcapacitor of 0.1 nF or 1000 nF gives a t_WD(typ)of 0.704 ms or 3.23 seconds, respectively.

(2) Using extended timing with a C_CWDcapacitor of 0.1 nF or 1000 nF gives a t_WD(typ)of 62.74 ms or 77.45 seconds, respectively.

Submit Document Feedback

Product Folder Links: TPS3851-Q1

TPS3851-Q1

ZHCSO14A –MARCH 2017 –REVISED SEPTEMBER 2021

www.ti.com.cn

6.4 Thermal Information

TPS3851-Q1

THERMAL METRIC ⁽¹⁾

DRB (VSON)

8 PINS

47.7

UNIT

R_θJA

Junction-to-ambient thermal resistance

°C/W

R_θJC(top)

R_θJB

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

51.5

22.2

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

1.3

ψ_JT

22.3

ψ_JB

R_θJC(bot)

4.3

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

6.5 Electrical Characteristics

at V_ITN+ V_HYST≤V_DD≤6.5 V over the operating temperature range of –40°C ≤T_A, T _A≤125°C (unless otherwise

noted); the open-drain pullup resistors are 10 kΩfor each output; typical values are at T_A= 25°C

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

GENERAL CHARACTERISTICS

(1) (2) (3)

V_DD

I_DD

Supply voltage

Supply current

1.6

6.5

µA

RESET FUNCTION

(2)

V_POR

Power-on reset voltage

I_RESET= 15 µA, V_OL(MAX)= 0.25 V

0.8

(1)

V_UVLO

Undervoltage lockout voltage

1.35

Undervoltage threshold accuracy, entering

RESET

V_ITN

V_DDfalling

V_ITN+ 0.8%

_ITN–0.8%

V_HYST

I_MR

Hysteresis voltage

V_DDrising

V_MR= 0 V

0.2%

500

0.5%

620

0.8%

700

MR pin internal pullup current

WATCHDOG FUNCTION

I_CWD

V_CWD

V_OL

CWD pin charge current

CWD = 0.5 V

347

375

403

1.224

0.4

CWD pin threshold voltage

RESET, WDO output low

1.196

1.21

VDD = 5 V, I_SINK= 3 mA

RESET, WDO output leakage current,

open-drain

VDD = V_ITN+ V_HYST

V_RESET= V_WDO= 6.5 V

I_D

µA

V_IL

Low-level input voltage ( MR, SET1)

High-level input voltage ( MR, SET1)

Low-level input voltage (WDI)

0.25

V_IH

0.8

V_IL(WDI)

V_IH(WDI)

0.3 × V_DD

High-level input voltage (WDI)

0.8 × V_DD

(1) When V_DDfalls below V_UVLO, RESET is driven low.

(2) When V_DDfalls below V_POR, RESET and WDO are undefined.

(3) During power-on, V_DDmust be a minimum 1.6 V for at least 300 µs before RESET correlates with V_DD

Submit Document Feedback

Product Folder Links: TPS3851-Q1

TPS3851-Q1

ZHCSO14A –MARCH 2017 –REVISED SEPTEMBER 2021

www.ti.com.cn

6.6 Timing Requirements

at V_ITN+ V_HYST≤V_DD≤6.5 V over the operating temperature range of –40°C ≤T_A, T _A≤125°C (unless otherwise

noted); the open-drain pullup resistors are 10 kΩfor each output; typical values are at T_A= 25°C

MIN

NOM

MAX UNIT

GENERAL

t_INIT

CWD pin evaluation period ⁽¹⁾

381

µs

Minimum MR, SET1 pin pulse duration

Startup delay ⁽³⁾

300

RESET FUNCTION

t_RST

Reset timeout period

170

200

230 ms

V_DD= V_ITN+ V_HYST+ 2.5%

t_RST-DELV_DDto RESET delay

µs

V_DD= V_ITN–2.5%

t_MR-DELMR to RESET delay

200

WATCHDOG FUNCTION

CWD = NC, SET1 = 0 ⁽²⁾

CWD = NC, SET1 = 1 ⁽²⁾

Watchdog disabled

1360

1600

1840 ms

Watchdog timeout ⁽³⁾

CWD = 10 kΩto VDD,

t_WD

Watchdog disabled

SET1 = 0 ⁽²⁾

CWD = 10 kΩto VDD,

170

200

150

230 ms

µs

SET1 = 1 ⁽²⁾

t_WD-

Setup time required for device to respond to changes on WDI after

being enabled

setup

Minimum WDI pulse duration

t_WD-delWDI to WDO delay

(1) Refer to 节8.1.1.2

(2) SET1 = 0 means V_SET1< V_IL; SET1 = 1 means V_SET1> V_IH.

(3) The fixed watchdog timing covers both standard and extended versions.

Submit Document Feedback

Product Folder Links: TPS3851-Q1

TPS3851-Q1

ZHCSO14A –MARCH 2017 –REVISED SEPTEMBER 2021

www.ti.com.cn

6.7 Timing Diagrams

V_ITN+ V_HYST

V_ITN

t_RST-DEL

VDD

V_ITN

t_RST

V_POR

t_RST

RESET

WDI

(1)

t < t_WDt = t_WD

t < t_WD

WDO

t_RST

A. See 图6-2 for WDI timing requirements.

图6-1. Timing Diagram

Correct

Operation

WDI

WDO

Late Fault

WDI

WDO

Valid

Region

Timing

t_WD(MIN)

t_WD(TYP)

t_WD(MAX)

= Tolerance Window

图6-2. Watchdog Timing Diagram

Submit Document Feedback

Product Folder Links: TPS3851-Q1

TPS3851-Q1

ZHCSO14A –MARCH 2017 –REVISED SEPTEMBER 2021

www.ti.com.cn

6.8 Typical Characteristics

all typical characteristics curves are taken at 25°C with 1.6 V ≤VDD ≤6.5 V (unless other wise noted)

0.7

0.6

0.5

0.4

0.3

-40èC

0èC

25èC

105èC

125èC

V_IL

V_IH

-50

-25

100

125

Temperature (èC)

V_DD(V)

VDD = 1.6 V

图6-3. Supply Current vs V_DD

图6-4. MR Threshold vs Temperature

380

376

372

368

364

0.5

Unit 1

Unit 2

Unit 3

Unit 4

Unit 5

Average

0.3

0.1

-0.1

-0.3

-0.5

1.6 V

6.5 V

-50

-25

100

125

-50

-25

100

125

Temperature (èC)

图6-5. CWD Charging Current vs Temperature

TPS3851G18-Q1, V_ITN= 1.728 V

图6-6. V_ITN+ V_HYSTAccuracy vs Temperature

0.5

0.3

0.5

0.3

Unit 1

Unit 2

Unit 3

Unit 4

Unit 5

Average

Unit 1

Unit 2

Unit 3

Unit 4

Unit 5

Average

0.1

-0.1

-0.3

-0.5

-0.1

-0.3

-0.5

-50

-25

100

125

-50

-25

100

125

Temperature (èC)

TPS3851G18-Q1, V_ITN= 1.728 V

图6-7. V_ITNAccuracy vs Temperature

TPS3851G50-Q1, V_ITN= 4.8 V

图6-8. V_ITN+ V_HYSTAccuracy vs Temperature

Submit Document Feedback

Product Folder Links: TPS3851-Q1

TPS3851-Q1

ZHCSO14A –MARCH 2017 –REVISED SEPTEMBER 2021

www.ti.com.cn

6.8 Typical Characteristics (continued)

all typical characteristics curves are taken at 25°C with 1.6 V ≤VDD ≤6.5 V (unless other wise noted)

0.5

0.3

Unit 1

Unit 2

Unit 3

Unit 4

Unit 5

Average

0.1

-0.1

-0.3

-0.5

-50

-25

100

125

-0.8 -0.6 -0.4 -0.2

0.2

0.4

V_ITN+ V_HYSTAccuracy (%)

0.6

0.8

Temperature (èC)

TPS3851G50-Q1, V_ITN= 4.8 V

图6-9. V_ITNAccuracy vs Temperature

Includes G and H versions; 1.8-V, 2.5-V, 3.0-V, 3.3-V, and 5-V

thresholds; total units = 36,627

图6-10. V_ITN+ V_HYSTAccuracy Histogram

-0.8 -0.6 -0.4 -0.2

V_ITNAccuracy (%)

0.2

0.4

0.6

0.8

0.2

0.35

0.5

Hysteresis (%)

0.8

Includes G and H versions; 1.8-V, 2.5-V, 3.0-V, 3.3-V, and 5-V

thresholds; total units = 36,627

Includes G and H versions; 1.8-V, 2.5-V, 3.0-V, 3.3-V, and 5-V

thresholds; total units = 36,627

图6-11. V_ITNAccuracy Histogram

图6-12. Hysteresis Histogram

1.6

-40èC

0èC

1.4

1.2

1.4

1.2

25èC

105èC

125èC

25èC

105èC

125èC

0.8

0.6

0.4

0.2

0.8

0.6

0.4

0.2

I_RESET(mA)

VDD = 1.6 V

VDD = 6.5 V

图6-13. Low-Level RESET Voltage vs RESET Current

图6-14. Low-Level RESET Voltage vs RESET Current

Submit Document Feedback

Product Folder Links: TPS3851-Q1

TPS3851-Q1

ZHCSO14A –MARCH 2017 –REVISED SEPTEMBER 2021

www.ti.com.cn

6.8 Typical Characteristics (continued)

all typical characteristics curves are taken at 25°C with 1.6 V ≤VDD ≤6.5 V (unless other wise noted)

100

-40èC

0èC

25èC

105èC

125èC

-40èC

0èC

25èC

105èC

125èC

Overdrive (%)

TPS3851G18-Q1 entering undervoltage

TPS3851G50-Q1 entering undervoltage

图6-15. Propagation Delay vs Overdrive

图6-16. Propagation Delay vs Overdrive

210

205

200

195

190

210

205

200

195

190

-40èC

0èC

25èC

105èC

125èC

-40èC

0èC

25èC

105èC

125èC

Overdrive (%)

TPS3851G18-Q1 exiting undervoltage

图6-17. Propagation Delay (t_RST) vs Overdrive

Overdrive (%)

TPS3851G50-Q1 exiting undervoltage

图6-18. Propagation Delay (t_RST) vs Overdrive

Overdrive = 3%

Overdrive = 5%

Overdrive = 7%

Overdrive = 9%

Overdrive = 10%

Overdrive = 3%

Overdrive = 5%

Overdrive = 7%

Overdrive = 9%

Overdrive = 10%

-50

-25

100

125

-50

-25

100

125

Temperature (èC)

V_ITN= 1.728 V

V_ITN= 4.8 V

图6-19. High-to-Low Glitch Immunity vs Temperature

图6-20. High-to-Low Glitch Immunity vs Temperature

Submit Document Feedback

Product Folder Links: TPS3851-Q1

TPS3851-Q1

ZHCSO14A –MARCH 2017 –REVISED SEPTEMBER 2021

www.ti.com.cn

7 Detailed Description

7.1 Overview

The TPS3851-Q1 is a high-accuracy voltage supervisor with an integrated watchdog timer. This device includes

a precision undervoltage supervisor with a threshold that achieves 0.8% accuracy over the specified temperature

range of –40°C to +125°C. In addition, the TPS3851-Q1 includes accurate hysteresis on the threshold, making

the device ideal for use with tight tolerance systems where voltage supervisors must ensure a RESET before the

minimum supply tolerance of the microprocessor or system-on-a-chip (SoC) is reached. There are two options

for the watchdog timing standard and extended timing. To get standard timing use the TPS3851Xyy(y)S-Q1, for

extended timing use the TPS3851Xyy(y)E-Q1.

7.2 Functional Block Diagram

VDD

R₁

RESET

R₂

Precision

Clock

Reference

VDD

WDO

State

Machine

Cap

Control

CWD

WDI

SET1

GND

R₁+ R₂= 4.5 MΩ.

7.3 Feature Description

7.3.1 RESET

Connect RESET to V_PUthrough a 1-kΩ to 100-kΩ pullup resistor. RESET remains high (deasserted) when V_DD

is greater than the negative threshold voltage (V_ITN). If V_DDfalls below the negative threshold (V_ITN), then

RESET is asserted, driving the RESET pin to low impedance. When V_DDrises above V_ITN+ V_HYST, a delay

circuit is enabled that holds RESET low for a specified reset delay period (t_RST). When the reset delay has

elapsed, the RESET pin goes to a high-impedance state and uses a pullup resistor to hold RESET high. The

pullup resistor must be connected to the proper voltage rail to allow other devices to be connected at the correct

interface voltage. To ensure proper voltage levels, give some consideration when choosing the pullup resistor

values. The pullup resistor value is determined by output logic low voltage (V_OL), capacitive loading, leakage

current (I_D), and the current through the RESET pin I_RESET

Submit Document Feedback

Product Folder Links: TPS3851-Q1

TPS3851-Q1

ZHCSO14A –MARCH 2017 –REVISED SEPTEMBER 2021

www.ti.com.cn

7.3.2 Manual Reset MR

The manual reset ( MR) input allows a processor or other logic circuits to initiate a reset. A logic low on MR

causes RESET to assert. After MR returns to a logic high and V_DDis above V_ITN+ V_HYST, RESET is deasserted

after the reset delay time (t_RST). If MR is not controlled externally, then MR can either be connected to V_DDor left

floating because the MR pin is internally pulled up.

7.3.3 UV Fault Detection

The TPS3851-Q1 features undervoltage detection for common rails between 1.8 V and 5 V. The voltage is

monitored on the input rail of the device. If V_DDdrops below V_ITN, then RESET is asserted (driven low).

图 7-1 shows that when V_DDis above V_ITN+ V_HYST, RESET deasserts after t_RST. The internal comparator has

built-in hysteresis that provides some noise immunity and ensures stable operation. Although not required in

most cases, for noisy applications, good analog design practice is to place a 1-nF to 100-nF bypass capacitor

close to the VDD pin to reduce sensitivity to transient voltages on the monitored signal.

VDD

V_ITN+ V_HYST

V_ITN

Undervoltage Limit

t_RST

RESET

图7-1. Undervoltage Detection

7.3.4 Watchdog Mode

This section provides information for the watchdog mode of operation.

7.3.4.1 CWD

The CWD pin provides the user the functionality of both high-precision, factory-programmed watchdog timing

options and user-programmable watchdog timing. The TPS3851-Q1 features three options for setting the

watchdog timer: connecting a capacitor to the CWD pin, connecting a pullup resistor to VDD, and leaving the

CWD pin unconnected. The configuration of the CWD pin is evaluated by the device every time V_DDenters the

valid region (V_ITN+ V_HYST< V_DD). The pin evaluation is controlled by an internal state machine that determines

which option is connected to the CWD pin. The sequence of events typically takes 381 μs (t_INIT) to determine if

the CWD pin is left unconnected, pulled-up through a resistor, or connected to a capacitor. If the CWD pin is

being pulled up to VDD, a 10-kΩresistor is required.

7.3.4.2 Watchdog Input WDI

WDI is the watchdog timer input that controls the WDO output. The WDI input is triggered by the falling edge of

the input signal. To ensure proper functionality of the watchdog timer, always issue the WDI pulse before

t_WD(min). If the pulse is issued in this region, then WDO remains unasserted. Otherwise, the device asserts WDO,

putting the WDO pin into a low-impedance state.

The watchdog input (WDI) is a digital pin. In order to ensure there is no increase in I_DD, drive the WDI pin to

either VDD or GND at all times. Putting the pin to an intermediate voltage can cause an increase in supply

current (I_DD) because of the architecture of the digital logic gates. When RESET is asserted, the watchdog is

disabled and all signals input to WDI are ignored. When RESET is no longer asserted, the device resumes

normal operation and no longer ignores the signal on WDI. If the watchdog is disabled, drive the WDI pin to

either VDD or GND. 图 7-2 shows the valid region for a WDI pulse to be issued to prevent WDO from being

triggered and pulled low.

Submit Document Feedback

Product Folder Links: TPS3851-Q1

TPS3851-Q1

ZHCSO14A –MARCH 2017 –REVISED SEPTEMBER 2021

www.ti.com.cn

Correct

Operation

WDI

WDO

Late Fault

WDI

WDO

Valid

Region

Timing

t_WD(MIN)

t_WD(TYP)

t_WD(MAX)

= Tolerance Window

图7-2. Watchdog Timing Diagram

7.3.4.3 Watchdog Output WDO

The TPS3851-Q1 features a watchdog timer with an independent watchdog output (WDO). The independent

watchdog output provides the flexibility to flag a fault in the watchdog timing without performing an entire system

reset. When RESET is not asserted (high), the WDO signal maintains normal operation. When asserted, WDO

remains low for t_RST. When the RESET signal is asserted (low), the WDO pin goes to a high-impedance state.

When RESET is unasserted, the watchdog timer resumes normal operation.

Submit Document Feedback

Product Folder Links: TPS3851-Q1

TPS3851-Q1

ZHCSO14A –MARCH 2017 –REVISED SEPTEMBER 2021

www.ti.com.cn

7.3.4.4 SET1

The SET1 pin can enable and disable the watchdog timer. If SET1 is set to GND, the watchdog timer is disabled

and WDI is ignored. If the watchdog timer is disabled, drive the WDI pin to either GND or VDD to ensure that

there is no increase in I_DD. When SET1 is logic high, the watchdog operates normally. The SET1 pin can be

changed dynamically; however, if the watchdog is going from disabled to enabled (as shown in 图 7-3) there is a

150-µs setup time where the watchdog does not respond to changes on WDI.

VDD

RESET

SET1

150 µs

Watchdog

Enabled/Disabled

Enabled

Disabled

Enabled

图7-3. Enabling and Disabling the Watchdog

7.4 Device Functional Modes

表7-1 summarises the functional modes of the TPS3851-Q1.

表7-1. Device Functional Modes

V_DD

WDI

WDO

RESET

Undefined

Low

V_DD< V_POR

—

Ignored

High

_POR≤V_DD< V_DD(min)

(1)

Ignored

High

Low

_DD(min)≤V_DD≤V_ITN+ V_HYST

(2)

(3)

V_DD> V_ITN

t_PULSE< t_WD(min)

t_PULSE> t_WD(min)

High

(2)

V_DD> V_ITN

High

(1) Only valid before V_DDhas gone above V_ITN+ V_HYST

(2) Only valid after V_DDhas gone above V_ITN+ V_HYST

(3) Where t_pulseis the time between the falling edges on WDI.

7.4.1 V_DDis Below V_POR( V_DD< V_POR

)

When V_DDis less than V_POR, RESET is undefined and can be either high or low. The state of RESET largely

depends on the load that the RESET pin is experiencing.

7.4.2 Above Power-On-Reset, But Less Than V_DD(min)(V_POR≤V_DD< V_DD(min)

)

When the voltage on V_DDis less than V_DD(min), and greater than or equal to V_POR, the RESET signal is asserted

(logic low). When RESET is asserted, the watchdog output WDO is in a high-impedance state regardless of the

WDI signal that is input to the device.

7.4.3 Normal Operation (V_DD≥V_DD(min)

)

When V_DDis greater than or equal to V_DD(min), the RESET signal is determined by V_DD. When RESET is

asserted, WDO goes to a high-impedance state. WDO is then pulled high through the pullup resistor.

Submit Document Feedback

Product Folder Links: TPS3851-Q1

TPS3851-Q1

ZHCSO14A –MARCH 2017 –REVISED SEPTEMBER 2021

www.ti.com.cn

8 Application and Implementation

Note

以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客户应负责确定

器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。

8.1 Application Information

The following sections describe in detail proper device implementation, depending on the final application

requirements.

8.1.1 CWD Functionality

The TPS3851-Q1 features three options for setting the watchdog timer: connecting a capacitor to the CWD pin,

connecting a pullup resistor to VDD, and leaving the CWD pin unconnected. 图 8-1 shows a schematic drawing

of all three options. If this pin is connected to VDD through a 10-kΩ pullup resistor or left unconnected (high

impedance), then the factory-programmed watchdog timeouts are enabled; see the 节 8.1.1.1 section.

Otherwise, the watchdog timeout can be adjusted by placing a capacitor from the CWD pin to ground.

VDD

TPS3851-Q1

VDD

375 nA

CWD

C_CWD

CWD

Cap

Control

Cap

Control

Cap

Control

User Programmable

Capacitor to GND

CWD

Unconnected

10 kΩ Resistor

to VDD

图8-1. CWD Charging Circuit

8.1.1.1 Factory-Programmed Timing Options

If using the factory-programmed timing options (listed in 表 8-1), the CWD pin must either be unconnected or

pulled up to VDD through a 10-kΩ pullup resistor. Using these options enables high-precision, 15% accurate

watchdog timing.

表8-1. Factory Programmed Watchdog Timing

INPUT

STANDARD AND EXTENDED TIMING WDT (t_WD)

UNIT

CWD

SET1

MIN

TYP

Watchdog disabled

1600

Watchdog disabled

200

MAX

1360

1840

10 kΩto VDD

170

230

Submit Document Feedback

Product Folder Links: TPS3851-Q1

TPS3851-Q1

ZHCSO14A –MARCH 2017 –REVISED SEPTEMBER 2021

www.ti.com.cn

8.1.1.2 Adjustable Capacitor Timing

Adjustable capacitor timing is achievable by connecting a capacitor to the CWD pin. If a capacitor is connected

to CWD, then a 375-nA, constant-current source charges C_CWDuntil V_CWD= 1.21 V. 表 8-2 shows how to

calculate t_WDusing 方程式 1, 方程式 2, and the SET1 pin. The TPS3851-Q1 determines the watchdog timeout

with the formulas given in 方程式1 and 方程式2, where C_CWDis in nanofarads and t_WDis in milliseconds.

t_WD(standard)(ms) = 3.23 × C_CWD(nF) + 0.381 (ms)

t_WD(extended)(ms) = 77.4 × C_CWD(nF) + 55 (ms)

(1)

(2)

The TPS3851-Q1 is designed and tested using C_CWDcapacitors between 100 pF and 1 µF. 方程式 1 and 方程式

2 are for ideal capacitors; capacitor tolerances vary the actual device timing. For the most accurate timing, use

ceramic capacitors with COG dielectric material. If a C_CWDcapacitor is used, 方程式 1 can be used to set t_WDfor

standard timing. Use 方程式 2 to calculate t_WDfor extended timing. 表 8-3 shows the minimum and maximum

calculated t_WDvalues using an ideal capacitor for both standard and extended timing.

表8-2. Programmable CWD Timing

INPUT

STANDARD TIMING WDT (t_WD

)

EXTENDED TIMING WDT (t_WD)

UNIT

CWD

SET1

MIN

TYP

MAX

MIN

TYP

MAX

C_CWD

Watchdog disabled

(1)

(2)

t_WD(std)× 0.905

t_WD(std)

t_WD(std)× 1.095

t_WD(ext)× 0.905

t_WD(ext)

t_WD(ext)× 1.095

(1) Calculated from 方程式1 using an ideal capacitor.

(2) Calculated from 方程式2 using an ideal capacitor.

表8-3. t_WDValues for Common Ideal Capacitor Values

STANDARD TIMING WDT (t_WD

)

EXTENDED TIMING WDT (t_WD)

C_CWD

UNIT

MIN ⁽¹⁾

0.637

3.268

29.58

292.7

2923

TYP

0.704

3.611

32.68

323.4

3230

MAX ⁽¹⁾

0.771

3.954

35.79

354.1

3537

MIN ⁽¹⁾

56.77

119.82

750

TYP

62.74

132.4

829

MAX ⁽¹⁾

68.7

100 pF

1 nF

144.98

908

10 nF

100 nF

1 μF

7054

7795

77455

8536

70096

84814

(1) The minimum and maximum values are calculated using an ideal capacitor.

Submit Document Feedback

Product Folder Links: TPS3851-Q1

TPS3851-Q1

ZHCSO14A –MARCH 2017 –REVISED SEPTEMBER 2021

www.ti.com.cn

8.1.2 Overdrive Voltage

Forcing a RESET is dependent on two conditions: the amplitude V_DDis beyond the trip point (ΔV₁and ΔV₂),

and the length of time that the voltage is beyond the trip point (t₁and t₂). If the voltage is just under the trip point

for a long period of time, RESET asserts and the output is pulled low. However, if V_DDis just under the trip point

for a few nanoseconds, RESET does not assert and the output remains high. The length of time required for

RESET to assert can be changed by increasing the amount V_DDgoes under the trip point. If V_DDis under the trip

point by 10%, the amount of time required for the comparator to respond is much faster and causes RESET to

assert much quicker than when barely under the trip point voltage. 方程式 3 shows how to calculate the

percentage overdrive.

Overdrive = |((V_DD/ V_ITX) –1) × 100% |

(3)

In 方程式3, V_ITXcorresponds to the threshold trip point. If V_DDis exceeding the positive threshold,

V_ITN+ V_HYSTis used. V_ITNis used when V_DDis falling below the negative threshold. In 图 8-2, t₁and t₂

correspond to the amount of time that V_DDis over the threshold; the propagation delay versus overdrive for V_ITN

and V_ITN+ V_HYSTis illustrated in 图6-16 and 图6-18, respectively.

The TPS3851-Q1 is relatively immune to short positive and negative transients on VDD because of the overdrive

voltage curve.

ûV₁

t₁

V_ITN+ V_HYST

V_DD

V_ITN

ûV₂

t₂

Time

图8-2. Overdrive Voltage

Submit Document Feedback

Product Folder Links: TPS3851-Q1

TPS3851-Q1

ZHCSO14A –MARCH 2017 –REVISED SEPTEMBER 2021

www.ti.com.cn

8.2 Typical Application

1.8 V

V_CORE

Microcontroller

RESET

TPS3851-Q1

TPS3890-Q1

VDD

RESET

WDO

WDI

VDD

SENSE

NMI

RESET

SET1

GPIO

GND

4.7 µF

CWD

GND

2.7 nF

图8-3. Monitoring the Supply Voltage and Watchdog Supervision of a Microcontroller

8.2.1 Design Requirements

PARAMETER

DESIGN REQUIREMENT

DESIGN RESULT

Watchdog disable for initialization Watchdog must remain disabled for 5 seconds

5.02 seconds (typ)

1.8-V CMOS

period

until logic enables the watchdog timer

1.8-V CMOS

Output logic voltage

Monitored rail

Watchdog timeout

1.8 V with a 5% threshold

10 ms, typical

Worst-case V_ITN= 1.714 V –4.7%

t_WD(min)= 7.3 ms, t_WD(TYP)= 9.1 ms, t_WD(max)= 11 ms

Maximum device current

consumption

50 µA

37 µA when RESET or WDO is asserted ⁽¹⁾

(1) Only includes the TPS3851G18S-Q1 current consumption.

8.2.2 Detailed Design Procedure

8.2.2.1 Monitoring the 1.8-V Rail

The undervoltage comparator allows for precise voltage supervision of common rails between 1.8 V and 5.0 V.

This application calls for very tight monitoring of the rail with only 5% of variation allowed on the rail. To ensure

this requirement is met, the TPS3851G18S-Q1 was chosen for its –4% threshold. To calculate the worst-case

for V_ITN, the accuracy must also be taken into account. The worst-case for V_ITNcan be calculated by 方程式4:

V_{ITN(Worst Case)}= V_ITN(typ)× 0.992 = 1.8 × 0.96 × 0.992 = 1.714 V

(4)

Submit Document Feedback

Product Folder Links: TPS3851-Q1

TPS3851-Q1

ZHCSO14A –MARCH 2017 –REVISED SEPTEMBER 2021

www.ti.com.cn

8.2.2.2 Calculating the RESET and WDO Pullup Resistor

图8-4 shows the TPS3851-Q1 using an open-drain configuration for the RESET circuit. When the FET is off, the

resistor pulls the drain of the transistor to VDD and when the FET is turned on, the FET attempts to pull the drain

to ground, thus creating an effective resistor divider. The resistors in this divider must be chosen to ensure that

V_OLis below the maximum value. To choose the proper pullup resistor, there are three key specifications to keep

in mind: the pullup voltage (V_PU), the recommended maximum RESET pin current (I_RESET), and V_OL. The

maximum V_OLis 0.4 V, meaning that the effective resistor divider created must be able to bring the voltage on

the reset pin below 0.4 V with I_RESETkept below 10 mA. For this example, with a V_PUof 1.8 V, a resistor must be

chosen to keep I_RESETbelow 50 μA because this value is the maximum consumption current allowed. To ensure

this specification is met, a pullup resistor value of 100 kΩwas selected, which sinks a maximum of 18 μA when

RESET or WDO is asserted. As illustrated in 图 6-13, the RESET current is at 18 μA and the low-level output

voltage is approximately zero.

V_PU

RESET

CONTROL

图8-4. RESET Open-Drain Configuration

8.2.2.3 Setting the Watchdog

As illustrated in 图 8-1 there are three options for setting the watchdog timer. The design specifications in this

application require the programmable timing option (external capacitor connected to CWD). When a capacitor is

connected to the CWD pin, the watchdog timer is governed by 方程式 1 for the standard timing version.

However, only the standard version is capable of meeting this timing requirement. 方程式 1 is only valid for ideal

capacitors, any temperature or voltage derating must be accounted for separately.

C_CWD(nF) = (t_WD(ms) –0.0381) / 3.23 = (10 –0.381) / 3.23 = 2.97 nF

(5)

The nearest standard capacitor value to 2.9 nF is 2.7 nF. Selecting 2.7 nF for the C_CWDcapacitor gives the

following minimum timing parameters:

t_WD(MIN)= 0.905 × t_WD(TYP)= 0.905 × (3.23 × 2.7 + 0.381) = 8.24 ms

t_WD(MAX)= 1.095 × t_WD(TYP)= 1.095 × (3.23 × 2.7 + 0.381) = 9.97 ms

(6)

(7)

Capacitor tolerance also influences t_WD(MIN)and t_WD(MAX). Select a ceramic COG dielectric capacitor for high

accuracy. For 2.7 nF, COG capacitors are readily available with 5% tolerances. This selection results in a 5%

decrease in t_WD(MIN)and a 5% increase in t_WD(MAX), giving 7.34 ms and 11 ms, respectively. To ensure proper

functionality, a falling edge must be issued before t_WD(min). 图 8-6 illustrates that a WDI signal with a period of 5

ms keeps WDO from asserting.

Submit Document Feedback

Product Folder Links: TPS3851-Q1

TPS3851-Q1

ZHCSO14A –MARCH 2017 –REVISED SEPTEMBER 2021

www.ti.com.cn

8.2.2.4 Watchdog Disabled During Initialization Period

The watchdog is often needed to be disabled during startup to allow for an initialization period. When the

initialization period is over, the watchdog timer is turned back on to allow the microcontroller to be monitored by

the TPS3851-Q1. To achieve this setup, SET1 must start at GND. In this design, SET1 is controlled by a

TPS3890-Q1 supervisor. In this application, the TPS3890-Q1 was chosen to monitor VDD as well, which means

that the RESET on the TPS3890-Q1 stays low until V_DDrises above V_ITN. When VDD comes up, the delay time

can be adjusted through the CT capacitor on the TPS3890-Q1. With this approach, the RESET delay can be

adjusted from a minimum of 25 μs to a maximum of 30 seconds. For this design, a typical delay of 5 seconds is

needed before the watchdog timer is enabled. The CT capacitor calculation (see the TPS3890-Q1 data sheet)

yields an ideal capacitance of 4.67 μF, giving a closest standard ceramic capacitor value of 4.7 μF. When

connecting a 4.7-μF capacitor from CT to GND, the typical delay time is 5 seconds. 图8-5 shows that when the

watchdog is disabled, the WDO output remains high. However when SET1 goes high and there is no WDI signal,

WDO begins to assert. See the TPS3890-Q1 data sheet for detailed information on the TPS3890-Q1.

8.2.3 Glitch Immunity

图 8-8 shows the high-to-low glitch immunity for the TPS3851G18S-Q1 with a 7% overdrive with V_DDstarting at

1.8 V. This curve shows that V_DDcan go below the threshold for at least 6 µs before RESET asserts.

8.2.4 Application Curves

Unless otherwise stated, application curves were taken at T_A= 25°C.

VDD

2V/div

VDD

2V/div

6 seconds

SET1

5ms

2V/div

WDI

2V/div

WDO

2V/div

WDO

2V/div

RESET

2V/div

RESET

2V/div

1s/div

2ms/div

图8-5. Startup Without a WDI Signal

图8-6. Typical WDI Signal

VDD

500mV/div

6µs

WDO

2V/div

195 ms

RESET

2V/div

RESET

2V/div

50ms/div

2µs/div

图8-7. Typical RESET Delay

图8-8. High-to-Low Glitch Immunity

Submit Document Feedback

Product Folder Links: TPS3851-Q1

TPS3851-Q1

ZHCSO14A –MARCH 2017 –REVISED SEPTEMBER 2021

www.ti.com.cn

9 Power Supply Recommendations

This device is designed to operate from an input supply with a voltage range between 1.6 V and 6.5 V. An input

supply capacitor is not required for this device; however, if the input supply is noisy, then good analog practice is

to place a 0.1-µF capacitor between the VDD pin and the GND pin.

Submit Document Feedback

Product Folder Links: TPS3851-Q1

TPS3851-Q1

ZHCSO14A –MARCH 2017 –REVISED SEPTEMBER 2021

www.ti.com.cn

10 Layout

10.1 Layout Guidelines

• Make sure that the connection to the VDD pin is low impedance. Good analog design practice is to place a

0.1-µF ceramic capacitor as near as possible to the VDD pin.

• If a C_CWDcapacitor or pullup resistor is used, place these components as close as possible to the CWD pin. If

the CWD pin is left unconnected, make sure to minimize the amount of parasitic capacitance on the pin.

• Place the pullup resistors on RESET and WDO as close to the pin as possible.

10.2 Layout Example

Vin

C_VDD

R_PU1

Vin

R_PU2

Vin

C_CWD

VDD

CWD

RESET

WDO

WDI

GND

SET1

GND Plane

Denotes a via

图10-1. TPS3851-Q1 Recommended Layout

Submit Document Feedback

Product Folder Links: TPS3851-Q1

TPS3851-Q1

ZHCSO14A –MARCH 2017 –REVISED SEPTEMBER 2021

www.ti.com.cn

11 Device and Documentation Support

11.1 Device Support

11.1.1 Device Nomenclature

表11-1. Device Nomenclature

DESCRIPTION

NOMENCLATURE

VALUE

TPS3851-Q1

(high-accuracy supervisor with watchdog)

—

V_ITN= –4%

V_ITN= –7%

(nominal threshold as a percent of the nominal

monitored voltage)

1.8 V

2.5 V

yy(y)

3.0 V

(nominal monitored voltage option)

3.3 V

5.0 V

t_WD(ms) = 3.23 x C_WD(nF) + 0.381 (ms)

t_WD(ms) = 77.4 x C_WD(nF) + 55.2 (ms)

(nominal watchdog timeout period)

11.2 Documentation Support

11.2.1 Related Documentation

For related documentation see the following:

•

• TPS3890-Q1 Low Quiescent Current, 1% Accurate Supervisor with Programmable Delay

• TPS3851EVM-780 Evaluation Module

11.3 接收文档更新通知

要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新进行注册，即可每周接收产品信息更

改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

11.4 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的《使用条款》。

11.5 Trademarks

TI E2E^™is a trademark of Texas Instruments.

所有商标均为其各自所有者的财产。

11.6 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

11.7 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

Submit Document Feedback

Product Folder Links: TPS3851-Q1

TPS3851-Q1

ZHCSO14A –MARCH 2017 –REVISED SEPTEMBER 2021

www.ti.com.cn

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

Submit Document Feedback

Product Folder Links: TPS3851-Q1

重要声明和免责声明

TI 提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，不保证没

有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担保。

这些资源可供使用TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的TI 产品，(2) 设计、验

证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。这些资源如有变更，恕不另行通知。TI 授权您仅可

将这些资源用于研发本资源所述的TI 产品的应用。严禁对这些资源进行其他复制或展示。您无权使用任何其他TI 知识产权或任何第三方知

识产权。您应全额赔偿因在这些资源的使用中对TI 及其代表造成的任何索赔、损害、成本、损失和债务，TI 对此概不负责。

TI 提供的产品受TI 的销售条款(https:www.ti.com/legal/termsofsale.html) 或ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI

提供这些资源并不会扩展或以其他方式更改TI 针对TI 产品发布的适用的担保或担保免责声明。重要声明

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

PACKAGE OPTION ADDENDUM

www.ti.com

23-Jun-2023

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

TPS3851G18EQDRBRQ1

TPS3851G18SQDRBRQ1

TPS3851G25EQDRBRQ1

TPS3851G25SQDRBRQ1

TPS3851G30EQDRBRQ1

TPS3851G30SQDRBRQ1

TPS3851G33EQDRBRQ1

TPS3851G33SQDRBRQ1

TPS3851G50EQDRBRQ1

TPS3851G50SQDRBRQ1

TPS3851H18EQDRBRQ1

TPS3851H18SQDRBRQ1

TPS3851H25EQDRBRQ1

TPS3851H25SQDRBRQ1

TPS3851H30EQDRBRQ1

TPS3851H30SQDRBRQ1

TPS3851H33EQDRBRQ1

TPS3851H33SQDRBRQ1

TPS3851H50EQDRBRQ1

TPS3851H50SQDRBRQ1

ACTIVE

SON

DRB

3000 RoHS & Green

NIPDAU | SN

Level-2-260C-1 YEAR

-40 to 125

851DF

Samples

NIPDAU | SN

851DE

851EF

851EE

851FF

851FE

851GF

851GE

851HF

851HE

851LF

851LE

851MF

851ME

851NF

851NE

851PF

851PE

851RF

851RE

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

23-Jun-2023

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF TPS3851-Q1 :

Catalog : TPS3851

•

NOTE: Qualified Version Definitions:

Catalog - TI's standard catalog product

•

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

22-Sep-2022

TAPE AND REEL INFORMATION

REEL DIMENSIONS

TAPE DIMENSIONS

Reel

Diameter

Cavity

A0 Dimension designed to accommodate the component width

B0 Dimension designed to accommodate the component length

K0 Dimension designed to accommodate the component thickness

Overall width of the carrier tape

P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2

Q3 Q4

Q1 Q2

Q3 Q4

User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TPS3851G18EQDRBRQ1 SON

TPS3851G18SQDRBRQ1 SON

TPS3851G25EQDRBRQ1 SON

TPS3851G25SQDRBRQ1 SON

TPS3851G30EQDRBRQ1 SON

TPS3851G30SQDRBRQ1 SON

TPS3851G33EQDRBRQ1 SON

TPS3851G33SQDRBRQ1 SON

TPS3851G50EQDRBRQ1 SON

TPS3851G50SQDRBRQ1 SON

TPS3851H18EQDRBRQ1 SON

TPS3851H18SQDRBRQ1 SON

TPS3851H25EQDRBRQ1 SON

TPS3851H25SQDRBRQ1 SON

TPS3851H30EQDRBRQ1 SON

TPS3851H30SQDRBRQ1 SON

DRB

3000

330.0

12.4

3.3

1.1

8.0

12.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

22-Sep-2022

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TPS3851H33EQDRBRQ1 SON

TPS3851H33SQDRBRQ1 SON

TPS3851H50EQDRBRQ1 SON

TPS3851H50SQDRBRQ1 SON

DRB

3000

330.0

12.4

3.3

1.1

8.0

12.0

Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

22-Sep-2022

TAPE AND REEL BOX DIMENSIONS

Width (mm)

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

TPS3851G18EQDRBRQ1

TPS3851G18SQDRBRQ1

TPS3851G25EQDRBRQ1

TPS3851G25SQDRBRQ1

TPS3851G30EQDRBRQ1

TPS3851G30SQDRBRQ1

TPS3851G33EQDRBRQ1

TPS3851G33SQDRBRQ1

TPS3851G50EQDRBRQ1

TPS3851G50SQDRBRQ1

TPS3851H18EQDRBRQ1

TPS3851H18SQDRBRQ1

TPS3851H25EQDRBRQ1

TPS3851H25SQDRBRQ1

TPS3851H30EQDRBRQ1

TPS3851H30SQDRBRQ1

TPS3851H33EQDRBRQ1

TPS3851H33SQDRBRQ1

SON

DRB

3000

367.0

35.0

Pack Materials-Page 3

PACKAGE MATERIALS INFORMATION

www.ti.com

22-Sep-2022

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

TPS3851H50EQDRBRQ1

TPS3851H50SQDRBRQ1

SON

DRB

3000

367.0

35.0

Pack Materials-Page 4

PACKAGE OUTLINE

DRB0008F

VSON - 1 mm max height

SCALE 4.000

PLASTIC SMALL OUTLINE - NO LEAD

3.1

2.9

PIN 1 INDEX AREA

3.1

2.9

0.1 MIN

(0.05)

SECTION A-A

TYPICAL

1 MAX

SEATING PLANE

0.08 C

0.05

0.00

EXPOSED

THERMAL PAD

1.6 0.05

(0.2) TYP

1.95

2.4 0.05

6X 0.65

0.35

0.25

PIN 1 ID

0.5

0.3

0.1

C A B

(OPTIONAL)

0.05

4222121/C 10/2016

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT

DRB0008F

VSON - 1 mm max height

PLASTIC SMALL OUTLINE - NO LEAD

(1.6)

SYMM

8X (0.6)

8X (0.3)

(2.4)

(0.95)

6X (0.65)

(R0.05) TYP

(0.55)

(2.8)

(

0.2) VIA

TYP

LAND PATTERN EXAMPLE

SCALE:20X

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

SOLDER MASK

OPENING

METAL

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4222121/C 10/2016

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com

EXAMPLE STENCIL DESIGN

DRB0008F

VSON - 1 mm max height

PLASTIC SMALL OUTLINE - NO LEAD

SYMM

METAL

TYP

8X (0.6)

8X (0.3)

(0.635)

SYMM

(1.07)

6X (0.65)

(R0.05) TYP

(1.47)

(2.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD

82% PRINTED SOLDER COVERAGE BY AREA

SCALE:25X

4222121/C 10/2016

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

PACKAGE OUTLINE

DRB0008K

VSON - 1 mm max height

SCALE 4.000

PLASTIC SMALL OUTLINE - NO LEAD

3.1

2.9

3.1

2.9

PIN 1 INDEX AREA

0.07 MIN

(0.13)

SECTION A-A

TYPICAL

1.0

0.8

SEATING PLANE

0.08 C

0.05

0.00

1.6 0.05

(0.2) TYP

EXPOSED

THERMAL PAD

(0.19) TYP

1.95

SYMM

2.4 0.05

6X 0.65

0.35

SYMM

PIN 1 ID

(45 X 0.3)

0.25

0.5

0.3

0.1

C A B

0.05

4227074/D 08/2022

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT

DRB0008K

VSON - 1 mm max height

PLASTIC SMALL OUTLINE - NO LEAD

(2.8)

(1.6)

8X (0.6)

8X (0.3)

(2.4)

SYMM

(0.95)

6X (0.65)

(R0.05) TYP

(

0.2) VIA

(0.55)

SYMM

TYP

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:20X

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

EXPOSED METAL

SOLDER MASK

OPENING

METAL

METAL UNDER

SOLDER MASK

OPENING

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4227074/D 08/2022

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com

EXAMPLE STENCIL DESIGN

DRB0008K

VSON - 1 mm max height

PLASTIC SMALL OUTLINE - NO LEAD

(2.8)

2X (1.5)

8X (0.6)

(1.06)

8X (0.3)

SYMM

(0.63)

6X (0.65)

(R0.05) TYP

SYMM

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD 9:

80% PRINTED SOLDER COVERAGE BY AREA

SCALE:25X

4227074/D 08/2022

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担

保。

这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验

证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。

这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。

您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成

本、损失和债务，TI 对此概不负责。

TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改

TI 针对 TI 产品发布的适用的担保或担保免责声明。

TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

TPS3851H30EQDRBRQ1 [TI]

相关型号：

TPS3851H30SQDRBRQ1

TPS3851H33EDRBR

TPS3851H33EDRBT

TPS3851H33EQDRBRQ1

TPS3851H33SQDRBRQ1

TPS3851H50EDRBR

TPS3851H50EDRBT

TPS3851H50EQDRBRQ1

TPS3851H50SQDRBRQ1

TPS3852

TPS3852-Q1

TPS3852G18QDRBRQ1