TPS389001DSET [TI]
具有可编程延迟的低静态电流、1% 精度监控器 | DSE | 6 | -40 to 125;
| 型号： | TPS389001DSET |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有可编程延迟的低静态电流、1% 精度监控器 | DSE | 6 | -40 to 125 监控 光电二极管 |
| 文件： | 总27页 (文件大小：1405K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TPS3890
ZHCSF70A –MARCH 2016–REVISED MAY 2016
TPS3890
延迟可编程的低静态电流、1% 精密监控器
1 特性
3 说明
1
•
上电复位 (POR) 发生器，可调节延迟时间：40μs
TPS3890 是一款静态电流较低的精密电压监控器，可
至 30s
监视低至 1.15V 的系统电压，开漏 RESET 信号在
SENSE 电压降至低于预设阈值或手动复位 (MR) 引脚
降为逻辑低电平时置为有效。RESET 输出在用户可调
节延迟时间内保持低电平，条件是 SENSE 电压和手动
复位 (MR) 返回至超出相应阈值。TPS3890 系列使用
精密电压实现 1% 的阈值精度。通过将 CT 引脚与外部
电容相连，可在 40μs 到 30s 范围内调节复位延迟时
间。TPS3890 具有 2.1μA 的超低静态电流，采用
1.5mm × 1.5mm 小型封装，使得器件非常适用于电池
供电和空间受限 应用。该器件的额定工作温度范围为 -
40℃ 至 +125℃ (TJ)。
•
•
•
•
超低静态电流：2.1μA（典型值）
高阈值精度：1%（最大值）
高精度迟滞
固定和可调节阈值电压：
–
固定阈值适用于标准电压轨：
1.2V 到 3.3V
–
可调节阈值电压低至 1.15V
•
•
•
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手动复位 (MR) 输入
开漏 RESET 输出
温度范围：-40°C 至 +125°C
封装：1.5mm × 1.5mm 晶圆级小外形无引线
(WSON) 封装
器件信息(1)
器件型号
TPS3890
封装
WSON (6)
封装尺寸（标称值）
2 应用
1.50mm x 1.50mm
(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。
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•
•
•
•
•
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数字信号处理器 (DSP) 或微控制器
现场可编程门阵列 (FPGA)、专用集成电路 (ASIC)
笔记本电脑、台式计算机
智能手机，手持产品
便携式电池供电产品
固态硬盘
机顶盒
工业控制系统
典型应用电路
VITN 精度与温度间的关系
1.8 V
1.2 V
0.75
Unit 1
Unit 2
Unit 3
Unit 4
Unit 5
Avg
0.5
0.25
0
VDD
SENSE
VCORE
VI/O
MR
CT
TPS389012
Microcontroller
RESET
RESET
-0.25
-0.5
-0.75
GND
GND
Copyright © 2016, Texas Instruments Incorporated
-50
-25
0
25
50
75
100
125
Temperature (èC)
D001
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLVSD65
TPS3890
ZHCSF70A –MARCH 2016–REVISED MAY 2016
www.ti.com.cn
目录
8.3 Feature Description................................................. 11
8.4 Device Functional Modes........................................ 14
Application and Implementation ........................ 15
9.1 Application Information............................................ 15
9.2 Typical Application ................................................. 15
1
2
3
4
5
6
7
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Device Comparison Table..................................... 3
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
7.1 Absolute Maximum Ratings ...................................... 4
7.2 ESD Ratings ............................................................ 4
7.3 Recommended Operating Conditions....................... 4
7.4 Thermal Information.................................................. 4
7.5 Electrical Characteristics........................................... 5
7.6 Timing Requirements................................................ 5
7.7 Typical Characteristics.............................................. 7
Detailed Description ............................................ 11
8.1 Overview ................................................................. 11
8.2 Functional Block Diagram ....................................... 11
9
10 Power Supply Recommendations ..................... 16
11 Layout................................................................... 17
11.1 Layout Guidelines ................................................. 17
11.2 Layout Example .................................................... 17
12 器件和文档支持 ..................................................... 18
12.1 文档支持 ............................................................... 18
12.2 社区资源................................................................ 18
12.3 商标....................................................................... 18
12.4 静电放电警告......................................................... 18
12.5 Glossary................................................................ 18
13 机械、封装和可订购信息....................................... 18
8
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Original (March 2016) to Revision A
Page
•
已发布为量产 .......................................................................................................................................................................... 1
2
Copyright © 2016, Texas Instruments Incorporated
TPS3890
www.ti.com.cn
ZHCSF70A –MARCH 2016–REVISED MAY 2016
5 Device Comparison Table
PART NUMBER
TPS389001
TPS389012
TPS389015
TPS389018
TPS389020
TPS389025
TPS389030
TPS389033
NOMINAL SUPPLY VOLTAGE NEGATIVE THRESHOLD (VITN
)
POSITIVE THRESHOLD (VITP)
Adjustable
1.2 V
1.15 V
1.15 V
1.44 V
1.73 V
1.90 V
2.40 V
2.89 V
3.17 V
1.157 V
1.157 V
1.449 V
1.740 V
1.911 V
2.414 V
2.907 V
3.189 V
1.5 V
1.8 V
2.0 V
2.5 V
3.0 V
3.3 V
6 Pin Configuration and Functions
DSE Package
6-Pin WSON
Top View
SENSE
GND
MR
1
2
3
6
5
4
RESET
CT
VDD
Not to scale
Pin Functions
PIN
I/O
DESCRIPTION
NO.
NAME
The CT pin offers a user-adjustable delay time. Connecting this pin to a ground-referenced capacitor sets
the RESET delay time to deassert.
5
CT
—
tPD(r) (sec) = CCT (µF) × 1.07 + 25 µs (nom).
2
3
GND
MR
—
I
Ground
Driving the manual reset pin (MR) low causes RESET to go low (assert).
RESET is an open-drain output that is driven to a low-impedance state when either the MR pin is driven to
a logic low or the monitored voltage on the SENSE pin is lower than the negative threshold voltage (VITN).
RESET remains low (asserted) for the delay time period after both MR is set to a logic high and the
SENSE input is above VITP. A pullup resistor from 10 kΩ to 1 MΩ can be used on this pin.
6
RESET
O
This pin is connected to the voltage to be monitored. When the voltage on SENSE falls below the
negative threshold voltage VITN, RESET goes low (asserts). When the voltage on SENSE rises above the
positive threshold voltage VITP, RESET goes high (deasserts).
1
4
SENSE
VDD
I
I
Supply voltage pin. Good analog design practice is to place a 0.1-µF ceramic capacitor close to this pin.
Copyright © 2016, Texas Instruments Incorporated
3
TPS3890
ZHCSF70A –MARCH 2016–REVISED MAY 2016
www.ti.com.cn
7 Specifications
7.1 Absolute Maximum Ratings
over operating junction temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
–0.3
–0.3
–0.3
–20
MAX
7
UNIT
VDD
SENSE
7
Voltage
RESET
7
V
MR
7
VCT
7
Current
RESET
20
125
150
mA
°C
Operating junction temperature, TJ
Storage temperature, Tstg
–40
Temperature
–65
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
VALUE
±1000
±750
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 500-V HBM is possible with the necessary precautions.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 250-V CDM is possible with the necessary precautions.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
1.5
0
NOM
MAX
5.5
5.5
5.5
5
UNIT
V
VDD
Power-supply voltage
VSENSE
VRESET
IRESET
CIN
SENSE voltage
V
RESET pin voltage
0
V
RESET pin current
–5
0
mA
µF
µF
kΩ
℃
Input capacitor, VDD pin
Reset timeout capacitor, CT pin
Pullup resistor, RESET pin
Junction temperature (free-air temperature)
0.1
25
CCT
0
22
1000
125
RPU
1
TJ
–40
7.4 Thermal Information
TPS3890
THERMAL METRIC(1)
DSE (WSON)
6 PINS
321.3
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
207.9
281.5
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
42.4
ψJB
284.8
RθJC(bot)
142.3
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
4
Copyright © 2016, Texas Instruments Incorporated
TPS3890
www.ti.com.cn
ZHCSF70A –MARCH 2016–REVISED MAY 2016
7.5 Electrical Characteristics
over the operating junction temperature range of –40°C to +125°C, 1.5 V ≤ VDD ≤ 5.5 V, and MR = VDD (unless otherwise
noted); typical values are at VDD = 5.5 V and TJ = 25°C
PARAMETER
Input supply voltage
Power-on reset voltage
TEST CONDITIONS
MIN
TYP
MAX
5.5
UNIT
V
VDD
1.5
VPOR
VOL(max) = 0.2 V, IRESET = 15 µA
0.8
V
VDD = 3.3 V, IRESET = 0 mA,
–40°C < TJ < 85°C
2.09
3.72
VDD = 3.3 V, IRESET = 0 mA,
–40°C < TJ < 105°C
4.5
5.8
4
VDD= 3.3 V, IRESET = 0 mA
IDD
Supply current (into VDD pin)
µA
VDD = 5.5 V, IRESET = 0 mA,
–40°C < TJ < 85°C
2.29
VDD = 5.5 V, IRESET = 0 mA,
–40°C < TJ < 105°C
5.2
6.5
1%
VDD = 5.5 V, IRESET = 0 mA
SENSE input threshold voltage
accuracy
Hysteresis(1)
VITN, VITP
VHYST
–1%
±0.5%
0.325%
0.575%
0.825%
8
VSENSE = 5 V
µA
nA
ISENSE
Input current
VSENSE = 5 V, TPS389001,
TPS389012
10
100
ICT
CT pin charge current
0.90
1.17
1.15
1.23
200
1.35
1.29
µA
V
VCT
RCT
VIL
CT pin comparator threshold voltage
CT pin pulldown resistance
Low-level input voltage (MR pin)
High-level output voltage
When RESET is deasserted
Ω
V
0.25 × VDD
VIH
0.7 x VDD
V
V
V
V
DD ≥ 1.5 V, IRESET = 0.4 mA
DD ≥ 2.7 V, IRESET = 2 mA
DD ≥ 4.5 V, IRESET = 3 mA
0.25
0.25
0.3
VOL
Low-level output voltage
Open-drain output leakage
V
High impedance,
VSENSE = VRESET = 5.5 V
ILKG(OD)
250
nA
(1) VHYST = [(VITP – VITN) / VITN] × 100%.
7.6 Timing Requirements
over the operating junction temperature range of –40°C to +125°C, 1.5 V ≤ VDD ≤ 5.5 V, MR = VDD, and 5% input overdrive(1)
(unless otherwise noted); typical values are at VDD = 5.5 V and TJ = 25°C
MIN
NOM
18
8
MAX
UNIT
CT = open, VDD = 3.3 V
CT = open, VDD = 5.5 V
CT = open, VDD = 3.3 V
VDD = 5.5 V
tPD(f)
SENSE (falling) to RESET propagation delay
µs
tPD(r)
SENSE (rising) to RESET propagation delay
SENSE pin glitch immunity
MR pin glitch immunity
25
9
µs
µs
ns
µs
ns
µs
tGI(SENSE)
tGI(MR)
tMRW
VDD = 5.5 V
100
MR pin pulse duration to assert RESET
MR pin low to out delay
1
td(MR)
250
325
tSTRT
Startup delay
(1) Overdrive = | (VIN / VTHRESH – 1) × 100% |.
版权 © 2016, Texas Instruments Incorporated
5
TPS3890
ZHCSF70A –MARCH 2016–REVISED MAY 2016
www.ti.com.cn
VDD
0.8 V
RESET
tPD(f)
=SENSE Falling Propagation Delay
=SENSE Rising Propagation Delay
= Undefined State
tPD(r)
tPD(r)
tPD(r)
tPD(f)
td(MR)
SENSE
VITP
VITN
MR
0.7 VDD
0.3 VDD
Time
图 1. Timing Diagram
6
版权 © 2016, Texas Instruments Incorporated
TPS3890
www.ti.com.cn
ZHCSF70A –MARCH 2016–REVISED MAY 2016
7.7 Typical Characteristics
over the operating junction temperature range of –40°C to +125°C, 1.5 V ≤ VDD ≤ 5.5 V, and MR = VDD (unless otherwise
noted)
0.75
0.5
0.75
0.5
Unit 1
Unit 2
Unit 3
Unit 4
Unit 5
Avg
Unit 1
Unit 2
Unit 3
Unit 4
Unit 5
Avg
0.25
0
0.25
0
-0.25
-0.5
-0.75
-0.25
-0.5
-0.75
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Temperature (èC)
Temperature (èC)
D001
D002
图 2. VITN Accuracy vs Temperature
图 3. VITP Accuracy vs Temperature
12
10
8
12
10
8
6
6
4
4
2
2
0
0
-0.25
-0.15
-0.05
0.05
0.15
0.25
-0.25
-0.15
-0.05
0.05
0.15
0.25
VITN Accuracy (%)
VITP Accuracy (%)
Tested at VDD = 1.5 V and VDD = 5.5 V, total tests = 136,348
Tested at VDD = 1.5 V and VDD = 5.5 V, total tests = 136,348
图 4. VITN Accuracy Histogram
图 5. VITP Accuracy Histogram
15
1.2
1.5 V
5.5 V
12
9
1.15
1.1
1.05
1
6
3
0
0.47
0.51
0.55
0.59
0.63
0.67
-50
-25
0
25
50
75
100
125
Hysteresis (%)
Temperature (èC)
D005
Tested at VDD = 1.5 V and VDD = 5.5 V, total tests = 136,348
图 6. Hysteresis Histogram
图 7. CT Current vs Temperature
版权 © 2016, Texas Instruments Incorporated
7
TPS3890
ZHCSF70A –MARCH 2016–REVISED MAY 2016
www.ti.com.cn
Typical Characteristics (接下页)
over the operating junction temperature range of –40°C to +125°C, 1.5 V ≤ VDD ≤ 5.5 V, and MR = VDD (unless otherwise
noted)
6
5
4
3
2
1
0
6
5
4
3
2
1
0
-40èC
0èC
25èC
85èC
105èC
125è
-40èC
0èC
25èC
85èC
105èC
125èC
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
VDD (V)
VDD (V)
D004
MR = VDD
MR = 0 V
图 9. Supply Current vs Power-Supply Voltage
图 8. Supply Current vs Power-Supply Voltage
3
1
VIL
VIH
VIL
VIH
2.75
2.5
2.25
2
0.75
0.5
0.25
0
1.75
1.5
1.25
1
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Temperature (èC)
Temperature (èC)
D006
VDD = 5.5 V
VDD = 1.5 V
图 11. MR Threshold vs Temperature
图 10. MR Threshold vs Temperature
600
500
400
300
200
100
0
34
33
32
31
30
29
VCC = 1.5 V
VCC = 3.3 V
VCC = 5.5 V
-40èC
0èC
25èC
85èC
125èC
-50
-25
0
25
50
75
100
125
1
10
100
Temperature (èC)
Overdrive (%)
D008
D009
VDD = 5.5 V
图 12. Startup Delay vs Temperature
图 13. Propagation Delay (tPD(r)) vs Overdrive
8
版权 © 2016, Texas Instruments Incorporated
TPS3890
www.ti.com.cn
ZHCSF70A –MARCH 2016–REVISED MAY 2016
Typical Characteristics (接下页)
over the operating junction temperature range of –40°C to +125°C, 1.5 V ≤ VDD ≤ 5.5 V, and MR = VDD (unless otherwise
noted)
34
33
32
31
30
29
34
30
26
22
18
14
10
6
-40èC
0èC
25èC
85èC
125èC
-40èC
0èC
25èC
85èC
125èC
2
1
10
100
1
10
100
Overdrive (%)
Overdrive (%)
D010
D011
VDD = 1.5 V
VDD = 5.5 V
图 14. Propagation Delay (tPD(r)) vs Overdrive
图 15. Propagation Delay (tPD(f)) vs Overdrive
34
30
26
22
18
14
10
6
32
31.5
31
-40èC
0èC
25èC
85èC
125èC
Overdrive=3%
Overdrive=5%
Overdrive=10%
30.5
30
29.5
29
2
-50
-25
0
25
50
75
100
125
1
10
100
Temperature (èC)
Overdrive (%)
D012
VDD = 5.5 V
VDD = 1.5 V
图 17. Low-to-High Glitch Immunity vs Temperature
图 16. Propagation Delay (tPD(f)) vs Overdrive
32
31.5
31
20
18
16
14
12
10
8
Overdrive=3%
Overdrive=5%
Overdrive=10%
Overdrive=3%
Overdrive=5%
Overdrive=10%
30.5
30
6
4
29.5
29
2
0
-50
-50
-25
0
25
50
75
100
125
-25
0
25
50
75
100
125
Temperature (èC)
Temperature (èC)
D017
VDD = 1.5 V
VDD = 5.5 V
图 18. Low-to-High Glitch Immunity vs Temperature
图 19. High-to-Low Glitch Immunity vs Temperature
版权 © 2016, Texas Instruments Incorporated
9
TPS3890
ZHCSF70A –MARCH 2016–REVISED MAY 2016
www.ti.com.cn
Typical Characteristics (接下页)
over the operating junction temperature range of –40°C to +125°C, 1.5 V ≤ VDD ≤ 5.5 V, and MR = VDD (unless otherwise
noted)
20
18
16
14
12
10
8
1.6
1.4
1.2
1
Overdrive=3%
Overdrive=5%
Overdrive=10%
-40èC
0èC
25èC
85èC
105èC
125èC
0.8
0.6
0.4
0.2
0
6
4
2
0
-50
-25
0
25
50
75
100
125
0
1
2
3
4
5
Temperature (èC)
IRESET (mA)
D018
D015
VDD = 1.5 V
VDD = 5.5 V
图 21. Low-Level Output Voltage vs RESET Current
图 20. High-to-Low Glitch Immunity vs Temperature
1.6
-40èC
0èC
25èC
85èC
105èC
125èC
1.4
1.2
1
0.8
0.6
0.4
0.2
0
0
1
2
3
4
5
IRESET (mA)
VDD = 1.5 V
图 22. Low-Level Output Voltage vs RESET Current
10
版权 © 2016, Texas Instruments Incorporated
TPS3890
www.ti.com.cn
ZHCSF70A –MARCH 2016–REVISED MAY 2016
8 Detailed Description
8.1 Overview
The TPS3890 supervisory product family is designed to assert a RESET signal when either the SENSE pin
voltage drops below VITN or the manual reset (MR) is driven low. The RESET output remains asserted for a user-
adjustable time after both the manual reset (MR) and SENSE voltages return above their respective thresholds.
8.2 Functional Block Diagram
VDD
VDD
TPS389001
Adjustable Version
RESET
RESET
MR
MR
SENSE
Reset
Logic
Timer
Reset
Logic
Timer
R1
CT
SENSE
CT
R2
1.15 V
VREF
1.15 V
VREF
GND
GND
Adjustable Voltage Version
Fixed Voltage Version
Copyright © 2016, Texas Instruments Incorporated
8.3 Feature Description
The combination of user-adjustable reset delay time with a broad range of threshold voltages allow these devices
to be used in a wide array of applications. Fixed negative threshold voltages (VITN) can be factory set from 1.15 V
to 3.17 V (see the Device Comparison Table for available options), and the adjustable device can be used to
customize the threshold voltage for other application needs by using an external resistor divider. The CT pin
allows the reset delay to be set between 25 μs and 30 s with the use of an external capacitor.
8.3.1 User-Configurable RESET Delay Time
The rising RESET delay time (tPD(r)) can be configured by installing a capacitor connected to the CT pin. The
TPS3890 uses a CT pin charging current (ICT) of 1.15 µA to help counter the effect of capacitor and board-level
leakage currents that can be substantial in certain applications. The rising RESET delay time can be set to any
value between 25 µs (no CCT installed) and 30 s (CCT = 26 µF).
The capacitor value needed for a given delay time can be calculated using 公式 1:
tPD(r) (sec) = CCT × VCT ÷ ICT+ tPD(r)(nom)
(1)
The slope of 公式 1 is determined by the time that the CT charging current (ICT) takes to charge the external
capacitor up to the CT comparator threshold voltage (VCT). When RESET is asserted, the capacitor is discharged
through the internal CT pulldown resistor (RCT). When the RESET conditions are cleared, the internal precision
current source is enabled and begins to charge the external capacitor and when the voltage on this capacitor
reaches 1.22 V, RESET is deasserted. Note that in order to minimize the difference between the calculated
RESET delay time and the actual RESET delay time, use a low-leakage type capacitor (such as a ceramic
capacitor) and minimize parasitic board capacitance around this pin.
版权 © 2016, Texas Instruments Incorporated
11
TPS3890
ZHCSF70A –MARCH 2016–REVISED MAY 2016
www.ti.com.cn
Feature Description (接下页)
8.3.2 Manual Reset (MR) Input
The manual reset (MR) input allows a processor or other logic circuits to initiate a reset. A logic low on MR
causes RESET to assert. After MR returns to a logic high and SENSE is above VITP, RESET is deasserted after
the user-defined reset delay. If MR is not controlled externally, then MR must be connected to VDD. Note that if
the logic signal driving MR is not greater than or equal to VDD, then some additional current flows into VDD and
out of MR and the difference is apparent when comparing 图 8 and 图 9.
图 23 shows how MR can be used to monitor multiple system voltages when only a single CT capacitor is
needed to set the RESET delay time.
1.2 V
3.3 V
V
V
CORE
SENSE VDD
SENSE VDD
I/O
3.3 V
TPS389012
TPS389033
DSP
MR
CT
RESET
MR
GPIO
GND
RESET
CT
GND
GND
Copyright © 2016, Texas Instruments Incorporated
图 23. Using MR to Monitor Multiple System Voltages
8.3.3 RESET Output
RESET remains high (deasserted) as long as SENSE is above the positive threshold (VITP) and the manual reset
signal (MR) is logic high. If SENSE falls below the negative threshold (VITN) or if MR is driven low, then RESET is
asserted, driving the RESET pin to a low impedance.
When MR is again logic high and SENSE is above VITP, a delay circuit is enabled that holds RESET low for a
specified reset delay period (tPD(r)). When the reset delay has elapsed, the RESET pin goes to a high-impedance
state and uses a pullup resistor to hold RESET high. Connect the pullup resistor to the proper voltage rail to
enable the outputs to be connected to other devices at the correct interface voltage level. RESET can be pulled
up to any voltage up to 5.5 V, independent of the device supply voltage. To ensure proper voltage levels, give
some consideration when choosing the pullup resistor values. The pullup resistor value is determined by VOL, the
output capacitive loading, and the output leakage current (ILKG(OD)).
8.3.4 SENSE Input
The SENSE input can vary from ground to 5.5 V (7.0 V, absolute maximum), regardless of the device supply
voltage used. The SENSE pin is used to monitor the critical voltage rail. If the voltage on this pin drops below
VITN, then RESET is asserted. When the voltage on the SENSE pin exceeds the positive threshold voltage,
RESET deasserts after the user-defined RESET delay time.
The internal comparator has built-in hysteresis to ensure well-defined RESET assertions and deassertions even
when there are small changes on the voltage rail being monitored.
The TPS3890 device is relatively immune to short transients on the SENSE pin. Glitch immunity is dependent on
threshold overdrive, as illustrated in 图 19 for VITN and 图 18 for VITP. Although not required in most cases, for
noisy applications good analog design practice is to place a 1-nF to 10-nF bypass capacitor at the SENSE input
to reduce sensitivity to transient voltages on the monitored signal.
12
版权 © 2016, Texas Instruments Incorporated
TPS3890
www.ti.com.cn
ZHCSF70A –MARCH 2016–REVISED MAY 2016
Feature Description (接下页)
The adjustable version (TPS389001) can be used to monitor any voltage rail down to 1.15 V using the circuit
shown in 图 24.
VIN
VMON
VDD
MR
R1
RPU
TPS389001
SENSE
RESET
R2
GND
Copyright © 2016, Texas Instruments Incorporated
图 24. Using the TPS389001 to Monitor a User-Defined Threshold Voltage
The target threshold voltage for the monitored supply (VITx(MON)) and the resistor divider values can be calculated
by using 公式 2 and 公式 3, respectively:
VITx(MON)= VITx × (1 + R1 ÷ R2)
(2)
公式 3 can be used to calculate either the negative threshold or the positive threshold by replacing VITx with
either VITN or VITP, respectively.
RTOTAL = R1 + R2
(3)
Resistors with high values minimize current consumption; however, the input bias current of the device degrades
accuracy if the current through the resistors is too low. Therefore, choosing an RTOTAL value so that the current
through the resistor divider is at least 100 times larger than the SENSE input current is simplest. See application
report Optimizing Resistor Dividers at a Comparator Input (SLVA450) for more details on sizing input resistors.
8.3.4.1 Immunity to SENSE Pin Voltage Transients
The TPS3702 is immune to short voltage transient spikes on the input pins. Sensitivity to transients depends on
both transient duration and overdrive (amplitude) of the transient. Overdrive is defined by how much VSENSE
exceeds the specified threshold, and is important to know because the smaller the overdrive, the slower the
response of the outputs (that is, undervoltage and overvoltage). Threshold overdrive is calculated as a percent of
the threshold in question, as shown in 公式 4.
Overdrive = | (VSENSE / VITx – 1) × 100% |
(4)
图 17 to 图 20 illustrate the glitch immunity that the TPS3890 has versus temperature with three different
overdrive voltages. The propagation delay versus overdrive curves (图 13 to 图 16) can be used to determine
how sensitive the TPS3890 family of devices are across an even wider range of overdrive voltages.
版权 © 2016, Texas Instruments Incorporated
13
TPS3890
ZHCSF70A –MARCH 2016–REVISED MAY 2016
www.ti.com.cn
8.4 Device Functional Modes
表 1 summarizes the various functional modes of the device.
表 1. Truth Table
VDD
MR
—
—
L
SENSE
—
RESET
VDD < VPOR
Undefined
(1)
VPOR < VDD < VDD(MIN)
—
L
L
V
V
V
DD ≥ VDD(MIN)
DD ≥ VDD(MIN)
DD ≥ VDD(MIN)
—
H
VSENSE < VITN
VSENSE > VITP
L
H
H
(1) When VDD falls below VDD(MIN), undervoltage-lockout (UVLO) takes effect and RESET is held low until VDD falls below VPOR
.
8.4.1 Normal Operation (VDD > VDD(min)
)
When VDD is greater than VDD(min), the RESET signal is determined by the voltage on the SENSE pin and the
logic state of MR.
•
MR high: when the voltage on VDD is greater than 1.5 V, the RESET signal corresponds to the voltage on
the SENSE pin relative to the threshold voltage.
•
MR low: in this mode, RESET is held low regardless of the voltage on the SENSE pin.
8.4.2 Above Power-On-Reset But Less Than VDD(min) (VPOR < VDD < VDD(min)
)
When the voltage on VDD is less than the VDD(min) voltage, and greater than the power-on-reset voltage (VPOR),
the RESET signal is asserted regardless of the voltage on the SENSE pin.
8.4.3 Below Power-On-Reset (VDD < VPOR
)
When the voltage on VDD is lower thanVPOR, the device does not have enough voltage to internally pull the
asserted output low and RESET is undefined and must not be relied upon for proper device function.
14
版权 © 2016, Texas Instruments Incorporated
TPS3890
www.ti.com.cn
ZHCSF70A –MARCH 2016–REVISED MAY 2016
9 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The following sections describe in detail how to properly use this device, depending on the requirements of the
final application.
9.2 Typical Application
A typical application for the TPS389018 is shown in 图 25. The TPS389018 can be used to monitor the 1.8-V
VDD rail required by the TI Delfino™ microprocessor family. The open-drain RESET output of the TPS389018 is
connected to the XRS input of the microprocessor. A reset event is initiated when the VDD voltage is less than
VITN or when MR is driven low by an external source.
1.8 V
3.3 V
SENSE VDD
VDD
TPS389018
Delfino MCU
1 MW
External
Reset
MR
RESET
XRS
GND
CT
GND
1.5 nF
Copyright © 2016, Texas Instruments Incorporated
图 25. TPS3890 Monitoring the Supply Voltage for a Delfino Microprocessor
9.2.1 Design Requirements
The TPS3890 RESET output can be used to drive the reset (XRS) input of a microprocessor. The RESET pin of
the TPS3890 is pulled high with a 1-MΩ resistor; the reset delay time is controlled by the CT capacitor and is set
depending on the reset requirement times of the microprocessor. During power-up, XRS must remain low for at
least 1 ms after VDD reaches 1.5 V for the C2000™ Delfino family of microprocessors. For 100-MHz operation,
the Delfino TMS320F2833x microcontroller uses a supply voltage of 1.8 V that must be monitored by the
TPS3890.
9.2.2 Detailed Design Procedure
The primary constraint for this application is choosing the correct device to monitor the supply voltage of the
microprocessor. The TPS389018 has a negative threshold of 1.73 V and a positive threshold of 1.74 V, making
the device suitable for monitoring a 1.8-V rail. The secondary constraint for this application is the reset delay time
that must be at least 1 ms to allow the Delfino microprocessor enough time to startup up correctly. Because a
minimum time is required, the worst-case scenario is a supervisor with a high CT charging current (ICT) and a low
CT comparator threshold (VCT). For applications with ambient temperatures ranging from –40°C to +125°C, CCT
can be calculated using ICT(Max), VCT(MIN), and solving for CCT in 公式 1 such that the minimum capacitance
required at the CT pin is 1.149 nF. If standard capacitors with ±20% tolerances are used, then the CT capacitor
must be 1.5 nF or larger to ensure that the 1-ms delay time is met.
A 0.1-µF decoupling capacitor is connected to the VDD pin as a good analog design practice and a 1-MΩ
resistor is used as the RESET pullup resistor to minimize the current consumption when RESET is asserted. The
MR pin can be connected to an external signal if desired or connected to VDD if not used.
版权 © 2016, Texas Instruments Incorporated
15
TPS3890
ZHCSF70A –MARCH 2016–REVISED MAY 2016
www.ti.com.cn
Typical Application (接下页)
9.2.3 Application Curve
600
VCC = 1.5 V
VCC = 3.3 V
VCC = 5.5 V
500
400
300
200
100
0
-50
-25
0
25
50
75
100
125
Temperature (èC)
D008
图 26. Startup Delay vs Temperature
10 Power Supply Recommendations
These devices are designed to operate from an input supply with a voltage range between 1.5 V and 5.5 V. An
input supply capacitor is not required for this device; however, if the input supply is noisy, then good analog
practice is to place a 0.1-µF capacitor between the VDD pin and the GND pin. This device has a 7-V absolute
maximum rating on the VDD pin. If the voltage supply providing power to VDD is susceptible to any large voltage
transient that can exceed 7 V, additional precautions must be taken.
16
版权 © 2016, Texas Instruments Incorporated
TPS3890
www.ti.com.cn
ZHCSF70A –MARCH 2016–REVISED MAY 2016
11 Layout
11.1 Layout Guidelines
Make sure that the connection to the VDD pin is low impedance. Good analog design practice is to place a 0.1-
µF ceramic capacitor near the VDD pin. If a capacitor is not connected to the CT pin, then minimize parasitic
capacitance on this pin so the RESET delay time is not adversely affected.
11.2 Layout Example
The layout example in shows how the TPS3890 is laid out on a printed circuit board (PCB) with a user-defined
delay.
RPU
SENSE
GND
MR
RESET
CT
CCT
VDD
CIN
GND
Vias used to connect pins for application-specific connections
图 27. Recommended Layout
版权 © 2016, Texas Instruments Incorporated
17
TPS3890
ZHCSF70A –MARCH 2016–REVISED MAY 2016
www.ti.com.cn
12 器件和文档支持
12.1 文档支持
12.1.1 相关文档ꢀ
以下相关文档可从 www.ti.com 下载：
•
•
•
•
•
•
优化比较器输入上的电阻分压器，SLVA450
《电源设计灵敏度分析》，SLVA481
《TMS320C28x 数字信号控制器入门》，SPRAAM0
《TPS3890EVM-775 评估模块用户指南》，SBVU030
C2000 Delfino 系列微处理器
《TMS320F2833x 微控制器》，SPRS439
12.2 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.3 商标
Delfino, C2000, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 机械、封装和可订购信息
以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对
本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
18
版权 © 2016, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS389001DSER
TPS389001DSET
TPS389012DSER
TPS389012DSET
TPS389015DSER
TPS389015DSET
TPS389018DSER
TPS389018DSET
TPS389020DSER
TPS389020DSET
TPS389025DSER
TPS389025DSET
TPS389030DSER
TPS389030DSET
TPS389033DSER
TPS389033DSET
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
DSE
DSE
DSE
DSE
DSE
DSE
DSE
DSE
DSE
DSE
DSE
DSE
DSE
DSE
DSE
DSE
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
NIPDAUAG
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
2V
2V
2W
2W
2X
2X
2Y
2Y
2Y
2Y
2Z
2Z
3A
3A
3B
3B
NIPDAUAG
NIPDAUAG
NIPDAUAG
NIPDAUAG
NIPDAUAG
NIPDAUAG
NIPDAUAG
NIPDAUAG
NIPDAUAG
NIPDAUAG
NIPDAUAG
NIPDAUAG
NIPDAUAG
NIPDAUAG
NIPDAUAG
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
15-Feb-2018
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS389001DSER
TPS389001DSET
TPS389012DSER
TPS389012DSET
TPS389015DSER
TPS389015DSET
TPS389018DSER
TPS389018DSET
TPS389020DSER
TPS389020DSET
TPS389025DSER
TPS389025DSET
TPS389030DSER
TPS389030DSET
TPS389033DSER
TPS389033DSET
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
DSE
DSE
DSE
DSE
DSE
DSE
DSE
DSE
DSE
DSE
DSE
DSE
DSE
DSE
DSE
DSE
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
3000
250
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
1.83
1.83
1.83
1.83
1.83
1.83
1.83
1.83
1.83
1.83
1.83
1.83
1.83
1.83
1.83
1.83
1.83
1.83
1.83
1.83
1.83
1.83
1.83
1.83
1.83
1.83
1.83
1.83
1.83
1.83
1.83
1.83
0.89
0.89
0.89
0.89
0.89
0.89
0.89
0.89
0.89
0.89
0.89
0.89
0.89
0.89
0.89
0.89
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
3000
250
3000
250
3000
250
3000
250
3000
250
3000
250
3000
250
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
15-Feb-2018
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS389001DSER
TPS389001DSET
TPS389012DSER
TPS389012DSET
TPS389015DSER
TPS389015DSET
TPS389018DSER
TPS389018DSET
TPS389020DSER
TPS389020DSET
TPS389025DSER
TPS389025DSET
TPS389030DSER
TPS389030DSET
TPS389033DSER
TPS389033DSET
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
DSE
DSE
DSE
DSE
DSE
DSE
DSE
DSE
DSE
DSE
DSE
DSE
DSE
DSE
DSE
DSE
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
3000
250
183.0
183.0
183.0
183.0
183.0
183.0
183.0
183.0
183.0
183.0
183.0
183.0
183.0
183.0
183.0
183.0
183.0
183.0
183.0
183.0
183.0
183.0
183.0
183.0
183.0
183.0
183.0
183.0
183.0
183.0
183.0
183.0
20.0
20.0
20.0
20.0
20.0
20.0
20.0
20.0
20.0
20.0
20.0
20.0
20.0
20.0
20.0
20.0
3000
250
3000
250
3000
250
3000
250
3000
250
3000
250
3000
250
Pack Materials-Page 2
PACKAGE OUTLINE
DSE0006A
WSON - 0.8 mm max height
SCALE 6.000
PLASTIC SMALL OUTLINE - NO LEAD
1.55
1.45
A
B
1.55
1.45
PIN 1 INDEX AREA
0.8 MAX
C
SEATING PLANE
0.08 C
(0.2) TYP
0.05
0.00
0.6
0.4
5X
3
4
2X 1
4X 0.5
6
1
0.3
6X
0.7
0.5
0.2
0.1
0.05
PIN 1 ID
C A B
C
4220552/A 04/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
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EXAMPLE BOARD LAYOUT
DSE0006A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
PKG
(0.8)
5X (0.7)
1
6
6X (0.25)
SYMM
4X 0.5
4
3
(R0.05) TYP
(1.6)
LAND PATTERN EXAMPLE
SCALE:40X
0.05 MIN
ALL AROUND
0.05 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
PADS 4-6
NON SOLDER MASK
DEFINED
PADS 1-3
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4220552/A 04/2021
NOTES: (continued)
3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
DSE0006A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
PKG
5X (0.7)
(0.8)
6X (0.25)
1
6
SYMM
4X (0.5)
4
3
(R0.05) TYP
(1.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:40X
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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