TPS3899DL49DSE [TI]
Nano 125 nA IQ, 1% Accurate Voltage Supervisor, Push-Button Monitor with Programmable Sense and Reset Delay;
| 型号： | TPS3899DL49DSE |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Nano 125 nA IQ, 1% Accurate Voltage Supervisor, Push-Button Monitor with Programmable Sense and Reset Delay |
| 文件： | 总23页 (文件大小：999K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS3899
SLVSFM0 – SEPTEMBER 2020
TPS3899
Nano 125 nA IQ, 1% Accurate Voltage Supervisor, Push-Button Monitor with
Programmable Sense and Reset Delay
1 Features
3 Description
•
•
•
•
•
•
•
•
Supply voltage monitor and push-button monitor
VDD range: 0.7 V to 6 V
Programmable sense and reset delay
Nano quiescent current: 125 nA (typ)
High threshold accuracy: ±0.5% (typ)
Precision hysteresis: 5% (typ)
Adjustable threshold voltage: 0.51 V (typ)
Multiple output topologies
– DL: open-drain active-low
– PL: push-pull active-low
– PH: push-pull active-high
Temperature range: –40°C to +125°C
Package: 1.5-mm × 1.5-mm WSON
The TPS3899 is a nano-Iq, precision voltage
supervisor that monitors system voltages or push-
button inputs as low as 0.51 V. When the voltage of
SENSE drops below the VIT- threshold, RESET/
RESET will toggle after the programmed sense delay,
set by CTS, has been reached. The TPS3899 asserts
an open-drain or push-pull RESET/RESET signal to
active-low logic (RESET) or active-high logic (RESET).
The RESET/RESET output remains active until the
SENSE voltage returns above the rising voltage
threshold (VIT- + VHYS) for the reset delay set by CTR.
The TPS3899 family uses a precision reference to
achieve ±1% threshold accuracy. The sense delay
and reset delay time can be user-adjusted by
connecting a capacitor to the CTS and CTR pins
respectively. The TPS3899 has a nano quiescent
current of 125 nA (typ) and is available in a small 1.5-
mm × 1.5-mm WSON package, making the device
•
•
2 Applications
•
•
•
•
•
•
•
•
•
Electricity meters
Building Automation
well-suited
for
battery-powered
and
space-
Body Control Module (BCM)
Data center and enterprise computing
Notebooks, desktop computers, servers
Smartphones, hand-held products
Portable, battery-powered equipment
Solid-state drives
constrained applications. The device is fully specified
over a temperature range of –40°C to +125°C (TA).
Device Information
PART NUMBER
TPS3899
PACKAGE (1)
BODY SIZE (NOM)
WSON (6) DSE
1.50 mm × 1.50 mm
STB & DVR
1. For all available packages, see the orderable
addendum at the end of the data sheet
0.7 V to 6.0 V
*Rpull-up
VDD
SENSE
RESET
CTR
Push-button
input
TPS3899
CTS
GND
Rpull-up required for open-drain variants only
Figure 3-1. Typical Application Circuit
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. ADVANCE INFORMATION for preproduction products; subject to change
without notice.
TPS3899
SLVSFM0 – SEPTEMBER 2020
www.ti.com
Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Device Comparison.........................................................3
6 Pin Configuration and Functions...................................4
Pin Functions.................................................................... 4
7 Specifications.................................................................. 5
7.1 Absolute Maximum Ratings........................................ 5
7.2 ESD Ratings .............................................................. 5
7.3 Recommended Operating Conditions.........................5
7.4 Thermal Information....................................................6
7.5 Electrical Characteristics.............................................7
7.6 Timing Requirements..................................................8
7.7 Timing Diagram...........................................................9
7.8 Typical Characteristics..............................................10
8 Detailed Description......................................................12
8.1 Overview...................................................................12
8.2 Functional Block Diagram.........................................12
8.3 Feature Description...................................................12
8.4 Device Functional Modes..........................................14
9 Application and Implementation..................................15
9.1 Application Information............................................. 15
9.2 Typical Application.................................................... 15
10 Power Supply Recommendations..............................17
11 Layout...........................................................................18
11.1 Layout Guidelines................................................... 18
11.2 Layout Example...................................................... 18
12 Device and Documentation Support..........................19
12.1 Device Support ...................................................... 19
12.2 Receiving Notification of Documentation Updates..20
12.3 Support Resources................................................. 20
12.4 Trademarks.............................................................20
12.5 Electrostatic Discharge Caution..............................21
12.6 Glossary..................................................................21
13 Mechanical, Packaging, and Orderable
Information.................................................................... 21
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
DATE
REVISION
NOTES
September 2020
*
Initial release.
Copyright © 2020 Texas Instruments Incorporated
2
Submit Document Feedback
Product Folder Links: TPS3899
TPS3899
SLVSFM0 – SEPTEMBER 2020
www.ti.com
5 Device Comparison
Figure 5-1 shows the device naming nomenclature of the TPS3899. For all possible output types and threshold
voltages options, see Device Naming Convention for a more detailed explanation. Contact TI sales
representatives or on TI's E2E forum for detail and availability of other options; minimum order quantities apply.
TPS3899 XX XX XXX
Package
DSE: WSON
Threshold Voltage
01: 0.51 V (adjustable)
Output Type
08: 0.8 V
...
54: 5.4 V
DL: Open-Drain Active-Low
PL: Push-Pull Active-Low
PH: Push-Pull Active-High
Figure 5-1. Device Naming Nomenclature
Copyright © 2020 Texas Instruments Incorporated
Submit Document Feedback
3
Product Folder Links: TPS3899
TPS3899
SLVSFM0 – SEPTEMBER 2020
www.ti.com
6 Pin Configuration and Functions
6
5
4
CTR
CTS
1
2
3
RESET /RESET
SENSE
GND
VDD
Figure 6-1. DSE Package, 6-Pin , TPS3899 Top View
Pin Functions
PIN
I/O
DESCRIPTION
NO.
NAME
Capacitor programmable reset delay. The CTR pin offers a user-adjustable delay time when returning from
reset condition. Connecting this pin to a ground-referenced capacitor sets the RESET/RESET delay time to
deassert.
1
CTR
—
Capacitor programmable sense delay.The CTS pin offers a user-adjustable delay time when asserting
reset condition. Connecting this pin to a ground-referenced capacitor sets the RESET/RESET delay time to
assert.
2
CTS
—
3
4
GND
VDD
—
I
Ground
Supply voltage pin. Good analog design practice is to place a 0.1-µF ceramic capacitor close to this pin.
This pin is connected to the voltage to be monitored for fixed variants or to a resistor divider for the
adjustable variant. When the voltage on the SENSE pin transistions below the negative threshold voltage
VIT-, RESET/RESET asserts to active logic after the sense delay set by CTS. When the voltage on the
SENSE pin transistions above the positive threshold voltage VIT- + VHYS, RESET/RESET releases to
inactive logic (deasserts) after the reset delay set by CTR.
5
SENSE
I
RESETactive-low output that asserts to a logic low state after CTS delay when the monitored voltage on
the SENSE pin is lower than the negative threshold voltage (VIT-). RESETremains logic low (asserted) until
the SENSE input rises above VIT- + VHYS and the CTR reset delay expires.
6
6
RESET
RESET
O
O
RESET active-high output that asserts to a logic high state after CTS delay when the monitored voltage on
the SENSE pin is lower than the negative threshold voltage (VIT-). RESET remains logic high (asserted)
until the SENSE input rises above VIT- + VHYS and the CTR reset delay expires.
Copyright © 2020 Texas Instruments Incorporated
4
Submit Document Feedback
Product Folder Links: TPS3899
TPS3899
SLVSFM0 – SEPTEMBER 2020
www.ti.com
7 Specifications
7.1 Absolute Maximum Ratings
Over operating free-air temperature range, unless otherwise noted(1)
MIN
–0.3
–0.3
–0.3
-0.3
MAX
6.5
UNIT
V
Voltage
Voltage
VDD, SENSE
CTR, CTS
VDD+0.3 (3)
V
RESET(TPS3899DL)
6.5
Voltage
V
RESET(TPS3899PL), RESET (TPS3899PH)
RESET pin and RESET pin
Operating Ambient temperature, TA
Storage, Tstg
VDD+0.3 (3)
±20
Current
mA
°C
Temperature(2)
Temperature(2)
–40
–65
125
150
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) As a result of the low dissipated power in this device, it is assumed that TJ = TA.
(3) The absolute maximum rating is (VDD + 0.3) V or 6.5 V, whichever is smaller
7.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC
JS-001(1)
± 2000
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC specification
JESD22-C101(2)
± 750
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
Over operating free-air temperature range (unless otherwise noted)
MIN
0
NOM
MAX
VDD
6
UNIT
V
Voltage
Voltage
SENSE, CTR,CTS
VDD
0
V
RESET(TPS3899DL)
0
6
Voltage
V
RESET(TPS3899PL), RESET (TPS3899PH)
RESET pin and RESET pin current
Junction temperature (free air temperature)
CTR pin capacitor range
0
VDD
±5
Current
TJ
0
mA
°C
–40
0
125
10
CCTR
CCTS
µF
µF
CTS pin capacitor range
0
10
Copyright © 2020 Texas Instruments Incorporated
Submit Document Feedback
5
Product Folder Links: TPS3899
TPS3899
SLVSFM0 – SEPTEMBER 2020
www.ti.com
7.4 Thermal Information
TPS3899
DSE
THERMAL METRIC(1)
UNIT
6 PINS
RθJA
Junction-to-ambient thermal resistance
214.9
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
Junction-to-top characterization parameter
153.7
112.3
25.5
°C/W
°C/W
°C/W
ψJT
ψJB
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
111.8
N/A
°C/W
°C/W
RθJC(bot)
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Copyright © 2020 Texas Instruments Incorporated
6
Submit Document Feedback
Product Folder Links: TPS3899
TPS3899
SLVSFM0 – SEPTEMBER 2020
www.ti.com
7.5 Electrical Characteristics
CTR = CTS = Open, RESETpull-up resistor (Rpull-up) = 100 kΩ to VDD, output reset load (CLOAD) = 10 pF and
over the operating free-air temperature range – 40°C to 125°C, unless otherwise noted. Typical values are at
TA = 25°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
COMMON PARAMETERS
Input supply voltage (Open Drain Low
and Push Pull Low)
VDD
VDD
0.7
1
6
6
V
V
V
Input supply voltage (Push Pull High)
Negative-going input threshold range
VIT-
Range
for all output configs
0.8
5.4
VREF-ADJ- Reference voltage for adjustable sense
0.51
±1
V
threshold version
VIT
VIT-
Negative-going input threshold accuracy
accuracy
TBD
TBD
%
VIT- = 0.8 V, VIT- = 0.51 V
VIT- = 0.9 V to 5.4 V
3
3
5
5
8
7
%
%
VHYS
Hysteresis on VIT- pin
ISENSE-
Current into Sense pin when sense pin is VDD = VSENSE = 6 V
separate VIT- = 0.8 V to 5.4 V
0.025
0.3
µA
SEP-
SENSE
ISENSE-
Current into Sense pin when sense pin is VDD = VSENSE = 6 V
separate,ADJ version VIT- = 0.51 V
0.025
0.125
0.05
1.2
µA
µA
SEP-
SENSE
IDD-SEP- Supply current into VDD pin when sense VDD = VSENSE = 6 V
pin is separate
VIT- = 0.8 V to 5.4 V
SENSE
RCTS
CTS pin internal resistance
CTR pin internal resistance
500
500
kΩ
kΩ
RCTR
TPS3899DL (Open-drain active-low)
VOL(max) = 300 mV
IOUT(Sink) = 15 µA
VPOR
Power on Reset Voltage
700
300
300
100
350
mV
mV
mV
nA
VDD = 0.85 V
IOUT(Sink) = 15 µA
Low level output voltage
VOL
VDD = 3.3 V
IOUT(Sink) = 2 mA
VDD = VPULLUP = 6V
―40°C to 85°C
10
10
Ilkg(OD)
Open-Drain output leakage current
VDD = VPULLUP = 6V
―40°C to 125°C
nA
TPS3899PL (Push-pull active-low)
VOL(max) = 300 mV
IOUT(Sink) = 15 µA
VPOR
Power on Reset Voltage (5)
700
300
300
mV
mV
mV
V
VDD = 0.85V
IOUT(Sink) = 15 µA
Low level output voltage
VOL
VDD = 3.3 V
IOUT(Sink) = 2mA
VDD = 1.8 V
IOUT(Source) = 500 µA
0.8VDD
0.8VDD
0.8VDD
High level output voltage
VDD = 3.3 V
IOUT(Source) = 500 µA
VOH
V
VDD = 6 V
IOUT(Source) = 2 mA
V
TPS3899PH (Push-pull active-high)
Copyright © 2020 Texas Instruments Incorporated
Submit Document Feedback
7
Product Folder Links: TPS3899
TPS3899
SLVSFM0 – SEPTEMBER 2020
www.ti.com
CTR = CTS = Open, RESETpull-up resistor (Rpull-up) = 100 kΩ to VDD, output reset load (CLOAD) = 10 pF and
over the operating free-air temperature range – 40°C to 125°C, unless otherwise noted. Typical values are at
TA = 25°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VOH(min) = 0.8VDD
IOUT (Source) = 15 uA
V
VPOR
Power on Reset Voltage(1)
900
mV
VDD = 3.3 V
IOUT(Sink) = 500 µA
300
300
mV
mV
V
Low level output voltage
High level output voltage
VOL
VDD = 6 V
IOUT(Sink) = 2 mA
VDD = 1V
IOUT(Sink) = 15 µA
0.8VDD
0.8VDD
0.8VDD
VDD = 1.5 V
IOUT(Sink) = 500 µA
VOH
V
VDD = 3.3 V
IOUT(Sink) = 2 mA
V
(1) VPOR is the minimum VDD voltage level for a controlled output state.
7.6 Timing Requirements
At 0.7 V ≤ VDD ≤ 6 V, CTR = CTS = Open, RESETpull-up resistor (Rpull-up) = 100 kΩ to VDD, output reset
load (CLOAD) = 10 pF and over the operating free-air temperature range ―40°C to 125°C, unless otherwise
noted. Typical values are at TA = 25°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
CTS pin = Open or NC; VDD
=
tD-SENSE
tD-SENSE
tD-SENSE
TPS3899x
Detect time delay
Detect time delay
Detect time delay
(VIT+ + 10%) to (VIT- - 10%)(2)
30
50
µs
CTS pin = 10 nF; VDD = (VIT+
10%) to (VIT- - 10%)(2)
+
TPS3899x+Detect
Pin
6.2
ms
CTS pin = 1 µF; VDD = (VIT+
10%) to (VIT- - 10%)(2)
+
TPS3899x+Detect
Pin
619
40
ms
µs
CTR pin = Open or NC
80
tD
Reset time delay
CTR pin = 10 nF
CTR pin = 1 µF
6.2
ms
ms
619
Glitch immunity VIT-
when sense pin is
separate
Glitch immunity VIT-
when sense pin is
separate
tGI_VIT-
5% VIT- overdrive(3)
10
10
µs
SENSE
tGI_VIT-
tSTRT
Glitch immunity VIT-
Startup Delay(1)
5% VIT- overdrive(3)
µs
µs
CTR pin = Open or NC
300
(1) When VDD starts from less than the specified minimum VDD and then exceeds VIT-, reset is release after the startup delay (tSTRT), a
capacitor at CT pin will add tD delay to tSTRT time
(2) tP_HL measured from threhold trip point (VIT-) to VOL for active low variants and VOH for active high variants.
(3) Overdrive % = [(VDD/ VIT-) - 1] × 100%
Copyright © 2020 Texas Instruments Incorporated
8
Submit Document Feedback
Product Folder Links: TPS3899
TPS3899
SLVSFM0 – SEPTEMBER 2020
www.ti.com
7.7 Timing Diagram
VDD
VPOR
SENSE
VIT- + VHYS
VIT-
tSTRT + tD
tD-SENSE
tD
RESET
tD-SENSE is controlled by CTS
tD is controlled by CTR
Undefined
Figure 7-1. TPS3899DL01 and TPS3899PL01 Timing Diagram
VDD
VPOR
SENSE
VIT- + VHYS
VIT-
tSTRT + tD
tD-SENSE
tD
RESET
tD-SENSE is controlled by CTS
tD is controlled by CTR
Undefined
Figure 7-2. TPS3899PH01 Timing Diagram
Copyright © 2020 Texas Instruments Incorporated
Submit Document Feedback
9
Product Folder Links: TPS3899
TPS3899
SLVSFM0 – SEPTEMBER 2020
www.ti.com
7.8 Typical Characteristics
Typical characteristics show the typical performance of the TPS3899 device. Test conditions are TA = 25°C, VDD
= 3.3V, and Rpull-up = 100KΩ, unless otherwise noted.
Figure 7-3. Supply Current vs Supply Voltage
Figure 7-4. SENSE Current vs VSENSE
Figure 7-5. VIT- Accuracy vs Temperature
Figure 7-6. VHYS vs Temperature
145
140
135
130
125
120
115
110
105
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
Figure 7-7. SENSE Glitch Immunity (VIT-) vs
Overdrive
Figure 7-8. Startup Delay vs Temperature
Copyright © 2020 Texas Instruments Incorporated
10
Submit Document Feedback
Product Folder Links: TPS3899
TPS3899
SLVSFM0 – SEPTEMBER 2020
www.ti.com
VDD falling below VIT-
CTR = OPEN
Figure 7-9. Propagation Delay vs Temperature
Figure 7-10. Reset Time Delay vs Temperature
CTS = OPEN
Figure 7-11. SENSE Delay vs Temperature
Copyright © 2020 Texas Instruments Incorporated
Submit Document Feedback
11
Product Folder Links: TPS3899
TPS3899
SLVSFM0 – SEPTEMBER 2020
www.ti.com
8 Detailed Description
8.1 Overview
The TPS3899 voltage supervisor, push-button monitor asserts a RESET/RESET signal to active when the
SENSE pin voltage drops below VIT- for the duration of the sense delay set by CTS. If the SENSE pin voltage
rises above VIT- + VHYS before the sense delay expires, the RESET/RESET pin does not assert. When asserted,
the RESET/RESET output remains asserted until SENSE voltage returns above VIT- + VHYS for the duration of
the reset delay set by CTR. If the SENSE pin voltage falls below VIT- before the reset delay expires while RESET
is asserted, RESET/RESET will remain asserted.
8.2 Functional Block Diagram
Push-pull variants only
VDD
VDD
RESET
LOGIC
TIMER
Cap ladder
Fixed
RESET (active-low variants: DL, PL)
ADJ
RESET (active-high variants: PH)
SENSE
+
œ
Reference
GND
VDD
VDD
RCTS
RCTR
CTR
CTS
GND
8.3 Feature Description
The combination of user-adjustable sense delay time via CTS and reset delay time via CTR with a broad range
of threshold voltages allow these devices to be used in a wide array of applications. Fixed negative threshold
voltages (VIT-) can be factory set from 0.8 V to 5.4 V in steps of 100 mV. CTS and CTR pins allows the sense
delay and reset delay to be set to a minimum of 80 μs by leaving these pins floating, or the CTS and CTS pins
can connect to an external capacitor to program the sense delay and reset delay independently.
8.3.1 User-Programmable Sense and Reset Time Delay
The sense delay corresponds to the configuration of CTS and the reset delay corresponds to the configuration of
CTR. The sense and reset time delay can be set to a minimum value of 50 µs and 80 µs by leaving the CTS and
CTR pins floating respectively, or a maximum value of approximately 6.2 seconds by connecting 10 µF delay
capacitor.
The relationship between external capacitor (CCT_EXT) in Farads at CTS or CTR pins and the time delay in
seconds is given by Equation 1.
tD = -ln (0.29) x RCT x CCT_EXT + tD (CTS or CTR = OPEN)
(1)
Equation 1 is simplified to Equation 2 and Equation 3 by plugging RCT and tD (CTS or CTR = OPEN) given in Electrical
Characteristics and Timing Requirements section:
tD-SENSE = 618937 x CCTS_EXT + 50µs
tD = 618937 x CCTR_EXT + 80µs
(2)
(3)
Copyright © 2020 Texas Instruments Incorporated
12
Submit Document Feedback
Product Folder Links: TPS3899
TPS3899
SLVSFM0 – SEPTEMBER 2020
www.ti.com
Equation 4 and Equation 5 solves for both external capacitor values (CCTS_EXT) and (CCTR_EXT) in units of
Farads where tD-SENSE and tD are in units of seconds
CCTS_EXT = (tD-SENSE - 50µs) ÷ 618937
CCTR_EXT = (tD - 80µs) ÷ 618937
(4)
(5)
The recommended maximum sense and reset delay capacitors for the TPS3899 is limited to 10 µF as this
ensures there is enough time for either capacitors to fully discharge when a voltage fault occurs. When a voltage
fault occurs, the previously charged up capacitor discharges, and if the monitored voltage returns from the fault
condition before either delay capacitors discharges completely, both delays will be shorter than expected
because the capacitors will begin charging from a voltage above zero. Larger delay capacitors can be used so
long as the capacitors have enough time to fully discharge during the duration of the voltage fault.
Figure 8-1 shows the charge and discharge behavior on CTS and CTR that defines the sense and reset delays
respectively. When SENSE transitions below VIT-, the capacitor connected to CTS begins to charge. Once the
CTS capacitor charges to an internal threshold shown as VTH_CTS, RESETtransistions to active-low logic state
and the CTS capacitor then begins to discharge immediately. When SENSE transistions above VIT- + VHYS, the
capacitor connected to CTR begins to charge. Once the CTR capacitor charges to the internal threhold VTH_CTR
,
RESET releases back to inactive logic high state and the CTR capacitor beginds to discharge immediately.
Please note that for active-high devices, RESET follows the inverse behavior of RESET.
SENSE
tdischarge-CTR
Vth_CTR
CTR
tdischarge-CTS
CTS
Vth_CTS
tD-SENSE
tD
RESET
Figure 8-1. CTS and CTS Charge and Discharge Behavior Relative to SENSE and RESET
8.3.2 RESET/RESET Output
Upon power up, RESET/RESET begins asserted and remains asserted until the SENSE pin voltage rises above
the positive voltage threshold (VIT- + VHYS) for the duration of the reset delay set by CTR. After the SENSE pin
voltage is above VIT- + VHYS for the reset delay, RESET/RESET deasserts. RESET/RESET remains deasserted
long as the SENSE pin voltage is above the positive threshold. If the SENSE pin voltage falls below the negative
threshold (VIT-) for the duration of the sense delay set by CTS, then RESET/RESET is asserted.
Copyright © 2020 Texas Instruments Incorporated
Submit Document Feedback
13
Product Folder Links: TPS3899
TPS3899
SLVSFM0 – SEPTEMBER 2020
www.ti.com
A pull-up resistor is required for the open-drain variants. Connect the pull-up resistor to the proper voltage rail to
enable the outputs to be connected to other devices at the correct interface voltage level. RESET/RESET can be
pulled up to any voltage up to 6.0 V, independent of the device supply voltage.
8.3.3 SENSE Input
The SENSE input can vary from ground to 6.0 V, regardless of the device supply voltage used. The SENSE pin
is used to monitor the critical voltage rail or push-button input. If the voltage on this pin drops below VIT-, then
RESET/RESET is asserted after the sense delay time set by CTS. When the voltage on the SENSE pin rises
above the positive threshold voltage (VIT- + VHYS), RESET/RESET deasserts after the reset delay time set by
CTR.
The internal comparator has built-in hysteresis to ensure well-defined RESET/RESET assertions and
deassertions even when there are small changes on the voltage rail being monitored.
The TPS3899 device is relatively immune to short transients on the SENSE pin. Glitch immunity, tGI_V SENSE, is
IT-
dependent on threshold overdrive, as illustrated in Figure 7-7. Although not required in most cases, for noisy
applications good analog design practice is to place a 1-nF to 10-nF bypass capacitor at the SENSE input to
reduce sensitivity to transient voltages on the monitored signal.
8.3.3.1 Immunity to SENSE Pin Voltage Transients
The TPS3899 is immune to short voltage transient spikes on the input pins. Sensitivity to transients depends on
both transient duration and overdrive (amplitude) of the transient. Overdrive is defined by how much VSENSE
exceeds the specified threshold, and is important to know because the smaller the overdrive, the slower the
response of the outputs. Threshold overdrive is calculated as a percent of the threshold in question, as shown in
Equation 6.
Overdrive = | (VSENSE / VIT- – 1) × 100% |
(6)
8.4 Device Functional Modes
Table 8-1 summarizes the various functional modes of the device.
Table 8-1. Truth Table
VDD
VDD < VPOR
SENSE(2)
RESET
RESET
—
—
Undefined
Undefined
(1)
VPOR < VDD < VDD(MIN)
VDD ≥ VDD(MIN)
VDD ≥ VDD(MIN)
L
L
H
H
L
VSENSE < VIT-
VSENSE > VIT- + VHYS
H
(1) When VDD falls below VDD(MIN), undervoltage-lockout (UVLO) takes effect and RESETis held logic low (RESET is held logic high) until
VDD falls below VPOR at which the RESET/RESET output is undefined.
(2) SENSE pin voltage must be < VIT- for the sense delay set by CTS or > VIT- + VHYS for the reset delay set by CTR before RESET
transistions
8.4.1 Normal Operation (VDD > VDD(min)
)
When VDD is greater than VDD(min), the RESET/RESET pin is determined by the voltage on the SENSE pin and
the sense delay and reset delay set by CTS and CTR respecively.
8.4.2 Above Power-On-Reset But Less Than VDD(min) (VPOR < VDD < VDD(min)
)
When the voltage on VDD is less than the VDD(min) voltage, and greater than the power-on-reset voltage (VPOR),
the RESET/RESET signal is asserted regardless of the voltage on the SENSE pin.
8.4.3 Below Power-On-Reset (VDD < VPOR
)
When the voltage on VDD is lower than VPOR, the device does not have enough voltage to internally pull the
asserted RESET output low and RESET is undefined. RESET is also undefined and may pull up to VDD or to
the pull-up voltage. Neither output should be relied upon for proper device function.
Copyright © 2020 Texas Instruments Incorporated
14
Submit Document Feedback
Product Folder Links: TPS3899
TPS3899
SLVSFM0 – SEPTEMBER 2020
www.ti.com
9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
9.1 Application Information
The following sections describe in detail how to properly use this device, depending on the requirements of the
final application.
9.2 Typical Application
Design 1: Adjustable Voltage Supervisor with Push-Button Functionality
A typical application for the TPS3899 is voltage rail monitoring with push-button functionality and specific timing
requirements.
In this design application, the TPS3899DL01 is being used to monitor a 3.3V power rail and will trigger a reset
when the voltage drops below 2.9V or when the push-button is pressed. The reset output connects to an MCU
for system resetting or servicing the push-button.
3.3V
0.1µF
Rpull-up
10kΩ
47.5kΩ
R1
VDD
RESET
TPS3899DL01
CTS CTR
SENSE
Push-button
input
R2
10kΩ
0.1µF
GND
0.1µF
Figure 9-1. Design 1 - Adjustable Voltage Supervisor with Push-Button Functionality Circuit
9.2.1 Design Requirements
The design requirements, described in Table 9-1, for this design cover a defined reset threshold voltage of 2.9V,
a sense delay of 60ms, a reset delay of 60ms, and an output current no larger than 500µA.
Table 9-1. Design Requirements
PARAMETER
Reset Asserting
DESIGN REQUIREMENTS
DESIGN RESULTS
Reset needs to assert when under the reset Reset asserts when under the reset condition
condition of a button press or VDD ≤ 2.9V. of a button press or VDD ≤ 2.93V.
Reset Asserting Timing
Output Current
Reset output needs to assert when the reset Reset output asserts when the reset
conditions are met for 60ms, and needs to
de-assert after 60ms of no reset conditions.
conditions are met for 62ms and will deassert
after 62ms of no reset conditions.
The output current must not exceed 500µA.
The output current is 300µA under the reset
condition.
Copyright © 2020 Texas Instruments Incorporated
Submit Document Feedback
15
Product Folder Links: TPS3899
TPS3899
SLVSFM0 – SEPTEMBER 2020
www.ti.com
9.2.2 Detailed Design Procedure
The TPS3899DL01 can monitor any voltage above 0.51V using an external voltage divider. This device has a
negative going input threshold voltage of 0.51V, however, the design needs to assert a reset when VDD drops
below 2.9V. By using a resistor divider (R1 = 47.5kΩ, R2 = 10kΩ) the negative going threshold voltage becomes
2.93V. The device's positive going voltage threshold is VIT- + VHYS. The typical VHYS is 25.5mV. This in
combination with the resistor divider makes the design's positive going threshold voltage equal to 3.08V. If VDD
falls below 2.93V for the duration of sense delay (tD-SENSE), the reset will assert. If VDD rises above 3.08V for the
duration of reset delay (tD), the reset will deassert. See Figure 9-2 for a timing diagram detailing the voltage
levels and reset assertion/deassertion conditions.
3.3 V
VIT+ = 3.08V
VIT- = 2.93V
SENSE
tD
tD-SENSE
tD
tD-SENSE
RESET
Figure 9-2. Design 1 Timing Diagram
This design will also enter a reset condition when the push-button (PB) is asserted. The push-button is tied to
ground and when pressed will drop the SENSE voltage to 0V, making the device assert a reset. As a good
analog practice, a 0.1µF capacitor was also placed on VDD.
The desired reset timing conditions are sense delay time of 60ms (how long it takes to trigger a reset) and a
reset delay time of 60ms (how long it takes to recover from a reset). Using Equation 4 and Equation 5,
respectively, to solve for CTS and CTR capacitor values, CTS = 0.1µF and CTR = 0.1µF. These capacitor values
give a nominal sense delay time of 62ms and nominal reset delay time of 62ms.
For the requirement of a maximum output current, a pull-up resistor needs to be selected so that the current
through the pull-up resistor exceeds no more than 500µA. When the reset output is low, the voltage drop across
the pull-up resistor is equal to VDD. Ohm’s law is used to calculate the minimum resistor value. The resistor
needs to be greater than 6kΩ in order to pull less than 500µA in the reset asserted low condition. A resistor
value of 10kΩ was selected to accomplish this.
Note that this design does not account for tolerances.
Copyright © 2020 Texas Instruments Incorporated
16
Submit Document Feedback
Product Folder Links: TPS3899
TPS3899
SLVSFM0 – SEPTEMBER 2020
www.ti.com
9.2.3 Application Curve
Figure 9-3. Sense Delay
Figure 9-4. Reset Delay
10 Power Supply Recommendations
These devices are designed to operate from an input supply with a voltage range between 0.7 V and 6 V. An
input supply capacitor is not required for this device; however, if the input supply is noisy, then good analog
practice is to place a 0.1-µF capacitor between the VDD pin and the GND pin. Also, placing a 1-nF to 10-nF
capacitor between the SENSE pin and GND can reduce the sensitivity to transient voltages on the monitored
signal. This device has a 6.5 V absolute maximum rating on the VDD pin. If the voltage supply providing power
to VDD is susceptible to any large voltage transient that can exceed 6.5 V, additional precautions must be taken.
Copyright © 2020 Texas Instruments Incorporated
Submit Document Feedback
17
Product Folder Links: TPS3899
TPS3899
SLVSFM0 – SEPTEMBER 2020
www.ti.com
11 Layout
11.1 Layout Guidelines
Make sure that the connection to the VDD pin is low impedance. Good analog design practice is to place a 0.1-
µF ceramic capacitor near the VDD pin. If a capacitor is not connected to the CTS or CTS pins, then minimize
parasitic capacitance on this pin so the sense delay or reset delay times are not adversely affected. For fixed
voltage threshold devices, good analog design practice is to place a 0.1-µF ceramic capacitor near the SENSE
pin.
11.2 Layout Example
The layout example in Figure 11-1 shows how the TPS3899 is laid out on a printed circuit board (PCB) with a
user-defined sense delay and reset delay.
RPU
RESET
CTR
CTS
GND
CCTS
SENSE
CCTS
VDD
CIN
GND
Figure 11-1. Recommended Layout
Copyright © 2020 Texas Instruments Incorporated
18
Submit Document Feedback
Product Folder Links: TPS3899
TPS3899
SLVSFM0 – SEPTEMBER 2020
www.ti.com
12 Device and Documentation Support
12.1 Device Support
12.1.1 Device Nomenclature
Figure 5-1 in Device Comparison shows how to decode the function of the device based on its part number
shown in Table 12-1.
Table 12-1. Device Naming Convention
ORDERABLE DEVICE NAME
THRESHOLD VOLTAGE (V)
-DL (OPEN-DRAIN ACTIVE-LOW) -PL (PUSH-PULL ACTIVE-LOW) -PH (PUSH-PULL ACTIVE-HIGH)
TPS3899DL01DSE
TPS3899DL08DSE
TPS3899DL09DSE
TPS3899DL10DSE
TPS3899DL11DSE
TPS3899DL12DSE
TPS3899DL13DSE
TPS3899DL14DSE
TPS3899DL15DSE
TPS3899DL16DSE
TPS3899DL17DSE
TPS3899DL18DSE
TPS3899DL19DSE
TPS3899DL20DSE
TPS3899DL21DSE
TPS3899DL22DSE
TPS3899DL23DSE
TPS3899DL24DSE
TPS3899DL25DSE
TPS3899DL26DSE
TPS3899DL27DSE
TPS3899DL28DSE
TPS3899DL29DSE
TPS3899DL30DSE
TPS3899DL31DSE
TPS3899DL32DSE
TPS3899DL33DSE
TPS3899PL01DSE
TPS3899PL08DSE
TPS3899PL09DSE
TPS3899PL10DSE
TPS3899PL11DSE
TPS3899PL12DSE
TPS3899PL13DSE
TPS3899PL14DSE
TPS3899PL15DSE
TPS3899PL16DSE
TPS3899PL17DSE
TPS3899PL18DSE
TPS3899PL19DSE
TPS3899PL20DSE
TPS3899PL21DSE
TPS3899PL22DSE
TPS3899PL23DSE
TPS3899PL24DSE
TPS3899PL25DSE
TPS3899PL26DSE
TPS3899PL27DSE
TPS3899PL28DSE
TPS3899PL29DSE
TPS3899PL30DSE
TPS3899PL31DSE
TPS3899PL32DSE
TPS3899PL33DSE
TPS3899PH01DSE
TPS3899PH08DSE
TPS3899PH09DSE
TPS3899PH10DSE
TPS3899PH11DSE
TPS3899PH12DSE
TPS3899PH13DSE
TPS3899PH14DSE
TPS3899PH15DSE
TPS3899PH16DSE
TPS3899PH17DSE
TPS3899PH18DSE
TPS3899PH19DSE
TPS3899PH20DSE
TPS3899PH21DSE
TPS3899PH22DSE
TPS3899PH23DSE
TPS3899PH24DSE
TPS3899PH25DSE
TPS3899PH26DSE
TPS3899PH27DSE
TPS3899PH28DSE
TPS3899PH29DSE
TPS3899PH30DSE
TPS3899PH31DSE
TPS3899PH32DSE
TPS3899PH33DSE
0.51
0.80
0.90
1.00
1.10
1.20
1.30
1.40
1.50
1.60
1.70
1.80
1.90
2.00
2.10
2.20
2.30
2.40
2.50
2.60
2.70
2.80
2.90
3.00
3.10
3.20
3.30
Copyright © 2020 Texas Instruments Incorporated
Submit Document Feedback
19
Product Folder Links: TPS3899
TPS3899
SLVSFM0 – SEPTEMBER 2020
www.ti.com
Table 12-1. Device Naming Convention (continued)
ORDERABLE DEVICE NAME
THRESHOLD VOLTAGE (V)
-DL (OPEN-DRAIN ACTIVE-LOW) -PL (PUSH-PULL ACTIVE-LOW) -PH (PUSH-PULL ACTIVE-HIGH)
TPS3899DL34DSE
TPS3899DL35DSE
TPS3899DL36DSE
TPS3899DL37DSE
TPS3899DL38DSE
TPS3899DL39DSE
TPS3899DL40DSE
TPS3899DL41DSE
TPS3899DL42DSE
TPS3899DL43DSE
TPS3899DL44DSE
TPS3899DL45DSE
TPS3899DL46DSE
TPS3899DL47DSE
TPS3899DL48DSE
TPS3899DL49DSE
TPS3899DL50DSE
TPS3899DL51DSE
TPS3899DL52DSE
TPS3899DL53DSE
TPS3899DL54DSE
TPS3899PL34DSE
TPS3899PL35DSE
TPS3899PL36DSE
TPS3899PL37DSE
TPS3899PL38DSE
TPS3899PL39DSE
TPS3899PL40DSE
TPS3899PL41DSE
TPS3899PL42DSE
TPS3899PL43DSE
TPS3899PL44DSE
TPS3899PL45DSE
TPS3899PL46DSE
TPS3899PL47DSE
TPS3899PL48DSE
TPS3899PL49DSE
TPS3899PL50DSE
TPS3899PL51DSE
TPS3899PL52DSE
TPS3899PL53DSE
TPS3899PL54DSE
TPS3899PH34DSE
TPS3899PH35DSE
TPS3899PH36DSE
TPS3899PH37DSE
TPS3899PH38DSE
TPS3899PH39DSE
TPS3899PH40DSE
TPS3899PH41DSE
TPS3899PH42DSE
TPS3899PH43DSE
TPS3899PH44DSE
TPS3899PH45DSE
TPS3899PH46DSE
TPS3899PH47DSE
TPS3899PH48DSE
TPS3899PH49DSE
TPS3899PH50DSE
TPS3899PH51DSE
TPS3899PH52DSE
TPS3899PH53DSE
TPS3899PH54DSE
3.40
3.50
3.60
3.70
3.80
3.90
4.00
4.10
4.20
4.30
4.40
4.50
4.60
4.70
4.80
4.90
5.00
5.10
5.20
5.30
5.40
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
Copyright © 2020 Texas Instruments Incorporated
20
Submit Document Feedback
Product Folder Links: TPS3899
TPS3899
SLVSFM0 – SEPTEMBER 2020
www.ti.com
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2020 Texas Instruments Incorporated
Submit Document Feedback
21
Product Folder Links: TPS3899
PACKAGE OPTION ADDENDUM
www.ti.com
12-Sep-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
PTPS3899DL01DSER
PREVIEW
WSON
DSE
6
3000
TBD
Call TI
Call TI
-40 to 125
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third
party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims,
damages, costs, losses, and liabilities arising out of your use of these resources.
TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on
ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable
warranties or warranty disclaimers for TI products.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2020, Texas Instruments Incorporated
相关型号：
TPS3899DL50-Q1
TPS3899-Q1 Nano-Power, Precision Voltage Supervisor, Push-Button Monitor with Programmable Sense and Reset DelayWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TPS3899DL50DSE
Nano 125 nA IQ, 1% Accurate Voltage Supervisor, Push-Button Monitor with Programmable Sense and Reset DelayWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TPS3899DL51-Q1
TPS3899-Q1 Nano-Power, Precision Voltage Supervisor, Push-Button Monitor with Programmable Sense and Reset DelayWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TPS3899DL51DSE
Nano 125 nA IQ, 1% Accurate Voltage Supervisor, Push-Button Monitor with Programmable Sense and Reset DelayWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TPS3899DL52-Q1
TPS3899-Q1 Nano-Power, Precision Voltage Supervisor, Push-Button Monitor with Programmable Sense and Reset DelayWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TPS3899DL52DSE
Nano 125 nA IQ, 1% Accurate Voltage Supervisor, Push-Button Monitor with Programmable Sense and Reset DelayWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TPS3899DL53-Q1
TPS3899-Q1 Nano-Power, Precision Voltage Supervisor, Push-Button Monitor with Programmable Sense and Reset DelayWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TPS3899DL53DSE
Nano 125 nA IQ, 1% Accurate Voltage Supervisor, Push-Button Monitor with Programmable Sense and Reset DelayWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TPS3899DL54-Q1
TPS3899-Q1 Nano-Power, Precision Voltage Supervisor, Push-Button Monitor with Programmable Sense and Reset DelayWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TPS3899DL54DSE
Nano 125 nA IQ, 1% Accurate Voltage Supervisor, Push-Button Monitor with Programmable Sense and Reset DelayWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TPS3899PH01-Q1
TPS3899-Q1 Nano-Power, Precision Voltage Supervisor, Push-Button Monitor with Programmable Sense and Reset DelayWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TPS3899PH01DSE
Nano 125 nA IQ, 1% Accurate Voltage Supervisor, Push-Button Monitor with Programmable Sense and Reset DelayWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
©2020 ICPDF网 联系我们和版权申明