TPS3899PL42-Q1 [TI]
TPS3899-Q1 Nano-Power, Precision Voltage Supervisor, Push-Button Monitor with Programmable Sense and Reset Delay;
| 型号： | TPS3899PL42-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | TPS3899-Q1 Nano-Power, Precision Voltage Supervisor, Push-Button Monitor with Programmable Sense and Reset Delay |
| 文件： | 总33页 (文件大小：2100K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS3899-Q1
SLVSG89A – APRIL 2021 – REVISED SEPTEMBER 2021
TPS3899-Q1 Nano-Power, Precision Voltage Supervisor, Push-Button Monitor with
Programmable Sense and Reset Delay
1 Features
3 Description
Qualified for automotive applications:
The TPS3899-Q1 is a nano power, precision voltage
supervisor with ±0.5% threshold accuracy and
programmable sense and reset time delay in a 6-pin
space saving 1.5 mm × 1.5 mm WSON package. The
TPS3899-Q1 is a feature-rich voltage supervisor that
offers the smallest total solution size in its class. Built-
in hysteresis along with programmable delay prevent
false reset signals when monitoring a voltage rail or
push button signals.
•
AEC-Q100 qualified with the following results:
– Device temperature grade 1: –40°C to +125°C
ambient operating temperature
– Device HBM ESD classification level 2
– Device CDM ESD classification level C7B
Designed for high performance:
•
•
•
Nano quiescent current: 125 nA (Typical)
High threshold accuracy: ±0.5% (Typical)
Built-in precision hysteresis (VHYS): 5% (Typical)
The separate VDD and SENSE pins allow for
the redundancy sought by high-reliability systems.
SENSE is decoupled from VDD and can monitor rail
voltages other than VDD. Optional use of external
resistors are supported by the high impedance input
of the SENSE pin. Both CTS and CTR provide delay
adjustability on the rising and falling edges of the
RESET signals. CTS also functions as a debouncer
by ignoring voltage glitches on the monitored voltage
rails and operates as a "manual reset" that can be
used to force a system reset.
Designed for a wide range of applications:
•
Operating voltage range:
– 0.85 V to 6 V (DL and PL outputs)
– 1 V to 6 V (PH output)
•
•
•
•
Adjustable threshold voltage: 0.505 V (Typical)
Precision voltage and push-button monitor
Programmable sense and reset delay
Fixed (VIT-) voltage: 0.8 V to 5.4 V in 0.1 V steps
The precision performance, best in-class features in
a compact form factor, makes the TPS3899-Q1 an
ideal solution for wide ranging automotive and battery-
powered / low-power applications. The device is fully
specified over a temperature range of
Multiple output topologies / Package type:
•
•
•
•
TPS3899DL-Q1: open-drain, active-low (RESET)
TPS3899PL-Q1: push-pull, active-low (RESET)
TPS3899PH-Q1: push-pull, active-high (RESET)
Package: 1.5-mm × 1.5-mm WSON (DSE)
–40°C to +125°C (TA).
2 Applications
Device Information
PART NUMBER
PACKAGE (1)
BODY SIZE (NOM)
•
•
•
•
•
•
Advance Driver Assistance Systems (ADAS)
Infotainment head unit
Automotive gateway
Camera module
Radar ECU
TPS3899-Q1
WSON (6) DSE
1.5 mm × 1.5 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet
0.85 V to 6.0 V
Automotive external amplifier
*Rpull-up
VDD
SENSE
RESET
CTR
Push-button
input
TPS3899-Q1
CTS
GND
*Rpull-up is required for open-drain variants only
Typical Application Circuit
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS3899-Q1
SLVSG89A – APRIL 2021 – REVISED SEPTEMBER 2021
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Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Device Nomenclature......................................................3
6 Pin Configuration and Functions...................................4
7 Specifications.................................................................. 5
7.1 Absolute Maximum Ratings ....................................... 5
7.2 ESD Ratings .............................................................. 5
7.3 Recommended Operating Conditions ........................5
7.4 Thermal Information ...................................................5
7.5 Electrical Characteristics ............................................6
7.6 Timing Requirements .................................................7
7.7 Timing Diagrams.........................................................8
7.8 Typical Characteristics................................................9
8 Detailed Description......................................................12
8.1 Overview...................................................................12
8.2 Functional Block Diagram.........................................12
8.3 Feature Description...................................................12
8.4 Device Functional Modes..........................................16
9 Application and Implementation..................................17
9.1 Application Information............................................. 17
9.2 Typical Application.................................................... 17
9.3 Application Curves....................................................19
10 Power Supply Recommendations..............................20
11 Layout...........................................................................21
11.1 Layout Guidelines................................................... 21
11.2 Layout Example...................................................... 21
12 Device and Documentation Support..........................22
12.1 Device Support ...................................................... 22
12.2 Receiving Notification of Documentation Updates..23
12.3 Support Resources................................................. 23
12.4 Trademarks.............................................................24
12.5 Electrostatic Discharge Caution..............................24
12.6 Glossary..................................................................24
13 Mechanical, Packaging, and Orderable
Information.................................................................... 24
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision * (April 2021) to Revision A (September 2021)
Page
•
Production Data Release....................................................................................................................................1
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5 Device Nomenclature
Figure 5-1 shows the device naming nomenclature of the TPS3899-Q1. For all possible output types and
threshold voltage options, see Device Naming Convention for a more detailed explanation. Contact TI sales
representatives or on TI's E2E forum for detail and availability of other options; minimum order quantities apply.
Q1
TPS3899 XX XX XXX
THRESHOLD VOLTAGE
01: 0.505 V (adjustable)
08: 0.8 V
...
54: 5.4 V
PACKAGE
DSE: WSON
AUTOMOTIVE
OUTPUT TYPE
DL: Open-Drain Ac ve-Low
PL: Push-Pull Ac ve-Low
PH: Push-Pull Ac ve-High
Figure 5-1. Device Naming Nomenclature
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6 Pin Configuration and Functions
6
5
4
CTR
CTS
1
2
3
RESET /RESET
SENSE
GND
VDD
Figure 6-1. DSE Package
6-Pin WSON
TPS3899-Q1 (Top View)
Table 6-1. Pin Functions
PIN
I/O
DESCRIPTION
NO.
NAME
Capacitor programmable reset delay: The CTR pin offers a user-adjustable delay time when returning from
reset condition. Connecting this pin to a ground-referenced capacitor sets the RESET/RESET delay time to
deassert.
1
2
CTR
—
—
Capacitor programmable sense delay: The CTS pin offers a user-adjustable delay time when asserting
reset condition. Connecting this pin to a ground-referenced capacitor sets the RESET/RESET delay time to
assert.
CTS
3
4
GND
VDD
—
I
Ground
Supply voltage pin: Good analog design practice is to place a 0.1-µF decoupling capacitor close to this pin.
This pin is connected to the voltage that will be monitored for fixed variants or to a resistor divider for
the adjustable variant. When the voltage on the SENSE pin transitions below the negative threshold
voltage VIT-, RESET/RESET asserts to active logic after the sense delay set by CTS. When the voltage
on the SENSE pin transitions above the positive threshold voltage VIT- + VHYS, RESET/RESET releases to
inactive logic (deasserts) after the reset delay set by CTR. For noisy applications, placing a 10 nF to
100 nF ceramic capacitor close to this pin may be needed for optimum performance.
5
SENSE
I
RESET active-low output that asserts to a logic low state after CTS delay when the monitored voltage on
the SENSE pin is lower than the negative threshold voltage VIT-. RESET remains logic low (asserted) until
the SENSE input rises above VIT- + VHYS and the CTR reset delay expires.
6
6
RESET
RESET
O
O
RESET active-high output that asserts to a logic high state after CTS delay when the monitored voltage on
the SENSE pin is lower than the negative threshold voltage VIT-. RESET remains logic high (asserted) until
the SENSE input rises above VIT- + VHYS and the CTR reset delay expires.
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7 Specifications
7.1 Absolute Maximum Ratings
Over operating free-air temperature range, unless otherwise noted (1)
MIN
–0.3
–0.3
MAX
6.5
UNIT
V
VDD, SENSE, RESET (TPS3899DL)
Voltage
CTR, CTS, RESET (TPS3899PL), RESET (TPS3899PH)
VDD+0.3 (3)
V
Current
RESET pin and RESET pin
Operating ambient temperature, TA
Storage, Tstg
±20
mA
Temperature (2)
Temperature (2)
–40
–65
125
°C
150
(1) Stresses beyond those listed under Absolute Maximum Rating (AMR) may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Condition. Exposure to absolute maximum rated conditions for long periods may affect device reliability.
(2) As a result of the low dissipated power in this device, it is assumed that TJ = TA.
(3) The absolute maximum rating is (VDD + 0.3) V or 6.5 V, whichever is smaller.
7.2 ESD Ratings
VALUE UNIT
Human body model (HBM), per AEC Q100-002 (1)
Charged device model (CDM), per AEC Q100-011
±2000
±750
V(ESD) Electrostatic discharge
V
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
7.3 Recommended Operating Conditions
Over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
Voltage
Voltage
VDD, SENSE, RESET (TPS3899DL)
0
6
V
V
CTR, CTS, RESET (TPS3899PL), RESET
(TPS3899PH)
0
VDD
Current
TA
RESET pin and RESET pin current
Operating free air temperature
CTR pin capacitor range
0
–40
0
±5
125
10
mA
°C
CCTR
CCTS
µF
µF
CTS pin capacitor range
0
10
7.4 Thermal Information
TPS3899-Q1
DSE
THERMAL METRIC(1)
UNIT
6 PINS
214.9
153.7
112.3
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
25.5
ψJB
111.8
RθJC(bot)
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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7.5 Electrical Characteristics
CTR = CTS = Open, RESET pull-up resistor (Rpull-up) = 100 kΩ to VDD, output reset load (CLOAD) = 10 pF and over the
operating free-air temperature range –40℃ to 125℃, unless otherwise noted. VDD ramp rate ≤ 1 V / µs. Typical values are at
TA = 25℃.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
COMMON PARAMETERS
Input supply voltage (Open Drain Low
and Push Pull Low)
VDD
0.85
6
V
VDD
VIT–
Input supply voltage (Push Pull High)
Negative-going input threshold range
1
6
V
V
(1)
for all output configs
0.8
5.4
Negative-going input threshold for
adjustable sense threshold version
VADJ-VIT–
0.505
±0.5
V
VIT– = 0.505 V (ADJ version) or 0.8 V to
1.7 V (Fixed threshold)
–2.5
2.5
VIT–
accuracy
Negative-going input threshold accuracy
Hysteresis on VIT–
%
VIT– = 1.8 V to 5.4 V (Fixed threshold)
VIT– = 0.505 V and 0.8 V
–2
3
±0.5
5
2
8
7
%
%
VHYS
VIT– = 0.9 V to 5.4 V
3
5
Current into Sense pin, fixed threshold
version
VDD = VSENSE = 6 V
VDD = VSENSE = 6 V
0.025
0.025
0.125
0.1 µA
ISENSE
Current into Sense pin, ADJ version
0.05 µA
Supply current into VDD pin when sense VDD = VSENSE = 6 V
pin is separate
IDD
1
µA
V
VIT– = 0.505 V and 0.8 V to 5.4 V
Voltage threshold to stop CTS capacitor
charge and assert RESET
VTH_CTS
VTH_CTR
0.73 * VDD
0.73 * VDD
Voltage threshold to stop CTR capacitor
charge and deassert RESET
V
RCTS
RCTR
CTS pin internal pull up resistance
CTR pin internal pull up resistance
410
410
500
500
590 kΩ
590 kΩ
TPS3899DL (Open-drain active-low)
VOL(max) = 300 mV
IRESET(Sink) = 15 µA
VPOR
Power on reset voltage (2)
Low level output voltage
700 mV
300 mV
300 mV
VDD = 0.85 V
IRESET(Sink) = 15 µA
VOL
VDD = 3.3 V
IRESET(Sink) = 2 mA
VDD = VPULLUP = 6 V, TA = –40℃ to 85℃
10
10
100 nA
350 nA
Ilkg(OD)
Open-Drain output leakage current
VDD = VPULLUP = 6 V
TPS3899PL (Push-pull active-low)
VOL(max) = 300 mV
IRESET(Sink) = 15 µA
VPOR
Power on reset voltage (2)
700 mV
VDD = 0.85 V
IRESET(Sink) = 15 µA
300 mV
Low level output voltage
VOL
VDD = 3.3 V
IRESET(Sink) = 2 mA
300 mV
VDD = 1.8 V
IRESET(Source) = 500 µA
0.8VDD
0.8VDD
0.8VDD
V
V
V
High level output voltage
VDD = 3.3 V
IRESET(Source) = 500 µA
VOH
VDD = 6 V
IRESET(Source) = 2 mA
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7.5 Electrical Characteristics (continued)
CTR = CTS = Open, RESET pull-up resistor (Rpull-up) = 100 kΩ to VDD, output reset load (CLOAD) = 10 pF and over the
operating free-air temperature range –40℃ to 125℃, unless otherwise noted. VDD ramp rate ≤ 1 V / µs. Typical values are at
TA = 25℃.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
TPS3899PH (Push-pull active-high)
VOH(min) = 0.8VDD
IRESET (Source) = 15 uA
VPOR
Power on reset voltage (2)
Low level output voltage
900 mV
VDD = 3.3 V
IRESET(Sink) = 500 µA
300 mV
VOL
VDD = 6 V
IRESET(Sink) = 2 mA
300 mV
VDD = 1V
IRESET(Sink) = 15 µA
0.8VDD
0.8VDD
0.8VDD
V
V
V
High level output voltage
VDD = 1.5 V
IRESET(Sink) = 500 µA
VOH
VDD = 3.3 V
IRESET(Sink) = 2 mA
(1) VIT- threshold voltage range from 0.8 V to 5.4 V (for DL, PL) and 1 to 5.4 V (for PH) in 100 mV steps, for released versions see Device
Voltage Thresholds table.
(2) Minimum VDD voltage level for a controlled output state. Below VPOR, the output cannot be determined.
7.6 Timing Requirements
At 0.85 V ≤ VDD ≤ 6 V, CTR = CTS = Open, RESET pull-up resistor (Rpull-up) = 100 kΩ to VDD, output reset load
(CLOAD) = 10 pF and over the operating free-air temperature range –40°C to 125°C, unless otherwise noted.
VDD ramp rate ≤ 1 V / µs. Typical values are at TA = 25°C
PARAMETER
Startup Delay (1)
TEST CONDITIONS
CTR pin = Open or NC
CTS pin = Open or NC
MIN
TYP
MAX
UNIT
tSTRT
300
µs
30
6.2
50
µs
ms
ms
Detect time delay
CTS pin = 10 nF
CTS pin = 1 µF
tD-SENSE
VDD = (VIT+ + 10%) to (VIT- – 10%) (2)
619
CTR pin = Open or NC
CTR pin = 10 nF (3)
CTR pin = 1 µF (3)
40
6.2
619
10
80
µs
ms
ms
µs
tD
Reset time delay
tGI_VIT-
Glitch immunity VIT-
5% VIT- overdrive (4)
(1) When VDD starts from less than VPOR and then exceeds the specified minimum VDD, reset is asserted till startup delay (tSTRT) + tD
delay based on capacitor on CTR pin. After this time, the device controls the RESET pin based on the SENSE pin voltage.
(2) tD_SENSE measured from threhold trip point (VIT-) to VOL for active low variants and VOH for active high variants.
(3) Ideal capacitor
(4) Overdrive % = [(VDD/ VIT-) - 1] × 100%
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7.7 Timing Diagrams
VDD(MIN)
VPOR
VDD
SENSE
RESET
VIT- + VHYS
VIT-
`
t
STRT + tD
tD-SENSE
tD
Unde ned
Unde ned
(tD-SENSE) is controlled by CTS
(tD) is controlled by CTR
(1) tD (no cap) is included in tSTRT time delay. If tD delay is programmed by an external capacitor connected to the CTR pin then tD programmed time
will be added to the startup time.
(2) Be advised, in some instances, that the VDD falling slew rate in Figure 7-1 can be slow or such that VDD decay time is much larger than the SENSE
delay time (tD-SENSE) time allowing the output to assert. If the VDD falling slew rate is much faster than the (tD-SENSE), the output will appear to be not
asserted.
Figure 7-1. TPS3899DL01-Q1 and TPS3899PL01-Q1 Timing Diagram
VDD
VDD(MIN)
VPOR
SENSE
VIT- + VHYS
VIT-
tD-SENSE
t
STRT + tD
tD
RESET
Unde ned
Unde ned
(tD-SENSE) is controlled by CTS
(tD) is controlled by CTR
(1) tD (no cap) is included in tSTRT time delay. If tD delay is programmed by an external capacitor connected to the CTR pin then tD programmed time
will be added to the startup time.
(2) Be advised, in some instances, that the VDD falling slew rate in Figure 7-2 can be slow or such that VDD decay time is much larger than the SENSE
delay time (tD-SENSE) time allowing the output to assert. If the VDD falling slew rate is much faster than the (tD-SENSE), the output will appear to be not
asserted.
Figure 7-2. TPS3899PH01-Q1 Timing Diagram
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7.8 Typical Characteristics
Typical characteristics show the typical performance of the TPS3899-Q1 device. Test conditions are TA = 25°C,
VDD = 3.3 V, and Rpull-up = 100 kΩ, unless otherwise noted.
Figure 7-3. Supply Current vs Supply Voltage
Figure 7-4. SENSE Current vs VSENSE
Figure 7-5. VIT- Accuracy vs Temperature
Figure 7-6. VHYS vs Temperature
Figure 7-7. SENSE Glitch Immunity (VIT-) vs Overdrive
Figure 7-8. Startup Delay vs Temperature
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7.8 Typical Characteristics (continued)
Typical characteristics show the typical performance of the TPS3899-Q1 device. Test conditions are TA = 25°C,
VDD = 3.3 V, and Rpull-up = 100 kΩ, unless otherwise noted.
VDD falling below VIT-
CTR = OPEN
Figure 7-9. Propagation Delay vs Temperature
Figure 7-10. Reset Time Delay vs Temperature
CTS = OPEN
Figure 7-11. RESET Delay vs CTR Capacitance
Figure 7-12. SENSE Delay vs Temperature
Figure 7-13. SENSE Delay vs CTS Capacitance
Figure 7-14. VOL vs IOL
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7.8 Typical Characteristics (continued)
Typical characteristics show the typical performance of the TPS3899-Q1 device. Test conditions are TA = 25°C,
VDD = 3.3 V, and Rpull-up = 100 kΩ, unless otherwise noted.
Figure 7-15. VOL vs Temperature
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8 Detailed Description
8.1 Overview
The TPS3899-Q1 voltage supervisor with separate SENSE monitor asserts a RESET/RESET signal when the
SENSE pin voltage drops below VIT- for the duration of the sense delay set by CTS. If the SENSE pin voltage
rises above VIT- + VHYS before the sense delay expires, the RESET/RESET pin does not assert. When asserted,
the RESET/RESET output remains asserted until SENSE voltage returns above VIT- + VHYS for the duration of
the reset delay set by CTR. If the SENSE pin voltage falls below VIT- before the reset delay expires while RESET
is asserted, RESET/RESET will remain asserted.
Like most voltage supervisors, the TPS3899-Q1 includes a reset delay tD to provide time for the power and
clocks to settle before letting the processor out of reset. At power up, the circuits inside the TPS3899-Q1 need
additional time to start the reset delay timer after its power supply VDD has reached minimum VDD(MIN) for
these circuits to start operating properly. This additional time is specified with the parameter start-up delay tSTRT
.
Figure 7-1 shows the timing diagram indicating this additional delay. After VDD is stable and above VDD(MIN)
subsequent changes of the sense voltage across the threshold voltage will trigger reset after only the reset
delay. The reset time delay tD is set by a capacitor on the CTR pin. The start-up delay has a maximum limit of
300 μs for a ramp rate of VDD ≤ 1 V / μs.
8.2 Functional Block Diagram
Push-pull variants only
VDD
VDD
RESET
LOGIC
TIMER
Cap ladder
Fixed
RESET (active-low variants: DL, PL)
ADJ
RESET (active-high variants: PH)
SENSE
+
œ
Reference
GND
VDD
VDD
RCTS
RCTR
CTR
CTS
GND
8.3 Feature Description
The combination of user-adjustable sense delay time via CTS and reset delay time via CTR with a broad range
of threshold voltages allow these devices to be used in a wide array of applications. Fixed negative threshold
voltages VIT- can be factory set from 0.8 V to 5.4 V in steps of 100 mV [1.1 V to 5.4 V for the -PH (push-pull
active high) variants]. CTS and CTR pins allow the sense delay and reset delay to be set to typical values of
30 μs and 40 μs, respectively, by leaving these pins floating. External capacitors can be placed on the CTS and
CTR pins to program the sense and reset delays independently.
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8.3.1 VDD Hysteresis
The internal comparator has built-in hysteresis to avoid erroneous output reset release. If the voltage at the VDD
pin falls below VIT- the output reset is asserted. When the voltage at the VDD pin goes above VIT- plus hysteresis
(VHYS) the output reset is deasserted after tD delay.
Hystersis Width
Hystersis Width
RESET
RESET
VIT-
VIT-
VIT+
VIT+
VDD
VDD
Figure 8-1. Hysteresis Diagram
8.3.2 User-Programmable Sense and Reset Time Delay
The sense delay corresponds to the configuration of CTS and the reset delay corresponds to the configuration of
CTR. The sense and reset time delay can be set to a minimum value of 50 µs and 80 µs by leaving the CTS and
CTR pins floating respectively, or a maximum value of approximately 6.2 seconds by connecting 10 µF delay
capacitor.
The relationship between external capacitor (CCT_EXT) in Farads at CTS or CTR pins and the time delay in
seconds is given by Equation 1.
tD-SENSE (typ) or tD (typ) = -ln (0.29) x RCT (typ) x CCT_EXT + tD (CTS or CTR = OPEN)
(1)
Equation 1 is simplified to Equation 2 and Equation 3 by plugging RCT (typ) and tD (CTS or CTR = OPEN) given in
Section 7.5 and Section 7.6 section:
tD-SENSE = 618937 x CCTS_EXT + 50 µs
tD = 618937 x CCTR_EXT + 80 µs
(2)
(3)
Equation 4 and Equation 5 solves for both external capacitor values (CCTS_EXT) and (CCTR_EXT) in units of
Farads where tD-SENSE and tD are in units of seconds:
CCTS_EXT = (tD-SENSE - 50 µs) ÷ 618937
CCTR_EXT = (tD - 80 µs) ÷ 618937
(4)
(5)
The sense or reset delay varies according to three variables: the external capacitor (CCT_EXT), CTS and CTR pin
internal resistance (RCT) provided in Section 7.5, and a constant. The minimum and maximum variance due to
the constant is show in Equation 6 and Equation 7:
tD-SENSE (min) or tD (min) = -ln (0.37) x RCT (min) x CCT_EXT (min) + tD (no cap, min)
tD-SENSE (max) or tD (max) = -ln (0.25) x RCT (max) x CCT_EXT (max) + tD (no cap, max)
(6)
(7)
The recommended maximum sense and reset delay capacitors for the TPS3899-Q1 is limited to 10 µF as this
ensures there is enough time for either capacitors to fully discharge when a voltage fault occurs. When a voltage
fault occurs, the previously charged up capacitor discharges and if the monitored voltage returns from the fault
condition before either delay capacitors discharges completely, both delays will be shorter than expected. The
capacitors will begin charging from a voltage above zero and resulting in shorter than expected time delays.
Larger delay capacitors can be used so long as the capacitors have enough time to fully discharge during the
duration of the voltage fault. To ensure the capacitors are fully discharged, the time period or duration of the
voltage fault needs to be greater than 10% of the programmed reset time delay.
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Figure 8-2 shows the charge and discharge behavior on CTS and CTR that defines the sense and reset delays
respectively. When SENSE transitions below VIT-, the capacitor connected to CTS begins to charge. Once the
CTS capacitor charges to an internal threshold shown as VTH_CTS, RESET transitions to active-low logic state
and the CTS capacitor then begins to discharge immediately. When SENSE transitions above
VIT- + VHYS, the capacitor connected to CTR begins to charge. Once the CTR capacitor charges to the internal
threshold VTH_CTR, RESET releases back to inactive logic high state and the CTR capacitor begins to discharge
immediately. Please note that for active-high variants, RESET follows the inverse behavior of RESET.
SENSE
VIT-
*tdischarge-CTR
VTH_CTR
CTR
*tdischarge-CTS
CTS
VTH_CTS
tD-SENSE
tD
RESET
(-DL Op on)
* tdischarge-CTS and tdischarge-CTR: To ensure the capacitors are fully discharged, the me period or
dura on of the voltage fault needs to be greater than 10% of the programmed reset me delay.
Figure 8-2. CTS and CTR Charge and Discharge Behavior Relative to SENSE and RESET
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Figure 8-3 shows the charge and discharge behavior on CTS and CTR where the monitored voltage is VDD.
Similar to Figure 8-2, Figure 8-3 illustrates a SENSE signal that is transitioning below VIT- before the CTR
capacitor reaches to an internal threshold voltage VTH_CTR and t < tD. The result of the CTR capacitor not
reaching the internal threshold voltage VTH_CTR is RESET will become deasserted. Once RESET is deasserted,
charging beings for the CTS capacitor. When the CTS voltage reaches the internal threshold VTH_CTS, RESET
will become asserted. This phenomenon is caused by the SENSE falling edge triggering the discharging of the
CTR capacitor and producing a deassert signal on the RESET output.
VIT-
VDD = SENSE
tdischarge-CTR
VTH_CTR
CTR
tdischarge-CTS
tdischarge-CTS
VTH_CTS
CTS
tD-SENSE
tD-SENSE
RESET
(-DL Op on)
t < tD
* tdischarge-CTS and tdischarge-CTR: To ensure the capacitors are fully discharged, the me period or
dura on of the voltage fault needs to be greater than 10% of the programmed reset me delay.
Figure 8-3. CTS and CTR Charge and Discharge Behavior Relative to VDD, SENSE and RESET
8.3.3 RESET/RESET Output
Upon power up, RESET/RESET begins asserted and remains asserted until the SENSE pin voltage rises above
the positive voltage threshold VIT- + VHYS for the duration of the reset delay set by CTR. After the SENSE pin
voltage is above VIT- + VHYS for the reset delay, RESET/RESET deasserts. RESET/RESET remains deasserted
long as the SENSE pin voltage is above the positive threshold. If the SENSE pin voltage falls below the negative
threshold (VIT-) for the duration of the sense delay set by CTS, then RESET/RESET is asserted.
An external pull-up resistor is required for the open-drain variants. Connect the external pull-up resistor to the
proper voltage rail to enable the outputs to be connected to other devices at the correct interface voltage level.
RESET/RESET can be pulled up to any voltage up to 6.0 V, independent of the device supply voltage.
8.3.4 SENSE Input
The SENSE input can vary from 0 V to 6.0 V, regardless of the device supply voltage used. The SENSE
pin is used to monitor a critical voltage rail or push-button input. If the voltage on this pin drops below VIT-,
then RESET/RESET is asserted after the sense delay time set by CTS. When the voltage on the SENSE pin
rises above the positive threshold voltage VIT- + VHYS, RESET/RESET deasserts after the reset delay time set
by CTR. The internal comparator has built-in hysteresis to ensure well-defined RESET/RESET assertions and
deassertions even when there are small changes on the voltage rail being monitored.
The TPS3899-Q1 device is relatively immune to short transients on the SENSE pin. Glitch immunity
(tGI_V SENSE), found in Section 7.6, is dependent on threshold overdrive, as illustrated in Figure 7-7. Although
IT-
not required in most cases, for noisy applications, good analog design practice is to place a 10 nF to 100 nF
bypass capacitor at the SENSE input to reduce sensitivity to transient voltages on the monitored signal.
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8.3.4.1 Immunity to SENSE Pin Voltage Transients
The TPS3899-Q1 is immune to short voltage transient spikes on the input pins. To further improve the noise
immunity on the SENSE pin, placing a 10 nF to 100 nF capacitor between the SENSE pin and GND can reduce
the sensitivity to transient voltages on the monitored signal.
Sensitivity to transients depends on both transient duration and overdrive (amplitude) of the transient. Overdrive
is defined by how much VSENSE exceeds the specified threshold, and is important to know because the smaller
the overdrive, the slower the response of the outputs. Threshold overdrive is calculated as a percent of the
threshold in question, as shown in Equation 8.
Overdrive = | ((VSENSE / VIT-) – 1) × 100% |
(8)
VSENSE
VIT- + VHYS
VIT-
Overdrive
Pulse
Duration
Figure 8-4. Overdrive vs Pulse Duration
8.4 Device Functional Modes
Table 8-1 summarizes the various functional modes of the device.
Table 8-1. Truth Table
VDD
VDD < VPOR
SENSE (1)
RESET
RESET
—
—
Undefined
Undefined
(2)
VPOR < VDD < VDD(MIN)
VDD ≥ VDD(MIN)
VDD ≥ VDD(MIN)
L
L
H
H
L
VSENSE < VIT-
VSENSE > VIT- + VHYS
H
(1) SENSE pin voltage must be less than VIT- for the sense delay set by CTS or greater than VIT- + VHYS for the reset delay set by CTR
before RESET transitions
(2) When VDD falls below VDD(MIN), the internal undervoltage-lockout takes effect and RESET is held logic low (RESET is held logic high)
until VDD falls below VPOR at which the RESET/RESET output is undefined.
8.4.1 Normal Operation (VDD > VDD(min)
)
When VDD is greater than VDD(min), the RESET/RESET pin is determined by the voltage on the SENSE pin and
the sense delay and reset delay set by CTS and CTR respectively.
8.4.2 Above Power-On-Reset But Less Than VDD(min) (VPOR < VDD < VDD(min)
)
When the voltage on VDD is less than the VDD(min) voltage, and greater than the power-on-reset voltage VPOR
,
the RESET/RESET signal is asserted regardless of the voltage on the SENSE pin.
8.4.3 Below Power-On-Reset (VDD < VPOR
)
When the voltage on VDD is lower than VPOR, the device does not have enough voltage to assert the output
RESET/RESET to its correct logic state. The output results in being undefined as shown in Figure 7-1 or in
Figure 7-2. If the output RESET/RESET is an open-drain variant, its voltage may be pulled up to VDD or to the
pull-up voltage. Neither output should be relied upon for proper device function.
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and
TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
9.1 Application Information
The following sections describe in detail how to properly use this device, depending on the requirements of the
final application.
9.2 Typical Application
9.2.1 Design 1: Dual Rail Monitoring with Power-Up Sequencing
A typical application for the TPS3899-Q1 is voltage rail monitoring and power-up sequencing as shown in
Figure 9-1. The TPS3899-Q1 can be used to monitor any rail above 0.8 V. In this design application,
two TPS3899-Q1 devices monitor two separate voltage rails and sequences the rails upon power-up. The
TPS3899DL01-Q1 is used to monitor the 3.3 V main power rail and the TPS3899PL16-Q1 is used to monitor
the 1.8 V rail provided by the LDO for other system peripherals. The RESET output of the TPS3899DL01-Q1 is
connected to the enable (EN) input of the LDO with an external pull-up resistor RPULL-UP to the 3.3 V power rail.
The RESET output of the TPS3899PL16-Q1 is connected to the (RESET) input of the microcontroller. A reset
event is initiated on either voltage supervisor when the VDD voltage is less than VIT- falling threshold voltage.
For a system reset event, a push-button input is placed at the SENSE pin of the TPS3899DL01-Q1.
LDO
1.8 V
IN
OUT
3.3V
1 µF
1 µF
EN
R1
47.5 k
RPULL-UP
VCORE
Microcontroller
RESET
VI/O
VDD
VDD
SENSE
SENSE
RESET
RESET
TPS3899DL01-Q1
CTS CTR
TPS3899PL16-Q1
CTS CTR
Push-button
input
R2
10 k
0.022 µF
0.047 µF
0.01 µF
0.022 µF
GND
GND
Figure 9-1. TPS3899-Q1 Voltage Rail Monitor and Power-Up Sequencer Design Block Diagram
9.2.1.1 Design Requirements
This design requires voltage supervision on two voltage rails: 3.3 V and 1.8 V. The voltage rails need to
sequence upon power up with the 3.3 V coming up at least 25 ms followed by the 1.8 V rail.
PARAMETER
DESIGN REQUIREMENT
DESIGN RESULT
Two TPS3899-Q1 devices provide voltage monitoring with 1% accuracy
with either an adjustable threshold device or fixed voltage options available
in 0.1 V variations.
Two Rail Voltage
Supervision
Monitor 3.3 V and 1.8 V rails
The CTR capacitors on TPS3899DL01-Q1 and TPS3899PL16-Q1 are set
to 0.047 µF and 0.022 µF, respectively, for a reset time delays of 29 ms
and 13.7 ms typical.
Voltage Rail
Sequencing
Power up the 3.3 V rail first within 25 ms
followed by 1.8 V rail
Reset needs to assert under the reset
condition of a push-button press or
VDD < 2.9 V after a period of 10 ms.
Reset will assert under the reset condition of a push-button press or
VDD < 2.9 V after a period of 13.7 ms. The RESEToutput will deassert
after 29 ms when VDD > 3.05 V.
Reset Asserting
and Timing 1
Reset needs to assert under the reset
condition of VDD < 1.6 V after a period
of 5 ms.
Reset Asserting
and Timing 2
Reset will assert under the reset condition of VDD < 1.6 V after a period of
6.2 ms. The RESET output will deassert after 13.7 ms when VDD > 1.68 V.
Max device current
consumption
1 µA
Each TPS3899-Q1 requires 125 nA typical.
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9.2.1.2 Detailed Design Procedure
The primary constraint for this application is choosing the correct device to monitor the supply voltage of the
microprocessor. The TPS3899-Q1 can monitor any voltage with the adjustable voltage threshold option or fixed
voltages between 0.8 V and 5.4 V. Depending on how far away from the nominal voltage rail the user wants the
voltage supervisor to trigger determines the correct voltage supervisor variant to choose. In this example,
Figure 9-2 shows the output, RESET, of the TPS3899DL01-Q1 when the 3.3 V rail falls to 2.9 V after the sense
time delay expires. The TPS3899PL16-Q1 triggers a reset when the 1.8 V rail falls to 1.6 V.
The secondary constraint for this application is the sense and reset time delay. If the monitored voltage rail 3.3 V
has large voltage ripple noise and it goes below the programmed threshold voltage but returns above the
VIT-+ VHYS before the sense time delay expires, the output will not assert. Therefore, the sense time delay
prevents false sense resets by allowing the monitored voltage rail 3.3 V to not assert the output during the
programmed sense time delay period set by the capacitor on the CTS pin. In the application, the CTS capacitors
for both the TPS3899DL01-Q1 and TPS3899PL16-Q1 are set to be 0.022 μF and 0.01 μF, respectively, and
resulted in sense time delays of 13.7 ms and 6.2 ms. In addition to the sense delay time, the reset time delay for
the TPS3899DL01-Q1 must be at least 25 ms to allow the microprocessor, and all other devices using the 3.3
V rail, enough time to startup correctly before the 1.8 V rail is enabled via the LDO. Once the LDO is enabled,
the reset time delay for the TPS3899PL16-Q1 must be at least 10 ms to allow the 1.8 V rail to settle. For
applications with ambient temperatures ranging from –40°C to +125°C, CTS and CTR can be calculated using
RCTS and RCTR. Solving for CCTS and CCTR in Equation 4 and Equation 5 for 10 ms and 25 ms gives a minimum
capacitor value of 0.016 µF and 0.0403 µF which are rounded up to standard values of 0.022 µF and 0.047 µF,
respectively, to account for capacitor tolerance.
3.3 V
VIT- + VHYS = 3.05V
VIT- = 2.90V
Push-bu on
input
SENSE
tD
tD-SENSE
tD
tD-SENSE
RESET
Figure 9-2. TPS3899DL01-Q1 3.3 V Voltage Rail Monitor Timing Diagram
A 1 µF decoupling capacitor is connected to the VDD pin as a good analog design practice. The pull-up resistor
is only required for the open-drain device variants and is calculated to ensure that VOL does not exceed max
limit given the IRESET(Sink) possible at the expected supply voltage. The open-drain variant is used in this design
example and the nominal VDD is 3.3 V but dropping to 2.9 V for VIT-, the voltage across the pull-up resistor can
be determined. In Section 7.5, max VOL provides 2 mA IRESET(Sink) for 3.3 V VDD. Using 2 mA of IRESET(Sink) and
300 mV max VOL, gives us 1.3 kΩ for the pull-up resistor. Any value higher than 1.3 kΩ would ensure that VOL
will not exceed 300 mV max specification.
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9.3 Application Curves
These application curves were taken with the TPS3899EVM which uses the TPS3899DL01DSER. Please see
the TPS3899EVM User Guide for more information.
Figure 9-3. Sense Delay where CTS = 0.1 μF
Figure 9-4. Reset Delay where CTR = 0.1μF
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10 Power Supply Recommendations
The TPS3899-Q1 is designed to operate from an input supply with a voltage range between 0.85 V and 6 V.
An input supply capacitor is not required for this device; however, if the input supply is noisy, then good analog
practice is to place a 0.1 µF capacitor between the VDD pin and the GND pin. Also, placing a 10 nF to 100 nF
capacitor between the SENSE pin and GND can reduce the sensitivity to transient voltages on the monitored
signal. This device has a 6.5 V absolute maximum rating on the VDD pin. If the voltage supply providing power
to VDD is susceptible to any large voltage transient that can exceed 6.5 V, additional precautions must be taken.
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11 Layout
11.1 Layout Guidelines
Make sure that the connection to the VDD pin is low impedance. Good analog design practice is to place a
0.1 µF ceramic capacitor near the VDD pin. If a capacitor is not connected to the CTS or CTS pins, then
minimize parasitic capacitance on this pin so the sense delay or reset delay times are not adversely affected. To
improve noise immunity on the SENSE pin, place a capacitor (CSENSE) as close as possible to the SENSE pin.
Placing a 10 nF to 100 nF capacitor between the SENSE pin and GND can reduce the sensitivity to transient
voltages on the monitored signal.
11.2 Layout Example
The layout example in Figure 11-1 shows how the TPS3899-Q1 is laid out on a printed circuit board (PCB) with a
user-defined sense delay and reset delay.
Rpull-up
RESET
CTR
CTS
GND
CCTR
SENSE
VDD
CCTS
CSENSE
CIN
GND
Vias used to connect pins for application-specific connections
Figure 11-1. Recommended Layout
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12 Device and Documentation Support
12.1 Device Support
12.1.1 Device Nomenclature
Figure 5-1 in Device Nomenclature and Table 12-1 shows how to decode the function of the device based on its
part number shown in Table 12-2.
Table 12-1. Device Naming Convention
DESCRIPTION
Generic Part number
NOMENCLATURE
VALUE
TPS3899-Q1
TPS3899-Q1
DL
PL
PH
Open-Drain, Active-Low
Push-Pull, Active-Low
Push-Pull, Active-High
01: 0.505 V (adjustable)
Variant code (Output Toplogy)
Detect Voltage Option
## (two characters)
Example: 08 stands for 0.8 V threshold
0.8 V to 5.4 V (fixed threshold voltage)
Package
DSE
R
WSON
Reel
Large Reel
AEC-Q100
Automotive Version
Q1
Table 12-2 shows the possible variants of the TPS3899-Q1. Please refer to the Package Option Addendum
(POA), in this datasheet, for which variant is orderable and available; minimum order quantities apply.
Table 12-2. Device Naming Convention
ORDERABLE DEVICE NAME
THRESHOLD VOLTAGE (V)
-DL (OPEN-DRAIN ACTIVE-LOW) -PL (PUSH-PULL ACTIVE-LOW) -PH (PUSH-PULL ACTIVE-HIGH)
TPS3899DL01-Q1
TPS3899DL08-Q1
TPS3899DL09-Q1
TPS3899DL10-Q1
TPS3899DL11-Q1
TPS3899DL12-Q1
TPS3899DL13-Q1
TPS3899DL14-Q1
TPS3899DL15-Q1
TPS3899DL16-Q1
TPS3899DL17-Q1
TPS3899DL18-Q1
TPS3899DL19-Q1
TPS3899DL20-Q1
TPS3899DL21-Q1
TPS3899DL22-Q1
TPS3899DL23-Q1
TPS3899DL24-Q1
TPS3899DL25-Q1
TPS3899DL26-Q1
TPS3899PL01-Q1
TPS3899PL08-Q1
TPS3899PL09-Q1
TPS3899PL10-Q1
TPS3899PL11-Q1
TPS3899PL12-Q1
TPS3899PL13-Q1
TPS3899PL14-Q1
TPS3899PL15-Q1
TPS3899PL16-Q1
TPS3899PL17-Q1
TPS3899PL18-Q1
TPS3899PL19-Q1
TPS3899PL20-Q1
TPS3899PL21-Q1
TPS3899PL22-Q1
TPS3899PL23-Q1
TPS3899PL24-Q1
TPS3899PL25-Q1
TPS3899PL26-Q1
TPS3899PH01-Q1
0.505
0.80
0.90
1.00
1.10
1.20
1.30
1.40
1.50
1.60
1.70
1.80
1.90
2.00
2.10
2.20
2.30
2.40
2.50
2.60
N/A
N/A
N/A
TPS3899PH11-Q1
TPS3899PH12-Q1
TPS3899PH13-Q1
TPS3899PH14-Q1
TPS3899PH15-Q1
TPS3899PH16-Q1
TPS3899PH17-Q1
TPS3899PH18-Q1
TPS3899PH19-Q1
TPS3899PH20-Q1
TPS3899PH21-Q1
TPS3899PH22-Q1
TPS3899PH23-Q1
TPS3899PH24-Q1
TPS3899PH25-Q1
TPS3899PH26-Q1
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Table 12-2. Device Naming Convention (continued)
ORDERABLE DEVICE NAME
THRESHOLD VOLTAGE (V)
-DL (OPEN-DRAIN ACTIVE-LOW) -PL (PUSH-PULL ACTIVE-LOW) -PH (PUSH-PULL ACTIVE-HIGH)
TPS3899DL27-Q1
TPS3899DL28-Q1
TPS3899DL29-Q1
TPS3899DL30-Q1
TPS3899DL31-Q1
TPS3899DL32-Q1
TPS3899DL33-Q1
TPS3899DL34-Q1
TPS3899DL35-Q1
TPS3899DL36-Q1
TPS3899DL37-Q1
TPS3899DL38-Q1
TPS3899DL39-Q1
TPS3899DL40-Q1
TPS3899DL41-Q1
TPS3899DL42-Q1
TPS3899DL43-Q1
TPS3899DL44-Q1
TPS3899DL45-Q1
TPS3899DL46-Q1
TPS3899DL47-Q1
TPS3899DL48-Q1
TPS3899DL49-Q1
TPS3899DL50-Q1
TPS3899DL51-Q1
TPS3899DL52-Q1
TPS3899DL53-Q1
TPS3899DL54-Q1
TPS3899PL27-Q1
TPS3899PL28-Q1
TPS3899PL29-Q1
TPS3899PL30-Q1
TPS3899PL31-Q1
TPS3899PL32-Q1
TPS3899PL33-Q1
TPS3899PL34-Q1
TPS3899PL35-Q1
TPS3899PL36-Q1
TPS3899PL37-Q1
TPS3899PL38-Q1
TPS3899PL39-Q1
TPS3899PL40-Q1
TPS3899PL41-Q1
TPS3899PL42-Q1
TPS3899PL43-Q1
TPS3899PL44-Q1
TPS3899PL45-Q1
TPS3899PL46-Q1
TPS3899PL47-Q1
TPS3899PL48-Q1
TPS3899PL49-Q1
TPS3899PL50-Q1
TPS3899PL51-Q1
TPS3899PL52-Q1
TPS3899PL53-Q1
TPS3899PL54-Q1
TPS3899PH27-Q1
TPS3899PH28-Q1
TPS3899PH29-Q1
TPS3899PH30-Q1
TPS3899PH31-Q1
TPS3899PH32-Q1
TPS3899PH33-Q1
TPS3899PH34-Q1
TPS3899PH35-Q1
TPS3899PH36-Q1
TPS3899PH37-Q1
TPS3899PH38-Q1
TPS3899PH39-Q1
TPS3899PH40-Q1
TPS3899PH41-Q1
TPS3899PH42-Q1
TPS3899PH43-Q1
TPS3899PH44-Q1
TPS3899PH45-Q1
TPS3899PH46-Q1
TPS3899PH47-Q1
TPS3899PH48-Q1
TPS3899PH49-Q1
TPS3899PH50-Q1
TPS3899PH51-Q1
TPS3899PH52-Q1
TPS3899PH53-Q1
TPS3899PH54-Q1
2.70
2.80
2.90
3.00
3.10
3.20
3.30
3.40
3.50
3.60
3.70
3.80
3.90
4.00
4.10
4.20
4.30
4.40
4.50
4.60
4.70
4.80
4.90
5.00
5.10
5.20
5.30
5.40
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
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12.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2021 Texas Instruments Incorporated
24
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Product Folder Links: TPS3899-Q1
PACKAGE OPTION ADDENDUM
www.ti.com
5-Oct-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS3899PL16DSERQ1
ACTIVE
WSON
DSE
6
3000 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LO
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TPS3899-Q1 :
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
5-Oct-2021
Catalog : TPS3899
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
25-Sep-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS3899PL16DSERQ1 WSON
DSE
6
3000
180.0
8.4
1.75
1.75
1.0
4.0
8.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
25-Sep-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
WSON DSE
SPQ
Length (mm) Width (mm) Height (mm)
210.0 185.0 35.0
TPS3899PL16DSERQ1
6
3000
Pack Materials-Page 2
PACKAGE OUTLINE
DSE0006A
WSON - 0.8 mm max height
SCALE 6.000
PLASTIC SMALL OUTLINE - NO LEAD
1.55
1.45
A
B
1.55
1.45
PIN 1 INDEX AREA
0.8 MAX
C
SEATING PLANE
0.08 C
(0.2) TYP
0.05
0.00
0.6
0.4
5X
3
4
2X 1
4X 0.5
6
1
0.3
6X
0.7
0.5
0.2
0.1
0.05
PIN 1 ID
C A B
C
4220552/A 04/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
DSE0006A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
PKG
(0.8)
5X (0.7)
1
6
6X (0.25)
SYMM
4X 0.5
4
3
(R0.05) TYP
(1.6)
LAND PATTERN EXAMPLE
SCALE:40X
0.05 MIN
ALL AROUND
0.05 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
PADS 4-6
NON SOLDER MASK
DEFINED
PADS 1-3
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4220552/A 04/2021
NOTES: (continued)
3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
DSE0006A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
PKG
5X (0.7)
(0.8)
6X (0.25)
1
6
SYMM
4X (0.5)
4
3
(R0.05) TYP
(1.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:40X
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
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applicable warranties or warranty disclaimers for TI products.IMPORTANT NOTICE
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Copyright © 2021, Texas Instruments Incorporated
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