TPS40021 [TI]

ENHANCED LOW INPUT VOLTAGE MODE SYNCHRONOUS BUCK CONTROLLER; 增强型低输入电压模式同步降压控制器
TPS40021
型号: TPS40021
厂家: TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述:

ENHANCED LOW INPUT VOLTAGE MODE SYNCHRONOUS BUCK CONTROLLER
增强型低输入电压模式同步降压控制器

输入元件 控制器
文件: 总32页 (文件大小:408K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
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FEATURES  
DESCRIPTION  
D
D
D
D
D
D
Operating Input Voltage 2.25 V to 5.5 V  
The TPS4002x family of dc-to-dc controllers are designed  
for non-isolated synchronous buck regulators, providing  
enhanced operation and design flexability through user  
programmability.  
Output Voltage as Low as 0.7 V  
1% Internal 0.7 V Reference  
Predictive Gate DriveN-Channel MOSFET  
Drivers for Higher Efficiency  
The TPS4002x utilizes a proprietary Predictive Gate  
Drivetechnology to minimize the diode conduction  
losses associated with the high-side and synchronous  
rectifier N-channel MOSFET transistions. The integrated  
charge pump with boost circuit provides a regulated 5-V  
gate drive for both the high side and synchronous rectifier  
N-channel MOSFETs. The use of the Predictive Gate  
Drivetechnology and charge pump/boost circuits  
combine to provide a highly efficient, smaller and less  
expensive converter.  
Externally Adjustable Soft-Start and Short  
Circuit Current Limit  
Programmable Fixed-Frequency  
100 KHz-to-1 MHz Voltage-Mode Control  
D
Source-Only Current or Source/Sink Current  
D
Quick Response Output Transient  
Comparators with Power Good Indication  
Provide Output Status  
Design flexibility is provided through user programmability  
of such functions as: operating frequency, short circuit  
current detection thresholds, soft-start ramp time, and  
external synchronization frequency. The operating  
frequency is programmable using a single resistor over a  
frequency range of 100 kHz to 1 MHz. Higher operating  
frequencies yield smaller component values for a given  
converter power level as well as faster loop closure.  
D
16-Pin PowerPADPackage  
APPLICATIONS  
D
D
D
D
D
Networking Equipment  
Telecom Equipment  
Base Stations  
Servers  
DSP Power  
VDD  
VOUT  
TPS40020  
VDD 2.25 V − 5.5 V  
ILIM/  
SYNC  
1
2
3
4
5
6
7
8
16  
15  
BOOT1  
HDRV  
VOUT  
VDD  
OSNS  
FB  
SW 14  
BOOT2 13  
PVDD 12  
LDRV 11  
PGND 10  
COMP  
SS/SD  
RT  
SGND  
9
PWRGD  
UDG−02094  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments  
semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PowerPADand Predictive Gate Driveare trademarks of Texas Instruments.  
ꢁꢘ ꢏ ꢌꢓ ꢋ ꢀꢒ ꢏ ꢈ ꢌ ꢊꢀꢊ ꢛꢜ ꢝꢞ ꢟ ꢠꢡ ꢢꢛꢞꢜ ꢛꢣ ꢤꢥ ꢟ ꢟ ꢦꢜꢢ ꢡꢣ ꢞꢝ ꢧꢥꢨ ꢩꢛꢤ ꢡꢢꢛ ꢞꢜ ꢪꢡ ꢢꢦꢫ ꢁꢟ ꢞꢪꢥ ꢤꢢꢣ  
ꢤ ꢞꢜ ꢝꢞꢟ ꢠ ꢢꢞ ꢣ ꢧꢦ ꢤ ꢛ ꢝꢛ ꢤ ꢡ ꢢꢛ ꢞꢜꢣ ꢧ ꢦꢟ ꢢꢬꢦ ꢢꢦ ꢟ ꢠꢣ ꢞꢝ ꢀꢦꢭ ꢡꢣ ꢒꢜꢣ ꢢꢟ ꢥꢠ ꢦꢜꢢ ꢣ ꢣꢢ ꢡꢜꢪ ꢡꢟ ꢪ ꢮ ꢡꢟ ꢟ ꢡ ꢜꢢꢯꢫ  
ꢁꢟ ꢞ ꢪꢥꢤ ꢢ ꢛꢞ ꢜ ꢧꢟ ꢞ ꢤ ꢦ ꢣ ꢣ ꢛꢜ ꢰ ꢪꢞ ꢦ ꢣ ꢜꢞꢢ ꢜꢦ ꢤꢦ ꢣꢣ ꢡꢟ ꢛꢩ ꢯ ꢛꢜꢤ ꢩꢥꢪ ꢦ ꢢꢦ ꢣꢢꢛ ꢜꢰ ꢞꢝ ꢡꢩ ꢩ ꢧꢡ ꢟ ꢡꢠ ꢦꢢꢦ ꢟ ꢣꢫ  
Copyright 2004, Texas Instruments Incorporated  
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SLUS535C − MARCH 2003 − REVISED SEPTEMBER 2004  
DESCRIPTION (CONTINUED)  
The short circuit current detection is programmable through a single resistor, allowing the short circuit current limit  
detection threshold to be easily tailored to accommodate different size (R ) MOSFETs. The short circuit current  
DS(on)  
function provides pulse-by-pulse current limiting during soft-start and short term transient conditions as well as a fault  
counter to handle longer duration short circuit current conditions. If a fault is detected the controller shuts down for  
a period of time determined by six (6) consecutive soft-start cycles. The controller automatically retries the output  
th  
every seventh (7 ) soft-start cycle.  
In addition to determining the off time during a fault condition, the soft-start ramp provides a closed loop controlled  
ramp of the converter output during startup. Programmability allows the ramp rate to be adjusted for a wide variety  
of output L-C component values.  
The output voltage transient comparators provide a quick response , first strike, approach to output voltage transients. The  
output voltage is sensed through a resistor divider at the OSNS pin. If an overvoltage condition is detected the HDRV gate  
drive is shut-off and the LDRV gate drive is turned on until the output is returned to regulation. Similarly, if an output  
undervoltage condition is sensed the HDRV gate drive goes to 95% duty cycle to pump the output back up quickly. In either  
case, the PowerGood open drain output pulls low to indicate an output voltage out of regulation condition. The PowerGood  
output can be daisy-chained to the SS/SD pin or enable pin of other controllers or converters for output voltage sequencing.  
The transient comparators can be disabled by simply tying the OSNS pin to VDD.  
The TPS4002x can be externally synchronized through the ILIM/SYNC pin up to 1.5× the free-running frequency. This  
allows multiple contollers to be synchronized to eliminate EMI concerns due to input beat frequencies between controllers.  
INTERNAL BLOCK DIAGRAM  
VDD  
2
3
VDD  
0.719 V  
OSNS  
VDD  
13 BOOT2  
12 PVDD  
16 BOOT1  
15 HDRV  
14 SW  
SS  
CHARGE  
PUMP  
ACTIVE  
PWRGD  
9
0.659 V  
FB  
4
5
0.69 V  
+
+
DRV  
PREDICTIVE  
GATE  
PWM  
COMP  
DRIVE(tm)  
PWM  
UVLO  
OSC  
CLK  
LOGIC  
PVDD  
RT  
7
UVLO  
IRT  
DRV  
11 LDRV  
10 PGND  
FAULT  
CLK  
VDD  
IRT  
SS  
ACTIVE  
CURRENT LIMIT  
COMPARATOR  
SOFT  
START  
FAULT  
COUNTER  
I
SS  
OC  
SS/SD  
SGND  
6
8
1
ILIM/SYNC  
DCHG  
+
UVLO  
SD  
SYNC  
0.28 V  
1 V  
VDD  
UVLO  
UVLO  
+
DISABLE  
V
DD  
1.4 V  
UDG−02092  
2
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SLUS535C − MARCH 2003 − REVISED SEPTEMBER 2004  
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during  
storage or handling to prevent electrostatic damage to the MOS gates.  
ORDERING INFORMATION  
(1)  
T
LOAD CURRENT  
PACKAGE  
PART NUMBER  
TPS40020PWP  
TPS40021PWP  
A
(2)  
(2)  
SOURCE  
Plastic HTSSOP (PWP)  
−40°C to 85°C  
SOURCE/SINK  
Plastic HTSSOP (PWP)  
(1)  
(2)  
See page 7 for explanation.  
The PWP package is also available taped and reeled. Add an R suffix to the device type (i.e., TPS40020PWPR). See the application section of  
the data sheet for PowerPAD drawing and layout information.  
ABSOLUTE MAXIMUM RATINGS  
over operating free-air temperature range unless otherwise noted  
(4)  
TPS4002X  
UNIT  
SS/SD, VDD, PVDD, OSNS  
BOOT2, BOOT1  
SW  
−0.3 to 6  
V
SW  
+ 6  
−3.0 to 10.5  
−5  
Input voltage range, V  
IN  
V
SWT (SW transient < 50 ns)  
FB, ILIM  
−0.3 to 6.0  
−0.3 to 6  
10  
Output voltage range, V  
OUT  
COMP, PWRGD, RT  
PWRGD  
Sink current, I  
mA  
S
Operating virtual junction temperature range, T  
−40 to 125  
−55 to 150  
260  
J
Storage temperature, T  
stg  
°C  
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds  
(4)  
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only,  
and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is  
not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.  
RECOMMENDED OPERATING CONDITIONS  
MIN NOM MAX UNIT  
Input voltage, V  
IN  
2.25  
−40  
5.5  
85  
V
Operating junction temperature, T  
°C  
J
(5)(6)  
PWP PACKAGE  
(TOP VIEW)  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
ILIM/SYNC  
VDD  
BOOT1  
HDRV  
SW  
BOOT2  
PVDD  
LDRV  
OSNS  
FB  
COMP  
SS/SD  
RT  
THERMAL  
PAD  
PGND  
PWRGD  
SGND  
(5) For more information on the PWP package, refer to TI Technical Brief, Literature No. SLMA002.  
(6) PowerPADt heat slug must be connected to SGND (Pin 8), or electrically isolated from all other pins.  
3
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SLUS535C − MARCH 2003 − REVISED SEPTEMBER 2004  
ELECTRICAL CHARACTERISTICS  
T = −40°C to 85°C, T = T  
V
= 5.0 V (unless otherwise noted)  
J
J
A, DD  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
INPUT SUPPLY  
V
V
Input voltage range, VDD  
PVDD pin voltage  
Switching current  
Quiescent current  
Shutdown current  
Minimum on-voltage  
Hysteresis  
2.25  
5.50  
5.2  
DD  
V
V
= 3.3 V  
4.9  
3.5  
PVDD  
DD  
500 kHz, No load on HDRV, LDRV  
FB = 0.8 V  
5.0  
2.0  
3.0  
I
mA  
DD  
SS/SD = 0 V, Outputs OFF  
0.38  
2.05  
130  
1.00  
2.15  
200  
1.95  
80  
V
V
UVLO  
mV  
OSCILLATOR  
2.25 V V  
2.25 V V  
5.00 V,  
5.00 V,  
R
= 69.8 kΩ  
= 34.8 kΩ  
425  
800  
500  
950  
575  
1100  
1.07  
0.41  
DD  
T
f
Accuracy  
kHz  
V
OSC  
R
T
DD  
V
V
Ramp voltage  
V
−V  
0.80  
0.24  
0.93  
0.31  
RAMP  
PEAK VAL  
Ramp valley voltage  
VAL  
PWM  
V
V
= V , R = 34.8 k,  
DD  
OSNS  
DD  
T
85%  
90%  
94%  
95%  
= 3.3 V, FB = 0 V  
d
d
Maximum duty cycle  
MAX  
V
V
= V , R = 70 k,  
DD  
OSNS  
DD  
T
= 5.0 V, FB = 0 V  
Minimum duty cycle  
0%  
MIN  
MIN  
(2)  
t
Minimum HDRV on-time  
250  
ns  
ERROR AMPLIFIER  
V
Feedback input voltage  
Input bias current  
−40°C T 85°C, 2.25V V  
DD  
5.00V  
0.685 0.690  
30  
0.697  
130  
V
FB  
A
I
nA  
BIAS  
V
High-level output voltage  
I
I
= 0.5 mA, V  
= GND  
2.0  
2.5  
0.08  
7
OH  
OL  
OH  
FB  
V
V
Low-level output voltage  
= 0.5 mA, V  
= GND  
= V  
DD  
0.15  
OL  
FB  
I
I
High-level output source current  
Low-level output sink current  
V
V
3
3
OH  
FB  
mA  
= V  
DD  
8
OL  
FB  
(1)  
Gain bandwidth  
G
5
10  
85  
MHz  
dB  
BW  
(1)  
Open loop gain  
A
OL  
55  
CURRENT LIMIT  
I
Current limit sink current  
2.25 V V  
DD  
5.00 V,  
R
T
= 69.8 kΩ  
165  
−20  
190  
0
215  
20  
µA  
SINK  
V
Current limit offset voltage  
mV  
OS  
ON  
ON  
SS  
t
t
t
Minimum HDRV on−time in overcurrent  
Switch leading-edge blanking pulse time  
Soft-start cycles  
V
DD  
= 3.3 V  
200  
140  
6
300  
ns  
(1)  
cycles  
V
V
Current limit input voltage range  
2
VDD  
5.4  
ILIM  
SOFT START  
I
Soft-start source current  
Outputs = OFF  
2.0  
3.3  
µA  
SS  
(1)  
(2)  
Ensured by design. Not production tested.  
Operation below the minimum on-time could result in overlap of the HDRV and LDRV outputs.  
4
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SLUS535C − MARCH 2003 − REVISED SEPTEMBER 2004  
ELECTRICAL CHARACTERISTICS (continued)  
T = −40°C to 85°C, T = T  
V
= 5.0 V (unless otherwise noted)  
J
J
A, DD  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
SHUTDOWN  
V
V
Shutdown threshold voltage  
0.22  
0.25  
0.26  
0.28  
0.29  
0.32  
SD  
V
Device enable threshold voltage  
EN  
OUTPUT DRIVER  
V
− V  
(SW)  
= 3.3 V,  
= 3.3 V,  
(BOOT1)  
R
R
High-side driver pull-up resistance  
High-side driver pull-down resistance  
1.0  
0.8  
2.5  
1.5  
5.0  
3.0  
HDHI  
I
100mA  
SOURCE =  
V
− V  
(SW)  
100mA  
(BOOT1)  
HDLO  
I
SINK =  
R
R
Low-side driver pull-up resistance  
Low-side driver pull-down resistance  
Low-side driver rise time  
P
P
= 3.3 V, I  
100 mA  
SOURCE =  
1.0  
2.5  
0.80  
15  
5.0  
1.50  
35  
LDHI  
VDD  
= 3.3 V, I 100 mA  
SINK =  
0.45  
LDLO  
VDD  
t
t
t
t
LRISE  
LFALL  
HRISE  
HFALL  
Low-side driver fall time  
10  
25  
C
= 1 nF  
ns  
LOAD  
High-side driver rise time  
15  
35  
High-side driver fall time  
10  
25  
THERMAL SHUTDOWN  
Shutdown temperature  
(1)  
(1)  
165  
15  
T
SD  
°C  
Hysteresis  
CHARGE PUMP  
R
VB2  
R
B2P  
R
PB1  
R
R
R
VDD to BOOT2  
BOOT2 to PVDD  
PVDD to BOOT1  
V
DD  
V
DD  
V
DD  
= 5.0 V,  
I
I
I
10 mA  
2.8  
2.8  
2.9  
6.6  
5.6  
5.9  
10.4  
8.4  
DS(on)  
DS(on)  
DS(on)  
SOURCE =  
SOURCE =  
SOURCE =  
= 5.0 V,  
= 5.0 V,  
10 mA  
10 mA  
8.9  
POWER GOOD  
V
V
= 0.8 V,  
I
0.5 mA,  
OSNS  
= 3.3 V  
PWRGD =  
V
Pull-down voltage  
50  
6
90  
10  
140  
14  
mV  
PGD  
DD  
Output sense high to power good low delay  
time  
0.7 VV  
0.8 V, I  
0.7 V, I  
0.5 mA,  
PWRGD =  
OSNS  
t
ONHPL  
V
DD  
= 3.3 V  
Output sense low to power good low delay  
time  
0.6 VV  
0.5 mA,  
PWRGD =  
OSNS  
= 3.3 V  
t
6
10  
14  
ONLPL  
V
DD  
µs  
V
V
= 0.7 V, I  
= 3.3 V, 0.0 V V  
0.5 mA,  
0.4 V  
OSNS  
DD  
PWRGD =  
t
Shutdown high to power good high delay time  
Shutdown low to power good low delay time  
2
4
6
SDHPH  
SS/SD  
V
V
= 0.7 V, I  
= 3.3 V, 0.0 V V  
SS/SD  
0.5 mA,  
0.4 V  
OSNS  
DD  
PWRGD =  
t
0.5  
140  
140  
1.5  
500  
500  
3.0  
SDLPL  
Output sense high to nominal to power good  
high delay time  
0.7 VV  
0.8 V, I  
0.5 mA,  
PWRGD =  
OSNS  
= 3.3 V  
t
1000  
1000  
ONHPH  
V
DD  
ns  
Output sense low to nominal to power good  
high delay time  
0.6 VV  
0.7 V, I  
0.5 mA,  
PWRGD =  
OSNS  
= 3.3 V  
t
ONLPH  
V
DD  
TRANSIENT COMPARATORS  
Overvoltage output threshold voltage  
23  
8
29  
15  
35  
22  
V
OV  
Hysteresis  
Referenced to V  
Referenced to V  
mV  
V
FB  
Undervoltage output threshold voltage  
Hysteresis  
−37  
8
−31  
15  
−25  
22  
V
V
UV  
OSNS minimum disable voltage  
0.5  
DIS  
DD  
(1)  
Ensured by design. Not production tested.  
5
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SLUS535C − MARCH 2003 − REVISED SEPTEMBER 2004  
ELECTRICAL CHARACTERISTICS (continued)  
T = −40°C to 85°C, T = T  
V
= 5.0 V (unless otherwise noted)  
J
J
A, DD  
PARAMETER  
SYNCHRONIZATION  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
V
Synchronization enable low threshold voltage  
0.7  
50  
ENSY  
BLNK  
MIN  
V
Synchronization current limit enable threshold  
voltage  
V
Referenced to VDD  
−0.7  
t
Minimum synchronization input pulse width  
35  
ns  
PREDICTIVE DELAY  
V
Sense voltage to modulate delay  
Maximum delay modulation  
Counter delay/bit time  
−200  
65  
mV  
ns  
SWP  
LDRV OFF-to-HDRV ON  
LDRV OFF-to-HDRV ON  
HDRV OFF-to-LDRV ON  
HDRV OFF-to-LDRV ON  
40  
2.5  
55  
90  
6.2  
105  
6.5  
t
LDHD  
4.5  
80  
Maximum delay modulation  
Counter delay/bit time  
t
HDLD  
2.2  
5.0  
RECTIFIER ZERO CURRENT COMPARATOR  
Sense voltage to turn off  
rectifier MOSFET  
V
TPS40020 LDRV output = OFF  
−5  
−2.5  
150  
2
mV  
ns  
SW  
(1)  
t
Zero current blanking time  
ZBLNK  
(1)  
Ensured by design. Not production tested.  
TERMINAL FUNCTIONS  
TERMINAL  
I/O  
DESCRIPTION  
NAME  
NO.  
This pin provides a bootstrapped supply for the high side FET driver, enabling the gate of the high side FET to be  
driven above the input supply rail. Connect a capacitor from this pin to the SW pin.  
BOOT1  
16  
I
I
This pin provides a secondary bootstrapping necessary for generation of PVDD. Connect a capacitor from this  
pin to SW.  
BOOT2  
13  
COMP  
FB  
5
4
O
I
Output of the error amplifier. Refer to Electrical Characteristics table for loading constraints.  
Inverting input of the error amplifier. In normal operation, V  
FB  
is equal to the internal reference level of 690 mV.  
The gate drive output for the high side N-channel MOSFET switch is bootstrapped to near PVDD for good  
enhancementof the high-side switch. The HDRV switches from BOOT1 to SW.  
HDRV  
15  
O
The current limit pin is used to set the current limit threshold. A current sink from this pin to GND sets the threshold  
voltage for output short circuit current across a resistor connected to VDD. Synchronization is accomplished by  
pulling IMAX to less than 1 V for a period greater than the minimum pulse width and then releasing. An open  
collector or drain device should be used. These pulses must be of higher frequency than the free running frequency  
of the local oscillator.  
ILIM/SYNC  
1
I
Gate drive output for the low-side synchronous rectifier N-channel MOSFET. LDRV switches from PVDD to  
PGND.  
LDRV  
OSNS  
11  
3
O
O
The output sense pin is connected to a resistor divider from VOUT to GND (identical to the main feedback loop)  
and is used to sense power good condition and provides reference for the transient comparators.  
PGND  
10  
9
O
Power (high-current) ground used by LDRV.  
PWRGD  
Power good. This is an open-drain output which connects to the supply via an external resistor.  
This pin is the regulated output of the charge-pump and provides the supply voltage for the LDRV driver stage.  
PVDD also drives the bootstrap circuit which generates the voltage on BOOT1.  
PVDD  
12  
O
RT  
7
8
I
External pin for programming the oscillator frequency. Connnected a resistor between this pin and GND.  
Signal ground  
SGND  
The soft-start/shutdown pin provides user programmable soft-start timing and shutdown capability for the  
controller.  
SS/SD  
6
I
This pin, used for overcurrent, zero-current, and in the anti-cross conduction sensing is connected to the switched  
node on the converter. Output short circuit is detected by sensing the voltage at this pin with respect to VDD while  
the high-side switch is on. Zero current is detected by sensing the pin voltage with respect to ground when the  
low-side rectifier MOSFET is on.  
SW  
14  
2
I
I
VDD  
Power input for the device. Maximum voltage is 5.5 V. De-coupling of this pin is required.  
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The TPS4002x series of devices are low-input voltage, synchronous, voltage mode-buck controllers. A typical  
application circuit is shown in Figure 1. These controllers are designed to allow construction of  
high-performance dc-to-dc converters with input voltages from 2.25 V to 5.5 V, and output voltages as low as  
690 mV. Using a top side N-channel MOSFET for the primary buck switch results in lower switch resistance  
for a given gate charge.  
The device controls the delays from main switch off to rectifier turn on and from rectifier turn off to main switch  
turn on in a way that minimizes diode losses (both conduction and recovery) in the synchronous rectifier. The  
reduction in these losses is significant and can mean that for a given converter power level, smaller FETs can  
be used, or that heat sinking can be reduced or even eliminated.  
The TPS40021 is the controller of choice for most general purpose synchronous buck designs, operating in two  
quadrant mode (i.e. source or sink current) full time. This choice provides the best performance for output  
voltage load transient response over the widest load current range.  
The TPS40020 operates in single quadrant mode (source current only) full time, allowing the paralleling of  
converters. Single quadrant operation ensures one converter does pull current from a paralleled converter. A  
converter using one of these controllers emulates a non-synchronous buck converter at light loads. When  
current in the output inductor attempts to reverse, an internal zero-current detection circuit turns OFF the  
synchronous rectifier and causes the current flow in the inductor to become discontinuous. At average load  
currents greater than the peak amplitude of the inductor ripple current, the converter returns to operation as  
a synchronous buck converter to maximize efficiency.  
The controller provides for a coarse short circuit current-limit function that provides pulse-by-pulse current  
limiting, as well as integrates short circuit current pulses to determine the existence of a persistant fault state  
at the converter output. If a fault is detected, the converter shuts down for a period of time (determined by six  
soft-start cycles) and then restarts. The current-limit threshold is adjustable with a single resistor connected  
from VDD to the ILIM/SYNC pin. This overcurrent function is designed to protect against catastrophic faults  
only, and cannot be guaranteed to protect against all overcurrent conditions.  
The controller implements a closed-loop soft start function. Startup ramp time is set by a single external  
capacitor connected to the SS/SD pin. The SS/SD pin also doubles as a shutdown function.  
VOLTAGE REFERENCE  
The bandgap cell is designed with a trimmed, curvature corrected (< 1%) 0.69-V output, allowing output  
voltages as low as 690 mV to be obtained.  
Oscillator  
The ramp waveform is a saw-tooth form at the PWM frequency with a peak voltage of 1.25 V, and a valley of  
0.3 V. The PWM duty cycle is limited to a maximum of 97%, allowing the bootstrap and charge pump capacitors  
to charge during every cycle.  
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Bootstrap/Charge Pump  
The TPS4002X series includes a charge pump to boost the drive voltage to the power MOSFET’s to higher  
levels when the input supply is low. A capacitor connected from PVDD to PGND is the storage cap for the pump.  
A capacitor connected from SW to BOOT2 gets charged every switching cycle while LDRV is high and its charge  
is dumped on the PVDD capacitor when HDRV goes high. An internal switch disables the charge pump when  
the voltage on PVDD reaches approximately 4.8 V and enables pumping when PVDD falls to approximately  
4.6 V. The high-side driver uses the capacitor from SW to BOOT1 as its power supply. When SW is low, this  
capacitor charges from the PVDD capacitor. When the SW pin goes high, this capacitor provides above-rail  
drive for the high-side N-channel FET.  
PVDD, BOOT1 and BOOT2 are pre-charged to the VDD voltage during a shutdown condition. For low-input  
voltage converters, utilizing higher gate threshold voltage MOSFETs, it may be necessary to add an Schottky  
diode from VDD (anode) to BOOT1 to guarantee sufficient voltage for initial start up. Once switching starts the  
charge pump reverses bias on the Schottky diode.  
When operating the TPS40020 under no load or extremely light-load conditions the controller will be operating  
in discontinuous Mode (DCM); reverse current is prevented from flowing in the synchronous rectifier. In DCM  
the on times for both the HDRV and LDRV pulses can become too narrow to provide adequate charging of  
PVDD and BOOT1 outputs, causing their voltages to collapse. Insufficient PVDD and BOOT1 voltages prevent  
the external MOSFETS from becomming fully enhanced, causing loss of converter output regulation. Schottky  
diodes from VIN (anode) to PVDD, and VIN (anode) to BOOT1, as well as a pre-load can be added to maintain  
PVDD and BOOT1 at voltage levels sufficient enough to fully enhance the external MOSFETs. The amount of  
pre-load typically ranges from 50 mA to 100 mA depending on operating conditions and external MOSFET  
selection.  
Drivers  
The HDRV and LDRV MOSFET drivers are capable of driving gate-to-source voltages up to 5.0 V. Using  
appropriate MOSFETs, a 25-A converter can be achieved. The LDRV driver switches between VDD and  
ground, while the HDRV driver is referenced to SW and switches between BOOT1 and SW. The maximum  
voltage between BOOT1 and SW is 5.0 V when PVDD is in regulation.  
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Figure 1. Typical Application  
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Synchronous Rectification and Predictive Delay  
In a normal buck converter, when the main switch turns off, current is flowing to the load in the inductor. This  
current cannot be stopped immediately without using infinite voltage. To give this current a path to flow and  
maintain voltage levels at a safe level, a rectifier or catch device is used. This device can be either a plain diode,  
or it can be a controlled active device if a control signal is available to drive it. The TPS4002X provides a signal  
to drive an N−channel MOSFET as a rectifier. This control signal is carefully coordinated with the drive signal  
for the main switch so that there is absolute minimum dead time from the time that the rectifier FET turns off  
and the main switch turns on, and minimum delay from when the main switch turns off and the rectifier FET  
turns on. This TI−patented function, predictive delay, uses information from the current switching cycle to adjust  
the delays that are used for the next cycle. Figure 2 shows the switch-node voltage waveform for a  
synchronously rectified buck converter. Illustrated are the relative effects of a fixed delay drive scheme  
(constant, pre-set delays for the turnoff to turn on intervals), an adaptive delay drive scheme (variable delays  
based upon voltages sensed on the current switching cycle) and the predictive delay drive scheme. Note that  
the longer the time spent in diode conduction during the rectifier conduction period, the lower the efficiency. Also,  
not shown in the figure, is the fact that the predictive delay circuit can actually prevent the body diode from  
becoming forward biased at all while at the same time avoiding cross conduction or shoot through. This results  
in a significant power savings when the main FET turns on. There is no reverse recovery loss in the body diode  
of the rectifier FET.  
GND  
Channel Conduction  
Body Diode Conduction  
Fixed Delay  
Adaptive Delay  
Predictive Delay  
UDG−01144  
Figure 2. Switch Node Waveforms for Synchronous Buck Converter  
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Output Short Circuit Protection  
Output short circuit protection in the TPS4002x is sensed by looking at the voltage across the main FET while  
it is on. If the voltage exceeds a pre-set threshold, the current pulse is terminated, and a counter inside the  
device is incremented. If this counter fills up, a fault condition is declared and the chip disables switching for  
a period of time and then attempts to restart the converter with a full soft-start cycle. The more detailed  
explanation follows.  
In each switching cycle, a comparator looks at the voltage across the top side FET while it is on. If the voltage  
across that FET exceeds a programmable threshold voltage, then the current switching pulse is terminated and  
a 3-bit counter (eight counts) is incremented by one count. If during the switching cycle the top side FET voltage  
does not exceed a preset threshold, then this counter is decremented by one count. (The counter does not wrap  
around from seven to zero or from zero to seven). If the counter reaches a full count of seven, the device  
declares that a fault condition exists at the output of the converter. In this state, switching stops and the soft-start  
capacitor is discharged. The counter is decremented by one by the soft start cap discharge. When the soft-start  
capacitor is fully discharged, the discharge circuit is turned off and the cap is allowed to charge up at the nominal  
charging rate, When the soft-start capacitor reaches approximately 1.3 V, it is discharged again and the  
overcurrent counter is decremented by one count. The capacitor is charged and discharged, and the counter  
decremented until the count reaches zero (a total of six times). When this happens, the outputs are again  
enabled as the soft-start capacitor generates a reference ramp for the converter to follow while attempting to  
restart. During this soft-start interval (whether or not the controller is attempting to do a fault recovery or starting  
for the first time), pulse-by-pulse current limiting is in effect, but overcurrent pulses are not counted to declare  
a fault until the soft-start cycle has been completed. It is possible to have a supply try to bring up a short circuit  
for the duration of the soft-start period plus seven switching cycles. Power stage designs should take this into  
account if it makes a difference thermally. Figure 3 shows the details of the overcurrent operation.  
(+)  
V
TS  
(−)  
Overcurrent  
Threshold  
Voltgage  
Internal PWM  
V
TS  
0 V  
External  
Main Drive  
Normal Cycle  
Overcurrent  
Cycle  
UDG−03029  
Figure 3. Switch Node Waveforms for Synchronous Buck Converter  
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APPLICATION INFORMATION  
Figure 4 shows the behavior of key signals during initial startup, during a fault and a successfully fault recovery.  
At time t0, power is applied to the converter. The voltage on the soft-start capacitor (V ) begins to ramp up  
CSS  
At t1, the soft-start period is over and the converter is regulating its output at the desired voltage level. From  
t0 to t1, pulse-by-pulse current limiting was in effect, and from t1 onward, overcurrent pulses are counted for  
purposes of determining if a fault exists. At t2, a heavy overload is applied to the converter. This overload is  
in excess of the overcurrent threshold, the converter starts limiting current and the output voltage falls to some  
level depending on the overload applied. During the period from t2 to t3, the counter is counting overcurrent  
pulses and at time t3 reaches a full count of 7. The soft-start capacitor is then discharged, the outputs are  
disabled, the counter decremented, and a fault condition is declared.  
V
DD  
1.3 V  
0.6 V  
0.6 V  
V
CSS  
FAULT  
I
LOAD  
V
OUT  
t
t4  
t0  
t1  
t2 t3  
t5  
t6  
t7  
t8  
t9  
t10  
Counter  
0
6
5
4
3
2
1
0
1
2
3
4
5
6
7
cycles  
UDG−03187  
Figure 4. Overcurrent/Fault Waveforms  
When the soft-start capacitor is fully discharged, it begins charging again at the same rate that it does on startup,  
with a nominal 3-µA current source. As the capacitor voltage reaches full charge, it is discharged again and the  
counter is decremented by one count. These transitions occur at t3 through t9. At t9, the counter has been  
decremented to zero. Now the fault logic is cleared, the outputs are enabled and the converter attempts to  
restart with a full soft-start cycle. The converter comes into regulation at t10.  
The internal SS signal is a diode drop below V  
. When V  
reaches one diode drop above ground, (0.6 V)  
CSS  
CSS  
the output (V  
) begins it’s soft-start ramp.  
OUT  
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APPLICATION INFORMATION  
Setting the Short Circuit Current Limit Threshold  
Connecting a resistor from VDD to ILIM sets the current limit. A current sink in the chip causes a voltage drop  
across the resistor connected to ILIM. This voltage drop is the short circuit current threshold for the part. The  
current that the ILIM pin sinks is dependent on the value of the resistor connected to RT and is given by:  
0.69 V  
I
+ 19.0   
ILIM  
R
T
(1)  
The tolerance of the current sink is too loose to do an accurate current limit. The main purpose is for hard fault  
protection of the power switches. Given the tolerance of the ILIM sink current, and the R range for a  
DS(on)  
MOSFET, it is generally possible to apply a load that thermally damages the converter. This device is intended  
for embedded converters where load characteristics are defined and can be controlled. A small capacitor can  
be added between ILIM and VDD for filtering. However, capacitors should not be used if the synchronization  
function is to be used.  
Soft-Start and Shutdown  
The soft-start and shutdown functions are common to the SS/SD pin. The voltage at this pin is the controlling  
voltage sent to the error amplifier during startup. This reduces the transient current required to charge the output  
capacitor at startup, and allows for a smooth startup with no overshoot of the output voltage. A shutdown feature  
can be implemented as shown in Figure 5.  
3.3 µA  
6
SS/SD  
C
SS  
SHUTDOWN  
TPS4002x  
Figure 5. Shutdown Implementation  
I
SS  
C
+
  t  
(F)  
SS  
SS  
V
FB  
(2)  
where  
D t is the start up time in seconds  
SS  
Switching Frequency  
The switching frequency is programmed by a resistor from RT to SGND. Nominal switching frequency can be  
calculated by:  
3
37.736   10  
(
)
R (kW) +  
* 5.09 kW  
T
(
)
kHz  
f
OSC  
(3)  
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Synchronization  
The TPS4002x can be synchronized to an external reference frequency higher than the free running oscillator  
frequency. The recommended method is to use a diode and a push pull drive signal as shown in Figure 6.  
PREFERRED  
VDD  
ALTERNATE  
VDD  
Minumize  
Output/Stray  
Capacitance  
on ILIM Node  
TPS4002XPWP  
TPS4002XPWP  
1
ILIM/SYNC  
VDD  
1
2
ILIM/SYNC  
VDD  
2
50 ns to 100 ns  
UDG−03032  
50 ns to 100 ns  
Figure 6. Synchronization Methods  
This design allows synchronization up to the maximum operating frequency of 1 MHz. For best results the  
nominal operating frequency of a converter that is to be synchronized should be kept as close as practicable  
to the synchronization frequency to avoid excessive noise induced pulse width jitter. A good target is to shoot  
for the free run frequency to be 80% of the synchronized frequency. This ensures that the synchronization  
source is the frequency determining element in the system and not to adversely affect noise immunity.  
Other methods of implementing the synchronization function include using an open collector or open drain  
output device directly, or discreet devices to pull the ILIM/SYNC pin down. These do work but performance can  
suffer at high frequency because the ILIM/SYNC pin must rise to (V  
− 1.0 V) before the next switching cycle  
DD  
begins. Any time that this requires is directly subtracted from the maximum pulse width available and should  
be considered when choosing devices to drive ILIM/SYNC. Consequently, the lowest output capacitance  
devices work best.  
During a synchronization cycle, the current sink on the ILIM/SYNC pin becomes disabled when ILIM/SYNC is  
pulled below 1.0 V. The ILIM/SYNC current sink remains disabled until ILIM/SYNC reaches (V  
−1.0 V) This  
DD  
removes the load on the ILIM/SYNC pin to allow the voltage to slew rapidly depending on the ILIM resistor and  
any stray capacitance on the pin. To maximize this slew rate, minimize stray capacitance on this pin.  
The duration of the synchronization pulse pulling ILIM/SYNC low shoud be between 50 ns and 100 ns. Longer  
durations may limit the maximum obtainable duty cycle.  
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Transient Comparators and Power Good  
The TPS4002x makes use of a separate pin, OSNS, to monitor output voltage for these two functions. In normal  
operation, OSNS is connected to the output via a resistor divider. It is important to make this divider the same  
ratio as the divider for the feedback network so that in normal operation the voltage at OSNS is the same as  
the voltage at FB, 0.69 V nominal.  
The PWRGD pin is an open drain output that is pulled low when the voltage at OSNS falls outside 0.69 V 4.6%  
(approximately). A delay has been purposely built into the PWRGD pin pulling low in response to an out of band  
voltage on OSNS, to minimize the need for filtering the signal in the event of a noise glitch causing a brief out  
of band OSNS voltage. The PWRGD signal returns to high when the OSNS signal returns to approximately 1%  
of nominal (0.69 V 1%).  
The transient comparators override the conventional voltage control loop when the output voltage exceeds a  
4.6% window. If the output transition is high (i.e. load steps down from 90% load to 10 % load) then the HDRV  
gate drive is terminated, 0% duty cycle, the LDRV gate drive is turned on to sink output current until V  
returns  
OUT  
to within 1% of nominal. Conversely when V  
drops outside the window (i.e. step load increases from 10%  
OUT  
load to 90% load) HDRV increases to maximum duty cycle until V  
Figure 7.)  
returns to within 1% of nominal. (See  
OUT  
During start-up, the transient comparators control the state of PWRGD as previously described. However, the  
operation of the gate drive outputs is not affected. (See Figure 8)  
The transient comparators provide an improvement in load transient recovery time if used properly. In some  
situations, recovery time may be one half of the time required without transient comparators. Keep in mind that  
the transient comparator concept is a double-edged sword. While they provide improved transient recovery  
time, they can also lead to instability if incorrectly applied. For proper functionality, design a feedback loop for  
the converter that places the closed loop unity gain frequency at least five times higher than the 0 dB frequency  
of the output L-C filter. If not, the feedback loop cannot respond to the ring of the L-C on a transient event. The  
ring is likely to be large enough to disturb the transient comparators and the result is a power oscillator. Another  
helpful action is to ground the feedback loop divider and the OSNS divider at the SGND pin. Make sure both  
dividers measure the same physical location on the output bus. These help avoid problems with resistive drops  
at higher loads causing problems.  
Connecting OSNS to VDD disables the transient comparators. This also disables the PWRGD function.  
Alternatively, OSNS and FB can be tied together. This connection allows a proper PWRGD at startup, though  
transient performance diminishes.  
< 10 µs  
4.6%  
1%  
FB  
−1%  
− 4.6%  
− 4.6%  
10 µs  
PWRGD  
µ
500 n s  
500 n s  
10  
s
SW  
98 % Duty Cycle  
0 % Duty Cycle  
98 % Duty Cycle  
0 % Duty Cycle  
UDG−03181  
Figure 7. Duty Cycle Waveforms  
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V
DD  
1.3 V  
0.6 V  
0.3 V  
SS/SD  
V
OUT  
− 1%  
500 ns  
V
OUT  
1.5 µs  
Transient Comparators Enabled  
4 µs  
PWRGD  
Transient Comparators Disabled  
UDG−03181  
Figure 8. Transient Comparator Waveforms  
Layout Considerations  
Successful operation of the TPS4002x family of controllers is dependent upon the proper converter layout and  
grounding techniques. High current returns for the SR MOSFET’s source, input capacitance, output  
capacitance, PVDD capacitance, and input bypass capacitors (if applicable), should be kept on a single ground  
plane or wide trace connected to the PGND (pin10) through a short wide trace. Control components connected  
to signal ground, as well as the PowerPad thermal pad, should be connected to a single ground plane connected  
to SGND (Pin 8) through a short trace. SGND and PGND should be connected at a single point using a narrow  
trace.  
Proper operation of Predictive Gate Drivetechnology and I  
functions are dependent upon detecting  
ZERO  
low-voltage thresholds on the SW node. To ensure that the signal at the SW pin accurately represents the  
voltage at the main switching node, the connection from SW (pin 14) to the main switching node of the converter  
should be kept as short and wide as possible and should ideally be kept on the top level with the power  
components. If the SW trace must traverse multiple board layers between the TPS4002x and the main  
switching node, multiple vias should be used to minimize the trace impedance.  
Gate drive outputs, LDRV and HDRV (pins 11 and 15, respectively) should be kept as short as possible to  
minimize inductances in the traces. If the gate drive outputs need to traverse multiple board layers multiple vias  
should be used.  
Charge pump components, BOOT1, BOOT2, PVDD, and any input bypass capacitors (if required), should be  
kept as close as possible to their respective pins. Ceramic bypass capacitors should be used if the input  
capacitors are located more than a couple of inches away from the TPS4002X. If a bypass capacitor is not  
needed the trace from the input capacitors to VDD (pin2) should be kept as short and wide as possible to  
minimize trace impedance. If multiple board layers are traversed multiple vias should be used.  
16  
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Manufacturer’s instructions should be followed for proper layout of the external MOSFETs. Thermal  
impedances given in the manufacturer’s datasheets are for a given mounting technique with a specified surface  
area under the drain of the MOSFET. PowerPad package information can be found in the APPLICATION  
INFORMATION section of this datasheet.  
Refer to TPS40021 EVM−001 High Efficiency Synchronous Buck Converter with PWM Controller Evaluation  
Module (HPA009) User’s Guide, (Literature No. sluu144A) for a typical board layout.  
The PowerPAD package provides low thermal impedance for heat removal from the device. The PowerPAD  
derives its name and low thermal impedance from the large bonding pad on the bottom of the device. The circuit  
board must have an area of solder-tinned-copper underneath the package. The dimensions of this area  
depends on the size of the PowerPAD package. For a 16-pin TSSOP (PWP) package the area is  
5 mm x 3.4 mm [3].  
X: Minimum PowerPAD = 1.8 mm  
Y: Minimum PowerPAD = 1.4 mm  
Thermal Pad  
6,60 mm  
4,50 mm  
X
4,30 mm 6,20 mm  
1
8
Y
Figure 9. PowerPAD Dimensions  
Thermal vias connect this area to internal or external copper planes and should have a drill diameter sufficiently  
small so that the via hole is effectively plugged when the barrel of the via is plated with copper. This plug is  
needed to prevent wicking the solder away from the interface between the package body and the solder-tinned  
area under the device during solder reflow. Drill diameters of 0.33 mm (13 mils) works well when 1-oz copper  
is plated at the surface of the board while simultaneously plating the barrel of the via. If the thermal vias are  
not plugged when the copper plating is performed, then a solder mask material should be used to cap the vias  
with a diameter equal to the via diameter of 0.1 mm minimum. This capping prevents the solder from being  
wicked through the thermal vias and potentially creating a solder void under the package. Refer to PowerPAD  
[3]  
Thermally Enhanced Package for more information on the PowerPAD package.  
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TYPICAL CHARACTERISTICS  
OSCILLATOR FREQUENCY  
vs  
JUNCTION TEMPERATURE  
MAXIMUM DUTY CYCLE  
vs  
JUNCTION TEMPERATURE  
99  
1000  
950  
900  
850  
800  
750  
700  
650  
600  
550  
500  
450  
98  
97  
R
T
= 35 kΩ  
96  
95  
V
= 3.3 V, R = 69.8 kΩ  
T
DD  
R
T
= 69.8 kΩ  
94  
93  
V
DD  
= 5 V, R = 35 kΩ  
T
−50  
−25  
0
25  
50  
75  
100  
125  
−50  
−25  
0
25  
50  
75  
100  
125  
T
J
− Junction Temperature − °C  
T
J
− Junction Temperature − °C  
Figure 11  
Figure 10  
SHUTDOWN SUPPLY CURRENT  
vs  
REFERENCE VOLTAGE  
vs  
JUNCTION TEMPERATURE  
JUNCTION TEMPERATURE  
0.700  
0.675  
697  
695  
693  
0.650  
0.625  
0.600  
0.575  
691  
689  
687  
685  
683  
0.550  
0.525  
0.500  
−50  
−25  
0
25  
50  
75  
100  
125  
−50  
−25  
0
25  
50  
75  
100  
125  
T
J
− Junction Temperature − °C  
T
J
− Junction Temperature − °C  
Figure 12  
Figure 13  
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TYPICAL CHARACTERISTICS  
SOFT-START CURRENT  
vs  
JUNCTION TEMPERATURE  
TIMING RESISTANCE  
vs  
SWITCHING FREQUENCY  
3.50  
3.45  
3.40  
1000  
900  
800  
700  
600  
V
IN  
= 3.9 V  
3.35  
3.30  
3.25  
500  
400  
3.20  
3.15  
3.10  
300  
200  
3.05  
3.00  
100  
20  
40  
60  
80  
100  
120  
140  
160  
−50  
−25  
0
25  
50  
75  
100  
125  
R
T
− Timing Resistance − kΩ  
T
J
− Junction Temperature − °C  
Figure 14  
Figure 15  
SHUTDOWN THRESHOLD VOLTAGE  
ILIM OFFSET VOLTAGE  
vs  
JUNCTION TEMPERATURE  
vs  
JUNCTION TEMPERATURE  
0.30  
20  
15  
10  
5
0.29  
0.28  
V
DD  
= 2.0 V  
Enable  
0.27  
0.26  
0.25  
0
Disable  
0.24  
0.23  
V
= 3.2 V  
DD  
−5  
−10  
−15  
0.22  
0.21  
0.20  
V
= 4.9 V  
DD  
−20  
−50  
−50  
−25  
0
25  
50  
75  
100  
125  
−25  
0
25  
50  
75  
100  
125  
T
J
− Junction Temperature − °C  
T
J
− Junction Temperature − °C  
Figure 16  
Figure 17  
19  
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TYPICAL CHARACTERISTICS  
ILIM SINK CURRENT  
vs  
JUNCTION TEMPERATURE  
200  
V
V
= 3.3 V  
= 1.5 V  
= 300 kHz  
DD  
OUT  
V
R
= 3 V  
DD  
= 69.8 kΩ  
V
OUT  
198  
196  
T
f
SW  
194  
192  
190  
LDRV  
SW  
188  
186  
184  
182  
180  
t − Time − 1 µs/div  
−50  
−25  
0
25  
50  
75  
100  
125  
T
J
− Junction Temperature − °C  
Figure 19. TPS40020 Discontinuous Mode (DCM)  
Figure 18  
V
V
DD  
= 3.3 V  
DD  
= 1.5 V  
f
SW  
= 300 kHz  
SS/SD  
V
OUT  
V
OUT  
LDRV  
SW  
SW  
t − Time − 1 µs/div  
t − Time − 20 ms/div  
Figure 21. Output Current Fault Operation  
Figure 20. TPS40020 I  
Detection − DCM  
ZERO  
20  
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TYPICAL CHARACTERISTICS  
V
V
= 3.3 V  
V
V
= 3.3 V  
DD  
DD  
SS/SD  
= 1.5 V  
= 300 kHz  
= 1.5 V  
= 300 kHz  
OUT  
OUT  
f
I
f
I
SW  
SW  
PVDD  
= 5 A  
= 5 A  
LOAD  
LOAD  
SW  
V
OUT  
PWRGD  
V
OUT  
t − Time − 25 µs/div  
t − Time − 1 ms/div  
Figure 22. Start−Up Operation Without  
Transient Comparators  
Figure 23. PVDD Hysteresis  
V
= 3.3 V  
= 1.5 V  
= 300 kHz  
= 5 A  
DD  
V
V
= 3.3 V  
DD  
SD  
V
OUT  
= 1.5 V  
= 300 kHz  
OUT  
f
SW  
f
I
SW  
I
LOAD  
= 5 A  
LOAD  
SS/SD  
COMP  
SW  
VOUT  
PWRGD  
t − Time − 1 ms/div  
t − Time − 200 µs/div  
Figure 24. Start−Up Operation With  
Transient Comparators  
Figure 25. COMP Shutdown Operation  
21  
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TYPICAL CHARACTERISTICS  
V
V
= 3.3 V  
= 1.5 V  
= 300 kHz  
DD  
OUT  
V
V
f
= 3.3 V  
DD  
ILIM  
SW  
= 1.5 V  
OUT  
SYNC  
f
SW  
= 330 kHz  
SS/SD  
PWRGD  
LDRV  
t − Time − 500 ns/div  
t − Time − 1 µs/div  
Figure 26. PWRGD Shutdown Operation  
Figure 27. External Synchronization  
22  
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REFERENCE DESIGN  
This design used the TPS40020 PWM controller to facilitate a step-down application from 3.3-V to 1.5 V. (see  
Figure 29) Design specifications include:  
D Input voltage: 2.5 V V 5.0 V  
IN  
D Nominal output voltage: 3.3 V  
D Output voltage V  
D Output current I  
: 1.5 V  
OUT  
: 20 A  
OUT  
D Switching frequency: 300 kHz  
DESIGN PROCEDURE  
Setting the Frequency  
Choosing the optimum switching frequency is complicated. The higher the frequency, the smaller the  
inductance and capacitance needed, so the smaller the size, but then the the switching losses are higher, the  
efficiency is poorer. For this evaluation module, 300 kHz is chosen for reasonable efficiency and size.  
A resistor R4, which is connected from pin 7 to ground, programs the oscillator frequency. The approximate  
operating frequency is calculated in equation (3)  
3
37.736   10  
(
)
R (kW) +  
* 5.09 kW  
T
(
)
kHz  
f
OSC  
(4)  
Using equation (2), R is calculated to be 120 kand a 118-kresistor is chosen for 300 kHz operation.  
T
Inductance Value  
The inductance value can be calculated by equation (2).  
V
V
OUT  
OUT  
L
+
 
1 *  
ǒ Ǔ  
(min)  
f   I  
V
RIPPLE  
IN(max)  
(5)  
where I  
losses.  
is the ripple current flowing through the inductor, which affects the output voltage ripple and core  
RIPPLE  
Based on 24% ripple current and 300 kHz, the inductance value is calculated to 0.71 µH and a 0.75-µH inductor  
(part number is CDEP149−0R7) is chosen. The DCR of this inductor is 1.1 mand the loss is 440 mW, which  
is approximately 1.5% of output power.  
I
RIPPLE  
C
+
OUT(min)  
8   f   V  
RIPPLE  
(6)  
(7)  
V
RIPPLE  
RIPPLE  
ESR  
+
OUT  
I
With 1.2% output voltage ripple, the needed capacitance is at least 109 µF and its ESR should be less than  
3.75 m. Three 2-V, 470-µF, POSCAP capacitors from Sanyo are used. The ESR is 10 meach.  
The required input capacitance is calculated in equation (5). The calculated value is approximately 390 µF for  
a 100-mV input ripple. Three 6.0-V, 330-µF POSCAP capacitors with 10 mESR are used to handle 10 A of  
RMS input current. Additionally, two ceramic capacitors are used to reduce the switching ripple current.  
1
  V  
C
+ I  
  D  
 
IN(min)  
OUT(max)  
(max)  
f
OSC  
IN(ripple)  
(8)  
23  
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REFERENCE DESIGN  
UDG−03031  
Figure 28. Reference Design Schematic  
24  
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REFERENCE DESIGN  
Input and Output Capacitors  
The output capacitance and its ESR needed are calculated in equations (5) and (6).  
Compensation Design  
Voltage-mode control is used in this evaluation module, using R2, R7, R8, C14, C15, and C16 to form a Type-III  
compensator network. The L-C frequency of the power stage is approximately 4.9-kHz and the ESR-zero is  
around 34 kHz. The overall crossover frequency, f  
, is chosen at 43-kHz for reasonable transient response  
0db  
and stability. Two zeros f and f from the compensator are set at 2.4 kHz and 4 kHz. The two poles, f and  
Z1  
Z2  
P1  
f
are set at 34 kHz and 115 kHz. The frequency of poles and zeros are defined by the following equations:  
P2  
1
f
f
f
f
+
+
+
+
Z1  
Z2  
P1  
P2  
2p   R7   C14  
(9)  
1
(assuming R2 ơ R8)  
2p   R2   C16  
(10)  
(11)  
(12)  
1
2p   R8   C16  
1
(assuming C14 ơ C15)  
2p   R7   C15  
The transfer function for the compensator is calculated in equation (10).  
(
)
[
(
)]  
1 ) s  ǒC14   R7   1 ) s   C16   R2 ) R3  
Ǔ) s   R7   C15   1 ) s   R8   C16  
A(s) +  
C15  
C14  
ƪ 1 )  
ƫ
(
)
s   R2   C14   
(13)  
Figure 30 shows the close loop gain and phase. The overall crossover frequency is approximately 30 kHz. The  
phase margin is 57°.  
OVERALL GAIN AND PHASE  
vs  
OSCILLATOR FREQUENCY  
50  
200  
Gain  
40  
30  
150  
100  
20  
10  
0
50  
0
Phase  
−10  
−20  
−30  
−40  
−50  
−100  
−50  
100  
−150  
100 k  
1 k  
10 k  
f
− Oscillator Frequency − kHz  
OSC  
Figure 29.  
25  
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REFERENCE DESIGN  
MOSFETs and Diodes  
For a 1.5-V output voltage, the lower the R  
of the MOSFET, the higher the efficiency. Due to the high  
DS(on)  
current and high conduction loss, the MOSFET should have very low conduction resistance (R  
) and  
DS(on)  
thermal resistance. Si7858DP is chosen for its low R  
(between 3 mand 4 m) and Power-Pak package.  
DS(on)  
Current Limiting  
Resistor R3 sets the short current limit threshold. The R  
of the upper MOSFET is used as a current sensor.  
DS(on)  
The current limit, I  
is initialized at 30% above the maximum output current, I  
, which is 28 A. Then  
OUT(CL)  
OUT(max)  
R3 can be calculated in equation (11) and yields a value of 1.4 k. An R3 of 1.43 kis selected.  
V
0.69 V  
118 kW  
FB  
+ ǒ19   
Ǔ+ 111.1 mA  
(
)
+ ǒ Ǔ  
I
19   
LIM  
R4  
(14)  
(15)  
K   R  
  I  
DS(on)  
I
OUT(CL)  
1.5   0.004   28 A  
(
)
R3 +  
+
+ 1.4 kW  
I
LIM  
LIM  
where  
D R  
is the on-resistor of Q1 (4 m)  
DS(on)  
D Temperature coefficient, K=1.5  
D V = 0.69 V  
FB  
D R4=118 kΩ  
Voltage Sense Regulator  
R1 and R2 operate as the output voltage divider. The error amplifier reference voltage (V ) is 0.69 V. The  
FB  
relationship between the output voltage and divider is described in equation (8). Using a 10-kresistor for R2  
and 1.5-V output regulation, R1 is calculated as 8.52 kΩ, 8.66 kis selected for R1.  
V
V
OUT  
0.69 V  
R1  
1.5 V  
R1 ) 10 kW  
FB  
+
³
+
³ R1 + 8.52 kW  
R1  
R1 ) R2  
(16)  
Transient Comparator  
The output voltage transient comparators provide a quick response, first strike, approach to output voltage  
transients. The output voltage is sensed through a resistor divider at the OSNS pin, using R5 and R6 shown  
in Figure 28. If an overvoltage condition is detected, the HDRV gate drive is shut off and the LDRV gate drive  
is turned on until the output is returned to regulation. Similarly, if an output undervoltage condition is sensed,  
the HDRV gate drive goes to 95% duty cycle to pump the output back up quickly. The voltage divider should  
be exactly the same as resistors R1 and R2 discussed previously. Resistor R5=8.66 kand R6=10 kin this  
evaluation module.  
26  
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REFERENCE DESIGN  
TEST RESULTS  
Efficiency Curves  
The tested efficiency at different loads and input voltages are shown in Figure 30. The maximum efficiency is  
as high as 93% at 1.5-V output. The efficiency is around 88% when the load current (I  
) is 20 A.  
LOAD  
EFFICIENCY  
vs  
OUTPUT LOAD CURRENT  
0.95  
V
IN  
= 2.5 V  
0.90  
0.85  
V
IN  
= 4.0 V  
0.80  
0.75  
V
IN  
= 5.0 V  
V
IN  
= 3.3 V  
0.70  
0
5
10  
− Load Current − A  
15  
20  
I
LOAD  
Figure 30.  
Typical Operating Waveforms  
Typical operating waveforms are shown in Figure 31 and 32.  
V
I
= 3.3 V  
V
I
= 3.3 V  
IN  
IN  
= 20 A  
= 20 A  
LOAD  
LOAD  
V
(10 mV/div)  
OUTac  
V
SW  
(2 V/div)  
t − Time − 1 µs/div  
t − Time − 1 µs/div  
Figure 32  
Figure 31  
27  
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REFERENCE DESIGN  
Transient Response and Output Ripple Voltage  
The output ripple is about 15 mV  
voltage is about 35 mV.  
at 20-A output. When the load changes from 4 A to 20 A, the overshooting  
P−P  
Figures 33 and 34 show the transient waveform with and without the transient comparator. Using the transient  
comparator yields a settling time of 10-µs faster than without.  
The output ripple is about 15 mV  
at 20-A output which is shown in Figure 33. When the load changes from  
P−P  
0 A to 13 A, the overshoot voltage is approximately 80 mV, and the undershoot is is approximately 60 mV as  
shown in Figure 35. When the transient comparator is triggered, the powergood (PWRGD) signal goes low.  
t − Time − 200 µs/div  
V
IN  
= 3.3 V  
WIthout Transient  
Comparator  
WIth Transient  
Comparator  
WIth Transient  
Comparator  
WIthout Transient  
Comparator  
I
(10 A/div)  
OUT  
I
(10 A/div)  
OUT  
t − Time − 10 µs/div  
t − Time − 10 µs/div  
Figure 33. Transient Response Undershoot  
Figure 34. Transient Response Overshoot  
28  
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REFERENCE DESIGN  
V
PWRGD  
(2.5 V/div)  
V
(100 mV/div)  
OUTac  
I
(10 A/div)  
OUT  
t − Time − 200 µs/div  
Figure 35. Transient Response  
29  
PACKAGE OPTION ADDENDUM  
www.ti.com  
8-Mar-2005  
PACKAGING INFORMATION  
Orderable Device  
TPS40020PWP  
Status (1)  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
Package Package  
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)  
Qty  
Type  
Drawing  
HTSSOP  
PWP  
16  
16  
16  
16  
16  
90 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR  
no Sb/Br)  
TPS40020PWPR  
TPS40021PWP  
HTSSOP  
HTSSOP  
HTSSOP  
PWP  
PWP  
PWP  
PWP  
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR  
no Sb/Br)  
90 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR  
no Sb/Br)  
TPS40021PWPR  
TPS40021PWPRG4  
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR  
no Sb/Br)  
PREVIEW HTSSOP  
2000  
None  
Call TI  
Call TI  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in  
a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2)  
Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional  
product content details.  
None: Not yet available Lead (Pb-Free).  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements  
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered  
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,  
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.  
(3)  
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder  
temperature.  
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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI  
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Addendum-Page 1  
IMPORTANT NOTICE  
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