TPS40050PWPR_技术文档

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SLUS540F − DECEMBER 2002 − REVISED JUNE 2004

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FEATURES

DESCRIPTION

D

Operating Input Voltage 8 V to 40 V

The TPS4005x is a family of high-voltage, wide input

(8 V to 40 V), synchronous, step-down converters.

The TPS4005x family offers design flexibility with a

variety of user programmable functions, including

soft-start, UVLO, operating frequency, voltage feed-

forward, high-side current limit, and loop compensation.

Input Voltage Feed-Forward Compensation

< 1 % Internal 0.7-V Reference

Programmable Fixed-Frequency Up to 1 MHz

Voltage Mode Controller

D

Internal Gate Drive Outputs for High-Side and

Synchronous N-Channel MOSFETs

D

16-Pin PowerPADt Package (θ = 2°C/W)

The TPS4005x are also synchronizable to an external

supply. They incorporate MOSFET gate drivers for

external N-channel high-side and synchronous rectifier

(SR) MOSFETs. Gate drive logic incorporates

anti-cross conduction circuitry to prevent simultaneous

high-side and synchronous rectifier conduction.

JC

Thermal Shutdown

Externally Synchronizable

Programmable High-Side Current Limit

Programmable Closed-Loop Soft-Start

TPS40050 Source Only

The TPS4005x uses voltage feed-forward control

techniques to provide good line regulation over the wide

(4:1) input voltage range, and fast response to input line

transients with near constant gain with input variation

which eases loop compensation.

TPS40051 Source/Sink

TPS40053 Source/Sink With V

Prebias

OUT

APPLICATIONS

D

Power Modules

Networking/Telecom

Industrial

The externally programmable current limit provides

pulse-by-pulse current limit, as well as hiccup mode

operation utilizing an internal fault counter for longer

duration overloads.

Servers

SIMPLIFIED APPLICATION

TPS40050PWP

1

KFF

16

15

ILIM

2

3

4

5

6

7

8

RT

VIN

V

IN

BP5

SYNC

BOOST 14

HDRV 13

12

SGND

SS/SD

VFB

SW

+

BP10 11

LDRV 10

V

OUT

−

COMP

PGND

9

UDG−02130

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments

semiconductor products and disclaimers thereto appears at the end of this data sheet.

PowerPADt is trademark of Texas Instruments.

ꢁꢒ ꢓ ꢊꢎ ꢐ ꢀꢉ ꢓꢍ ꢊ ꢗꢀꢗ ꢘꢙ ꢚꢛ ꢜ ꢝꢞ ꢟꢘꢛꢙ ꢘꢠ ꢡꢢ ꢜ ꢜ ꢣꢙꢟ ꢞꢠ ꢛꢚ ꢤꢢꢥ ꢦꢘꢡ ꢞꢟꢘ ꢛꢙ ꢧꢞ ꢟꢣꢨ ꢁꢜ ꢛꢧꢢ ꢡꢟꢠ

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Copyright  2002, 2004, Texas Instruments Incorporated

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SLUS540F − DECEMBER 2002 − REVISED JUNE 2004

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during

storage or handling to prevent electrostatic damage to the MOS gates.

ORDERING INFORMATION

T

APPLICATION

(2)

PACKAGE

PART NUMBER

TPS40050PWP

TPS40051PWP

TPS40053PWP

A

(1)

SOURCE

SOURCE/SINK

(2)

Plastic HTSSOP (PWP)

(2)

SOURCE/SINK with prebias

−40°C to 85°C

(1)

(2)

The PWP package is also available taped and reeled. Add an R suffix to the device type (i.e., TPS40050PWPR). See the application section of

the data sheet for PowerPAD drawing and layout information.

See Application Information section, pg. 7

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range unless otherwise noted

(3)

TPS40050

TPS40051

TPS40053

UNIT

VIN

45

−0.3 to 6

−0.3 to 45

−2.5

VFB, SS, SYNC

SW

Input voltage range, V

IN

V

SW, transient < 50 ns

KFF, with I

IN(max)

= −5 mA

−0.3 to 11

−0.3 to 6

5

Output voltage range, V

OUT

COMP, RT, SS

Input current, I

IN

KFF

RT

mA

Output current, I

OUT

200

µA

Operating junction temperature range, T

−40 to 125

−55 to 150

260

J

Storage temperature, T

stg

°C

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds

(3)

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only,

and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is

not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

RECOMMENDED OPERATING CONDITIONS

MIN NOM MAX UNIT

Input voltage, V

8

40

85

V

I

Operating free-air temperature, T

−40

°C

A

(4)(5)

PWP PACKAGE

(TOP VIEW)

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

KFF

RT

BP5

SYNC

SGND

SS/SD

VFB

ILIM

VIN

BOOST

HDRV

SW

BP10

LDRV

PGND

THERMAL

PAD

COMP

(4)

(5)

For more information on the PWP package, refer to TI Technical Brief, Literature No. SLMA002.

PowerPADt heat slug must be connected to SGND (pin 5) or electrically isolated from all other pins.

2

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SLUS540F − DECEMBER 2002 − REVISED JUNE 2004

ELECTRICAL CHARACTERISTICS

T

= −40°C to 85°C, V = 24 V , R = 90.9 kΩ, I

KFF

= 150 µA, f = 500 kHz, all parameters at zero power dissipation

SW

A

IN

dc

T

(unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

INPUT SUPPLY

Input voltage range, VIN

OPERATING CURRENT

V

IN

8

40

V

Output drivers not switching,

I

Quiescent current

1.5

5.0

3.0

mA

V

DD

V

FB

≥ 0.75 V

BP5

V

Output voltage

I

≤ 1 mA

4.7

470

2

5.2

BP5

OUT

(2)

OSCILLATOR/RAMP GENERATOR

f

Accuracy

8 V ≤ V ≤ 40 V

IN

500

2.0

570

kHz

V

OSC

(1)

V

PWM ramp voltage

V

−V

RAMP

PEAK VAL

High-level input voltage, SYNC

Low-level input voltage, SYNC

Input current, SYNC

5

0.8

10

IH

V

µA

ns

V

IL

I

5

SYNC

Pulse width, SYNC

50

2.38

85%

80%

V

RT voltage

2.50

2.58

94%

RT

V

FB

V

FB

V

FB

= 0 V,

f

≤ 500 kHz

SW

Maximum duty cycle

= 0 V, 500 kHz ≤ f

≥ 0.75 V

≤ 1 MHz

SW

Minumum duty cycle

0%

3.65

1100

V

Feed-forward voltage

3.35

20

3.48

V

KFF

(1)

I

Feed-forward current operating range

µA

SOFT START

I

Soft-start source current

Soft-start clamp voltage

Discharge time

1.75

2.35

3.7

2.85

µA

SS

V

SS

t

C

= 220 pF

1.6

2.2

2.8

DSCH

SS

µs

Soft-start time

= 220 pF, 0 V ≤ V

≤ 1.6 V

115

155

205

SS

BP10

V

BP10

Ouput voltage

I

≤ 1 mA

9.0

9.6

10.3

V

OUT

ERROR AMPLIFIER

8 V ≤ V ≤ 40 V,

T

= 25°C

0.698 0.700

0.690 0.700

0.704

0.707

0.715

IN

A

8 V ≤ V ≤ 40 V,

0°C ≤ T ≤ 85°C

A

V

FB

Feedback input voltage

V

IN

8 V ≤ V ≤ 40 V,

IN

−40°C ≤ T ≤ 85°C

A

G

Gain bandwidth

3.0

60

5.0

80

MHz

dB

BW

A

VOL

Open loop gain

I

High-level output source current

Low-level output sink current

High-level output voltage

Low-level output voltage

Input bias current

2.0

2.5

3.2

4.0

OH

mA

4.0

OL

V

I

= 500 µA

3.5

OH

OL

SOURCE

= 500 µA

V

0.20

100

0.35

200

SINK

= 0.7 V

I

V

nA

BIAS

FB

(1) Ensured by design. Not production tested.

(2) increases with SYNC frequency, I

I

decreases with maximum duty cycle

KFF

3

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SLUS540F − DECEMBER 2002 − REVISED JUNE 2004

ELECTRICAL CHARACTERISTICS

T

= −40°C to 85°C, V = 24 V , R = 90.9 kΩ, I

KFF

= 150 µA, f = 500 kHz, all parameters at zero power dissipation

SW

A

IN

dc

T

(unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

CURRENT LIMIT

I

Current limit sink current

8.6

10.0

300

200

11.5

µA

SINK

V

= 23.7 V,

V

= (V

− 0.5 V)

− 2 V)

ILIM

SW

ILIM

Propagation delay to output

ns

ILIM

SW

ILIM

(1)

t

Switch leading-edge blanking pulse time

100

ON

Off time during a fault

7

cycles

OFF

V

= 23.6 V,

T

= 25°C

−125

−140

−30

−15

10

ILIM

A

0°C ≤ T ≤ 85°C

−75

V

Offset voltage SW vs. ILIM

mV

ns

A

OS

−40°C ≤ T ≤ 85°C

A

OUTPUT DRIVER

t

Low-side driver rise time

Low-side driver fall time

High-side driver rise time

High-side driver fall time

48

24

48

36

96

48

96

72

LRISE

LFALL

HRISE

HFALL

C

= 2200 pF

LOAD

= 2200 pF, (HDRV − SW)

LOAD

BOOST BOOST

−1.5 V −1.0 V

V

OH

V

OL

V

OH

V

OL

High-level ouput voltage, HDRV

Low-level ouput voltage, HDRV

High-level ouput voltage, LDRV

I

−0.1 A (HDRV − SW)

0.1 A (HDRV − SW)

−0.1 A

HDRV =

LDRV =

0.75

V

BP10 BP10

−1.4 V − 1.0 V

Low-level ouput voltage, LDRV

Minimum controllable pulse width

0.1 A

0.5

100

150

ns

SS/SD SHUTDOWN

V

Shutdown threshold voltage

Outputs off

90

125

210

150

245

SD

EN

mV

V

Device active threshold voltage

190

BOOST REGULATOR

Output voltage

V

= 24.0 V

31.5

−5.5

32.5

−0.5

33.5

4.5

25

V

BOOST

RECTIFIER ZERO CURRENT COMPARATOR (TPS40050/TPS40053 SS ONLY)

Switch voltage LDRV output OFF

SW NODE

Leakage current

THERMAL SHUTDOWN

Shutdown temperature

(1)

IN

V

SW

mV

µA

(1)

I

LEAK

(1)

165

20

T

SD

°C

Hysteresis

UVLO

V

KFF programmable threshold voltage

R

= 28.7 kΩ

6.9

7.5

7.9

V

UVLO

KFF

decreases with maximum duty cycle

KFF

(1) Ensured by design. Not production tested.

(2) increases with SYNC frequency, I

I

KFF

4

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SLUS540F − DECEMBER 2002 − REVISED JUNE 2004

TERMINAL FUNCTIONS

TERMINAL

I/O

DESCRIPTION

NAME

NO.

Gate drive voltage for the high side N-channel MOSFET. The BOOST voltage is 9 V greater than the input voltage.

A 0.1-µF ceramic capacitor should be connected from this pin to the drain of the lower MOSFET.

BOOST

14

O

5-V reference. This pin should be bypassed to ground with a 0.1-µF ceramic capacitor. This pin may be used with

BP5

3

O

an external DC load of 1 mA or less.

10-V reference used for gate drive of the N-channel synchronous rectifier. This pin should be bypassed by a 1-µF

BP10

11

ceramic capacitor. This pin may be used with an external DC load of 1 mA or less.

Output of the error amplifier, input to the PWM comparator. A feedback network is connected from this pin to the

VFB pin to compensate the overall loop. The comp pin is internally clamped above the peak of the ramp to improve

large signal transient response.

COMP

HDRV

ILIM

8

O

I

Floating gate drive for the high-side N-channel MOSFET. This pin switches from BOOST (MOSFET on) to SW

(MOSFET off).

13

16

Current limit pin, used to set the overcurrent threshold. An internal current sink from this pin to ground sets a voltage

drop across an external resistor connected from this pin to VCC. The voltage on this pin is compared to the voltage

drop (VIN −SW) across the high side MOSFET during conduction.

A resistor is connected from this pin to VIN to program the amount of voltage feed-forward. The current fed into

this pin is internally divided and used to control the slope of the PWM ramp.

KFF

1

10

9

I

Gate drive for the N-channel synchronous rectifier. This pin switches from BP10 (MOSFET on) to ground

(MOSFET off).

LDRV

PGND

O

−

Power ground reference for the device. There should be a low-impedance path from this pin to the source(s) of

the lower MOSFET(s).

RT

2

5

I

A resistor is connected from this pin to ground to set the internal oscillator and switching frequency.

Signal ground reference for the device.

SGND

−

Soft-start programming pin. A capacitor connected from this pin to ground programs the soft-start time. The

capacitor is charged with an internal current source of 2.3 µA. The resulting voltage ramp on the SS pin is used

as a second non-inverting input to the error amplifier. The output voltage begins to rise when V

is

SS/SD

6

I

approximately0.85 V. The output continues to rise and reaches regulation when V

SS/SD

is approximately 1.55 V.

The controller is considered shut down when V

is 125 mV or less. All internal circuitry is inactive. The internal

is 210 mV or greater. When V is less than approximately 0.85 V, the outputs

SS/SD

circuitry is enabled when V

SS/SD

cease switching and the output voltage (V ) decays while the internal circuitry remains active.

OUT

This pin is connected to the switched node of the converter and used for overcurrent sensing. The TPS40050 and

TPS40053 versions use this pin for zero current sensing as well.

SW

12

4

I

Syncronization input for the device. This pin can be used to synchronize the oscillator to an external master

frequency. If synchronization is not used, connect this pin to SGND.

SYNC

Inverting input to the error amplifier. In normal operation the voltage on this pin is equal to the internal reference

voltage, 0.7 V.

VFB

VIN

7

I

15

Supply voltage for the device.

5

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SLUS540F − DECEMBER 2002 − REVISED JUNE 2004

SIMPLIFIED BLOCK DIAGRAM

ILIM

16

10V Regulator

BP10

15

2

11

14

VIN

RT

−

+

CLK

CLK Oscillator

BOOST

1V5REF

7

CLK

7

SYNC

4

07VREF

1V5REF

3V5REF

BP5

CL

7

Ramp Generator

7

Reference

Voltages

3−bit up/down

Fault Counter

N−channel

Driver

13

12

HDRV

SW

1

KFF

BP5

Restart Fault

BP5

3

7

BP10

7

Fault

7

S

R

Q

CL

07VREF

7

+

VFB

7

6

10

n−channel

Driver

LDRV

PGND

Soft Start

0V7REF

+

SS/SD

07VREF

7

SW

CLK

t

7

start

7

S

R

Q

9

Restart

Q

8

COMP

Zero Current Detector

(TPS40050 Only)

5

UDG−02128

SGND

6

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SLUS540F − DECEMBER 2002 − REVISED JUNE 2004

APPLICATION INFORMATION

The TPS40050/51/53 family of parts allows the user to optimize the PWM controller to the specific application.

The TPS40051 will be the controller of choice for synchronous buck designs which will include most

applications. It has two quadrant operation and will source or sink output current. This provides the best

transient response.

The TPS40050 operates in one quadrant and sources output current only, allowing for paralleling of converters

and ensures that one converter does not sink current from another converter. This controller also emulates a

standard buck converter at light loads where the inductor current goes discontinuous. At continuous output

inductor currents the controller operates as a synchronous buck converter to optimize efficiency.

The TPS40053 operates in one quadrant as a standard buck converter during start up. After the output has

reached the regulation point, the controller operates in two quadrant mode and is put in a synchronous buck

configuration. This is useful for applications that have the output voltage ’pre-biased’ at some voltage before

the controller is enabled. When the TPS40053 controller is enabled it does not sink current during start up which

would pull current from the pre-biased voltage supply.

SW NODE RESISTOR AND DIODE

The SW node of the converter is negative during the dead time when both the upper and lower MOSFETs are

OFF. The magnitude of this negative voltage is dependent on the lower MOSFET body diode and the output

current which flows during this dead time. This negative voltage could affect the operation of the controller,

especially at low input voltages.

Therefore, a resistor (between 3.3 Ω and 4.7 Ω ) and Schottky diode must be placed between the lower

MOSFET drain and pin 12, SW, of the controller as shown in Figure 15. The Schottky diode must have a voltage

rating to accommodate the input voltage and ringing on the SW node of the converter. A 30-V Schottky such

as a BAT54 or a 40-V Schottky such as a Zetex ZHCS400 or Vishay SD103AWS are adequate. These

components are shown in Figure 15 as R

and D2.

SW

SETTING THE SWITCHING FREQUENCY (PROGRAMMING THE CLOCK OSCILLATOR)

The TPS4005x has independent clock oscillator and ramp generator circuits. The clock oscillator serves as the

master clock to the ramp generator circuit. The switching frequency, f

in kHz, of the clock oscillator is set

SW

by a single resistor (R ) to ground. The clock frequency is related to R , in kΩ by equation (1) and the relationship

T

is charted in Figure 2.

1

_{R +}ǒ

_* 23Ǔ_kW

T

*6

f

17.82 10

SW

(1)

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SLUS540F − DECEMBER 2002 − REVISED JUNE 2004

APPLICATION INFORMATION

PROGRAMMING THE RAMP GENERATOR CIRCUIT

The ramp generator circuit provides the actual ramp used by the PWM comparator. The ramp generator

provides voltage feed-forward control by varying the PWM ramp slope with line voltage, while maintaining a

constant ramp magnitude. Varying the PWM ramp directly with line voltage provides excellent response to line

variations since the PWM does not have to wait for loop delays before changing the duty cycle. (See Figure 1).

VIN

SW

RAMP

V

PEAK

COMP

RAMP

COMP

V

VALLEY

T

1

T

2

t

ON2

> t

t

ON1

d +

t_ON

T

t

and d > d

1 2

ON1 ON2

UDG−02131

Figure 1. Voltage Feed-Forward Effect on PWM Duty Cycle

The PWM ramp must be faster than the master clock frequency or the PWM is prevented from starting. The

PWM ramp time is programmed via a single resistor (R

) pulled up to VIN. R

is related to R , and the

KFF

KFF T

minimum input voltage, V

through the following:

IN(min)

_* 3.5ǒ_{58.14 R ) 1340 W}

Ǔ

₊ǒ_V

Ǔ

R

KFF

IN (min)

T

(2)

where:

D V

is the ensured minimum start-up voltage. The actual start-up voltage is nominally about 10% lower

IN(min)

at 25°C.

D R is the timing resistance in kΩ

T

The curve showing the R

required for a given switching frequency, f , is shown in Figure 3.

SW

KFF

For low input voltage and high duty cycle applications, the voltage feed-forward may limit the duty cycle

prematurely. This does not occur for most applications. The voltage control loop controls the duty cycle and

regulates the output voltage. For more information on large duty cycle operation, refer to Application Note

(SLUA310).

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SLUS540F − DECEMBER 2002 − REVISED JUNE 2004

FEED-FORWARD IMPEDANCE

vs

SWITCHING FREQUENCY

vs

TIMING RESISTANCE

700

600

500

400

300

200

500

400

300

V

IN

= 9 V

V

= 15 V

IN

V

IN

= 25 V

200

100

0

100

0

100 200 300 400 500 600 700 800 900 1000

0

200

400

600

800

1000

f

− Switching Frequency − kHz

SW

f

− Switching Frequency − kHz

SW

Figure 2

Figure 3

UVLO OPERATION

The TPS4005x uses variable (user programmable) UVLO protection. The UVLO circuit holds the soft-start low

until the input voltage has exceeded the user programmable undervoltage threshold.

The TPS4005x uses the feed-forward pin, KFF, as a user programmable low-line UVLO detection. This variable

low-line UVLO threshold compares the PWM ramp duration to the oscillator clock period. An undervoltage

condition exists if the TPS4005x receives a clock pulse before the ramp has reached 90% of its full amplitude.

The ramp duration is a function of the ramp slope, which is directly related to the current into the KFF pin. The

KFF current is a function of the input voltage and the resistance from KFF to the input voltage. The KFF resistor

can be referenced to the oscillator frequency as descibed in equation (3):

_* 3.5ǒ_{58.14 R ) 1340}

Ǔ

₊ǒ_V

Ǔ

R

W

KFF

IN (min)

T

(3)

where:.

D V is the desired start-up (UVLO) input voltage

IN

D R is the timing resistance in kΩ

T

The variable UVLO function uses a three−bit full adder to prevent spurious shut-downs or turn-ons due to spikes

or fast line transients. When the adder reaches a total of seven counts in which the ramp duration is shorter

than the clock cycle a powergood signal is asserted and a soft-start initiated, and the upper and lower

MOSFETS are turned off.

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APPLICATION INFORMATION

Once the soft-start is initiated, the UVLO cicruit must see a total count of seven cycles in which the ramp duration

is longer than the clock cycle before an undervoltage condition is declared. (See Figure 4).

UVLO Threshold

VIN

Clock

PWM RAMP

1

2

3

4

5

6

7

1

2

1 2 3 4 5 6 7

PowerGood

UDG−02132

Figure 4. Undervoltage Lockout Operation

Some applications may require an additional circuit to prevent false restarts at the UVLO voltage level. This

applies to applications which have high impedance on the input voltage line or which have excessive ringing

on the V line. The input voltage impedance can cause the input voltage to sag enough at start-up to cause

IN

a UVLO shutdown and subsequent restart. Excessive ringing can also affect the voltage seen by the device

and cause a UVLO shutdown and restart. A simple external circuit provides a selectable amount of hysteresis

to prevent the nuisance UVLO shutdown.

Assuming a hysteresis current of 10% I

, and the peak detector charges to 8 V and V

= 18 V, the value

KFF

IN(min)

of R is calculated by:

A

(

)

R

8 * 3.5

KFF

R +

+ 565 kW ^ 562 kW

A

_0.1ǒ_V

Ǔ

* 3.5

IN(min)

(4)

C

is chosen to maintain the peak voltage between switching cycles. To keep the capacitor charge from

A

drooping 0.1-V, or from 8 V to 7.9 V.

(

)

8 * 3.5

C +

A

ǒ

_SWǓ

R 7.9 f

A

(5)

The value of C imay calculate to less than 10 pF, but some standard value up to 470 pF works adequately.

A

The diode can be a small signal switching diode or Schottky rated for more then 20 V. Figure 5 illustrates a typical

implementation using a small switching diode.

The tolerance on the UVLO set point also affects the maximum duty cycle achievable. If the UVLO starts the

device at 10% below the nominal start up voltage, the maximum duty cycle is reduced approximately 10% at

the nominal start up voltage.

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SLUS540F − DECEMBER 2002 − REVISED JUNE 2004

APPLICATION INFORMATION

+

VIN

−

R

TPS40050PWP

TPS40051PWP

KFF

182 kW

R

A

562 kW

1

2

3

4

5

6

7

8

KFF

ILIM 16

VIN 15

C

A

470 pF

RT

BP5

BOOST 14

HDRV 13

SW 12

SYNC

SGND

SS

BP10 11

LDRV 10

PGND 9

VFB

COMP

D

A

1N914, 1N4150

Type Signal Diode

PWP

UDG−03034

Figure 5. Hysteresis for Programmable UVLO

BP5 AND BP10 INTERNAL VOLTAGE REGULATORS

Start-up characteristics of the BP5 and BP10 regulators over different temperature ranges are shown in

Figures 6 and 7. Slight variations in the BP5 occurs dependent upon the switching frequency. Variation in the

BP10 regulation characteristics is also based on the load presented by switching the external MOSFETs.

INPUT VOLTAGE

vs

BP5 VOLTAGE

BP10 VOLTAGE

6

10

5

4

8

6

110°C

25°C

−55°C

3

2

4

2

−55°C

25°C

1

0

2

4

6

8

10

12

2

4

6

8

10

12

V − Input Voltage − V

IN

V − Input Voltage − V

IN

Figure 6.

Figure 7.

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APPLICATION INFORMATION

SELECTING THE INDUCTOR VALUE

The inductor value determines the magnitude of ripple current in the output capacitors as well as the load current

at which the converter enters discontinuous mode. Too large an inductance results in lower ripple current but

is physically larger for the same load current. Too small an inductance results in larger ripple currents and a

greater number of (or more expensive output capacitors for) the same output ripple voltage requirement. A good

compromise is to select the inductance value such that the converter doesn’t enter discontinuous mode until

the load approximated somewhere between 10% and 30% of the rated output. The inductance value is

described in equation (6).

ǒ_V

V

Ǔ

* V V

IN

O

L +

(Henries)

DI f

SW

(6)

where:.

D V is the output voltage

O

D

∆I is the peak-to-peak inductor current

CALCULATING THE OUTPUT CAPACITANCE

The output capacitance depends on the output ripple voltage requirement, output ripple current, as well as any

output voltage deviation requirement during a load transient.

The output ripple voltage is a function of both the output capacitance and capacitor ESR. The worst case output

ripple is described in equation (7).

1

DV + DI ESR )

ǒ

Ǔ

V

P*P

ƪ

ƫ

8 C f

O

SW

(7)

The output ripple voltage is typically between 90% and 95% due to the ESR component.

The output capacitance requirement typically increases in the presence of a load transient requirement. During

a step load, the output capacitance must provide energy to the load (light to heavy load step) or absorb excess

inductor energy (heavy to light load step) while maintaining the output voltage within acceptable limits. The

amount of capacitance depends on the magnitude of the load step, the speed of the loop and the size of the

inductor.

Stepping the load from a heavy load to a light load results in an output overshoot. Excess energy stored in the

inductor must be absorbed by the output capacitance. The energy stored in the inductor is described in

equation (8).

1

2

E + L I (Joules)

L

(8)

where:

_OHǓ²ǒ Ǔ²

2

ǒ

ǒ₍

₎Ǔ

_{I +}ƪ_I

ƫ

* I

Amperes

OL

(9)

where:

D I

is the output current under heavy load conditions

OH

D I is the output current under light load conditions

OL

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APPLICATION INFORMATION

Energy in the capacitor is described in equation (10).

1

2

E

+

C V (Joules)

C

(10)

(11)

where:

ǒ Ǔ²ǒ Ǔ²ǒ_Volts

2

Ǔ

_{V +}ƪ_V

ƫ

* V

f

i

where:

D V is the final peak capacitor voltage

f

D V is the initial capacitor voltage

i

Substituting equation (9) into equation (8), then substituting equation (11) into equation (10), then setting

equation (10) equal to equation (8), and then solving for C yields the capacitance described in equation (12).

O

ǒ

_OHǓ²ǒ Ǔ²

ƪ_I

ƫ

(Farads)

L

* I

OL

C

+

O

ǒ Ǔ²ǒ Ǔ²

ƪ_V

ƫ

* V

f

i

(12)

PROGRAMMING SOFT START

TPS4005x uses a closed-loop approach to ensure a controlled ramp on the output during start-up. Soft-start

is programmed by charging an external capacitor (C ) via an internally generated current source. The voltage

SS

on C is fed into a separate non-inverting input to the error amplifier (in addition to FB and 0.7-V VREF). The

SS

loop is closed on the lower of the C voltage or the internal reference voltage ( 0.7-V VREF). Once the C

SS

voltage rises above the internal reference voltage, regulation is based on the internal reference. To ensure a

controlled ramp-up of the output voltage the soft-start time should be greater than the L-C time constant as

O

described in equation (13).

_w 2pǸ_{L C}

t

(seconds)

START

O

(13)

There is a direct correlation between t

and the input current required during start-up. The faster t

,

START

the higher the input current required during start-up. This relationship is describe in more detail in the section

titled, Programming the Current Limit which follows. The soft-start capacitance, C , is described in

SS

equation (14).

For applications in which the V supply ramps up slowly, (typically between 50 ms and 100 ms) it may be

IN

necessary to increase the soft-start time to between approximately 2 ms and 5 ms to prevent nuisance UVLO

tripping. The soft-start time should be longer than the time that the V supply transitions between 6 V and 7 V.

IN

2.3 mA

0.7 V

C

+

t

(Farads)

START

SS

(14)

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APPLICATION INFORMATION

PROGRAMMING CURRENT LIMIT

The TPS4005x uses a two-tier approach for overcurrent protection. The first tier is a pulse-by-pulse protection

scheme. Current limit is implemented on the high-side MOSFET by sensing the voltage drop across the

MOSFET when the gate is driven high. The MOSFET voltage is compared to the voltage dropped across a

resistor connected from VIN pin to the ILIM pin when driven by a constant current sink. If the voltage drop across

the MOSFET exceeds the voltage drop across the ILIM resistor, the switching pulse is immediately terminated.

The MOSFET remains off until the next switching cycle is initiated.

The second tier consists of a fault counter. The fault counter is incremented on an overcurrent pulse and

decremented on a clock cycle without an overcurrent pulse. When the counter reaches seven (7) a restart is

issued and seven soft-start cycles are initiated. Both the upper and lower MOSFETs are turned off during this

period. The counter is decremented on each soft-start cycle. When the counter is decremented to zero, the

PWM is re-enabled. If the fault has been removed the output starts up normally. If the output is still present the

counter counts seven overcurrent pulses and re-enters the second-tier fault mode. See Figure 6 for typical

overcurrent protection waveforms.

The minimum current limit setpoint (I ) depends on t

, C , V , and the load current at turn-on (I ).

LIM

START

O

L

ǒ_C

t

_OǓ

V

O

I

+

) I (Amperes)

L

ƪ ƫ

LIM

START

(15)

The current limit programming resistor (R

) is calculated using equation (16).

ILIM

I

R

DS(on)[max]

V

OC

OS

R

+

)

(W)

ILIM

1.12 I

I

SINK

(16)

where:

D I

is the current into the ILIM pin and is nominally 10 µA,

SINK

is the overcurrent setpoint which is the DC output current plus one-half of the peak inductor current

is the overcurrent comparator offset and is nominally −75 mV

OC

D V

OS

HDRV

CLOCK

t

BLANKING

V

ILIM

−V

VIN SW

SS

7 CURRENT LIMIT TRIPS

(HDRV CYCLE TERMINATED BY CURRENT LIMIT TRIP)

UDG−02136

7 SOFT-START CYCLES

Figure 8. Typical Current Limit Protection Waveforms

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APPLICATION INFORMATION

SYNCHRONIZING TO AN EXTERNAL SUPPLY

The TPS4005x can be synchronized to an external clock through the SYNC pin. Synchronization occurs on the

falling edge of the SYNC signal. The synchronization frequency should be in the range of 20% to 30% higher

than its programmed free-run frequency. The clock frequency at the SYNC pin replaces the master clock

generated by the oscillator circuit. Pulling the SYNC pin low programs the TPS4005x to freely run at the

frequency programmed by R .

T

The higher synchronization must be factored in when programming the PWM ramp generator circuit. If the PWM

ramp is interrupted by the SYNC pulse, a UVLO condition is declared and the PWM becomes disabled. Typically

this is of concern under low-line conditions only. In any case, R

frequency.

needs to be adjusted for the higher switching

KFF

In order to specify the correct value for RKFF at the synchronizing frequency, calculate a ’dummy’ value for RT

that would cause the oscillator to run at the synchronizing frequency. Do not use this value of RT in the design.

1

₊ǒ

_* 23Ǔ_kW

R

T(dummy)

*6

f

17.82 10

SYNC

(17)

Use the value of R

to calculate the value for R

.

T(dummy)

KFF

₊ǒ_V

_{* 3.5 V}Ǔǒ_{58.14 R}

_) 1340Ǔ _W

R

KFF

IN(min)

T(dummy)

(18)

This value of R

ensures that UVLO is not engaged when operating at the synchronization frequency.

KFF

D R

is in kΩ

T(dummy)

LOOP COMPENSATION

Voltage-mode buck-type converters are typically compensated using Type III networks. Since the TPS4005x

uses voltage feedforward control, the gain of the PWM modulator with voltage feedforward circuit must be

included. The modulator gain is described in Figure 9, with V being the minimum input voltage required to

IN

cause the ramp excursion to cover the entire switching period as described in equation (19).

V

IN

V

S

IN

_{+ 20 log}ǒ Ǔ

A

+

or

A

MOD(dB)

MOD

V

S

(19)

Duty dycle, D, varies from 0 to 1 as the control voltage, V , varies from the minimum ramp voltage to the

C

maximum ramp voltage, V . Also, for a synchronous buck converter, D = V / V . To get the control voltage

S

O

IN

to output voltage modulator gain in terms of the input voltage and ramp voltage,

V

O

C

S

O

C

IN

D +

+

or

+

V

IN

S

(20)

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APPLICATION INFORMATION

Calculate the Poles and Zeros

For a buck converter using voltage mode control there is a double pole due to the output L-C . The double pole

O

is located at the frequency calculated in equation (21).

1

f

+

(Hertz)

LC

_2pǸ_{L C}

O

(21)

There is also a zero created by the output capacitance, C , and its associated ESR. The ESR zero is located

O

at the frequency calculated in equation (22).

1

f +

(Hertz)

Z

2p ESR C

O

(22)

Calculate the value of R

to set the output voltage, V

.

OUT

BIAS

0.7 R1

R

+

W

BIAS

V

* 0.7

OUT

(23)

(24)

The maximum crossover frequency (0 dB loop gain) is calculated in equation (24).

f

SW

f

+

(Hertz)

C

4

Typically, f is selected to be close to the midpoint between the L-C double pole and the ESR zero. At this

C

O

frequency, the control to output gain has a –2 slope (−40 dB/decade), while the Type III topology has a +1 slope

(20 dB/decade), resulting in an overall closed loop –1 slope (−20 dB/decade).

Figure 10 shows the modulator gain, L-C filter, output capacitor ESR zero, and the resulting response to be

compensated.

MODULATOR GAIN

PWM MODULATOR RELATIONSHIPS

vs

SWITCHING FREQUENCY

ESR Zero, + 1

A

= V / V

MOD IN

S

V

S

Resultant, − 1

V

C

D = V / V

C

S

LC Filter, − 2

100

1 k

10 k

100 k

f

− Switching Frequency − Hz

SW

Figure 9

Figure 10

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APPLICATION INFORMATION

A Type III topology, shown in Figure 11, has two zero-pole pairs in addition to a pole at the origin. The gain and

phase boost of a Type III topology is shown in Figure 12. The two zeros are used to compensate the L-C double

O

pole and provide phase boost. The double pole is used to compensate for the ESR zero and provide controlled

gain roll-off. In many cases the second pole can be eliminated and the amplifier’s gain roll-off used to roll-off

the overall gain at higher frequencies.

C2

(optional)

− 1

C1

R2

R3

+ 1

0 dB

− 1

C3

VFB

R1

GAIN

−90°

7

8

COMP

VOUT

+

180°

R

BIAS

PHASE

−270°

VREF

UDG−02189

Figure 11. Type III Compensation Configuration

Figure 12. Type III Compensation Gain and

Phase

The poles and zeros for a Type III network are described in equations (25).

1

f

+

(Hertz)

f

+

(Hertz)

Z1

P1

Z2

P2

2p R2 C1

2p R1 C3

(25)

1

f

2p R2 C2

2p R3 C3

The value of R1 is somewhat arbitraty, but influences other component values. A value between 50kΩ and

100kΩ usually yields reasonable values.

The unity gain frequency is described in equation (26)

1

f

+

(Hertz)

C

2p R1 C2 G

(26)

(27)

where G is the reciprocal of the modulator gain at f .

C

The modulator gain as a function of frequency at f , is described in equation (27).

C

2

f

LC

1

ǒ Ǔ

AMOD(f) + AMOD

and G +

f

AMOD(f)

C

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APPLICATION INFORMATION

Minimum Load Resistance

Care must be taken not to load down the output of the error amplifier with the feedback resistor, R2, that is too

small. The error amplifier has a finite output source and sink current which must be considered when sizing R2.

Too small a value does not allow the output to swing over its full range.

V

C (max)

3.5 V

2 mA

R2

+

+ 1750 W

(MIN)

I

SOURCE (min)

(28)

CALCULATING THE BOOST AN BP10 BYPASS CAPACITOR

The BOOST capacitance provides a local, low impedance source for the high-side driver. The BOOST capacitor

should be a good quality, high-frequency capacitor. The size of the bypass capacitor depends on the total gate

charge of the MOSFET and the amount of droop allowed on the bypass capacitor. The BOOST capacitance

is described in equation (29).

Q

g

C

+

(Farads)

BOOST

(29)

DV

The 10-V reference pin, BP10V provides energy for both the synchronous MOSFET and the high-side

MOSFET via the BOOST capacitor. Neglecting any efficiency penalty, the BP10V capacitance is described in

equation (30).

ǒ_Q

_gSRǓ

) Q

DV

gHS

C

+

(Farads)

BP10

(30)

dv/dt INDUCED TURN-ON

MOSFETs are susceptible to dv/dt turn-on particularly in high-voltage (V ) applications. The turn-on is caused

DS

by the capacitor divider that is formed by C

and C . High dv/dt conditions and drain-to-source voltage, on

GD

GS

the MOSFET causes current flow through C

and causes the gate-to-source voltage to rise. If the

GD

gate-to-source voltage rises above the MOSFET threshold voltage, the MOSFET turns on, resulting in large

shoot-through currents. Therefore, the SR MOSFET should be chosen so that the C capacitance is smaller

GD

than the C

capacitance.

GS

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APPLICATION INFORMATION

HIGH SIDE MOSFET POWER DISSIPATION

The power dissipated in the external high-side MOSFET is comprised of conduction and switching losses. The

conduction losses are a function of the I

high-side MOSFET conduction losses are defined by equation (31).

current through the MOSFET and the R

of the MOSFET. The

RMS

DS(on)

₊ǒ_I_RMSǓ²

O

_{1 ) TC}ƪ_{T * 25 C}

ƫ

ǒ

Ǔ

P

R

(Watts)

COND

DS(on)

R

J

(31)

where:

D TC is the temperature coefficient of the MOSFET R

R

DS(on)

The TC varies depending on MOSFET technology and manufacturer, but typically ranges between

R

.0035 ppm/_C and .010 ppm/_C.

The I

current for the high side MOSFET is described in equation (32).

RMS

Ǹ

ǒ_A_RMSǓ

I

+ I

d

RMS

OUT

(32)

(33)

The switching losses for the high-side MOSFET are descibed in equation (33).

₊ǒ_V

Ǔ

f

P

I

t

(Watts)

SW

SW(fsw)

IN

OUT

SW

where:

D I is the DC output current

O

D t

D f

is the switching rise time, typically < 20 ns

is the switching frequency

SW

Typical switching waveforms are shown in Figure 13.

I

D2

I

O

∆I

}

I

D1

d

1−d

BODY DIODE

CONDUCTION

BODY DIODE

CONDUCTION

SW

0

ANTI−CROSS

CONDUCTION

SYNCHRONOUS

RECTIFIER ON

HIGH SIDE ON

UDG−02139

Figure 13. Inductor Current and SW Node Waveforms

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APPLICATION INFORMATION

The maximum allowable power dissipation in the MOSFET is determined by equation (34).

ǒ_{T * T}_AǓ

J

P +

(Watts)

T

q

JA

(34)

where:

P + P

) P

(Watts)

T

COND

SW(fsw)

(35)

and θ is the package thermal impedance.

JA

SYNCHRONOUS RECTIFIER MOSFET POWER DISSIPATION

The power dissipated in the synchronous rectifier MOSFET is comprised of three components: R

DS(on)

conduction losses, body diode conduction losses, and reverse recovery losses. R

) conduction losses can

DS(on

be found using equation (29) and the RMS current through the synchronous rectifier MOSFET is described in

equation (36).

Ǹ

ǒ_Amperes_RMSǓ

I

+ I 1 * d

RMS

O

(36)

The body-diode conduction losses are due to forward conduction of the body diode during the anti−cross

conduction delay time. The body diode conduction losses are described by equation (37).

P

+ 2 I V t

f

(Watts)

SW

(37)

DC

O

F

DELAY

where:

D V is the body diode forward voltage

F

D t

is the delay time just before the SW node rises

DELAY

The 2-multiplier is used because the body diode conducts twice during each cycle (once on the rising edge and

once on the falling edge). The reverse recovery losses are due to the time it takes for the body diode to recovery

from a forward bias to a reverse blocking state. The reverse recovery losses are described in equation (38).

P

+ 0.5 Q V f

(Watts)

SW

(38)

RR

IN

where:

D Q

is the reverse recovery charge of the body diode

RR

The Q

is not always described in a MOSFET’s data sheet, but may be obtained from the MOSFET vendor.

RR

The total synchronous rectifier MOSFET power dissipation is described in equation (39).

P

+ P ) P ) P (Watts)

(39)

SR

DC

RR

COND

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APPLICATION INFORMATION

TPS4005X POWER DISSIPATION

The power dissipation in the TPS4005x is largely dependent on the MOSFET driver currents and the input

voltage. The driver current is proportional to the total gate charge, Qg, of the external MOSFETs. Driver power

(neglecting external gate resistance, refer to [2] can be calculated from equation (40).

P

+ Q V f

(Wattsńdriver)

SW

g

(40)

D

DR

And the total power dissipation in the TPS4005x, assuming the same MOSFET is selected for both the high-side

and synchronous rectifier is described in equation (41).

2 P

D

_{P +}ǒ Ǔ

) I

V

(Watts)

IN

T

Q

V

DR

(41)

(42)

or

_{P +}ǒ_{2 Q f}

Ǔ

) I V (Watts)

g

T

SW

Q

IN

where:

D I is the quiescent operating current (neglecting drivers)

Q

The maximum power capability of the device’s PowerPad package is dependent on the layout as well as air

flow. The thermal impedance from junction to air, assuming 2 oz. copper trace and thermal pad with solder and

no air flow.

O

q

+ 36.515 CńW

(43)

JA

The maximum allowable package power dissipation is related to ambient temperature by equation (44).

T * T

J

A

P +

(Watts)

T

q

JA

(44)

Substituting equation (37) into equation (35) and solving for f

the TPS4005x. The result is described in equation (45).

yields the maximum operating frequency for

SW

ǒ

_AǓ

_DDǓ

V

T *T

J

ƪ ƫ* I

ǒ Ǔ

Q

ǒ

q

JA

f

+

(Hz)

SW

ǒ_{2 Q}_gǓ

(45)

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LAYOUT CONSIDERATIONS

THE POWERPADt PACKAGE

The PowerPAD package provides low thermal impedance for heat removal from the device. The PowerPAD

derives its name and low thermal impedance from the large bonding pad on the bottom of the device. For

maximum thermal performance, the circuit board must have an area of solder-tinned-copper underneath the

package. The dimensions of this area depends on the size of the PowerPAD package. For a 16-pin TSSOP

(PWP) package the area is 5 mm x 3.4 mm [3].

Thermal vias connect this area to internal or external copper planes and should have a drill diameter sufficiently

small so that the via hole is effectively plugged when the barrel of the via is plated with copper. This plug is

needed to prevent wicking the solder away from the interface between the package body and the solder-tinned

area under the device during solder reflow. Drill diameters of 0.33 mm (13 mils) works well when 1-oz copper

is plated at the surface of the board while simultaneously plating the barrel of the via. If the thermal vias are

not plugged when the copper plating is performed, then a solder mask material should be used to cap the vias

with a diameter equal to the via diameter of 0.1 mm minimum. This capping prevents the solder from being

wicked through the thermal vias and potentially creating a solder void under the package. Refer to PowerPAD

[3]

Thermally Enhanced Package and the mechanical illustration at the end of this document for more information

on the PowerPAD package.

X: Minimum PowerPAD = 1.8 mm

Y: Minimum PowerPAD = 1.4 mm

Thermal Pad

4,50 mm 6,60 mm

4,30 mm

X

6,20 mm

1

10

Y

Figure 14. PowerPAD Dimensions

MOSFET PACKAGING

MOSFET package selection depends on MOSFET power dissipation and the projected operating conditions.

In general, for a surface-mount applications, the DPAK style package provides the lowest thermal impedance

(θ ) and, therefore, the highest power dissipation capability. However, the effectiveness of the DPAK depends

JA

on proper layout and thermal management. The θ specified in the MOSFET data sheet refers to a given

JA

copper area and thickness. In most cases, a lowest thermal impedance of 40°C/W requires one square inch

of 2-ounce copper on a G−10/FR−4 board. Lower thermal impedances can be achieved at the expense of board

area. Please refer to the selected MOSFET’s data sheet for more information regarding proper mounting.

GROUNDING AND CIRCUIT LAYOUT CONSIDERATIONS

The TPS4005x provides separate signal ground (SGND) and power ground (PGND) pins. It is important that

circuit grounds are properly separated. Each ground should consist of a plane to minimize its impedance if

possible. The high power noisy circuits such as the output, synchronous rectifier, MOSFET driver decoupling

capacitor (BP10), and the input capacitor should be connected to PGND plane at the input capacitor.

Sensitive nodes such as the FB resistor divider, R , and ILIM should be connected to the SGND plane. The

T

SGND plane should only make a single point connection to the PGND plane.

Component placement should ensure that bypass capacitors (BP10 and BP5) are located as close as possible

to their respective power and ground pins. Also, sensitive circuits such as FB, RT and ILIM should not be located

near high dv/dt nodes such as HDRV, LDRV, BOOST, and the switch node (SW).

22

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SLUS540F − DECEMBER 2002 − REVISED JUNE 2004

DESIGN EXAMPLE

D Input Voltage: 10 Vdc to 24 Vdc

D Output voltage: 3.3 V 2% (3.234 ≤ V ≤ 3.366)

O

D Output current: 8 A (maximum, steady state), 10 A (surge, 10 ms duration, 10% duty cycle maximum)

D Output ripple: 33 mV

at 8 A

P-P

D Output load response: 0.3 V => 10% to 90% step load change, from 1 A to 7 A

D Operating temperature: −40°C to 85°C

D f =300 kHz

SW

1. Calculate maximum and minimum duty cycles

V

O(min)

O(max)

IN(min)

3.324

24

3.366

10

d

+

+ 0.135

d

+

MAX

+

+ 0.337

MIN

V

IN(max)

(46)

2. Select switching frequency

The switching frequency is based on the minimum duty cycle ratio and the propagation delay of the current limit

comparator. In order to maintain current limit capability, the on time of the upper MOSFET, t , must be greater

ON

than 300 ns (see Electrical Characteristics table). Therefore

V

t

O(min)

ON

+

or

V

T

SW

IN(max)

(47)

V

O(min)

^ȡǒ Ǔ^ȣ

V

IN(max)

₊ȧ

ȧ

1

+ f

ȧ

SW

T

SW

ON

ȧ

Ȣ

Ȥ

(48)

(49)

Using 400 ns to provide margin,

0.135

f

+

+ 337 kHz

SW

400 ns

Since the oscillator can vary by 10%, decrease f , by 10%

SW

f

+ 0.9 337 kHz + 303 kHz

SW

and therefore choose a frequency of 300 kHz.

3. Select ∆I

In this case ∆I is chosen so that the converter enters discontinuous mode at 20% of nominal load.

DI + I 2 0.2 + 8 2 0.2 + 3.2 A

(50)

O

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SLUS540F − DECEMBER 2002 − REVISED JUNE 2004

DESIGN EXAMPLE

4. Calculate the power losses

Power losses in the high-side MOSFET (Si7860DP) at 24-V where switching losses dominate can be

IN

calculated from equation (51).

Ǹ

I

+ I d + 8 0.135 + 2.93 A

O

(51)

(52)

RMS

substituting (32) into (31) yields

2

(

))

P

+ 2.93 0.008 1 ) 0.007 150 * 25 + 0.129 W

COND

and from equation (33), the switching losses can be determined.

₊ǒ_V

Ǔ

f

P

I t

+ 24 V 8 A 20 ns 300 kHz + 1.152 W

SW

SW(fsw)

IN

O

SW

(53)

(54)

The MOSFET junction temperature can be found by substituting equation (35) into equation (34)

O

_{T +}ǒ_P

Ǔ

(

)

) P

q ) T + 0.129 ) 1.152 40 ) 85 + 136 C

J

COND

SW

JA

A

5. Calculate synchronous rectifier losses

The synchronous rectifier MOSFET has two (2) loss components, conduction, and diode reverse recovery

losses. The conduction losses are due to I losses as well as body diode conduction losses during the dead

RMS

time associated with the anti-cross conduction delay.

The I

current through the synchronous rectifier from (36)

RMS

Ǹ

I

+ I 1 * d + 8 1 * 0.135 + 7.44 A

O RMS

RMS

(55)

The synchronous MOSFET conduction loss from (31) is:

2

(

))

P

+ I

R

RMS DS(on)

+ 7.44 0.008 1 ) 0.007 150 * 25 + 0.83 W

COND

(56)

(57)

(58)

(59)

(60)

The body diode conduction loss from (37) is:

+ 2 I V t f

P

+ 2 8.0 A 0.8 V 100 ns 300 kHz + 0.384

SW

DC

O

FD

DELAY

The body diode reverse recovery loss from (38) is:

+ 0.5 Q V f + 0.5 30 nC 24 V 300 kHz + 0.108 W

P

RR

IN

SW

The total power dissipated in the synchronous rectifier MOSFET from (39) is:

+ P ) P ) P + 0.108 ) 0.83 ) 0.384 + 1.322 W

P

SR

RR

COND

DC

The junction temperature of the synchronous rectifier at 85°C is:

o

(

)

T + P q ) T + 1.322 40 ) 85 + 139 C

J

SR

JA

A

In typical applications, paralleling the synchronous rectifier MOSFET with a Schottky rectifier increases the

overall converter efficiency by approximately 2% due to the lower power dissipation during the body diode

conduction and reverse recovery periods.

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DESIGN EXAMPLE

6. Calculate the inductor value

The inductor value is calculated from equation (6).

(

)

24 * 3.3 V 3.3 V

L +

+ 2.96 mH

24 V 3.2 A 300 kHz

(61)

A 2.9-µH Coev DXM1306−2R9 or 2.6-µH Panasonic ETQ−P6F2R9LFA can be used.

7. Setting the switching frequency

The clock frequency is set with a resistor (R ) from the RT pin to ground. The value of R can be found from

T

equation (1), with f

in kHz.

SW

1

_{R +}ǒ

_* 23Ǔ_{kW + 164 kW N use 165 kW}

T

*6

f

17.82 10

SW

(62)

8. Programming the ramp generator circuit

The PWM ramp is programmed through a resistor (R

) from the KFF pin to V . The ramp generator also

IN

KFF

controls the input UVLO voltage. For an undervoltage level of 10 V, R

can be calculated from (2)

KFF

_* 3.5ǒ_{58.14 R ) 1340}Ǔ _{kW + 71 kW N use 71.5 kW}

T

₊ǒ_V

Ǔ

R

KFF

IN(min)

(63)

9. Calculating the output capacitance (C )

O

In this example the output capacitance is determined by the load response requirement of ∆V = 0.3 V for a 1 A

to 8 A step load. C can be calculated using (12)

O

2

_{2.9 m}ǒ_{(8 A *}_{1 A)}Ǔ

)

(

C

+

+ 97 mF

O

2

ǒ₍

₎Ǔ

)

(

3.3 * 3.0

(64)

Using (7) we can calculate the ESR required to meet the output ripple requirements.

1

_{33 mV + 3.2 A}ǒ_{ESR )}

Ǔ

8 73 mF 300 kHz

(65)

(66)

ESR + 10.3 mW * 3.33 mW + 6.97 mW

For this design example two (2) Panasonic SP EEFUEOJ1B1R capacitors, (6.3 V, 180 µF, 12 mΩ) are used.

10. Calculate the soft-start capacitor (C

)

SS

This design requires a soft−start time (t

) of 1 ms. C can be calculated on (14)

SS

START

2.3 mA

0.7 V

C

+

1 ms + 3.29 nF + 3300 pF

SS

(67)

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DESIGN EXAMPLE

11. Calculate the current limit resistor (R

)

ILIM

The current limit set point depends on t

design,

, V ,C and I

LOAD

at start-up as shown in equation (15). For this

(68)

START

O

360 mF 3.3 V

I

u

) 8.0 A + 9.2 A

LIM

1 ms

For this design, set I

for 11.0 A

minimum. From equation (16), with I

equal to the DC output surge

OC

LIM

DC

current plus one-half the ripple current of 3.2 A and R

heating.

is increased 30% (1.3 * 0.008) to allow for MOSFET

DS(on)

(* 0.075)

10 mA

12.6 A 0.0104W

1.12 10 mA

R

+

)

+ 11.7 kW * 7.5 kW + 4.2 kW ^ 4.22 kW

ILIM

(69)

(70)

12. Calculate loop compensation values

Calculate the DC modulator gain (A

10

) from equation (19)

MOD

( )

+ 20 log 5 + 14 dB

A

+

+ 5.0

A

MOD(dB)

MOD

2

Calculate the output filter L-C poles and C ESR zeros from (21) and (22)

O

1

f

+

+ 4.93 kHz

LC

Ǹ

_2pǸ_{L C}

2p 2.9 mH 360 mF

O

(71)

(72)

and

f +

1

+

+ 73.7 kHz

Z

2p ESR C

2p 0.006 360 mF

O

Select the close-loop 0 dB crossover frequency, f . For this example f = 20 kHz.

C

Select the double zero location for the Type III compensation network at the output filter double pole at 4.93kHz.

Select the double pole location for the Type III compensation network at the output capacitor ESR zero at

73.7 kHz.

The amplifier gain at the crossover frequency of 20 kHz is determined by the reciprocal of the modulator gain

AMOD at the crossover frequency from equation (27).

2

f

LC

4.93 kHz

20 kHz

ǒ

Ǔ

ǒ Ǔ

A

+ A

MOD

+ 5

+ 0.304

MOD(f)

f

C

(73)

(74)

And also from equation (27).

1

G +

+

+ 3.29

0.304

A

MOD(f)

Choose R1 = 100 kΩ

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DESIGN EXAMPLE

The poles and zeros for a type III network are described in equations (25) and (26).

1

f

+

N C3 +

N R3 +

+ 323 pF, choose 330 pF

+ 6.55 kW, choose 6.49 kW

Z2

2p R1 C3

2p 100 kW 4.93 kHz

(75)

1

f

P2

2p R3 C3

2p 330 pF 73.3 kHz

(76)

(77)

1

f

+

N C2 +

+ 24.2 pF, choose 22 pF

C

2p R1 C2 G

2p 100 kW 3.29 20 kHz

1

N R2 +

+ 98.2 kW, choose 97.6 kW

P1

2p R2 C2

2p 22 pF 73.3 kHz

(78)

(79)

1

f

+

N C1 +

+ 331 pF, choose 330 pF

Z1

2p R2 C1

2p 97.6 kW 4.93 kHz

Calculate the value of R

from equation (23) with R1 = 100 kΩ.

0.7 V 100kW

BIAS

0.7 V R1

R

+

+ 26.9 kW, choose 26.7 kW

BIAS

V

* 0.7 V

3.3 V * 0.7 V

O

(80)

CALCULATING THE BOOST AND BP10V BYPASS CAPACITANCE

The size of the bypass capacitor depends on the total gate charge of the MOSFET being used and the amount

of droop allowed on the bypass cap. The BOOST capacitance for the Si7860DP, allowing for a 0.5 voltage droop

on the BOOST pin from equation (29) is:

Q

g

18 nC

0.5 V

C

+

+ 36 nF

BOOST

DV

(81)

(82)

and the BP10V capacitance from (30) is

Q

) Q

DV

2 Q

DV

gHS

gSR

g

36 nC

0.5 V

C

+

+ 72 nF

BP(10 V)

For this application, a 0.1-µF capacitor is used for the BOOST bypass capacitor and a 1.0-µF capacitor is used

for the BP10V bypass.

Figure 15 shows component selection for the 10-V to 24-V to 3.3-V at 8 A dc-to-dc converter specified in the

design example. For an 8-V input application, it may be necessary to add a Schottky diode from BP10 to BOOST

to get sufficient gate drive for the upper MOSFET. As seen in Figure 7, the BP10 output is about 6 V with the

input at 8 V so the upper MOSFET gate drive may be less than 5 V.

REFERENCES

1. Balogh, Laszlo, Design and Application Guide for High Speed MOSFET Gate Drive Circuits, Unitrode

Power Supply Design Seminar, SEM−1400 Topic 2 (SLUP169)

2. PowerPAD Thermally Enhanced Package, Technical Brief (SLMA002)

3. Effect of Programmable UVLO on Maximum Duty Cycle Achievable with the TPS4005x and TPS4006x

Family of Synchronous Buck Controllers Application Note (SLUA310)

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Figure 15. 24-V to 3.3-V at 8-A DC-to-DC Converter Design Example

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PWP (R-PDSO-G**)

PowerPAD PLASTIC SMALL-OUTLINE

20 PINS SHOWN

0,30

0,19

M

0,65

20

0,10

11

Thermal Pad

(See Note D)

0,15 NOM

4,50

4,30

6,60

6,20

Gage Plane

1

10

0,25

A

0°−ā8°

0,75

0,50

Seating Plane

0,10

0,15

0,05

1,20 MAX

PINS **

14

16

20

24

28

DIM

5,10

4,90

5,10

4,90

6,60

6,40

7,90

7,70

9,80

9,60

A MAX

A MIN

4073225/F10/98

NOTES:A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusions.

D. The package thermal performance may be enhanced by bonding the thermal pad to an external thermal plane.

This pad is electrically and thermally connected to the backside of the die and possibly selected leads.

E. Falls within JEDEC MO-153

PowerPAD is a trademark of Texas Instruments Incorporated.

29

IMPORTANT NOTICE

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TI warrants performance of its hardware products to the specifications applicable at the time of sale in

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