TPS40101RGETG4 [TI]
Mid Range Input Synchronous Buck Controller with Advanced Sequencing and Output Margining 24-VQFN -40 to 85;
| 型号： | TPS40101RGETG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Mid Range Input Synchronous Buck Controller with Advanced Sequencing and Output Margining 24-VQFN -40 to 85 开关 |
| 文件： | 总37页 (文件大小：898K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS40101
www.ti.com
SLUS726–SEPTEMBER 2006
MIDRANGE INPUT SYNCHRONOUS BUCK CONTROLLER
WITH ADVANCED SEQUENCING AND OUTPUT MARGINING
FEATURES
CONTENTS
•
•
•
•
Operation over 4.5 V to 18 V Input Range
Device Ratings
2
3
100 kHz to 1 MHz Voltage Mode Control
Output Voltage Range From 0.69 V to 5.5 V
Electrical Characteristics
Terminal Information
Typical Characteristics
Application Information
Design Example
5
Simultaneous, Ratiometric and Sequential
Startup Sequencing
8
•
•
•
•
•
•
•
•
•
Remote Sensing (Via Separate GND/PGND)
24-Pin QFN Package
15
29
30
Thermal Shutdown
Additional References
Programmable Overcurrent Protection
Power Good Indicator
DESCRIPTION
1%, 690-mV Reference
The TPS40101 is
a
wide-input synchronous,
Output Margining, 3% and 5%
Programmable UVLO and Hysteresis
Frequency Synchronization
step-down controller that offers programmable closed
loop soft-start, programmable UVLO and hysteresis,
programmable current limit with hiccup recovery and
can be synchronized to other timebases. The
TPS40101 incorporates MOSFET gate drivers for
external N-channel MOSFETs. Gate drive logic
incorporates adaptive anti-cross conduction circuitry
for improved efficiency, reducing diode conduction in
the rectifier MOSFET.
APPLICATIONS
•
•
•
•
Servers
Networking Equipment
Telecommunications Equipment
Power Supply Modules
TYPICAL APPLICATION
24
23
22
21
20
19
1
2
3
4
5
6
COMP
FB
VDD 18
SW 17
TRKOUT
TRKIN
UVLO
HDRV 16
BST 15
TPS40101
VTRKN
VIN
5VBP 14
LDRV 13
ILIM
7
8
9
10
11
12
UDG−06054
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006, Texas Instruments Incorporated
TPS40101
www.ti.com
SLUS726–SEPTEMBER 2006
ORDERING INFORMATION
TA
PACKAGE
PART NUMBER(1)
TPS40101RGER
TPS40101RGET
-40°C to 85°C
QFN
(1) The QFN package (RGE) is available taped and reeled only. Use
large reel device type R (TPS40101RGER) to order quantities of
3,000 per reel. Use small reel device type T (TPS40101RGET) to
order quantities of 250 per reel.
DEVICE RATINGS
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1)
TPS40101
UNIT
VDD
-0.3 to 20
5VBP, BIAS, FB, ILIM, ISNS, LDRV, MGU, MGD, PG, SS,
SYNC, UVLO, VO
-0.3 to 6
BST to SW, HDRV to SW(2)
-0.3 to 6.0
-1.5 to VVIN
-6 to 30
-0.3 to 20
-0.3 to 0.3
-0.3 to 8.0
0.5
SW
VIN
Input voltage range
V
SW (transient) < 100 ns
TRKIN
GND to PGND
TRKOUT
HDRV, LDRV (RMS)
A
HDRV, LDRV (peak)
2.0
FB, COMP, TRKOUT
10 to -10
20 to -20
20
mA
SS
IIN
Input current range
PG
GM
1
mA
RT
10
V5BP
RT source
50(3)
100
µA
TJ
Operating junction temperature range
Storage temperature
–40 to 125
–55 to 150
°C
Tstg
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) BST to SW and HDRV to SW are relative measurements. BST and HDRV can be this amount of voltage above or below the voltage at
SW.
(3) V5BP current includes gate drive current requirements. Observe maximum TJ rating for the device.
2
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SLUS726–SEPTEMBER 2006
ELECTRICAL CHARACTERISTICS
-40°C ≤ TA = TJ≤ 85°C, VVDD = 12 V, RRT = 182 kΩ, RGM = 232 kΩ, RILIM = 121 kΩ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
INPUT VOLTAGE
VVDD Operating range
OPERATING CURRENT
4.5
18.0
2.5
V
IDD
Quiescent current
VFB > 0.8 V, 0% duty cycle
VUVLO < 1 V
1.3
1.8
mA
ISD
Shutdown current
500
µA
5VPB
7 V ≤ VVDD≤ 18 V, 0 mA ≤ ILOAD≤ 30 mA
4.5 V ≤ VVDD < 7 V, 0 mA ≤ ILOAD≤ 30 mA
4.7
4.3
5.0
5.0
5.3
5.3
Internal regulator
V
OSCILLATOR/RAMP GENERATOR
fSW
Programmable oscillator frequency
100
250
1000
300
kHz
4.5 V ≤ VIN < 18 V,
-40°C ≤ TA = TJ≤ 125°C
fOSC
Oscillator frequency accuracy
275
VRAMP
tOFF
DMIN
tMIN
Ramp amplitude(1)
0.5
VP-P
ns
Fixed off-time
100
150
0%
100
2.0
Minimum duty cycle
Minimum controllable pulse width(1)
Valley voltage(1)
CLOAD = 4.7 nF, -40°C ≤ TA = TJ≤ 125°C
90
ns
V
VVLY
1.0
2
1.6
FREQUENCY SYNCHRONIZATION
VIH
High-level input voltage
V
VIL
Low-level input voltage
0.8
ISYNC
tSYNC
tSYNC_SH
Input current, SYNC
VSYNC = 2.5 V
4.0
50
5.5
10.0
µA
ns
Mimimum pulse width, SYNC
Minimum set-up/hold time, SYNC(2)
100
SOFT-START AND FAULT IDLE
ISS
Soft-start source (charge) current
13
3.4
20
5.0
25
6.6
µA
ISS_SINK
VSSC
VSSD
Soft-start sink (discharge) current
Soft-start completed voltage
3.25
0.15
16
3.40
0.20
3.75
0.25
V
Soft-start discharged voltage
Retry interval time to SS time ratio(1)
VSSOS
Offset from SS to error amplifier
300
500
800
mV
ERROR AMPLIFIER
GBWP
AVOL
IBIAS
IOH
Gain bandwidth product(1)
3.5
60
5.0
80
50
3
MHz
dB
Open loop
Input bias current, FB
High-level output current
Low-level output current
Slew rate(1)
200
nA
2
2
mA
IOL
3
2.1
V/µs
FEEDBACK REFERENCE
TA =TJ =25°C
686
683
690
694
697
VFB
Feedback voltage reference
mV
-40°C < TA = TJ≤ 125°C
(1) Ensured by design. Not production tested.
(2) To meet set up time requirements for the synchronization circuit, a negative logic pulse must be greater than 100 ns wide.
3
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SLUS726–SEPTEMBER 2006
ELECTRICAL CHARACTERISTICS (continued)
-40°C ≤ TA = TJ≤ 85°C, VVDD = 12 V, RRT = 182 kΩ, RGM = 232 kΩ, RILIM = 121 kΩ (unless otherwise noted)
PARAMETER
VOLTAGE MARGINING
TEST CONDITIONS
MIN
TYP
MAX UNIT
Feedback voltage margin 5% up
Feedback voltage margin 3% up
Margin-up bias current
V
MGU ≤ 500 mV
715
700
60
725
711
80
735
mV
720
VFBMGU
IMGUP
2 V ≤ VMGU ≤ 3 V
100
665
680
100
30
µA
mA
µA
ms
Feedback voltage margin 5% down
Feedback voltage margin 3% down
Margin-down bias current
VMGD ≤ 500 mV
645
660
60
655
669
80
VFBMGD
2 V ≤ VMGD ≤ 3 V
IMGDN
tMGDLY
tMGTRAN
Margining delay time(3)
12
Margining transition time
1.5
300
-50
7.0
CURRENT SENSE AMPLIFIER
gmCSA
TCGM
VGMLIN
IISNS
Current sense amplifier gain
TJ =25°C
333
365
µS
ppm/°C
mV
Amplifier gain temperature coefficient
Gm linear range voltage
-2000
TJ =25°C
50
250
6
Bias current at ISNS pin
VVO = VISNS = 3.3 V
nA
0
0
VGMCM
Input voltage common mode
V
4.5 V ≤ VIN ≤ 5.5 V
3.6
CURRENT LIMIT
VILIM
ILIM pin voltage to trip overcurrent
Current limit comparator propagation delay
1.44
1.48
70
1.52
140
V
tILIMDLY
HDRV transition from on to off
ns
DRIVER SPECIFICATIONS
tRHDRV
HIgh-side driver rise time(4)
tFHDRV
HIgh-side driver fall time(4)
IHDRVSRPKS HIgh-side driver peak source current(4)
CLOAD = 4.7 nF
CLOAD = 4.7 nF
57
47
ns
mA
A
800
700
1.3
1.2
2.4
1.0
57
IHDRVSRMIL
IHSDVSNPK
IHDRVSNMIL
RHDRVUP
RHDRVDN
tRLDRV
HIgh-side driver source current at 2.5 V(4)
HIgh-side driver peak sink current(4)
High-side driver sink current at 2.5 V(4)
HIgh-side driver pullup resistance
HIgh-side driver pulldown resistance
Low-side driver rise time(4)
VHDRV - VSW = 2.5 V
VHDRV - VSW = 2.5 V
IHDRV = 300 mA
IHDRV = 300 mA
CLOAD = 4.7 nF
CLOAD = 4.7 nF
4.0
1.8
Ω
ns
mA
A
tFLDRV
Low-side driver fall time(4)
47
ILDRVSRPK
ILDRVSNMIL
ILSDVSNPK
Low-side driver peak source current(4)
Low-side driver source current at 2.5 V(4)
Low-side driver peak sink current(4)
Low-side driver sink current at 2.5 V(4)
Low-side driver pullup resistance
Low-side driver pulldown resistance
Leakage current from SW pin
800
700
1.3
1.2
2.0
0.8
VLDRV = 2.5 V
VLDRV = 2.5 V
ILDRV = 300 mA
ILDRV = 300 mA
RLDRVUP
RLDRVDN
ISWLEAK
4.0
1.5
1
Ω
-1
µA
POWERGOOD
VLPGD Powergood low voltage
tPGD
IPGD= 2 mA
30
25
100
35
mV
Powergood delay time
15
µs
VVDD = OPEN, 10-kΩ pullup to external
5-V supply
VLPGDNP
Powergood low voltage , no device power
1.00
1.25
V
VOV
VUV
Power good overvoltage threshold, VFB
Power good undervoltage threshold, VFB
765
615
mV
(3) Margining delay time is the time delay from an assertion of a margining command until the output voltage begins to transition to the
margined voltage.
(4) Ensured by design. Not production tested.
4
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SLUS726–SEPTEMBER 2006
ELECTRICAL CHARACTERISTICS (continued)
-40°C ≤ TA = TJ≤ 85°C, VVDD = 12 V, RRT = 182 kΩ, RGM = 232 kΩ, RILIM = 121 kΩ (unless otherwise noted)
PARAMETER
TRACKING AMPLIFIER
TEST CONDITIONS
MIN
TYP
MAX UNIT
VTRKOS = VTRKIN - VO ; VVO≤ 2 V
7
-5
25
25
40
VTRKOS
VTRKCM
VTRK
Tracking amplifier input offset voltage
Input common mode, active range
Tracking amplifier voltage range
mV
40
VTRKOS = VTRKIN - VO ; 2 V < VVO≤ 6 V
0
6
4.5 V ≤ VVDD ≤ 5.5 V
5 V < VVDD ≤ 18 V(5)
VVDD = 12 V
0
3.6
0
6
V
5.0
3.2
0
6.5
3.6
8.0
VHTRKOUT
VLTRKOUT
High-level output voltage, TRKOUT
Low-level output voltage, TRKOUT
VVDD = 4.5 V
0.5
ISRCTRKOUT Source current, TRKOUT
ISNKTRKOUT Sink current, TRKOUT
0.65
1
2.00
2
mA
VTRKDIF
Differential voltage from TRKIN to VO
18
V
GBWPTRK
AVOLTRK
Tracking amplifier gain bandwidth product(6)
Tracking amplifier open loop DC gain(6)
1
MHz
dB
60
PROGRAMMABLE UVLO
VUVLO Undervoltage lockout threshold
IUVLO Hysteresis current
INTERNALLY FIXED UVLO
1.285 1.332 1.378
9.0 10.0 10.8
V
µA
VUVLOFON
VUVLOFOFF
VUVLOHYST
Fixed UVLO turn-on voltage at VDD pin
-40°C ≤ TA < 125°C
3.850 4.150 4.425
V
Fixed UVLO turn-off voltage at VDD pin
UVLO hysteresis at VDD pin
3.750
130
4.06
85
4.35
mV
THERMAL SHUTDOWN
TSD
Thermal shutdown temperature(6)
Hysteresis(6)
165
25
°C
TSDHYST
(5) Amplifier can track to the lesser of 6 V or (VDD× 0.95)
(6) Ensured by design. Not production tested.
DEVICE INFORMATION
RGE PACKAGE
(BOTTOM VIEW)
1
2
3
4
5
6
MGU
MGD
SYNC
PG
24
7
8
9
RT
23
22
21
20
19
BIAS
GND
SS
10
11
12
VO
GM
ISNS
PGND
18 17 16 15 14 13
5
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SLUS726–SEPTEMBER 2006
DEVICE INFORMATION (continued)
TERMINAL FUNCTIONS
TERMINAL
I/O
DESCRIPTION
NAME
NO.
Output of an internal 5-V regulator. A 1-µF bypass capacitor should be connected from this
pin to PGND. Power for external circuitry may be drawn from this pin. The total gate drive
current and external current draw should not cause the device to exceed thermal capabilities
5VBP
14
O
O
I
The bypassed supply for internal device circuitry. Connect a 0.1-µF or greater ceramic
capacitor from this pin to GND.
BIAS
BST
8
15
1
Gate drive voltage for the high-side N-channel MOSFET. An external diode must be
connected from 5VBP (A) to BST(K). A schottky diode is recommended for this purpose. A
capacitor must be connected from this pin to the SW pin.
Output of the error amplifier. A feedback network is connected from this pin to the FB pin for
control loop compensation.
COMP
O
Inverting input to the error amplifier. In normal operation the voltage on this pin is equal to
the internal reference voltage (approximately 690 mV).
FB
2
11
9
I
I
GM
Connect a resistor from this pin to GND to set the gain of the current sense amplifier.
Low power or signal ground for the device. All signal level circuits should be referenced to
this pin unless otherwise noted.
GND
HDRV
-
16
O
Floating gate drive for the high side N-channel MOSFET.
Current limit pin used to set the overcurrent threshold and transient ride out time. An internal
current source that is proportional to the inductor current sets a voltage on a resistor
connected from this pin to GND. When this voltage reaches 1.48 V, an overcurrent condition
is declared by the device. Adding a capacitor in parallel with the resistor to GND sets a time
delay that can be used to help avoid nuisance trips.
ILIM
6
O
Current input from the inductor DCR sensing. This input signal is one of the inputs of the
current sense amplifier for over current detection.
ISNS
19
13
I
LDRV
O
Gate drive for the N-channel synchronous rectifier.
Margin down pin used for load stress test. When this pin is pulled to GND through less than
10 kΩ, the output voltage is decreased by 5%. The 3% margin down at the output voltage is
accommodated when this pin is connected to GND through a 30-kΩ resistor.
MGD
MGU
PG
23
24
21
I
I
Margin up pin used for load stress test. When this pin is pulled to GND through less than 10
kΩ, the output voltage is increased by 5%. The 3% margin up at the output voltage is
accommodated when this pin is connected to GND through a 30-kΩ resistor.
Open drain power good output for the device. This pin is pulled low when the voltage at the
FB pin is more than 10% higher or lower than 690 mV, a UVLO condition exists, soft-start is
active, tracking is active, an overcurrent condition exists or the die is over temperature.
O
PGND
RT
12
7
-
I
Power ground for internal drivers
A resistor connected from this pin to GND sets operating frequency.
Soft-start programming pin. A capacitor connected from this pin to ground programs the
soft-start time. This pin is also used as a time out function during an overcurrent event.
SS
10
17
I
I
Connected to the switched node of the converter. This pin is the return line for the flying high
side driver.
SW
Rising edge triggered synchronization input for the device. This pin can be used to
synchronize the oscillator frequency to an external master clock. This pin may be left floating
or grounded if the function is not used.
SYNC
TRKIN
22
4
I
I
Control input allowing simultaneous startup of multiple controllers. The converter output
tracks TRKIN voltage with a small controlled offset (typically 25 mV) when the tracking
amplifier is used. See application secttion for more information.
Output of the tracking amplifier. If the tracking feature is used, this pin should be connected
to FB pin through a resistor in series with a diode. The resistor value can be calculated from
the equivalent impedance at the FB node. The diode should be a low leakage type to
minimize errors due to diode reverse current. For further information on compensation of the
tracking amplifier refer to the application information
TRKOUT
UVLO
3
5
O
I
Provides for programming the undervoltage lockout level and serves as a shutdown input for
the device.
VDD
VO
18
20
I
I
Supply voltage for the device.
Output voltage. This is the reference input to the current sense amplifier.
6
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SLUS726–SEPTEMBER 2006
FUNCTIONAL BLOCK DIAGRAM
RT
7
SYNC
22
UVLO
5
TPS40100
UVLO
15 BST
16 HDRV
17 SW
+
Oscillator
1.33 V
CLK
10 µA
COMP
FB
1
2
PWM
Adaptive
Gate
Drive
and
Prebias
Control
SS
+
+
OC
FAULT
CLK
0.725 V
14 5VBP
13 LDRV
12 PGND
MGU 24
0.711 V
0.690 V
0.669 V
0.655 V
+
Reference
Select
MGD 23
ISNS 19
+
OC
1.48 V
VO 20
21 PG
Reference
Voltages
2 V
+
OC/SS
Controller
CLK
OC
FAULT
GM 11
TRKOUT
TRKIN
3
4
Housekeeping
18 VDD
+
6
10
8
9
UDG−04142x
ILIM
SS
BIAS
GND
7
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SLUS726–SEPTEMBER 2006
TYPICAL CHARACTERISTICS
SUPPLY CURRENT
vs
TEMPERATURE (NO SWITCHING)
SHUTDOWN SUPPLY CURRENT
vs
TEMPERATURE
2.5
2.0
0.6
V
DD
= 18 V
V
DD
= 18 V
0.5
0.4
V
DD
= 12 V
1.5
1.0
V
DD
= 4.5 V
V
DD
= 12 V
0.3
V
DD
= 4.5 V
0.2
0.1
0.5
0
UVLO = 0 V
0
0
−50
0
50
100
150
−50
50
100
150
T − Temperature − °C
T − Temperature − °C
Figure 1.
Figure 2.
REGULATOR OUTPUT VOLTAGE
FEEDBACK BIAS CURRENT
vs
vs
TEMPERATURE
TEMPERATURE
5.0
4.9
−20
−30
−40
V
BP5
= 18 V,
= 0, 30 mA
DD
4.8
4.7
4.6
4.5
I
V
= 18 V, I
= 0 mA
DD
BP5
−50
V
= 7 V, I
= 0 mA
DD
BP5
V
= 7 V, I
= 30 mA
DD
BP5
−60
−70
V
= 4.5 V, I
= 0 mA
DD
BP5
4.4
4.3
V
DD
= 4.5 V, I
0
= −30 mA
50
BP5
−80
−50
100
150
−50
0
50
100
150
T − Temperature − °C
T − Temperature − °C
Figure 3.
Figure 4.
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TYPICAL CHARACTERISTICS (continued)
REFERENCE VOLTAGE CHANGE
MARGIN DELAY
vs
vs
TEMPERATURE
TEMPERATURE
0.5
0.4
20
18
0.3
0.2
16
14
12
10
8
0.1
0
−0.1
−0.2
−0.3
−0.4
6
4
2
0
−0.5
−50
0
50
100
150
−50
0
50
100
150
T − Temperature − °C
T − Temperature − °C
Figure 5.
Figure 6.
MARGIN TRANSITION
vs
POWERGOOD UNDERVOLTAGE THRESHOLD
vs
TEMPERATURE
TEMPERATURE
8.0
7.5
−10.50
−10.55
−10.60
−10.65
−10.70
−10.75
−10.80
−10.85
−10.90
7.0
6.5
6.0
5.5
−10.95
−11.00
5.0
−50
0
50
100
150
−50
0
50
100
150
T − Temperature − °C
T − Temperature − °C
Figure 7.
Figure 8.
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TYPICAL CHARACTERISTICS (continued)
POWERGOOD OVERVOLTAGE THRESHOLD
FIXED UVLO VOLTAGE
vs
vs
TEMPERATURE
TEMPERATURE
4.10
11.1
Turn On
4.08
4.06
11.0
10.9
4.04
10.8
4.02
4.00
10.7
10.6
Turn Off
3.98
3.96
10.5
−50
0
50
100
150
−50
0
50
100
150
T − Temperature − °C
T − Temperature − °C
Figure 9.
Figure 10.
PROGRAMMABLE UVLO THRESHOLD
PROGRAMMABLE UVLO HYSTERESIS CURRENT
vs
vs
TEMPERATURE
TEMPERATURE
1.350
1.345
1.340
11.0
10.8
10.6
10.4
10.2
10.0
9.8
1.335
1.330
1.325
1.320
1.315
9.6
1.310
1.305
1.300
9.4
9.2
9.0
−50
0
50
100
150
−50
0
50
100
150
T − Temperature − °C
T − Temperature − °C
Figure 11.
Figure 12.
10
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TYPICAL CHARACTERISTICS (continued)
FREQUENCY CHANGE
TRACKING AMPLIFIER OFFSET VOLTAGE
vs
vs
TEMPERATURE
TEMPERATURE
25
20
3
2
1
15
10
0
−1
−2
−3
5
0
−4
−50
0
50
100
150
−50
0
50
100
150
T − Temperature − °C
T − Temperature − °C
Figure 13.
Figure 14.
TRACKING AMPLIFIER OUTPUT VOLTAGE
TRACKING AMPLIFIER BIAS CURRENT
vs
vs
TEMPERATURE
TEMPERATURE
7.5
7.0
0
I
= 500 µA
TRKOUT
−20
−40
V
= 12 V
6.5
6.0
DD
and V = 18 V
DD
−60
−80
5.5
5.0
V
DD
= 5.5 V
4.5
5.0
−100
−120
3.5
3.0
V
DD
= 4.5 V
−140
−50
0
50
100
150
−50
0
50
100
150
T − Temperature − °C
T − Temperature − °C
Figure 15.
Figure 16.
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TYPICAL CHARACTERISTICS (continued)
SOFT-START CHARGE AND DISCHARGE
POWER GOOD VOLTAGE
vs
vs
TEMPERATURE
TEMPERATURE
25
20
45
I
= 2 mA
PGOOD
40
35
Charge
30
15
10
25
20
15
Discharge
10
5
5
0
0
−50
−50
0
50
100
150
0
50
100
150
T − Temperature − °C
T − Temperature − °C
Figure 17.
Figure 18.
CURRENT LIMIT THRESHOLD VOLTAGE
OUTPUT VOLTAGE BIAS CURRENT
vs
vs
TEMPERATURE
TEMPERATURE
16
1.50
V
VO
= 3.3 V
14
12
10
1.49
1.48
8
6
1.47
4
2
0
1.46
1.45
−50
0
50
100
150
−50
0
50
100
150
T − Temperature − °C
T − Temperature − °C
Figure 19.
Figure 20.
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TYPICAL CHARACTERISTICS (continued)
CURRENT SENSE BIAS CURRENT
CURRENT SENSE BIAS CURRENT
vs
vs
TEMPERATURE
CURRENT SENSE VOLTAGE
400
200
120
V
VO
= V
= 3.3 V
ISNS
100
80
0
−200
−400
−600
−800
−1000
−1200
60
40
20
0
−50
0
50
100
150
0
1
2
3
4
5
6
T − Temperature − °C
V
ISNS
− Current Sense Bias Voltage − V
Figure 21.
Figure 22.
CURRENT SENSE BIAS CURRENT
RELATIVE CURRENT SENSE AMPLIFIER GAIN
vs
vs
TEMPERATURE
TEMPERATURE
−0.80
15
V
VO
= V
= 0 V
ISNS
10
5
−0.85
−0.90
0
−0.95
−1.00
−5
−10
−15
−1.05
−1.10
−20
−50
−50
0
50
100
150
0
50
100
150
T − Temperature − °C
T − Temperature − °C
Figure 23.
Figure 24.
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TYPICAL CHARACTERISTICS (continued)
TIMING RESISTOR
vs
SWITCHING FREQUENCY
(100 kHz to 400 kHz)
TIMING RESISTOR
vs
SWITCHING FREQUENCY
(400 kHz to 1 MHz)
550
500
130
120
450
400
110
100
350
300
90
80
250
200
70
60
150
100
50
40
100
150
f
200
250
300
350
400
400
500
f
600
700
800
900
1000
− Switching Frequency − kHz
− Switching Frequency − kHz
SW
SW
Figure 25.
Figure 26.
CURRENT SENSE AMPLIFIER GAIN SETTING
RESISTANCE
vs
POWERGOOD VOLTAGE
vs
POWERGOOD CURRENT (NO DEVICE POWER)
CURRENT SENSE AMPLIFIER GAIN
RGM > 50 kΩ
2.5
325
V
VDD
= 0 V
275
225
2.0
1.5
175
1.0
0.5
0
125
75
25
250
0
1
2
3
4
5
400
550
700
850
1000
I
− Powergood Current − mA
PGD
gm − Sense Amplifier Transconductance − µS
Figure 27.
Figure 28.
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APPLICATION INFORMATION
Introduction
The TPS40101 is a voltage mode synchronous buck controller targeted at applications that require sequencing
and output voltage margining features.Current sensing is true differential and can be done using the inductor DC
resistance (with a R-C filter) or with a separate sense resistor in series with the inductor. The programmable
overcurrent function has user programmable integration to eliminate nuisance tripping and allow the user to tailor
the response to application requirements. The controller provides an integrated method to margin the output
voltage to ±3% and ±5% of its nominal value by simply grounding one of two pins directly or through a
resistance. Powergood and clock synchronization functions are provided on dedicated pins. Users can program
operating frequency and the closed loop soft-start time by means of a resistor and capacitor to ground
respectively. Output sequencing/tracking can be accomplished in one of three ways: sequential (one output
comes up, then a second comes up), ratiometric (one or more outputs reach regulation at the same time – the
voltages all follow a constant ratio while starting) and simultaneous (one or more outputs track together on
startup and reach regulation in order from lowest to highest).
Programming Operating Frequency
Operating frequency is set by connecting a resistor to GND from the RT pin. The relationship is:
R +ȡ* 3.98 10
4
ȣ
4
5.14 10
) ǒ Ǔ* 8.6 (kW)
ȧ
ȧ
T
2
f
SW
f
SW
(1)
where
•
•
fSW is the switching frequency in kHz
RT is in kΩ
Figure 25 and Figure 26 show the relationship between the switching frequency and the RT resistor as described
in Equation 1. The scaling is different between them to allow the user a more accurate views at both high and
low frequency.
Selecting an Inductor Value
The inductor value determines the ripple current in the output capacitors and has an effect on the achievable
transient response. A large inductance decreases ripple current and output voltage ripple, but is physically larger
than a smaller inductance at the same current rating and limits output current slew rate more that a smaller
inductance would. A lower inductance increases ripple current and output voltage ripple, but is physically smaller
than a larger inductance at the same current rating. For most applications, a good compromise is selecting an
inductance value that gives a ripple current between 20% and 30% of the full load current of the converter. The
required inductance for a given ripple current can be found from:
ǒV
Ǔ
V
DI
SW
* V
IN
OUT
OUT
L +
(H)
V
f
IN
(2)
where
•
•
•
•
•
L is the inductance value (H)
VIN is the input voltage to the converter (V)
VOUT is the output voltage of the converter (V)
fSW is the switching frequency chosen for the converter (Hz)
∆I is the peak-to-peak ripple current in the inductor (A)
Selecting the Output Capacitance
The required value for the output capacitance depends on the output ripple voltage requirements and the ripple
current in the inductor, as well as any load transient specifications that may exist.
The output voltage ripple depends directly on the ripple current and is affected by two parameters from the
output capacitor: total capacitance and the capacitors equivalent series resistance (ESR). The output ripple
voltage (worst case) can be found from:
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APPLICATION INFORMATION (continued)
1
DV + DI ESR )
ǒ
Ǔ
(V)
ƪ
ƫ
8 C
f
SW
OUT
(3)
where
•
•
•
•
•
∆V is the peak to peak output ripple voltage (V)
∆I is the peak-to-peak ripple current in the inductor (A)
fSW is the switching frequency chosen for the converter (Hz)
COUT is the capacitance value of the output capacitor (F)
ESR is the equivalent series resistance of the capacitor, COUT (Ω)
For electrolytic capacitors, the output ripple voltage is almost entirely (90% or more) due to the ESR of the
capacitor. When using ceramic output capacitors, the output ripple contribution from ESR is much smaller and
the capacitance value itself becomes more significant. Paralleling output capacitors to achieve a desired output
capacitance generally lowers the effective ESR more effectively than using a single larger capacitor. This
increases performance at the expense of board area.
If there are load transient requirements that must be met, the overshoot and undershoot of the output voltage
must be considered. If the load suddenly increases, the output voltage momentarily dips until the current in the
inductor can ramp up to match the new load requirement. If the feedback loop is designed aggressively, this
undershoot can be minimized. For a given undershoot specification, the required output capacitance can be
found by:
2
L I
STEP
C
+
(F)
O(under)
ǒV OUTǓ
* V
IN
2 V
D
UNDER
MAX
(4)
where
•
•
•
•
•
•
•
CO(under) is the output capacitance required to meet the undershoot specification (F)
L is the inductor value (H)
ISTEP is the change in load current (A)
VUNDER is the maximum allowable output voltage undershoot
DMAX is the maximum duty cycle for the converter
VIN is the input voltage
VOUT is the output voltage
Similarly, if the load current suddenly goes from a high value to a low value, the output voltage overshoots. The
ouput voltage rises until the current in the inductor drops to the new load current. The required capacitance for a
given amount of overshoot can be found by:
2
L I
STEP
C
+
(F)
O(over)
2 V
V
OUT
OVER
(5)
where
•
•
•
•
•
CO(over) is the output capacitance required to meet the undershoot specification (F)
L in the inductor value (H)
ISTEP is the change in load current (A)
VOVER is the maximum allowable output voltage overshoot
VOUT is the output voltage
The required value of output capacitance is the maximum of CO(under) and CO(over)
.
Knowing the inductor ripple current, the switching frequency, the required load step and the allowable output
voltage excursion allows calculation of the required output capacitance from a transient response perspective.
The actual value and type of output capacitance is the one that satisfies both the ripple and transient
specifications.
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APPLICATION INFORMATION (continued)
Calculating the Current Sense Filter Network
The TPS40101 gets current feedback information by sensing the voltage across the inductor resistance, RLDC. In
order to do this, a filter must be constructed that allows the sensed voltage to be representative of the actual
current in the inductor. This filter is a series R-C network connected across the inductor as shown in Figure 29.
To ISNS pin
V
IN
To VO pin
R
FLT
C
FLT
100 Ω
L
R
LDC
V
O
C
O
UDG−04150
Figure 29. Current Sensing Filter Circuit
If the RFLT-CFLT time constant is matched to the L/RLDC time constant, the voltage across CFLT is equal to the
voltage across RLDC. It is recommended to keep RFLT 10 kΩ or less. CFLT can be arbitrarily chosen to meet this
condition (100 nF is suggested). RFLT can then be calculated.
L
C
R
+
* 100 (W)
FLT
R
LDC
FLT
(6)
where
•
•
•
•
RFLT is the current sense filter resistance (Ω)
CFLT is the current sense filter capacitance (F)
L is the output inductance (H)
RLDC is the DC resistance of the output inductor (Ω)
When laying out the board, better performance can be accomplished by locating CFLT as close as possible to the
VO and ISNS pins. The closer the two resistors can be brought to the device the better as this reduces the
length of high impedance runs that are susceptible to noise pickup. The 100-Ω resistor from VOUT to the VO pin
of the device is to limit current in the event that the output voltage dips below ground when a short is applied to
the output of the converter.
Compensation for Inductor Resistance Change Over Temperature
The resistance in the inductor that is sensed is the resistance of the copper winding. This value changes over
temperature and has approximately a 4000 ppm/°C temperature coefficient. The gain of current sense amplifier
in the TPS40101 has a built in temperature coefficient of approximately -2000 ppm/°C. If the circuit is physically
arranged so that there is good thermal coupling between the inductor and the device, the thermal shifts tend to
offset. If the thermal coupling is perfect, the net temperature coefficient is 2000 ppm/°C. If the coupling is not
perfect, the net temperature coefficient lies between 2000 ppm/°C and 4000 ppm/°C. For most applications this
is sufficient. If desired, the temperature drifts can be compensated for. The following compensation scheme
assumes that the temperature rise at the device is directly proportional to the temperature rise at the inductor. If
this is not the case, compensation accuracy suffers. Also, there is generally a time lag in the temperature rise at
the device vs. at the inductor that could introduce transient errors beyond those predicted by the compensation.
Also, the 100-Ω resistor in Figure 29 is not shown. However, it is required if the output voltage can dip below
ground during fault conditions. The calculations are not afffected, other than increasing the effective value of RF1
by 100-Ω.
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APPLICATION INFORMATION (continued)
The relative resistance change in the inductor is given by:
+ 1 ) TC ǒT * TBASEǓ
R
(dimensionless)
REL(L)
L
L
(7)
where
•
•
•
•
RREL(L) is the relative resistance of the inductor at TL compared to the resistance at TBASE
TCL is the temperature coefficient of copper, 4000 ppm/°C or 0.004
TL is the inductor copper temperature (°C)
TBASE is the reference temperature, typically lowest ambient (°C)
The relative gain of the current sense amplifier is given by a similar equation:
ǒT
* T
IC
BASEǓ
gm
+ 1 ) TC
(dimensionless)
(REL)
GM
(8)
where
•
•
•
•
gm(REL) is the relative gain of the amplifier at TIC compared to the gain at TBASE
TCGM is the temperature coefficient of the amplifier gain, -2000 ppm/°C or -0.002
TIC is the device junction temperature (°C)
TBASE is the reference temperature, typically lowest ambient (°C)
The temperature rise of the device can usually be related to the temperature rise of the inductor. The
relationship between the two temperature rises can be approximated as a linear relationship in most cases:
+ ǒT * T
Ǔ
k
T
* T
IC
BASE
L
BASE
THM
(9)
where
•
•
•
•
TIC is the device junction temperature (°C)
TBASE is the reference temperature, typically lowest ambient (°C)
TL is the inductor copper temperature (°C)
kTHM is the constant that relates device temperature rise to the inductor temperature rise and must be
determined experimentally for any given design
With these assumptions, the effective inductor resistance over temperature is:
+ ƪ1 ) TC T * T
Lǒ
Ǔƫ ƪ
1 ) k
ǒT * TBASEǓƫ
R
+ R
gm
TC
(dimensionless)
(10)
REL(eff)
REL(L)
REL
L
BASE
THM
GM
L
RREL(eff) is the relative effective resistance that must be compensated for when doing the compensation. The
circuit of Figure 30 shows a method of compensating for thermal shifts in current limit. The NTC thermistor
(RNTC) must be well coupled to the inductor. CFLT should be located as close to the device as possible.
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APPLICATION INFORMATION (continued)
VO
20
ILIM
6
ISNS
19
+
R
ILIM
−2000 ppm/°C
R
THE
R
F3
R
F2
R
NTC
V
IN
C
FLT
R
F1
L
R
LDG
V
OUT
C
OUT
UDG−04148
Figure 30. Compensation for Temperature Coefficient of the Inductor Resistance
The first step is to determine an attenuation ratio α. This ratio should be near to 1 but not too close. If it is too
close to 1, the circuit requires large impedances and thermistor values too high. If α is too low, the current signal
is attenuated unnecessarily. A suggested value is 0.8.
R
THE
) R
F1
a ^ 0.8
(dimensionless)
R
THE
(11)
RTHE is the equivalent resistance of the RF2-RF3-RNTC network:
R
R
) R
F3
F3
NTC
NTC
R
+ R
)
F2
(W)
THE
R
(12)
The base temperature (TBASE) should be selected to be the lowest temperature of interest for the thermal
matching – the lowest ambient expected. The resistance of the inductor at this base temperature should be used
to calculate effective resistance. The expected current sense amplifier gain at TBASE should be used for
calculating over current components (RILIM).
The next step is to decide at what two temperatures the compensation is matched to the response of the
deviceand inductor copper, T1 and T2. Once these are chosen, an NTC thermistor can be chosen and its value
found from its data sheet at these two temperatures: RNTC(T1) and RNTC(T2). The component values in the network
can be calculated using the following equations:
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APPLICATION INFORMATION (continued)
L
R
+
(W)
F1
R
LDC(Tbase) C
a
FLT
(13)
(14)
(15)
R
+ R
R
R
(W)
(W)
LDC(T1)
LDC(Tbase)
REL(effT1)
R
+ R
LDC(T2)
LDC(Tbase)
REL(effT2)
a R
R
LDC(Tbase)
F1
R
+
(W)
(W)
THE(T1)
R
* a R
LDC(T1)
LDC(Tbase)
(16)
(17)
a R
R
LDC(Tbase)
F1
R
+
THE(T2)
R
* a R
LDC(T2)
LDC(Tbase)
R
* R
NTC(T1)
NTC(T2)
THE(T2)
(W)
a + 1 *
b + R
(dimensionless)
R
* R
THE(T1)
(18)
(19)
) R
R
NTC(T1)
NTC(T2)
2
c + R
(W )
NTC(T1)
NTC(T2)
(20)
(21)
Ǹ
2a
2
* b " b * 4ac
R
+
(W)
F3
ǒR
NTC(T1)Ǔ * R
R
) R
R
F3 NTC(T1)
THE(T1)
F3
R
+
(W)
F2
R
) R
F3
NTC(T1)
(22)
where
•
•
•
•
•
•
•
•
L is the value of the output inductance (H)
CFLT is the value of the current sense filter capacitor (F)
α is the attenuation ratio chosen from Equation 11
RTHE(T1), RTHE(T2) are the equivalent resistances of the RTHE network at temperatures T1 and T2
RLDC(Tbase) is the DC resistance of the inductor at temperature TBASE in Ω
RLDC(T1), RLDC(T2) are the inductor resistances at temperatures T1 and T2
RREL(effT1), RREL(effT2), are the relative resistances of the inductor at T1 and T2 vs. Tbase
RNCT(T1), RNTC(T2) are the effective resistance of the NTC thermistor at temperatures T1 and T2
Setting the Current Sense Amplifier Gain
The amplifier is a transconductance type and its gain is a set by connecting a resistor from the GM pin to GND:
3
R
+
(W)
GM
2
*6
43.443 gm
) 0.01543 gm
) 3.225 10
CSA
CSA
(23)
where
•
•
RGM is the resistor that sets the gain of the amplifier (Ω)
gmCSA is the gain of the current sense amplifier (S)
The value of the sense amplifier gain should be less than 1000 µS, and more than 250 µS, with the resulting
gain setting resistor greater than 50 kΩ. As a suggested starting point, set the gain of the current sense amplifier
to a nominal 400 µS with RGM of 182 kΩ. This value should accommodate most applications adequately.
Figure 27 shows the current sense amplifier gain setting resistance vs. the sense amplifier gain.
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APPLICATION INFORMATION (continued)
Establishing Tracking and Designing a Tracking Control Loop
The tracking startup feature of the TPS40101 is a separate control loop that controls the output voltage to a
reference applied to the TRKIN pin. This reference voltage is typically a ramp generated by an external R-C
circuit. Connecting the junction of R5, C5 and R6 (see Figure 31) of multiple converters together allows the
converters output voltages to track together during start up. A controlled power down is accomplished by pulling
down the common junction in a controlled manner and then removing power to the converters or turning them
off by grounding the UVLO pin.The relevant circuit fragment is shown in Figure 31.
V
OUT
A
R
3
C
1
R
1
V
IN
C
C
R
2
2
3
VO
20
TRKOUT
3
R
D
1
4
+
R
6
FB
TRKIN
4
COMP
1
R
5
2
+
C
4
R
BIAS
C
5
A
To PWM
690 mV
UDG−04145
Figure 31. Tracking Loop Control Schematic
First, select a value for R4. In order for this circuit to work properly, the output of the tracking amplifier must be
able to cause the FB pin to reach at least 690 mV with the output voltage at zero volts. This is so that the output
voltage can be forced to zero by the tracking amplifier. This places a maximum value on R4:
ƪV
FBƫ
* V
* V
DIODE
R R
HTRKOUT(min)
1
BIAS
BIAS
R t
W
4
V
R ) R
1
FB
(24)
where
•
•
•
VHTRKOUT(min) is the minimum output voltage of the tracking amplifier (see Electrical Characteristics table)
VDIODE is the forward voltage of the device selected for D1
VFB is the value of the reference voltage (690 mV)
R4 should not be chosen much lower than this value since that unnecessarily increases tracking loop gain,
making compensation more difficult and opening the door to potential non-linear control issues. D1 could be a
schottky if the impedance of the R1-RBIAS string is low enough that the leakage current is not a consequence. Be
aware that schottky diode leakage currents rise significantly at elevated temperature. If elevated temperature
operation and increased accuracy are important, use a standard or low leakage junction diode or the
base-emitter junction of a transistor for D1.
Once R4 is selected, the gain of the closed loop power supply looking into “A” is known. That gain is the ratio of
R1 and R4:
dV
R
R
OUT
1
4
+ *
(dimensionless)
dV
TRKOUT
(25)
The tracking loop itself should have a crossover frequency much less that the crossover frequency of the voltage
control loop. Typically, the tracking loop crossover frequency is 1/10th or less of the voltage loop crossover
frequency to avoid loop interactions. Note that the presence of the diode in the circuit gives a non-linear control
mechanism for the tracking loop. The presence of this non-linearity makes designing a control loop more
challenging. The simplest approach is to simply limit the bandwidth of this loop to no more than necessary.
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APPLICATION INFORMATION (continued)
Knowing the gain of the voltage loop looking into R4 and the desired tracking loop crossover frequency, R5 and
C4 can be found:
R
4
R C +
(s)
5
4
2 p R f
1
cTRK
(26)
where
•
fCTRK is the desired tracking loop crossover frequency
The actual values of R5 and C4 are a balance between impedance level and component size. Any of a range of
values is applicable. In general, R5 should be no more than 20% of R6, and less than 10 kΩ. If this is done, then
R6 can safely be ignored for purposes of tracking loop gain calculations. For general usage, R6 should probably
be between 100 kΩ and 500 kΩ.
If an overshoot bump is present on the output at the beginning a tracking controlled startup, the tracking loop
bandwidth is likely too high. Reducing the bandwidth helps reduce the initial overshoot. See Figure 32 and
Figure 33.
t − Time − 1 ms/div
Figure 32. Excessive Tracking Loop Bandwidth
Figure 33. Limited Tracking Loop Bandwidth
The tracking ramp time is the time required for C5 to charge to the same voltage as the output voltage of the
converter.
V
OUT
+ * R C lnǒ1 * Ǔ
t
(s)
6
5
TRK
V
IN
(27)
where
•
•
•
VOUT is the output voltage of the converter
VIN is the voltage applied to the top of R6
tTRK is the desired tracking ramp time
With these equations, it is possible to design the tracking loop so that the impedance level of the loop and the
component size are balanced for the particular application. Note that higher impedances make the loop more
susceptible to noise issues while lower impedances require increased capacitor size.
Figure 34 shows the spice model for the voltage loop expanded for use with the tracking loop.
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APPLICATION INFORMATION (continued)
L
R
LDC
V
OUT
V
IN
+
C
OUT
X2
R
LOAD
R
CESR
C
1
C
3
R
3
C
2
R
2
R
1
+
R
+
BIAS
V
X
+
R
4
R
5
C
4
+
UDG−06060
Figure 34. AC Behavioral Model for Tracking Control Loop
To use the model, the AC voltage source is swept over the frequency range of interest. The open loop ac
response is VX/VOUT
.
Programming Soft-Start Time
The soft-start time of the TPS40101 is fully user programmable by selecting a single capacitor. The SS pin
sources 20 µA to charge this capacitor. The actual output ramp-up time is the amount of time that it takes for the
20 µA to charge the capacitor through a 690 mV range. There is some initial lag due to an offset from the actual
SS pin voltage to the voltage applied to the error amplifier. See Figure 36. The soft-start is done in a closed loop
fashion, meaning that the error amplifier controls the output voltage at all times during the soft start period and
the feedback loop is never open as occurs in duty cycle limit soft-start schemes. The error amplifier has two
non-inverting inputs, one connected to the 690 mV reference voltage, and one connected to the offset SS pin
voltage. The lower of these two voltages is what the error amplifier controls the FB pin to. As the voltage on the
SS pin ramps up past approximately 1.04 V (resulting in 690 mV at the error amplifier “+” input – See Figure 36),
the 690 mV reference voltage becomes the dominant input and the converter has reached its final regulation
voltage.
The capacitor required for a given soft-start ramp time for the output voltage is given by:
20 mA
C
+ T
SS
F
SS
V
FB
(28)
where
•
•
•
TSS is the desired soft-start ramp time (s)
CSS is the required capacitance on the SS pin (F)
VFB is the reference voltage feedback loop (690 mV)
23
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APPLICATION INFORMATION (continued)
COMP
FB
1
2
350 mV
COMP
Error Amplifier
+
+
690 mV
20 µA
SS
10
CHARGE
From UVLO circuits,
Fault controller
5 µA
C
SS
UDG−04138
Figure 35. Error Amplifier and Soft-Start Functional Diagram
UVLO
(Internal Logic State)
4.8 V
3.5 V
1.04 V
0.35 V
SS
Tss
Tss Delay
VOUT
PDG
Figure 36. Relationship Between UVLO (Internal Logic State), SS, VOUT and PGD at Startup
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APPLICATION INFORMATION (continued)
Interaction Between Soft-Start and Tracking Startup
Since the TPS40101 provides two means of controlling the startup (closed loop soft-start and tracking) care
must be taken to ensure that the two methods do not interfere with each other. The two methods should not be
allowed to try and control the output at the same time. If tracking is to be used, the reference input to the
tracking amplifier (TRKIN) should be held low until soft-start completes, or the voltage at the SS pin is at least
above 1.04 V. This ensures that the soft-start circuit is not trying to control the startup at the same time as
tracking circuit. If it is desired to have soft-start control the startup, then there are two options:
•
Disconnect the tracking amplifier output from the FB node (this is the recommended solution. The tracking
amplifier can then be used for other system purposes if desired)
•
Maintain the tracking amplifier output connection to the FB circuit - the reference to the tracking amplifier
should be tied to VDD pin in this case. This places the tracking amplifier output (TRKOUT) in a low state
continuously and therefore removes any influence the tracking circuit has on the converter startup.
Additionally, when tracking is allowed to control the startup, soft-start should not be set to an arbitrarily short
time. This causes the output voltage to bump up when power is applied to the converter as soft-start ramps up
quickly and the tracking loop (which is necessarily low bandwidth) cannot respond fast enough to control the
output to zero voltage. In other words, the soft start ramp rate must be within the capability of the tracking loop
to override.
Overcurrent Protection
Overcurrent characteristics are determined by connecting a parallel R-C network from the ILIM pin to GND. The
ILIM pin sources a current that is proportional to the current sense amplifier transconductance and the voltage
between ISNS and VO. This current produces a voltage on the R-C network at ILIM. If the voltage at the ILIM
pin reaches 1.48 V, an overcurrent condition is declared and the outputs stop switching for a period of time. This
time period is determined by the time is takes to discharge the soft-start capacitor with a controlled current sink.
To set the overcurrent level:
V
ILIM
I
LDC OC
R
+
W
ILIM
gm
R
CSA
(29)
where
•
•
•
•
•
VILIM is the overcurrent comparator threshold (1.48 V typically)
IOC is the overcurrent level to be set
gmCSA is the transconductance of the current sensing amplifier
RLDC is the equivalent series resistance of the inductor (or the sense resistor value)
RILIM is the value of the resistor from ILIM to GND
The response time of the overcurrent circuit is determined by the R-C time constant at the ILIM pin and the level
of the overcurrent. The response time is given by:
1
lnǒ1 * Ǔ
t
+ * R
C
ILIM
(s)
OC
ILIM
n
(30)
where
•
•
•
tOC is the response time before declaring an overcurrent
RILIM (Ω) and CILIM (F) are the components connected to the ILIM pin
n is the multiplier of the overcurrent. If the overcurrent is 2 times the programmed level, then n is 2.
By suitable manipulation of the time constant at ILIM, the overcurrent response can be tailored to ride out short
term transients and still provide protection for overloads and short circuits. The gm of the current sense amplifier
has a temperature coefficient of approximately -2000 ppm/°C. This is to help offset the temperature coefficient of
resistance of the copper in the inductor, about +4000 ppm/°C. The net is a +2000 ppm/°C temperature
coefficient. So, for a 100°C increase in temperature, the overcurrent threshold decreases by 20%, assuming
good thermal coupling between the controller and the inductor. Temperature compensation can be done as
described earlier if desired.
When an overcurrent condition is declared, the controller stops switching and turns off both the high-side
25
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APPLICATION INFORMATION (continued)
MOSFET and the low-side MOSFET. The soft-start capacitor is then discharged at 25% of the charge rate
during an overcurrent condition and the converter remains idle until the soft start pin reaches 200 mV, at which
point the soft-start circuit starts charging again and the converter attempts to restart. In normal operation, the
soft-start capacitor is charged to approximately 3.5 V when an initial fault is applied to the output. This means
that the minimum time before the first restart attempt is:
3.3 C
SS
t
+
(s)
RESTART
I
SSDIS
(31)
where
•
•
•
tRESTART is the initial restart time (s)
CSS is soft start capacitance (F)
ISSDIS is the soft start discharge current – 5 µA
If the output fault is persistent, and an overcurrent is declared on the restart, both of the MOSFETs are turned
off and the soft-start capacitor continues to charge to 3.5 V and then discharge to 200 mV before another restart
is attempted.
UVLO Programming
The TPS40101 provides the user with programmable UVLO level and programmable hysteresis. The UVLO
detection circuit schematic is described in Figure 37 from a functional perspective.
R
1
UVLO
1.33 V
+
UVLO
5
R
2
10 µA
TPS40100
UDG−04139
Figure 37. UVLO Circuit Functional Diagram
To program this circuit, first select the amount of hysteresis (the difference between the startup voltage and the
shutdown voltage) desired:
V
HYST
R +
W
1
I
UVLO
(32)
(33)
Then select the turn-on voltage and solve for R2.
V
R
1
UVLO
R +
W
2
V
* V
* R I
1
UVLO UVLO
ON
where
•
•
•
VHYST is the desired level of hysteresis in the programmable UVLO circuit
IUVLO is the undervoltage lockout circuit hysteresis current (10 µA typ)
VUVLO is the UVLO comparator threshold voltage (1.33 V typ)
26
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APPLICATION INFORMATION (continued)
Voltage Margining
The TPS40101 allows the user to make the output voltage temporarily be 3% above or below the nominal
output, or 5% above or below the nominal output. This is accomplished by connecting the MGU or MGD pins to
GND directly or through a resistance. See Table 1.
Table 1. Output Voltage Margining States
RESISTANCE TO GND (kΩ)
OUTPUT VOLTAGE
RMGU
OPEN
< 10
RMGD
OPEN
OPEN
< 10
Nominal
+ 5%
-5%
OPEN
25 to 37
OPEN
OPEN
25 to 37
+3%
-3%
There are some important considerations when adjusting the output voltage.
•
•
•
Only one of these pins should be anything other than an open circuit at any given time. States not listed in
the table are invalid states and the behavior of the circuit may be erratic if this is tried.
When changing the output voltage using the margin pins, it is very important to let the margin transition
complete before altering the state of the margin pins again.
Do not use mechanical means (switches, non-wetted relay contacts, etc) to alter the margining state. The
contact bounce causes erratic behavior.
Synchronization
The TPS40101 may be synchronized to an external clock source that is faster than the free running frequency of
the circuit. The SYNC pin is a rising edge sensitive trigger to the oscillator that causes the current cycle to
terminate and starts the next switching cycle. It is recommended that the synchronization frequency be no more
than 120% of the free running frequency. Following this guideline leads to fewer noise and jitter problems with
the pulse width modulator in the device. The circuit can be synchronized to higher multiples of the free running
frequency, but be aware that this results in a proportional decrease in the amplitude of the ramp from the
oscillator applied to the PWM, leading to increased noise sensitivity and increased PWM gain, possibly affecting
control loop stability.
The pulse applied to the SYNC pin can be any duty ratio as long as the pulse either high or low is at least 100
ns wide. Levels are logic compatible with any voltage under 0.8 V considered a low and any voltage over 2 V
considered a high.
Power Good Indication
The PGD pin is an open drain output that actively pulls to GND if any of the following conditions are met
(assuming that the input voltage is above 4.5V)
•
•
•
•
•
•
•
Soft-start is active (VSS < 3.5 V)
Tracking is active (VTRKOUT > 0.7 V)
VFB < 0.61 V
VFB > 0.77 V
VUVLO < 1.33 V
Overcurrent condition exists
Die temperature is greater than 165°C
A short filter (20 µs) must be overcome before PGD pulls to GND from a high state to allow for short transient
conditions and noise and not indicate a power NOT good condition.
The PGD pin attempts to pull low in the absence of input power. If the VDD pin is open circuited, the voltage on
PGD typically behaves as shown in Figure 28.
27
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Pre-Bias Operation
Some applications require that the converter not sink current during startup if a pre-existing voltage exists at the
output. Since synchronous buck converters inherently sink current some method of overcoming this
characteristic must be employed. Applications that require this operation are typically power rails for a multiple
supply processor or ASIC. The method used in this controller, is to not allow the low side or rectifier FET to turn
on until the output voltage commanded by the start up ramp is higher than the pre-existing output voltage. This
is detected by monitoring the internal pulse width modulator (PWM) for its first output pulse. Since this controller
uses a closed loop startup, the first output pulse from the PWM does not occur until the output voltage is
commanded to be higher than the pre-existing voltage. This effectively limits the controller to sourcing current
only during the startup sequence. If the pre-existing voltage is higher that the intended regulation point for the
output of the converter, the converter starts and sinks current when the soft-start time has completed.
Remote Sense
The TPS 40100 is capable of remotely sensing the load voltage to improve load regulation. This is accomplished
by connecting the GND pin of the device and the feedback voltage divider as near to the load as possible.
CAUTION:
Trace Length Considerations
More than a few inches of trace length between the GND pin of the device and the load GND can lead to
significantly increased pulse width jitter. As a starting point, the GND pin connection should be no further than
six inches from the PGND connection. The actual distance that starts causing erratic behavior is application and
layout dependent and must be evaluated on an individual basis. If the controller exhibits output pulse jitter in
excess of 25 ns and the GND pin is tied to the load ground, connecting the GND pin closer to the PGND pin
(and thereby sacrificing some load regulation) may improve performance. In either case, connecting the
feedback voltage divider at the point of load should not cause any problems. For layout, the voltage divider
components should be close to the device and a trace can be run from there to the load point.
28
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Design Examples
Margin down 3%
Power Good Indication
3.3 V ot 5 V logic supply or 5VBP pin
27 kΩ
27 kΩ
Margin up 3%
2N7002
2N7002
V
OUT
270 pF
24
23
22
21
20
19
Connect at load
12 V
18 nF
1.5 kΩ
200 Ω
1
2
COMP
FB
VDD 18
SW 17
100 nF
7.15 kΩ
Si73444DP
12 V
1.0 µH
Pulse
PG0006.102
1.4 mΩ (typ)
100 Ω
10 kΩ
30 kΩ
3
2.7 nF
TRKOUT
HDRV 16
BST 15
MMBD1501A
200 kΩ
100 kΩ
TPS40101
100 nF
BAT54
47 nF
4
5
6
TRKIN
UVLO
ILIM
4.99 kΩ
V
OUT
5VBP 14
LDRV 13
470 µF
Panasonic
1.2 V
15 A
Si7868ADP
EEF−SEOD471R
2
1 µF
13.0 kΩ
40.2 kΩ
1 µF
7
8
9
10
11
12
130 pF
100 kΩ
169 kΩ
1
1
1 µF
150 nF
90.9 kΩ
Remote
10 nF
(if required)
10 Ω
GND Sense
Connect at
Load
22 µF TDK C4532X7R1C226M
Open switch after input power is stable and SS capacitor had finished charging.
1
2
BAT54S
(if required)
UDG−06055
Figure 38. 500-kHz, 12-V to 1.2-V Converter With Tracking Startup Capability and Remote Sensing
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ADDITIONAL REFERENCES
Related Parts
The following parts have characteristics similar to the TPS40101 and may be of interest.
Related Parts
DEVICE
TPS40100
TPS40075
TPS40190
DESCRIPTION
Midrange Input Synchronous Controller with Advanced Sequencing and Output Margining
Wide Input Synchronous Controller with Voltage Feed Forward
Low Pin Count Synchronous Buck Controller
References
These references may be found on the web at www.power.ti.com under Technical Documents. Many design
tools and links to additional references, including design software, may also be found at www.power.ti.com
1. Under The Hood Of Low Voltage DC/DC Converters, SEM1500 Topic 5, 2002 Seminar Series
2. Understanding Buck Power Stages in Switchmode Power Supplies, SLVA057, March 1999
3. Design and Application Guide for High Speed MOSFET Gate Drive Circuits, SEM 1400, 2001 Seminar
Series
4. Designing Stable Control Loops, SEM 1400, 2001 Seminar Series
5. Additional PowerPADTM information may be found in Applications Briefs SLMA002 and SLMA004
6. QFN/SON PCB Attachment, Texas Instruments Literature Number SLUA271, June 2002
30
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EXAMPLE LAND PATTERN
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PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS40101RGER
TPS40101RGET
VQFN
VQFN
RGE
RGE
24
24
3000
250
330.0
180.0
12.4
12.4
4.25
4.25
4.25
4.25
1.15
1.15
8.0
8.0
12.0
12.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS40101RGER
TPS40101RGET
VQFN
VQFN
RGE
RGE
24
24
3000
250
367.0
210.0
367.0
185.0
35.0
35.0
Pack Materials-Page 2
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