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TPS40210DGQRG4 [TI]

4.5-V TO 52-V INPUT CURRENT MODE BOOST CONTROLLER; 4.5 V至52 V输入电流模式升压控制器
TPS40210DGQRG4
型号： TPS40210DGQRG4
厂家： TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述：

4.5-V TO 52-V INPUT CURRENT MODE BOOST CONTROLLER
4.5 V至52 V输入电流模式升压控制器

输入元件 控制器
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TPS40210, TPS40211  
www.ti.com .......................................................................................................................................................... SLUS772B–MARCH 2008–REVISED JUNE 2008  
4.5-V TO 52-V INPUT CURRENT MODE BOOST CONTROLLER  
1
FEATURES  
CONTENTS  
•
•
•
•
•
•
•
•
•
•
For Boost, Flyback, SEPIC, LED Drive Apps  
Wide Input Operating Voltage: 4.5 V to 52 V  
Adjustable Oscillator Frequency  
Fixed Frequency Current Mode Control  
Internal Slope Compensation  
Device Ratings  
2
3
Electrical Characteristics  
Typical Characteristics  
Terminal Information  
Application Information  
Additional References  
Design Examples  
5
10  
12  
25  
26  
Integrated Low-Side Driver  
Programmable Closed Loop Soft Start  
Overcurrent Protection  
External Synchronization Capable  
Reference700-mV (TPS40210), 260-mV  
(TPS40211)  
DESCRIPTION  
The TPS40210 and TPS40211 are wide-input voltage  
(4.5 V to 52 V), non-synchronous boost controllers.  
They are suitable for topologies which require a  
grounded source N-channel FET including boost,  
flyback, SEPIC and various LED Driver applications.  
The device features include programmable soft start,  
overcurrent protection with automatic retry and  
programmable oscillator frequency. Current mode  
control provides improved transient response and  
simplified loop compensation. The main difference  
between the two parts is the reference voltage to  
which the error amplifier regulates the FB pin.  
•
Low Current Disable Function  
APPLICATIONS  
•
•
•
LED Lighting  
Industrial Control Systems  
Battery Powered Systems  
V
IN  
TPS40210  
RC VDD 10  
SS  
DIS/EN GDRV  
V
OUT  
1
2
3
4
5
BP  
9
8
7
6
COMP  
FB  
ISNS  
GND  
R
SENSE  
UDG-07110  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2008, Texas Instruments Incorporated  
TPS40210, TPS40211  
SLUS772B–MARCH 2008–REVISED JUNE 2008.......................................................................................................................................................... www.ti.com  
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam  
during storage or handling to prevent electrostatic damage to the MOS gates.  
ORDERING INFORMATION  
PACKAGE  
LEAD  
TAPE AND REEL  
QUANTITY  
TJ  
PACKAGE  
PART NUMBER  
2500  
80  
TPS40210DGQR  
TPS40210DGQ  
TPS40210DRCR  
TPS40210DRCT  
TPS40211DGQR  
TPS40211DGQ  
TPS40211DRCR  
TPS40211DRCT  
10-Pin MSOP  
PowerPAD  
DGQ  
DRC  
DGQ  
DRC  
-40°C to 125°C  
3000  
250  
2500  
80  
10-Pin SON  
10-Pin MSOP  
PowerPAD  
-40°C to 125°C  
3000  
250  
10-Pin SON  
DEVICE RATINGS  
ABSOLUTE MAXIMUM RATINGS  
over operating free-air temperature range unless otherwise noted(1)  
TPS40210  
TPS40211  
UNIT  
VDD  
–0.3 to 52  
–0.3 to 10  
–0.3 to 8  
Input voltage range  
Output voltage range  
RC, SS, FB, DIS/EN  
ISNS  
V
COMP, BP, GDRV  
–0.3 to 9  
TJ  
Operating junction temperature range  
Storage temperature  
–40 to 150  
–55 to 150  
°C  
Tstg  
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings  
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating  
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.  
RECOMMENDED OPERATING CONDITIONS  
MIN NOM  
MAX  
52  
UNIT  
V
VVDD  
TJ  
Input voltage  
4.5  
-40  
Operating Junction temperature  
125  
°C  
PACKAGE DISSIPATION RATINGS  
R
θJA High-K Board(1)  
(°C/W)  
Power Rating (W)  
TA = 25°C  
Power Rating (W)  
TA = 85°C  
PACKAGE  
AIRFLOW (LFM)  
10-Pin MSOP PowerPAD  
(DGQ)  
0 (Natural Convection)  
57.7  
1.73  
0.693  
10-Pin SON (DRC)  
0 (Natural Convection)  
47.9  
2.08  
0.835  
(1) Ratings based on JEDEC High Thermal Conductivity (High K) Board. For more information on the test method, see TI Technical Brief  
SZZA017.  
ELECTROSTATIC DISCHARGE (ESD) PROTECTION  
MIN  
TYP  
1500  
1500  
MAX  
UNIT  
Human Body Model (HBM)  
V
Charged Device Model (CDM)  
2
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Copyright © 2008, Texas Instruments Incorporated  
Product Folder Link(s): TPS40210 TPS40211  
TPS40210, TPS40211  
www.ti.com .......................................................................................................................................................... SLUS772B–MARCH 2008–REVISED JUNE 2008  
ELECTRICAL CHARACTERISTICS  
TJ = –40°C to 125°C, VVDD= 12 Vdc, all parameters at zero power dissipation (unless otherwise noted)  
PARAMETER  
VOLTAGE REFERENCE  
TEST CONDITIONS  
MIN  
TYP  
MAX UNIT  
TPS40210 COMP = FB, 4.5 ≤ VVDD ≤ 52 V, TJ = 25°C  
TPS40211 COMP=FB, 4.5 ≤ VVDD ≤ 52 V, TJ = 25°C  
693  
254  
700  
260  
707  
266  
Feedback voltage range  
COMP = FB, 4.5 ≤ VVDD ≤ 52 V, -40°C ≤ TJ ≤  
VFB  
mV  
TPS40210  
125°C  
686  
250  
700  
260  
714  
270  
COMP = FB, 4.5 ≤ VVDD ≤ 52 V, -40°C ≤ TJ ≤  
TPS40211  
125°C  
INPUT SUPPLY  
VVDD Input voltage range  
4.5  
52  
2.5  
20  
V
4.5 ≤ VVDD ≤ 52 V, no switching, VDIS < 0.8  
2.5 ≤ VDIS ≤ 7 V  
1.5  
10  
mA  
µA  
µA  
IVDD  
Operating current  
VVDD < VUVLO(on), VDIS < 0.8  
530  
UNDERVOLTAGE LOCKOUT  
VUVLO(on)  
Turn on threshold voltage  
UVLO hysteresis  
4.00  
140  
4.25  
195  
4.50  
240  
V
VUVLO(hyst)  
mV  
OSCILLATOR  
Oscillator frequency range(1)  
35  
260  
1000  
340  
7%  
fOSC  
kHz  
mV  
Oscillator frequency  
RRC = 182 kΩ, CRC = 330 pF  
4.5 ≤ VDD ≤ 52 V  
300  
620  
Frequency line regulation  
Slope compensation ramp  
-20%  
520  
VSLP  
720  
PWM  
VVDD = 12V(1)  
VVDD = 30V  
275  
90  
400  
200  
200  
tON(min)  
Minimum pulse width  
ns  
V
tOFF(min)  
Minimum off time  
Valley voltage  
170  
1.2  
VVLY  
SOFT-START  
Offset voltage from SS pin to error  
amplifier input  
VSS(ofst)  
700  
mV  
RSS(chg)  
Soft-start charge resistance  
320  
840  
430  
600  
kΩ  
RSS(dchg)  
Soft-start discharge resistance  
1200  
1600  
ERROR AMPLIFIER  
GBWP  
AOL  
Unity gain bandwidth product(1)  
Open loop gain(1)  
1.5  
60  
3.0  
80  
MHz  
dB  
Input bias current (current out of FB  
pin)  
IIB(FB)  
100  
300  
nA  
ICOMP(src)  
ICOMP(snk)  
Output source current  
Output sink current  
VFB = 0.6 V, VCOMP = 1 V  
VFB = 1.2 V, VCOMP = 1 V  
100  
1.2  
250  
2.5  
µA  
mA  
OVERCURRENT PROTECTION  
Overcurrent detection threshold (at  
VISNS(oc)  
DOC  
VSS(rst)  
TBLNK  
4.5 ≤ VDD < 52 V, -40°C ≤ TJ ≤ 125°C  
120  
100  
150  
180  
2%  
mV  
ISNS pin)  
Overcurrent duty cycle(1)  
Overcurrent reset threshold voltage (at  
SS pin)  
Leading edge blanking(1)  
150  
75  
350  
mV  
ns  
(1) Ensured by design. Not production tested.  
Copyright © 2008, Texas Instruments Incorporated  
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Product Folder Link(s): TPS40210 TPS40211  
TPS40210, TPS40211  
SLUS772B–MARCH 2008–REVISED JUNE 2008.......................................................................................................................................................... www.ti.com  
ELECTRICAL CHARACTERISTICS (continued)  
TJ = –40°C to 125°C, VVDD= 12 Vdc, all parameters at zero power dissipation (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
MAX UNIT  
CURRENT SENSE AMPLIFIER  
ACS  
Current sense amplifier gain  
4..2  
5.6  
1
7.2  
3
V/V  
IB(ISNS)  
DRIVER  
IGDRV(src)  
IGDRV(snk)  
Input bias current  
µA  
Gate driver source current  
Gate driver sink current  
VGDRV = 4 V, TJ = 25°C  
375  
330  
400  
400  
mA  
V
VGDRV = 4 V, TJ = 25°C  
LINEAR REGULATOR  
VBP  
Bypass voltage output  
0 mA < IBP < 15 mA  
7
8
9
DISABLE/ENABLE  
VDIS(en)  
VDIS(hys)  
RDIS  
Turn on voltage  
0.7  
25  
1.3  
220  
1.5  
V
Hysteresis voltage  
130  
1.1  
mV  
MΩ  
DIS pin pulldown resistance  
0.7  
4
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Copyright © 2008, Texas Instruments Incorporated  
Product Folder Link(s): TPS40210 TPS40211  
TPS40210, TPS40211  
www.ti.com .......................................................................................................................................................... SLUS772B–MARCH 2008–REVISED JUNE 2008  
TYPICAL CHARACTERISTICS  
FREQUENCY  
vs  
TIMING RESISTANCE  
SWITCHING FREQUENCY  
vs  
DUTY CYCLE  
1200  
1200  
1000  
68 pF  
33pF  
C (pF)  
T
470  
100  
800  
220  
100  
68  
800  
600  
33  
100pF  
600  
220 pF  
400  
200  
400  
200  
470 pF  
0
0
0
0.2  
0.4  
0.6  
D - Duty Cycle  
0.8  
1.0  
1.2  
100 200 300 400 500 600 700 800 900 1000  
- Timing Resistance - kW  
R
T
Figure 1.  
Figure 2.  
QUIESCENT CURRENT  
vs  
JUNCTION TEMPERATURE  
SHUTDOWN CURRENT  
vs  
JUNCTION TEMPERATURE  
1.4  
1.2  
1.0  
6
52 V  
4.5 V  
5
4
12 V  
0.8  
0.6  
3
2
1
0.4  
0.2  
V
VDD  
12 V  
4.5 V  
52 V  
0
0
-40 -25 -10  
T
5 20 35 50 65 80 95 110 125  
– Junction Temperature – ° C  
-40 -25 -10  
T
5
20 35 50 65 80 95 110 125  
– Junction Temperature – ° C  
J
J
Figure 3.  
Figure 4.  
Copyright © 2008, Texas Instruments Incorporated  
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5
Product Folder Link(s): TPS40210 TPS40211  
 
TPS40210, TPS40211  
SLUS772B–MARCH 2008–REVISED JUNE 2008.......................................................................................................................................................... www.ti.com  
TYPICAL CHARACTERISTICS (continued)  
REFERENCE VOLTAGE CHANGE  
vs  
REFERENCE VOLTAGE CHANGE  
vs  
JUNCTION TEMPERATURE  
INPUT VOLTAGE  
0.4  
0.5  
52 V  
0.4  
0.3  
0.2  
0.0  
0.2  
0.1  
-0.2  
0.0  
-0.1  
-0.2  
-0.3  
-0.4  
-0.5  
-0.4  
-0.6  
4.5 V  
V
VDD  
12 V  
4.5 V  
52 V  
12 V  
-0.8  
-40 -25 -10  
T
5 20 35 50 65 80 95 110 125  
– Junction Temperature – ° C  
0
10  
20  
30  
40  
– Input Voltage – V  
50  
60  
V
J
VDD  
Figure 5.  
Figure 6.  
UNDERVOLTAGE LOCKOUT THRESHOLD  
OVERCURRENT THRESHOLD  
vs  
JUNCTION TEMPERATURE  
vs  
JUNCTION TEMPERATURE  
4.30  
155  
154  
153  
152  
151  
150  
UVLO  
4.5 V  
V
VDD  
Off  
On  
4.5 V  
7.5 V  
12 V & 20 V  
30 V  
4.25  
4.20  
7.5 V  
UVLO On  
30 V  
4.15  
4.10  
4.05  
12 V & 20 V  
149  
148  
UVLO Off  
4.00  
147  
-40 -25 -10  
T
5 20 35 50 65 80 95 110 125  
– Junction Temperature – ° C  
-40 -25 -10  
T
5
20 35 50 65 80 95 110 125  
– Junction Temperature – ° C  
J
J
Figure 7.  
Figure 8.  
6
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Copyright © 2008, Texas Instruments Incorporated  
Product Folder Link(s): TPS40210 TPS40211  
TPS40210, TPS40211  
www.ti.com .......................................................................................................................................................... SLUS772B–MARCH 2008–REVISED JUNE 2008  
TYPICAL CHARACTERISTICS (continued)  
OVERCURRENT THRESHOLD  
SWITCHING FREQUENCY CHANGE  
vs  
vs  
INPUT VOLTAGE  
JUNCTION TEMPERATURE  
155  
5
4
154  
153  
3
2
152  
151  
150  
149  
4.5 V  
1
0
12 V  
-1  
-2  
30 V  
148  
147  
V
(V)  
VDD  
-3  
-4  
-5  
4.5 V  
12 V  
30 V  
146  
145  
0
5
10 15  
V
20  
25  
– Input Voltage – V  
30 35  
40  
45  
-40 -25 -10  
T
5 20 35 50 65 80 95 110 125  
– Junction Temperature – ° C  
VDD  
J
Figure 9.  
Figure 10.  
OSCILLATOR AMPLITUDE  
vs  
JUNCTION TEMPERATURE  
SOFT-START CHARGE/DISCHARGE RESISTANCE  
vs  
JUNCTION TEMPERATURE  
29  
27  
1400  
R
Discharge  
SS(DSCH)  
4.5 V  
1200  
1000  
800  
25  
12 V  
23  
21  
24 V  
600  
19  
17  
V
(V)  
400  
200  
VDD  
36 V  
12 V  
24 V  
36 V  
4.5 V  
R
Charge  
SS(CHG)  
15  
0
-40 -25 -10  
T
5 20 35 50 65 80 95 110 125  
– Junction Temperature – ° C  
-40 -25 -10  
T
5 20 35 50 65 80 95 110 125  
– Junction Temperature – ° C  
J
J
Figure 11.  
Figure 12.  
Copyright © 2008, Texas Instruments Incorporated  
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Product Folder Link(s): TPS40210 TPS40211  
TPS40210, TPS40211  
SLUS772B–MARCH 2008–REVISED JUNE 2008.......................................................................................................................................................... www.ti.com  
TYPICAL CHARACTERISTICS (continued)  
FB BIAS CURRENT  
vs  
JUNCTION TEMPERATURE  
COMPENSATION SOURCE CURRENT  
vs  
JUNCTION TEMPERATURE  
180  
160  
300  
250  
200  
140  
120  
100  
80  
150  
60  
40  
100  
50  
20  
0
0
-40 -25 -10  
T
5 20 35 50 65 80 95 110 125  
– Junction Temperature – ° C  
-40 -25 -10  
T
5 20 35 50 65 80 95 110 125  
– Junction Temperature – ° C  
J
J
Figure 13.  
Figure 14.  
COMPENSATION SINK CURRENT  
vs  
VALLEY VOLTAGE CHANGE  
vs  
JUNCTION TEMPERATURE  
JUNCTION TEMPERATURE  
300  
5
4
250  
200  
3
2
1
0
150  
-1  
-2  
100  
50  
-3  
-4  
-5  
0
-40 -25 -10  
T
5 20 35 50 65 80 95 110 125  
– Junction Temperature – ° C  
-40 -25 -10  
T
5 20 35 50 65 80 95 110 125  
– Junction Temperature – ° C  
J
J
Figure 15.  
Figure 16.  
8
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Product Folder Link(s): TPS40210 TPS40211  
TPS40210, TPS40211  
www.ti.com .......................................................................................................................................................... SLUS772B–MARCH 2008–REVISED JUNE 2008  
TYPICAL CHARACTERISTICS (continued)  
REGULATOR VOLTAGE  
vs  
JUNCTION TEMPERATURE  
DIS/EN TURN-ON THRESHOLD  
vs  
JUNCTION TEMPERATURE  
8.8  
8.6  
1.10  
1.09  
1.08  
1.07  
1.06  
1.05  
I
= 0 mA  
LOAD  
8.4  
8.2  
8.0  
1.06  
1.03  
7.8  
7.6  
I
= 5 mA  
LOAD  
1.02  
1.01  
1.00  
7.4  
-40 -25 -10  
T
5 20 35 50 65 80 95 110 125  
– Junction Temperature – ° C  
-40 -25 -10  
T
5 20 35 50 65 80 95 110 125  
– Junction Temperature – ° C  
J
J
Figure 17.  
Figure 18.  
CURRENT SENSE AMPLIFIER GAIN  
vs  
JUNCTION TEMPERATURE  
7
6
5
4
3
2
1
0
-40 -25 -10  
T
5 20 35 50 65 80 95 110 125  
– Junction Temperature – ° C  
J
Figure 19.  
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Product Folder Link(s): TPS40210 TPS40211  
TPS40210, TPS40211  
SLUS772B–MARCH 2008–REVISED JUNE 2008.......................................................................................................................................................... www.ti.com  
DEVICE INFORMATION  
TERMINAL FUNCTIONS  
TERMINAL  
I/O  
DESCRIPTION  
NAME  
NO.  
COMP  
4
O
Error amplifier output. Connect control loop compensation network between COMP pin and FB pin.  
Disable pin. Pulling this pin high, places the part into a shutdown mode. Shutdown mode is characterized by  
a very low quiescent current. While in shutdown mode, the functionality of all blocks is disabled and the BP  
regulator is shut down. This pin has an internal 1-MΩ pull-down resistor to GND. Leaving this pin  
unconnected enables the device.  
DIS/EN  
3
I
Error amplifier inverting input. Connect a voltage divider from the output to this pin to set output voltage.  
Compensation network is connected between this pin and COMP.  
FB  
5
I
GDRV  
GND  
8
6
O
-
Connect the gate of the power N channel MOSFET to this pin.  
Device ground.  
Current sense pin. Connect an external current sensing resistor between this pin and GND. The voltage on  
this pin is used to provide current feedback in the control loop and detect an overcurrent condition. An  
overcurrent condition is declared when ISNS pin voltage exceeds the overcurrent threshold voltage, 150 mV  
typical.  
ISNS  
RC  
7
1
I
I
Switching frequency setting pin. Connect capacitor from RC pin to GND. Connect a resistor from RC pin  
toVDD of the IC power supply and a capacitor from RC to GND.  
Soft-start time programming pin. Connect capacitor from SS pin to GND to program converter soft-start time.  
This pin also functions as a timeout timer when the power supply is in an overcurrent condition.  
SS  
BP  
2
9
I
O
Regulator output pin. Connect a 1.0-µF bypass capacitor from this pin to GND.  
System input voltage. Connect a local bypass capacitor from this pin to GND. Depending on the amount of  
required slope compensation, this pin can be connected to the converter output. See Application Information  
section for additional details.  
VDD  
10  
I
DGQ PowerPAD PACKAGE  
(TOP VIEW)  
DRC PACKAGE  
(TOP VIEW)  
DGQ PowerPAD PACKAGE  
(Top View)  
DRC SURFACE MOUNT PACKAGE  
(Top View)  
RC  
1
10  
9
VDD  
BP  
1
10  
RC  
SS  
VDD  
BP  
1
2
SS  
DIS/EN  
COMP  
FB  
2
9
3
4
5
8
GDRV  
ISNS  
GND  
DIS/EN  
COMP  
FB  
3
4
5
8
GDRV  
ISNS  
GND  
7
7
6
6
10  
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Product Folder Link(s): TPS40210 TPS40211  
TPS40210, TPS40211  
www.ti.com .......................................................................................................................................................... SLUS772B–MARCH 2008–REVISED JUNE 2008  
FUNCTIONAL BLOCK DIAGRAM  
DIS/EN  
COMP  
FB  
3
4
5
10 VDD  
+
+
SS  
2
LDO  
9
BP  
E/A  
700 mV  
Soft Start  
and  
SS Ref  
Driver  
Overcurrent  
OC Fault  
PWM  
Logic  
8
6
GDRV  
GND  
Enable E/A  
Gain = 6  
+
Oscillator  
and  
RC  
1
Slope  
Compensation  
OC Fault  
7
ISNS  
150 mV  
UVLO  
+
LEB  
UDG-07107  
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Product Folder Link(s): TPS40210 TPS40211  
TPS40210, TPS40211  
SLUS772B–MARCH 2008–REVISED JUNE 2008.......................................................................................................................................................... www.ti.com  
APPLICATION INFORMATION  
Minimum On-Time and Off Time Considerations  
The TPS40210 has a minimum off time of approximately 200 ns and a minimum on time of 300 ns. These two  
constraints place limitations on the operating frequency that can be used for a given input to output conversion  
ratio. See Figure 2 for the maximum frequency that can be used for a given duty cycle.  
The duty cycle at which the converter operates is dependent on the mode in which the converter is running. If the  
converter is running in discontinuous conduction mode, the duty cycle varies with changes to the load much  
more than it does when running in continuous conduction mode.  
In continuous conduction mode, the duty cycle is related primarily to the input and output voltages.  
VOUT + VD  
1
=
V
1- D  
IN  
(1)  
(2)  
æ
ö
æ
ç
è
ö
÷
ø
V
IN  
D = 1-  
ç
÷
÷
ø
ç
VOUT + VD  
è
In discontinuous mode the duty cycle is a function of the load, input and output voltages, inductance and  
switching frequency.  
2´ V  
(
+ V ´I  
)
D
´L ´ f  
OUT  
OUT SW  
D =  
2
V
( )  
IN  
(3)  
All converters using a diode as the freewheeling or catch component have a load current level at which they  
transition from discontinuous conduction to continuous conduction. This is the point where the inductor current  
just falls to zero. At higher load currents, the inductor current does not fall to zero but remains flowing in a  
positive direction and assumes a trapezoidal wave shape as opposed to a triangular wave shape. This load  
boundary between discontinuous conduction and continuous conduction can be found for a set of converter  
parameters as follows.  
2
V
(
+ V - V ´ V  
IN ) ( )  
D IN  
OUT  
I
=
OUT(crit)  
2
2´ V  
(
+ V  
´ f  
´L  
)
OUT  
D
SW  
(4)  
For loads higher than the result of Equation 4, the duty cycle is given by Equation 2 and for loads less that the  
results of Equation 4, the duty cycle is given Equation 3. For Equations 1 through 4, the variable definitions are  
as follows.  
•
•
•
•
•
•
VOUT is the output voltage of the converter in V  
VD is the forward conduction voltage drop across the rectifier or catch diode in V  
VIN is the input voltage to the converter in V  
IOUT is the output current of the converter in A  
L is the inductor value in H  
fSW is the switching frequency in Hz  
12  
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Setting the Oscillator Frequency  
The oscillator frequency is determined by a resistor and capacitor connected to the RC pin of the TPS40210. The  
capacitor is charged to a level of approximately VVDD/20 by current flowing through the resistor and is then  
discharged by a transistor internal to the TPS40210. The required resistor for a given oscillator frequency is  
found from either Figure 1 or Equation 5.  
1
R
=
T
-8  
5.8 ´10 ´ f  
-10  
2
-7  
-4  
-6  
- 1.5 ´10 + 1.7 ´10 ´ C - 4 ´10 ´ C  
SW T T  
-9  
2
´ C +8 ´10  
´ f  
+ 1.4 ´10 ´ f  
SW  
T
SW  
(5)  
where  
•
•
•
RT is the timing resistance in kΩ  
fSW is the switching frequency in kHz  
CT is the timing capacitance in pF  
For most applications a capacitor in the range of 68 pF to 120 pF gives the best results. Resistor values should  
be limited to between 100 kΩ and 1 MΩ as well. If the resistor value falls below 100 kΩ, decrease the capacitor  
size and recalculate the resistor value for the desired frequency. As the capacitor size decreases below 47 pF,  
the accuracy of Equation 5 degrades and empirical means may be needed to fine tune the timing component  
values to achieve the desired switching frequency.  
Synchronizing the Oscillator  
The TPS40210 and TPS40211 can be synchronized to an external clock source. Figure 20 shows the functional  
diagram of the oscillator. When synchronizing the oscillator to an external clock, the RC pin must be pulled below  
150 mV for 20 ns or more. The external clock frequency must be higher than the free running frequency of the  
converter as well. When synchronizing the controller, if the RC pin is held low for an excessive amount of time,  
erratic operation may occur. The maximum amount of time that the RC pin should be held low is 50% of a  
nominal output pulse, or 10% of the period of the synchronization frequency.  
Under circumstances where the duty cycle is less than 50%, a Schottky diode connected from the RC pin to an  
external clock may be used to synchronize the oscillator. The cathode of the diode is connected to the RC pin.  
The trip point of the oscillator is set by an internal voltage divider to be 1/20 of the input voltage. The clock signal  
must have an amplitude higher than this trip point. When the clock goes low, it allows the reset current to restart  
the RC ramp, synchronizing the oscillator to the external clock. This provides a simple, single-component method  
for clock synchronization.  
VDD  
8
V
IN  
CLK  
+
S
R
Q
Q
R
RC  
External Frequency  
Synchronization  
(optional)  
RC  
+
1
+
150 mV  
C
RC  
GND  
5
TPS40210/11  
UDG-08063  
Figure 20. Oscillator Functional Diagram  
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VDD  
8
V
IN  
V
IN  
Amplitude >  
CLK  
+
S
R
Q
Q
20  
R
RC  
Duty Cycle < 50%  
RC  
+
1
Frequency > Controller  
Frequency  
+
150 mV  
C
RC  
GND  
5
TPS40210/11  
UDG-08064  
Figure 21. Diode Connected Synchronization  
Current Sense and Overcurrent  
The tps40210 and TPS40211 are current mode controllers and use a resistor in series with the source terminal  
power FET to sense current for both the current mode control and overcurrent protection. The device enters a  
current limit state if the voltage on the ISNS pin exceeds the current limit threshold voltage VISNS(oc) from the  
electrical specifications table. When this happens the controller discharges the SS capacitor through a relatively  
high impedance and then attempt to restart. The amount of output current that causes this to happen is  
dependent on several variables in the converter.  
V
IN  
TPS40210/11  
10 VDD  
TPS40210/11  
L
V
R
OUT  
VDD 10  
T
1
6
RC  
GDRV  
ISNS  
8
7
R
C
IFLT  
T
GND  
R
ISNS  
C
IFLT  
6
GND  
UDG-07119  
UDG-07120  
Figure 22. Oscillator Components  
Figure 23. Current Sense Components  
The load current overcurrent threshold is set by proper choice of RISNS. If the converter is operating in  
discontinuous mode the current sense resistor is found in Equation 6.  
14  
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f
´L ´ V  
ISNS(oc)  
SW  
R
=
ISNS  
2´L ´ f  
´I  
´ V  
(
+ V - V  
)
SW  
OUT(oc)  
OUT D IN  
(6)  
(7)  
If the converter is operating in continuous conduction mode RISNS can be found in Equation 7.  
V
V
ISNS  
ISNS  
R
=
=
ISNS  
I
I
RIPPLE  
æ
ç
è
ö
æ
ö
÷
ø
æ
ö
æ
ç
è
ö
÷
ø
I
D´ V  
IN  
OUT  
OUT  
+
+
÷
ø
ç
è
ç
ç
è
÷
÷
ø
1- D  
2
1- D  
(
2´ f  
´L  
)
SW  
where  
•
•
•
•
•
•
•
•
RISNS is the value of the current sense resistor in Ω.  
VISNS(oc) is the overcurrent threshold voltage at the ISNS pin (from electrical specifications)  
D is the duty cycle (from Equation 2)  
fSW is the switching frequency in Hz  
VIN is the input voltage to the power stage in V (see text)  
L is the value of the inductor in H  
IOUT(oc) is the desired overcurrent trip point in A  
VD is the drop across the diode in Figure 23  
The TPS40210/11 has a fixed undervoltage lockout (UVLO) that allows the controller to start at a typical input  
voltage of 4.25 V. If the input voltage is slowly rising, the converter might have less than its designed nominal  
input voltage available when it has reached regulation. As a result, this may decreases the apparent current limit  
load current value and must be taken into consideration when selecting RISNS. The value of VIN used to calculate  
RISNS must be the value at which the converter finishes startup. The total converter output current at startup is  
the sum of the external load current and the current required to charge the output capacitor(s). See the Soft Start  
section of this datasheet for information on calculating the required output capacitor charging current.  
The topology of the standard boost converter has no method to limit current from the input to the output in the  
event of a short circuit fault on the output of the converter. If protection from this type of event is desired, it is  
necessary to use some secondary protection scheme such a fuse or rely on the current limit of the upstream  
power source.  
Current Sense and Sub-Harmonic Instability  
A characteristic of peak current mode control results in a condition where the current control loop can exhibit  
instability. This results in alternating long and short pulses from the pulse width modulator. The voltage loop  
maintains regulation and dioes not oscillate, but the output ripple voltage increases. The condition occurs only  
when the converter is operating in continuous conduction mode and the duty cycle is 50% or greater. The cause  
of this condition is described in Texas Instruments literature number SLUA101, available at www.ti.com. The  
remedy for this condition is to apply a compensating ramp from the oscillator to the signal going to the pulse  
width modulator. In the TPS40210/11 the oscillator ramp is applied in a fixed amount to the pulse width  
modulator. The slope of the ramp is given in Equation 8.  
V
æ
ç
è
ö
÷
ø
VDD  
s
= f  
´
e
SW  
20  
(8)  
To ensure that the converter does not enter into sub-harmonic instability, the slope of the compensating ramp  
signal must be at least half of the down slope of the current ramp signal. Since the compensating ramp is fixed in  
the TPS40210/11, this places a constraint on the selection of the current sense resistor.  
The down slope of the current sense wave form at the pulse width modulator is described in Equation 9.  
A
´R  
´ V  
(
+ V - V  
)
CS  
ISNS  
OUT D IN  
m2 =  
L
(9)  
Since the slope compensation ramp must be at least half, and preferably equal to the down slope of the current  
sense waveform seen at the pulse width modulator, a maximum value is placed on the current sense resistor  
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when operating in continuous mode at 50% duty cycle or greater. For design purposes, some margin should be  
applied to the actual value of the current sense resistor. As a starting point, the actual resistor chosen should be  
80% or less that the value calculated in Equation 10. This equation calculates the resistor value that makes the  
slope compensation ramp equal to one half of the current ramp downslope. Values no more than 80% of this  
result would be acceptable.  
V
VDD ´L ´ fSW  
RISNS(max)  
=
60´ V + VD - V  
(
OUT  
)
IN  
(10)  
where  
•
•
•
•
•
•
•
Se is the slope of the voltage compensating ramp applied to the pulse width modulator in V/s  
fSW is the switching frequency in Hz  
VVDD is the voltage at the VDD pin in V  
m2 is the down slope of the current sense waveform seen at the pulse width modulator in V/s  
RISNS is the value of the current sense resistor in Ω  
VOUT is the converter output voltage VIN is the converter power stage input voltage  
VD is the drop across the diode in Figure 23  
It is possible to increase the voltage compensation ramp slope by connecting the VDD pin to the output voltage  
of the converter instead of the input voltage as shown in Figure 23. This can help in situations where the  
converter design calls for a large ripple current value in relation to the desired output current limit setting.  
NOTE:  
Connecting the VDD pin to the output voltage of the converter affects the startup  
voltage of the converter since the controller undervoltage lockout (UVLO) circuit  
monitors the VDD pin and senses the input voltage less the diode drop before startup.  
The effect is to increase the startup voltage by the value of the diode voltage drop.  
If an acceptable RISNS value is not available, the next higher value can be used and the signal from the resistor  
divided down to an acceptable level by placing another resistor in parallel with CISNS  
.
Current Sense Filtering  
In most cases, a small filter placed on the ISNS pin improves performance of the converter. These are the  
components RIFLT and CIFLT in Figure 23. The time constant of this filter should be approximately 10% of the  
nominal pulse width of the converter. The pulse width can be found using Equation 11.  
D
t
=
ON  
f
SW  
(11)  
The suggested time constant is then  
´ C = 0.1´ t  
R
IFLT  
IFLT  
ON  
(12)  
The range of RIFLT should be from about 1 kΩ to 5 kΩ for best results. Higher values can be used but this raises  
the impedance of the ISNS pin connection more than necessary and can lead to noise pickup issues in some  
layouts. CISNS should be located as close as possible to the ISNS pin as well to provide noise immunity.  
Soft Start  
The soft-start feature of the TPS40210/11 is a closed loop soft start, meaning that the output voltage follows a  
linear ramp that is proportional to the ramp generated at the SS pin. This ramp is generated by an internal  
resistor connected from the BP pin to the SS pin and an external capacitor connected from the SS pin to GND.  
The SS pin voltage (VSS) is level shifted down by approximately VSS(ofst) (approximately 700 mV) and sent to one  
of the “+” (the “+” input with the lowest voltage dominates) inputs of the error amplifier. When this level shifted  
voltage (VSSE) starts to rise at time t1 (see Figure 24), the output voltage the controller expects, rises as well.  
Since VSSE starts at near 0 V, the controller attempts to regulate the output voltage from a starting point of zero  
volts. It cannot do this due to the converter architecture. The output voltage starts from the input voltage less the  
16  
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drop across the diode (VIN - VD) and rise from there. The point at which the output voltage starts to rise (t2) is the  
point where the VSSE ramp passes the point where it is commanding more output voltage than (VIN - VD). This  
voltage level is labeled VSSE(1). The time required for the output voltage to ramp from a theoretical zero to the  
final regulated value (from t1 to t3) is determined by the time it takes for the capacitor connected to the SS pin  
(CSS) to rise through a 700 mV range, beginning at VSS(ofst) above GND.  
TPS40210/11  
V
SS  
R
SS(chg)  
700 mV REF  
SS  
Error Amplifier  
V
+700 mV  
SS(ofst)  
2
V
+
+
SSE  
V
SS(ofst)  
R
SS(dchg)  
V
SSE(1)  
t
t
1
0
V
- V  
D
IN  
V
OUT  
t
t
3
2
DIS  
UVLO  
OC Fault  
FB  
5
4
COMP  
UDG-07121  
Figure 24. SS Pin Voltage adn Output Voltage  
Figure 25. SS Pin Functional Circuit  
The required capacitance for a given soft start time t3 – t1 in Figure 24 is calculated in Equation 13.  
t
SS  
C
=
SS  
æ
ç
ö
÷
÷
V
- V  
SS(ofst)  
BP  
R
´ln  
SS  
ç
è
V
- V  
(
+ V  
)
BP  
SS(ofst) FB  
ø
(13)  
where  
•
•
•
•
•
•
tSS is the soft-start time  
RSS(chg) is the SS charging resistance in Ω, typically 500 kΩ  
CSS is the value of the capacitor on the SS pin, in F  
VBP is the value of the voltage on the BP pin in V  
VSS(ofst) is the approximate level shift from the SS pin to the error amplifier (~700 mV)  
VFB is the error amplifier reference voltage, 700m V typical  
Note that tSS is the time it takes for the output voltage to rise from 0 V to the final output voltage. Also note the  
tolerance on RSS(chg) given in the electrical specifications table. This contributes to some variability in the output  
voltage rise time and margin must be applied to account for it in design.  
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Also take note of VBP. Its value varies depending on input conditions. For example, a converter operating from a  
slowly rising input initializes VBP at a fairly low value and increases during the entire startup sequence. If the  
controller has a voltage above 8 V at the input and the DIS pin is used to stop and then restart the converter, VBP  
is approximately 8 V for the entire startup sequence. The higher the voltage on BP, the shorter the startup time is  
and conversely, the lower the voltage on BP, the longer the startup time is.  
The soft-start time (tSS) must be chosen long enough so that the converter can start up without going into an  
overcurrent state. Since the over current state is triggered by sensing the peak voltage on the ISNS pin, that  
voltage must be kept below the overcurrent threshold voltage VISNS(oc). The voltage on the ISNS pin is a function  
of the load current of the converter, the rate of rise of the output voltage and the output capacitance, and the  
current sensing resistor. The total output current that must be supported by the converter is the sum of the  
charging current required by the output capacitor and any external load that must be supplied during startup. This  
current must be less than the IOUT(oc) value used in Equation 6 or Equation 7 (depending on the operating mode  
of the converter) to determine the current sense resistor value. In these equations, the actual input voltage at the  
time that the controller reaches the final output voltage is the important input voltage to use in the calculations. If  
the input voltage is slowly rising and is at less than the nominal input voltage when the startup time ends, the  
output current limit is less than IOUT(oc) at the nominal input voltage. The output capacitor charging current must  
be reduced (decrease COUT or increase the tSS) or IOUT(oc) must be increased and a new value for RISNS  
calculated.  
æ
ç
è
ö
÷
ø
C
OUT  
I
=
C(chg)  
t
SS  
(14)  
(15)  
æ
ö
÷
÷
C
OUT  
ç
ç
è
t
>
SS  
I
(
- I  
EXT  
)
OUT(oc)  
ø
where  
•
•
•
•
•
IC(chg) is the output capacitor charging current in A  
COUT is the total output capacitance in F  
tSS is the soft start time from Equation 13  
IOUT(oc) is the desired over current trip point in A  
IEXT is any external load current in A  
The capacitor on the SS pin (CSS) also plays a role in overcurrent functionality. It is used as the timer between  
restart attempts. The SS pin is connected to GND through a resistor, RSS(dchg), whenever the controller senses an  
overcurrent condition. Switching stops and nothing else happens until the SS pin discharges to the soft-start  
reset threshold, VSS(rst). At this point, the SS pin capacitor is allowed to charge again through the charging  
resistor RSS(chg), and the controller restarts from that point. The shortest time between restart attempts occurs  
when the SS pin discharges from VSS(ofst) (approximately 700 mV) to VSS(rst) (150 mV) and then back to VSS(ofst)  
and switching resumes. In actuality, this is a conservative estimate since switching does not resume until the  
VSSE ramp rises to a point where it is commanding more output voltage than exists at the output of the controller.  
This occurs at some SS pin voltage greater than VSS(ofst) and depends on the voltage that remains on the output  
overvoltage the converter while switching has been halted. The fastest restart time can be calculated by using  
Equation 16, Equation 17 and Equation 18.  
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æ
´ C ´lnç  
ö
V
SS(ofst)  
t
= R  
÷
÷
ø
DCHG  
SS(dchg)  
SS  
ç
V
SS(rst)  
è
(16)  
æ
ö
÷
÷
V
- VSS(rst)  
(
)
BP  
ç
ç
è
tCHG = RSS(chg) ´ CSS ´ln  
V
- VSS(ofst)  
(
)
BP  
ø
(17)  
(18)  
tRSTRT min = tCHG + tDCHG  
(
)
V
BP  
V
SS  
t
RSTR(min)  
V
SS(ofst)  
V
SS(rst)  
T - Time  
Figure 26. Soft Start During Overcurrent  
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BP Regulator  
The TPS40210/11 has an on board linear regulator the supplies power for the internal circuitry of the controller,  
including the gate driver. This regulator has a nominal output voltage of 8 V and must be bypassed with a 1-µF  
capacitor. If the voltage at the VDD pin is less than 8 V, the voltage on the BP pin ia also be less and the gate  
drive voltage to the external FET ia reduced from the nominal 8 V. This should be considered when choosing a  
FET for the converter.  
Connecting external loads to this regulator can be done, but care must be taken to ensure that the thermal rating  
of the device is observed since is no thermal shutdown feature in this controller. Exceeding the thermal ratings  
cause out of specification behavior and can lead to reduced reliability. The controller dissipates more power  
when there is an external load on the BP pin and is tested for dropout voltage for up to 5-mA load. When the  
controller is in the disabled state, the BP pin regulator also shuts off so loads connected there power down as  
well. When the controller is disabled with the DIS/EN pin, this regulator is turned off.  
The total power dissipation in the controller can be calculated as follows. The total power is the sum of PQ, PG  
and PE.  
P
= V  
´I  
Q
VDD VDD(en)  
(19)  
P
= V  
´ Q ´ f  
SW  
G
VDD  
g
(20)  
(21)  
P = V  
´I  
E
VDD EXT  
where  
•
•
•
•
•
•
•
•
PQ is the quiescent power of the device in W  
VVDD is the VDD pin voltage in V  
IVDD(en) is the quiescent current of the controller when enabled but not switching in A  
PG is the power dissipated by driving the gate of the FET in W  
Qg is the total gate charge of the FET at the voltage on the BP pin in C  
fSW is the switching frequency in Hz  
PE is the dissipation caused be external loading of the BP pin in W  
IEXT is the external load current in A  
Shutdown (DIS/EN Pin)  
The DIS/EN pin is an active high shutdown command for the controller. Pulling this pin above 1.2 V causes the  
controller to completely shut down and enter a low current consumption state. In this state, the regulator  
connected to the BP pin is turned off. There is an internal 1.1-MΩ pull-down resistor connected to this pin that  
keeps the pin at GND level when left floating. If this function is not used in an application, it is best to connect  
this pin to GND  
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Control Loop Considerations  
There are two methods to design a suitable control loop for the TPS4021x. The first and preferred if equipment is  
available is to use a frequency response analyzer to measure the open loop modulator and power stage gain  
and to then design compensation to fit that. The usage of these tools for this purpose is well documented with  
the literature that accompanies the tool and is not be discussed here.  
The second option is to make an initial guess at compensation, and then evaluate the transient response of the  
system to see if the compensation is acceptable to the application or not. For most systems, an adequate  
response can be obtained by simply placing a series resistor and capacitor (RFB and CFB) from the COMP pin to  
the FB pin as shown in Figure 27.  
V
IN  
TPS40210  
L
V
OUT  
1
2
3
4
5
RC  
SS  
VDD 10  
BP  
9
8
7
6
C
HF  
DIS/EN GDRV  
C
R
OUT  
C
OUT  
R
FB  
R
FB  
IFLT  
COMP  
FB  
ISNS  
GND  
C
R
IFLT  
SENSE  
R
1
R
2
UDG-07177  
Figure 27. Basic Compensation Network  
The natural phase characteristics of most capacitors used for boost outputs combined with the current mode  
control provide adequate phase margin when using this type of compensation. To determine an initial starting  
point for the compensation, the desired crossover frequency must be considered when estimating the control to  
output gain. The model used is a current source into the output capacitor and load.  
When using these equations, the loop bandwidth should be no more than 20% of the switching frequency, fSW. A  
more reasonable loop bandwidth would be 10% of the switching frequency. Be sure to evaluate the transient  
response of the converter over the expected load range to ensure acceptable operation.  
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A
KCO = gM ´ Z  
f
OUT (CO )  
= 19.1  
´0.146W = 2.80  
V
(22)  
(23)  
(24)  
fSW  
600kHz  
0.13´ L ´  
0.13´ 10mH´  
ROUT  
240W  
A
gM  
=
=
= 19.1  
2
ISNS ) (  
2
12mW ´ 120´12mW +10mH´ 600kHz  
( ) ( )  
V
R
(
´ 120´R  
+ L ´ fSW  
)
ISNS  
2
)
1+ 2p´ f ´RESR ´ COUT  
(
L
(
+ 2´ROUT ´RESR + R  
)
´ 2p´ f ´ C  
ZOUT = ROUT  
´
2
2
ESR ) (  
2
)
1+  
R
(
)
(
OUT  
L OUT  
(
)
where  
•
•
•
•
•
•
•
•
•
•
KCO is the control to output gain of the converter, in V/V  
gM is the transconductance of the power stage and modulator, in S  
ROUT is the output load equivalent resistance, in Ω  
ZOUT is the output impedance, including the output capacitor, in Ω  
RISNS is the value of the current sense resistor, in Ω  
L is the value of the inductor, in H  
COUT is the value of the output capacitance, in µF  
RESR is the equivalent series resistance of COUT, in Ω  
fSW is the switching frequency, in Hz  
fL is the desired crossover frequency for the control loop, in Hz  
These equations assume that the operation is discontinuous and that the load is purely resistive. The gain in  
continuous conduction can be found by evaluating Equation 23 at the resistance that gives the critical conduction  
current for the converter. Loads that are more like current sources give slightly higher gains than predicted here.  
To find the gain of the compensation network required for a control loop of bandwidth fL, take the reciprocal of  
Equation 22.  
1
1
KCOMP  
=
=
= 0.356  
KCO  
2.80  
(25)  
The GBWP of the error amplifier is only guaranteed to be at least 1.5 MHz. If KCOMP multiplied by the fL is greater  
than 750 kHz, reduce the desired loop crossover frequency until this condition is satisfied. This ensures that the  
high-frequency pole from the error amplifier response with the compensation network in place does not cause  
excessive phase lag at the fL and decrease phase margin in the loop.  
The R-C network connected from COMP to FB places a zero in the compensation response. That zero should be  
approximately 1/10th of the desired crossover frequency, fL. With that being the case, RFB and CFB can be found  
from Equation 26 and Equation 27  
R1  
RFB  
=
= R1´KCOMP  
KCO  
(26)  
(27)  
10  
2p´ f ´R  
C
=
FB  
L
FB  
where  
•
•
R1 is in fL is the loop crossover frequency desired, in Hz  
RFB is the feedback resistor in CFB is the feedback capacitance in µF.  
Thought not strictly necessary, it is recommended that a capacitor be added between COMP and FB to provide  
high-frequency noise attenuation in the control loop circuit. This capacitor introduces another pole in the  
compensation response. The allowable location of that pole frequency determines the capacitor value. As a  
starting point, the pole frequency should be 10 × fL. The value of CHF can be found from Equation 28.  
22  
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1
C
=
HF  
20p´ f ´R  
L
FB  
(28)  
The error amplifier GBWP will usually be higher, but is ensured by design to be at least 1.5 MHz. If the gain  
required in Equation 25 multiplied by 10 times the desired control loop crossover frequency, the high-frequency  
pole introduced by CHF is overridden by the error amplifier capability and the effective pole is lower in frequency.  
If this is the case, CHF can be made larger to provide a consistent high-frequency roll off in the control loop  
design. Equation 29 calculates the required CHF in this case.  
1
CHF  
=
6
2p´1.5´ 10 ´RFB  
( )  
(29)  
where  
•
•
CHF is the high-frequency roll-off capacitor value in µF  
RFB is the mid band gain setting resistor value in Ω  
GATE DRIVE CIRCUIT  
Some applications benefit from the addition of a resistor connected between the GDRV pin and the gate of the  
switching MOSFET. In applications that have particularly stringent load regulation (under 0.75%) requirements  
and operate from input voltages above 5 V, or are sensitive to pulse jitter in the discontinuous conduction region,  
this resistor is recommended. The recommended starting point for the value of this resistor can be calculated  
from Equation 30.  
105  
R
=
G
Q
G
(30)  
where  
•
•
QG is the MOSFET total gate charge at 8-V VGS in nC  
RG is the suggested starting point gate resistance in Ω  
V
IN  
TPS40210/11  
VDD 10  
L
V
OUT  
R
G
GDRV  
ISNS  
GND  
8
7
6
UDG-07196  
Figure 28. Gate Drive Resistor  
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TPS40211  
The only difference between the TPS40210 and the TPS40211 is the reference voltage that the error amplifier  
uses to regulate the output voltage. The TPS40211 uses a 260-mV reference and is intended for applications  
where the output is actually a current instead of a regulated voltage. A typical example of an application of this  
type is an LED driver. An example schematic is shown in Figure 29.  
V
IN  
I
OUT  
TPS40210/11  
RC VDD 10  
L
1
2
3
4
5
SS  
BP  
GDRV  
ISNS  
9
8
7
6
DIS/EN  
COMP  
FB  
R
IFB  
GND  
UDG-07197  
Figure 29. Typical LED Drive Schematic  
The current in the LED string is set by the choice of the resistor RISNS as shown in Equation 31.  
V
FB  
R
=
IFB  
I
OUT  
(31)  
where  
•
•
•
RIFB is the value of the current sense resistor for the LED string in Ω  
VFB is the reference voltage for the TPS40211 in V (0.260 V typ)  
IOUT is the desired DC current in the LED string in A  
24  
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ADDITIONAL REFERENCES  
Related Devices  
The following devices have characteristics similar to the TPS40210 and may be of interest.  
Related Parts  
DEVICE  
TPS6100X  
TPS6101X  
TPS6300X  
DESCRIPTION  
Single- and Dual-Cell Boost Converter with Strart-up into Full Load  
High Efficiency 1-Cell and 2-Cell Bost Converters  
High Effiency Single Inductor Buck-Boost Converter with 1.8A Switches  
References  
These references may be found on the web at www.power.ti.com under Technical Documents. Many design  
tools and links to additional references, may also be found at www.power.ti.com  
1. Design and Application Guide for High Speed MOSFET Gate Drive Circuits, SEM 1400, 2001 Seminar  
Series  
2. Designing Stable Control Loops, SEM 1400, 2001 Seminar Series  
3. Additional PowerPADTM information may be found in Applications Briefs SLMA002 and SLMA004  
4. QFN/SON PCB Attachment, Texas Instruments Literature Number SLUA271, June 2002  
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DESIGN EXAMPLE 1  
12-V to 24-V Non-Synchronous Boost Regulator  
The following example illustrates the design process and component selection for a 12-V to 24-V  
non-synchronous boost regulator using the TPS40210 controller.  
+
+
Figure 30. TPS40210 Design Example – 8-V to 24-V at 2-A  
TPS40210 Design Example Specifications  
PARAMETER  
INPUT CHARACTERISTICS  
CONDITIONS  
MIN NOM MAX UNIT  
VIN  
IIN  
Input voltage  
8
12  
14  
V
A
V
Input current  
4.4  
No load input current  
Input undervoltage lockout  
0.05  
VIN(UVLO)  
4.5  
OUTPUT CHARACTERISTICS  
VOUT  
Output voltage  
Line regulation  
Load regulation  
23.5 24.0 24.5  
V
1%  
1%  
VOUT(ripple) Output voltage ripple  
500 mVPP  
IOUT  
IOCP  
Output current  
8 V ≤ VIN ≤ 14 V  
0.2  
3.5  
1
2.0  
A
Output overcurrent inception point  
Transient response  
Load step  
ΔI  
1
1
A
Load slew rate  
A/µs  
mV  
ms  
Overshoot threshold voltage  
Settling time  
500  
5
26  
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TPS40210 Design Example Specifications (continued)  
PARAMETER  
SYSTEM CHARACTERISTICS  
CONDITIONS  
MIN NOM MAX UNIT  
fSW  
ηPK  
η
Switching frequency  
Peak efficiency  
600  
95%  
94%  
25  
kHz  
°C  
in  
VIN = 12 V, 0.2 A ≤ IOUT ≤ 2 A  
VIN = 12 V, IOUT = 2 A  
Full load efficiency  
TOP  
Operating temperature range  
10 V ≤ VIN ≤ 14 V, 0.2 A ≤ IOUT ≤ 2 A  
MECHANICAL DIMENSIONS  
W
L
Width  
1.5  
1.5  
0.5  
Length  
Height  
h
Step-By-Step Design Procedure  
Duty Cycle Estimation  
The duty cycle of the main switching MOSFET is estimated using Equation 32 and Equation 33.  
V
- V  
+ V  
24V -14V + 0.5V  
24V + 0.5V  
OUT  
IN(max) FD  
D
»
=
= 42.8%  
MIN  
V
+ V  
OUT  
FD  
(32)  
V
- V  
+ V  
24 V - 8 V + 0.5 V  
24 V + 0.5 V  
OUT  
IN(min) FD  
D
»
=
= 67.3%  
MAX  
V
+ V  
OUT  
FD  
(33)  
Using and estimated forward drop of 0.5 V for a schottkey rectifier diode, the approximate duty cycle is 42.8%  
(minimum) to 67.3% (maximum).  
Inductor Selection  
The peak-to-peak ripple is limited to 30% of the maximum output current.  
I
2
OUT(max)  
I
= 0.3 ´  
= 0.3 ´  
= 1.05 A  
Lrip(max)  
1- D  
1- 0.428  
MIN  
(34)  
(35)  
The minimum inductor size can be estimated using Equation 35.  
V
1
14V  
1
IN(max)  
LMIN  
»
´DMIN  
´
=
fSW 1.05A  
´ 0.673´  
= 9.5mH  
ILrip(max)  
600kHz  
The next higher standard inductor value of 10 µH is selected. The ripple current is estimated by Equation 36.  
V
1
12 V  
1
IN  
I
»
´ D ´  
=
´ 0.50 ´  
= 1.02 A  
RIPPLE  
L
f
10 mH  
600kHz  
SW  
(36)  
(37)  
V
1
8V  
1
IN  
I
»
´D´  
=
´ 0.673´  
= 0.89A  
RIPPLE(Vinmin)  
L
f
10mH  
600kHz  
SW  
The worst case peak-to-peak ripple current occurs at 50% duty cycle and is estimated as 1.02 A. Worst case  
RMS current through the inductor is approximated by Equation 38.  
2
2
2
I
æ
ö
2
2
2
)
2
æ
ç
è
ö
÷
ø
OUT(max)  
1
12  
1
12  
1
ILrms  
=
I
( )  
L avg  
(
+
IRIPPLE  
»
+
IRIPPLE(VINmin)  
=
+
´ 0.817A = 6.13Arms  
ç
÷
(
( )  
(
12  
(
)
)
)
ç
÷
1- DMAX  
1- 0.673  
è
ø
(38)  
The worst case RMS inductor current is 6.13 Arms. The peak inductor current is estimated by Equation 39.  
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I
2
OUT(max)  
1
( 2)RIPPLE(Vinmin)  
1
( 2)  
I
»
+
I
=
+
0.718 = 6.57A  
Lpeak  
1- D  
1- 0.673  
MAX  
(39)  
A 10-µH inductor with a minimum RMS current rating of 6.13 A and minimum saturation current rating of 6.57 A  
must be selected. A TDK RLF12560T-100M-7R5 7.5-A 10-µH inductor is selected.  
This inductor power dissipation is estimated by Equation 40.  
2
P » I  
(
L
´DCR  
)
Lrms  
(40)  
The TDK RLF12560T-100M-7R5 12.4-mΩ DCR dissipates 466 mW of power.  
Rectifier Diode Selection  
A low-forward voltage drop schottky diode is used as a rectifier diode to reduce its power dissipation and improve  
efficiency. Using 80% derating, on VOUT for ringing on the switch node, the rectifier diode minimum reverse  
break-down voltage is given by Equation 41.  
V
OUT  
V
³
= 1.25´ V  
= 1.25´ 24V = 30V  
(BR)R(min)  
OUT  
0.8  
(41)  
The diode must have reverse breakdown voltage greater than 30 V. The rectifier diode peak and average  
currents are estimated by Equation 42 and Equation 43.  
ID avg » IOUT max = 2 A  
(
)
(
)
(42)  
(43)  
ID peak = IL peak = 6.57A  
(
)
(
)
For this design, 2-A average and 6.57-A peak is  
The power dissipation in the diode is estimated by Equation 44.  
P
» V ´I  
= 0.5V ´ 2A = 1W  
D(max)  
F
OUT(max)  
(44)  
For this design, the maximum power dissipation is estimated as 1 W. Reviewing 30-V and 40-V schottky diodes,  
the MBRS340T3, 40-V, 3-A diode in an SMC package is selected. This diode has a forward voltage drop of  
0.48-V at 6-A, so the conduction power dissipation is approximately 960 mW, less than half its rated power  
dissipation.  
Output Capacitor Selection  
Output capacitors must be selected to meet the required output ripple and transient specifications.  
I
OUT ´D  
æ
ç
è
ö
÷
ø
1
2A ´0.673  
1
COUT = 8  
´
VOUT(ripple) fSW  
= 8  
´
= 35mF  
500mV  
600kHz  
(45)  
(46)  
VOUT ripple  
7
(
)
7
500mV  
ESR =  
´
=
´
= 95mW  
8
IL peak -IOUT  
8
6.57A - 2A  
(
)
A Panasonic EEEFC1V330P 35V 33-µF, 120-mΩ bulk capacitor and 6.8-µF ceramic capacitor is selected to  
provide the required capacitance and ESR at the switching frequency. The combined capacitance of 39.8 µF and  
60 mΩ are used in compensation calculations.  
Input Capacitor Selection  
Since a boost converter has continuous input current, the input capacitor senses only the inductor ripple current.  
The input capacitor value can be calculated by Equation 47 and Equation 48 .  
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IL ripple  
(
)
1.02A  
CIN  
>
=
= 7.0mF  
4´ V  
´ fSW  
4´ 60mV ´ 600kHz  
IN ripple  
(
)
(47)  
V
IN ripple  
(
)
60mV  
ESR <  
=
= 30mW  
2´IL ripple  
2´1.02A  
(
)
(48)  
For this design, to meet a maximum input ripple of 60 mV, a minimum 7.0-µF input capacitor with ESR less than  
30 mΩ is needed. A 10-µF X7R ceramic capacitor is selected.  
Current Sense and Current Limit  
The maximum allowable current sense resistor value is limited by both the current limit and sub-harmonic  
stability. These two limitations are given by Equation 49 and Equation 50.  
V
110mV  
OCP(min)  
R
<
=
= 14.2mW  
ISNS  
1.1´ 6.57A + 0.50A  
1.1´ I  
(
+I  
Drive  
)
L peak  
(
)
(49)  
(50)  
VDD  
´L ´ f  
SW  
14V ´10mH´ 600kHz  
MAX  
R
<
=
+ V - V ) 60´(24V + 0.48V -14V)  
= 133mW  
ISNS  
60´(V  
OUT  
fd  
IN  
The current limit requires a resistor less than 14.2 mΩ and stability requires a sense resistor less than 133 mΩ. A  
10-mΩ resistor is selected. Approximately 2-mΩ of routing resistance added in compensation calculations.  
Current Sense Filter  
To remove switching noise from the current sense, an R-C filter is placed between the current sense resistor and  
the ISNS pin. A resistor with a value between 1 kΩ and 5 kΩ is selected and a capacitor value is calculated by  
Equation 51.  
0.1´D  
0.1´0.428  
MIN  
C
=
=
= 71pF  
IFLT  
f
´R  
600kHz ´1kW  
SW  
IFLT  
(51)  
For a 1-kΩ filter resistor, 71 pF is calculated and a 100-pF capacitor is selected.  
Switching MOSFET Selection  
The TPS40210 drives a ground referenced N-channel FET. The RDS(on) and gate charge are estimated based on  
the desired efficiency target.  
æ
ç
è
ö
æ
ç
è
ö
1
1
1
æ
ç
è
ö
÷
ø
PDISS(total) » POUT  
´
-1 = VOUT ´IOUT  
´
-1 = 24V ´ 2A ´  
-1 = 2.526W  
÷
ø
÷
ø
h
h
0.95  
(52)  
For a target of 95% efficiency with a 24 V Input voltage at 2 A, maximum power dissipation is limited to 2.526 W.  
The main power dissipating devices are the MOSFET, inductor, diode, current sense resistor and the integrated  
circuit, the TPS40210.  
P
< PDISS total - P - PD - PRisns - VIN(max) ´IVDD  
L
( )  
FET  
(53)  
This leaves 740 mW of power dissipation for the MOSFET. This can likely cause an SO-8 MOSFET to get too  
hot, so power dissipation is limited to 500 mW. Allowing half for conduction and half for switching losses, we can  
determine a target RDS(on) and QGS for the MOSFET by Equation 54 and Equation 55.  
3´P  
´I  
3´ 0.50W ´0.50A  
FET DRIVE  
Q
<
=
= 13.0nC  
GS  
2´ V  
´I  
´ f  
2´ 24V ´ 2A ´ 600kHz  
OUT OUT  
SW  
(54)  
A target MOSFET gate-to-source charge of less than 13.0 nC is calculated to limit the switching losses to less  
than 250 mW.  
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P
0.50W  
FET  
RDS on  
<
=
= 9.8mW  
( )  
2´ 6.132 ´0.674  
2
2´ I  
(
´D  
)
RMS  
(55)  
A target MOSFET RDS(on) of 9.8 mΩ is calculated to limit the conduction losses to less than 250 mW. Reviewing  
30-V and 40-V MOSFETs, an Si4386DY 9-mΩ MOSFET is selected. A gate resistor was added per equation  
(30). The maximum gate charge at Vgs=8 V for the Si4386DY is 33.2 nC, this impiles RG = 3.3 Ω.  
Feedback Divider Resistors  
The primary feedback divider resistor (RFB) from VOUT to FB should be selected between 10-kΩ and 100-kΩ to  
maintain a balance between power dissipation and noise sensitivity. For a 24-V output a high feedback  
resistance is desirable to limit power dissipation so RFB = 51.1 kΩ is selected.  
V
´R  
FB  
0.700V ´51.1kW  
24V - 0.700V  
FB  
R
=
=
= 1.53kW  
BIAS  
V
- V  
FB  
OUT  
(56)  
RBIAS = 1.50 kΩ is selected.  
Error Amplifier Compensation  
While current mode control typically only requires Type II compensation, it is desirable to layout for Type III  
compensation to increase flexibility during design and development.  
Current mode control boost converters have higher gain with higher output impedance, so it is necessary to  
calculate the control loop gain at the maximum output impedance, estimated by Equation 57.  
VOUT  
24V  
0.1A  
ROUT max  
=
=
= 240W  
(
)
IOUT min  
(
)
(57)  
(58)  
(59)  
The transconductance of the TPS40210 current mode control can be estimated by Equation 58.  
fSW  
600kHz  
0.13´ L ´  
0.13´ 10mH´  
ROUT  
240W  
A
gM  
=
=
= 19.1  
2
ISNS ) (  
2
12mW ´ 120´12mW +10mH´ 600kHz  
( ) ( )  
V
R
(
´ 120´R  
+ L ´ fSW  
)
ISNS  
The maximum output impedance ZOUT, can be estimated by Equation 59.  
2
1+ 2p´ f ´RESR ´ COUT  
(
(
+ 2´ROUT ´RESR + R  
)
)
´ 2p´ f ´C  
ZOUT(f ) = ROUT  
´
2
2
ESR ) (  
2
1+  
R
(
)
(
)
OUT  
OUT  
(
)
2
1+ 2p´ 20kHz ´ 60mW ´39.8mF  
(
)
(
)
1+ 240W + 2´ 240W´ 60mW + 60mW ´ 2p´ 20kHz ´39.8mF  
Z
f
OUT (CO )  
= 240W ´  
= 0.146W  
2
)
2
) (  
2
(
(
(
)
)
(60)  
The modulator gain at the desired cross-over can be estimated by Equation 61.  
A
KCO = gM ´ Z  
f
OUT (CO )  
= 19.1  
´0.146W = 2.80  
V
(61)  
The feedback compensation network needs to be designed to provide an inverse gain at the cross-over  
frequency for unit loop gain. This sets the compensation mid-band gain at a value calculated in Equation 62.  
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1
1
KCOMP  
=
=
= 0.356  
KCO  
2.80  
(62)  
(63)  
To set the mid-band gain of the error amplifier to KCOMP use Equation 63.  
R7  
51.1kW  
R4 = R7´KCOMP  
=
=
= 18.2kW  
KCO  
2.80  
R4 = 18.7 kΩ selected.  
Place the zero at 10th the desired cross-over frequency.  
10 10  
2p´ f ´R4 2p´ 30kHz ´18.7kW  
C2 =  
=
= 2837pF  
L
(64)  
C2 = 2200 pF selected.  
Place a high-frequency pole at about 5 times the desired cross-over frequency and less than one-half the unity  
gain bandwidth of the error amplifier:  
1
1
C4 »  
=
10p´ f ´R4 10p´ 30kHz ´18.7kW  
= 56.74pF  
L
(65)  
(66)  
1
1
C4 >  
=
p´ GBW ´R4 p´1.5MHz ´18.7kW  
= 11.35pF  
C4 = 47 pF selected.  
R-C Oscillator  
The R-C oscillator calculation is given as shown in Equation 5, in the datasheet substituting 100 for CT and 600  
for fSW. For a 600-kHz switching frequency, a 100-pF capacitor is selected and a 262-kΩ resistor is calculated  
(261 kΩ selected)  
Soft-Start Capacitor  
Since VDD > 8V, the soft-start capacitor is selected by using Equation 67 to calculate the value.  
-6  
C
= 20´ T ´10  
SS  
SS  
(67)  
For TSS = 12 ms, CSS = 240 nF, a 220-nF capacitor selected.  
Regulator Bypass  
A regulator bypass capacitor of 1.0-µF is selected per the datasheet recommendation.  
Copyright © 2008, Texas Instruments Incorporated  
Submit Documentation Feedback  
31  
Product Folder Link(s): TPS40210 TPS40211  
 
 
TPS40210, TPS40211  
SLUS772B–MARCH 2008–REVISED JUNE 2008.......................................................................................................................................................... www.ti.com  
TEST DATA  
GAIN AND PHASE  
vs  
FREQUENCY  
FET VDS and VGS VOLTAGES  
vs  
TIME  
80  
60  
180  
135  
90  
V
V
I
= 8 V  
IN  
OUT  
= 24 V  
GDRV  
(5 V/ div)  
= 2 A  
Phase  
OUT  
40  
20  
45  
0
0
Gain  
-20  
-40  
-60  
-80  
-45  
-90  
-135  
-180  
FET Vds  
(20 V/ div)  
100  
1000  
10 k 100 k  
– Frequency – Hz  
1 M  
f
SW  
T – Time – 400 ns  
Figure 31.  
Figure 32.  
EFFICIENCY  
vs  
LOAD CURRENT  
POWER LOSS  
vs  
LOAD CURRENT  
100  
6
5
V
= 8 V  
V
(V)  
V
(V)  
IN  
IN  
IN  
V
= 14V  
98  
96  
IN  
14  
12  
8
14  
12  
8
94  
92  
90  
4
3
2
V
= 12 V  
IN  
V
= 12 V  
IN  
88  
86  
V
= 8 V  
IN  
V
= 14 V  
IN  
84  
82  
80  
1
0
0
0.5  
1.0 1.5  
– Load Current – A  
2.0  
2.5  
0
0.5  
1.0  
1.5  
2.0  
2.5  
I
I
– Load Current – A  
LOAD  
LOAD  
Figure 33.  
Figure 34.  
32  
Submit Documentation Feedback  
Copyright © 2008, Texas Instruments Incorporated  
Product Folder Link(s): TPS40210 TPS40211  
TPS40210, TPS40211  
www.ti.com .......................................................................................................................................................... SLUS772B–MARCH 2008–REVISED JUNE 2008  
OUTPUT VOLTAGE  
vs  
LOAD CURRENT  
24.820  
V
(V)  
14  
IN  
24.772  
12  
8
24.724  
24.676  
24.628  
24.580  
V
= 8 V  
IN  
V
= 14 V  
IN  
24.532  
24.484  
V
= 12 V  
IN  
24.436  
24.388  
24.340  
0
0.5  
1.0 1.5  
– Load Current – A  
2.0  
2.5  
I
LOAD  
Figure 35.  
List of Materials  
List of Materials  
REFERENCE  
DESIGNATOR  
PART  
NUMBER  
MANUFAC-  
TURER  
DESCRIPTION  
SIZE  
C1  
C2  
C3  
C4  
C5  
C7  
C8  
C9  
C10  
D1  
L1  
100 µF, aluminum capacitor, SM, ± 20%, 35 V  
2200 pF, ceramic capacitor, 25 V, X7R, 20%  
100 pF, ceramic capacitor, 16 V, C0G, 10%  
47 pF, ceramic capacitor, 16V, X7R, 20%  
0.22 µF, ceramic capacitor, 16 V, X7R, 20%  
1.0 µF, ceramic capacitor, 16 V, X5R, 20%  
10 µF, ceramic capacitor, 25 V, X7R, 20%  
0.1 µF, ceramic capacitor, 50 V, X7R, 20%  
100 pF, ceramic capacitor, 16 V, X7R, 20%  
Schottky diode, 3 A, 40 V  
0.406 x 0.457  
0603  
EEEFC1V101P  
Panasonic  
Std  
Std  
Std  
Std  
Std  
Std  
0603  
Std  
0603  
Std  
0603  
Std  
0603  
Std  
0805  
C3225X7R1E106M  
TDK  
Std  
0603  
Std  
Std  
0603  
Std  
SMC  
MBRS340T3  
On Semi  
TDK  
Vishay  
Std  
10 µH, inductor, SMT, 7.5 A, 12.4 mΩ  
MOSFET, N-channel, 40 V, 14 A, 9mΩ  
10 kΩ, chip resistor, 1/16 W, 5%  
0.325 x 0.318 inch RLF12560T-100M-7R5  
Q1  
R3  
R4  
R5  
R6  
R7  
R9  
R10  
R11  
U1  
SO-8  
0603  
0603  
0603  
0603  
0603  
0603  
0603  
1812  
DGQ10  
Si4840DY  
Std  
18.7 kΩ, chip resistor, 1/16 W, 1%  
Std  
Std  
1.5 kΩ, chip resistor, 1/16 W, 1%  
Std  
Std  
261 kΩ, chip resistor, 1/16 W, 1%  
Std  
Std  
51.1 kΩ, chip resistor, 1/16 W, 1%  
Std  
Std  
3.3 Ω, chip resistor, 1/16 W, 5%  
Std  
Std  
Std  
1.0 kΩ, chip resistor, 1/16 W, 5%  
Std  
10 mΩ, chip resistor, 1/2 W, 2%  
Std  
Std  
IC, 4.5 V-52 V I/P, current mode boost controller  
TPS40210DGQ  
TI  
Copyright © 2008, Texas Instruments Incorporated  
Submit Documentation Feedback  
33  
Product Folder Link(s): TPS40210 TPS40211  
TPS40210, TPS40211  
SLUS772B–MARCH 2008–REVISED JUNE 2008.......................................................................................................................................................... www.ti.com  
DESIGN EXAMPLE 2  
12-V Input, 700-mA LED Driver, Up to 35-V LED String  
Application Schematic  
L1  
V
IN  
D1  
B2100  
R2  
GDRV  
ISNS  
C3  
C4  
C21  
C1  
C2  
R1  
R11  
V
IN  
R3  
D2  
U1  
C8  
TPS40211  
1
2
3
4
5
RC  
VIN 10  
C10  
C9  
C11  
SS  
BP  
9
8
7
6
Loop  
Response  
Injection  
DIS/EN  
DIS/EN GDRV  
GDRV  
LEDC  
ISNS  
C6  
COMP  
FB  
ISNS  
GND  
R4  
C6  
R23  
R13  
R24  
C13  
LEDC  
R6  
D3  
R15  
C14  
PWM Dimming  
UDG-08015  
Figure 36. 12-V Input, 700-mA LED Driver, Up to 35-V LED String  
34  
Submit Documentation Feedback  
Copyright © 2008, Texas Instruments Incorporated  
Product Folder Link(s): TPS40210 TPS40211  
TPS40210, TPS40211  
www.ti.com .......................................................................................................................................................... SLUS772B–MARCH 2008–REVISED JUNE 2008  
List of Materials  
List of Materials  
REFERENCE  
DESIGNATOR  
TYPE  
DESCRIPTION  
SIZE  
C1,C2  
10 µF, 25 V  
2.2 µF, 100 V  
1 nF, NPO  
100 pF, NPO  
100 pF  
1206  
1210  
0603  
0603  
0603  
0603  
0805  
1206  
0603  
0603  
C3, C4  
C5  
C6  
C8  
C9  
Capacitor  
0.1 µF  
C10  
C11  
C13  
C14  
C21  
D1  
0.1 µF, 25 V  
1 µF, 25 V  
220 pF  
10 nF, X7R  
330µF, 25V electrolytic  
B2100, SHTKY, 100 V, 2 A  
SMB  
SOD-123  
SOT-23  
12 × 12 × 10 mm  
SO-8  
D2  
Diode  
BZT52C43  
D3  
MMBD7000  
L1  
Inductor  
Wurth 7447709100, 10 µH, 6 A  
Q1  
Si7850DP, 60 V, 31 mΩ  
2N7002, 60 V, 0.1 A  
15 mΩ  
MOSFET  
Q3  
SOT-23  
2512  
R1  
R2  
3.01 Ω  
0805  
R3  
402 kΩ  
0603  
R4  
14.3 kΩ  
0603  
R6  
0.36 Ω  
2512  
Resistor  
R11  
R13  
R15  
R24  
R23  
U1  
1 kΩ  
0603  
30.1 kΩ  
0603  
49.9 kΩ  
0603  
10 kΩ  
0603  
10 Ω  
0603  
Integrated circuit  
TPS40211  
DRC-10  
Copyright © 2008, Texas Instruments Incorporated  
Submit Documentation Feedback  
35  
Product Folder Link(s): TPS40210 TPS40211  
PACKAGE OPTION ADDENDUM  
www.ti.com  
11-Jul-2008  
PACKAGING INFORMATION  
Orderable Device  
Status (1)  
Package Package  
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)  
Qty  
Type  
Drawing  
TPS40210DGQ  
ACTIVE  
MSOP-  
Power  
PAD  
DGQ  
10  
10  
10  
80 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
TPS40210DGQR  
ACTIVE  
ACTIVE  
MSOP-  
Power  
PAD  
DGQ  
DGQ  
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
TPS40210DGQRG4  
MSOP-  
Power  
PAD  
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
TPS40210DRCR  
TPS40210DRCRG4  
TPS40210DRCT  
TPS40211DGQ  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
SON  
SON  
SON  
DRC  
DRC  
DRC  
DGQ  
10  
10  
10  
10  
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR  
no Sb/Br)  
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR  
no Sb/Br)  
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR  
no Sb/Br)  
MSOP-  
Power  
PAD  
80 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
TPS40211DGQR  
ACTIVE  
ACTIVE  
MSOP-  
Power  
PAD  
DGQ  
DGQ  
10  
10  
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
TPS40211DGQRG4  
MSOP-  
Power  
PAD  
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
TPS40211DRCR  
TPS40211DRCRG4  
TPS40211DRCT  
ACTIVE  
ACTIVE  
ACTIVE  
SON  
SON  
SON  
DRC  
DRC  
DRC  
10  
10  
10  
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR  
no Sb/Br)  
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR  
no Sb/Br)  
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR  
no Sb/Br)  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in  
a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2)  
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check  
http://www.ti.com/productcontent for the latest availability information and additional product content details.  
TBD: The Pb-Free/Green conversion plan has not been defined.  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements  
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered  
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and  
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS  
compatible) as defined above.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame  
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)  
(3)  
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder  
temperature.  
Addendum-Page 1  
PACKAGE OPTION ADDENDUM  
www.ti.com  
11-Jul-2008  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is  
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the  
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take  
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on  
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited  
information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI  
to Customer on an annual basis.  
Addendum-Page 2  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
28-Jun-2008  
TAPE AND REEL INFORMATION  
*All dimensions are nominal  
Device  
Package Package Pins  
Type Drawing  
SPQ  
Reel  
Reel  
A0 (mm)  
B0 (mm)  
K0 (mm)  
P1  
W
Pin1  
Diameter Width  
(mm) W1 (mm)  
(mm) (mm) Quadrant  
TPS40210DGQR  
MSOP-  
Power  
PAD  
DGQ  
10  
2500  
330.0  
12.4  
5.3  
3.3  
1.3  
8.0  
12.0  
Q1  
TPS40210DRCR  
TPS40210DRCT  
TPS40211DGQR  
SON  
SON  
DRC  
DRC  
DGQ  
10  
10  
10  
3000  
250  
330.0  
180.0  
330.0  
12.4  
12.4  
12.4  
3.3  
3.3  
5.3  
3.3  
3.3  
3.3  
1.1  
1.1  
1.3  
8.0  
8.0  
8.0  
12.0  
12.0  
12.0  
Q2  
Q2  
Q1  
MSOP-  
Power  
PAD  
2500  
TPS40211DRCR  
TPS40211DRCT  
SON  
SON  
DRC  
DRC  
10  
10  
3000  
250  
330.0  
180.0  
12.4  
12.4  
3.3  
3.3  
3.3  
3.3  
1.1  
1.1  
8.0  
8.0  
12.0  
12.0  
Q2  
Q2  
Pack Materials-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
28-Jun-2008  
*All dimensions are nominal  
Device  
Package Type Package Drawing Pins  
SPQ  
Length (mm) Width (mm) Height (mm)  
TPS40210DGQR  
TPS40210DRCR  
TPS40210DRCT  
TPS40211DGQR  
TPS40211DRCR  
TPS40211DRCT  
MSOP-PowerPAD  
DGQ  
DRC  
DRC  
DGQ  
DRC  
DRC  
10  
10  
10  
10  
10  
10  
2500  
3000  
250  
370.0  
346.0  
190.5  
370.0  
346.0  
190.5  
355.0  
346.0  
212.7  
355.0  
346.0  
212.7  
55.0  
29.0  
31.8  
55.0  
29.0  
31.8  
SON  
SON  
MSOP-PowerPAD  
SON  
2500  
3000  
250  
SON  
Pack Materials-Page 2  
IMPORTANT NOTICE  
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