TPS40400_技术文档

TPS40400

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SLUS930B –APRIL 2011–REVISED OCTOBER 2011

3.0-V TO 20-V PMBus SYNCHRONOUS BUCK CONTROLLER

Check for Samples: TPS40400

1

FEATURES

APPLICATIONS

2

•

Input Operating Voltage Range: 3 V to 20 V

PMBus Enabled Analog Controller

Reference 600 mV ± 1%

•

Smart Power Systems

Power Supply Modules

Communications Equipment

Computing Equipment

•

Remote Voltage Sense Amplifier

Internal 6-V Regulator and 6-V Gate Drive

Programmable Overcurrent Protection

DESCRIPTION

The TPS40400 is

a

cost-optimized flexible

Inductor Resistance or Series Resistance

Used for Current Sensing

synchronous buck controller that operates from a

nominal 3 V to 20 V supply. This controller is an

analog PWM controller that allows programming and

monitoring via the PMBus interface. Flexible features

found on this device include programmable soft-start

time, programmable short circuit limit and

programmable undervoltage lockout (UVLO).

•

Programmable Switching Frequency: 200 kHz

to 2 MHz

•

Powergood Indicator

Thermal Shutdown

Programmable Soft-Start

Internal Bootstrap Diode

Pre-bias Output Safe

24-Pin QFN Package

XXspacerXX

XXXX

SMBALRT

DATA

V_IN

CLK

CNTL

1

2

3

4

5

6

CLK

DATA 24

SMBALRT 23

ADDR1 22

ADDR0 21

VDD 20

CNTL

PGOOD

SYNC

PGOOD

SYNC

TRACK

COMP

TRACK

HDRV 19

TPS40400

7

8

FB

BOOT 18

SW 17

V_OUT

+

–

DIFFO

9

VSNS+

LDRV 16

GND 15

V_OUT

10 VSNS–

11 ISNS–

ISNS+

12

BP6 14

BP3

SGND

25

13

SNS+

SNS–

UDG-09073

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2

SwitcherPro is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

TPS40400

SLUS930B –APRIL 2011–REVISED OCTOBER 2011

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DESCRIPTION (CONTINUED)

An adaptive anti-cross conduction scheme is used to prevent shoot through current in the power FETs. Gate

drive voltage is 6 V to better enhance the power FETs for reduced losses. Short circuit detection is done by

sensing the voltage drop across the inductor or across a resistor placed in series with the inductor. A PMBus

programmable threshold is compared to this voltage and is used to detect overcurrent. When the overcurrent

threshold is reached, a pulse by pulse current limit scheme is used to limit current to acceptable levels. If the

overcurrent condition persists for more than 7 clock cycles of the converter, a fault condition is declared and the

converter shuts down and goes into either a hiccup restart mode or latches off. The behavior is selectable though

the PMBus interface. Other PMBus interface features include programmable operating frequency, soft-start time,

overvoltage and undervoltage thresholds and the response to those events, output voltage change including

margining as well as status monitoring.

ORDERING INFORMATION⁽¹⁾⁽²⁾

PACKAGE

PINS

TAPE AND REEL QTY. ORDERABLE NUMBER

250

TPS40400RHLT

TPS40400RHLR

Plastic QFN (RHL)

24

3000

(1) For the most current package and ordering information see the Package Option Addendum at the end

of this document, or see the TI web site at www.ti.com.

(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.

ABSOLUTE MAXIMUM RATINGS

VALUE

MIN

MAX

22

27

30

7

UNIT

VDD

–0.3

–5

SW

BOOT

–0.3

–40

BOOT-SW, HDRV-SW (Differential from BOOT or HDRV to SW)

Input voltage range

V

VSNS+, TRACK, SYNC, FB

DATA, CLK, CNTL

ISNS+, ISNS–

7

3.6

15

0.3

30

3.8

7

VSNS–

HDRV

BP3

Output voltage range

V

BP6, COMP, PGOOD, DIFFO, LDRV

SMBALRT, ADDR0

3.6

150

T_JOperating junction temperature range

T_STGStorage temperature range

°C

–55

PACKAGE DISSIPATION RATINGS⁽¹⁾

THERMAL IMPEDANCE

JUNCTION-TO-AMBIENT

T_A= 25°C

POWER RATING

(W)

T_A= 85°C

POWER RATING

(W)

PACKAGE

AIRFLOW

(°C/W)

31.1

25.2

23

Natural Convection

200 LFM

3.21

3.96

4.36

1.29

1.58

1.74

24-Pin Plastic

QFN (RHL)

400 LFM

(1) Ratings based on JEDEC High Thermal Conductivity (High K) Board. For more information on the test method, see TI Technical Brief

SZZA017.

RECOMMENDED OPERATING CONDITIONS

MIN

3.0

TYP

MAX

20

UNIT

V

VDD

T_J

Input operating voltage

Operating junction temperature

–40

125

°C

2

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SLUS930B –APRIL 2011–REVISED OCTOBER 2011

ELECTROSTATIC DISCHARGE PROTECTION

MIN

TYP

2500

1500

MAX

UNIT

V

Human Body Model (HBM)

Charged Device Model (CDM)

V

ELECTRICAL CHARACTERISTICS

Unless otherwise stated, these specifications apply for –40°C ≤ T_J≤ 125°C, V_DD= 12 Vdc, FREQUENCY_SWITCH = 600 kHz

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

INPUT SUPPLY

V_VDD

I_VDD

Input voltage range

3

20

15

V

Input operating current

Switching, no driver load

6

mA

VOLTAGE REFERENCE

V_FB

Feedback pin voltage default settings

-40ºC ≤ T_J≤ 125ºC

594

600

750

450

2.34

606

mV

V_FB(max)

V_FB(min)

V_FB(inc)

Feedback pin voltage maximum adjustment

Feedback pin voltage minimum adjustment

Feedback pin voltage adjustment resolution

Maximum nonlinearity error over adjustment

range

V_FB(NL)

10

mV

BP6 REGULATOR

V_BP6

V_DO6

I_BP6

6-V regulator output voltage

6.2

100

3.1

6.5

6.8

V

Regulator dropout voltage, (V_VDD– V_BP6

)

V_VDD= 6 V, I_BP6= 50 mA

300

mV

mA

Regulator current limit

BP3 REGULATOR

V_BP3

3.3-V regulator output voltage

3.3

3.5

V

V_DO3

Regulator dropout voltage, (V_VDD– V_BP3

)

V_VDD= 3V, I_BP3= 5 mA

100

200

mV

OSCILLATOR

f_SW

Switching frequency

Factory default setting

480

200

600

720

2000

20%

kHz

Nominal frequency range

Accuracy

3 V ≤ V_VDD≤ 20 V, 200 kHz ≤ f_SW≤ 2 MHz

–20%

2.0

V_IH

V_IL

SYNC high-level input voltage

SYNC low-level input voltage

V

0.4

100

V_SYNC= 6 V

V_SYNC= 0 V

I_SYNC

SYNC pin leakage current

nA

t_SRISE

t_SYNC

Maximum SYNC rise time⁽¹⁾

Minimum SYNC pulse width

100

ns

V

FREQUENCY_SWITCH = 200 kHz

FREQUENCY_SWITCH = 600 kHz

FREQUENCY_SWITCH = 2000 kHz

V_VDD/6.6 V_VDD/6.5

V_VDD/7.0 V_VDD/6.8

V_VDD/10 V_VDD/9.6

0.9

V_VDD/6.3

V_VDD/6.6

V_VDD/9.2

V_RMP

Ramp amplitude⁽¹⁾

Valley voltage⁽¹⁾

V_VLY

f_SYNC

SYNC range % of nominal oscillator frequency

200 kHz ≤ f_SW≤ 2 MHz

85%

150%

PULSE WIDTH MODULATOR (PWM)

FREQUENCY_SWITCH = 600 kHz

FREQUENCY_SWITCH = 1.2 MHz

FREQUENCY_SWITCH = 2 MHz

90%

85%

75%

170

(2)

D_MAX

Maximum duty cycle⁽¹⁾

t_OFF(min)

t_ON(min)

Minimum OFF time

225

75

ns

Minimum controllable pulse⁽¹⁾

T_J= 25°C, f_SW= 600 kHz

(1) Ensured by design. Not production tested.

(2) Operation at 3 V reduces maximum duty cycle by approximately 5%.

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ELECTRICAL CHARACTERISTICS (continued)

Unless otherwise stated, these specifications apply for –40°C ≤ T_J≤ 125°C, V_DD= 12 Vdc, FREQUENCY_SWITCH = 600 kHz

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

SOFT-START

(3)

Soft-start time

Accuracy

Factory default setting

2.7

3.1

3.5

ms

t_SS

600 μs ≤ t_SS≤ 9 ms

–15%

15%

ERROR AMPLIFIER

GBWP

A_OL

Gain bandwidth product⁽⁴⁾

DC gain⁽⁴⁾

15

60

0

20

MHz

dB

I_IBFB

Input bias current: FB (out of pin)

Input bias current: TRACK (out of pin)

Output source current

100

250

nA

I_IBT

0

nA

I_EAOP

V_FB= 0 V, V_COMP≥ 2 V

V_FB= 2 V, V_COMP≤ 0.3 V

V_FB= 0 V

1

mA

I_EAOM

Output sink current

1

V_COMPH

V_COMPL

V_TRACK(ofst)

Error amplifier high output voltage

Error amplifier low output voltage

TRACK pin offset voltage

3.8

V

V_FB= 2 V

50

+5

mV

–5

CURRENT SENSE AMPLIFIER

I_ISNS+

I_ISNS–

V_ICM

ISNS+ bias current

200

100

15

nA

μA

V

ISNS– bias current

Input common mode range

Common mode gain

Input linear range, VISNS+ - VISNS-⁽⁵⁾

0.45

AO_CM

V_LIN

–80

110

dB

mV

–45

CURRENT LIMIT PROTECTION

t_OFF

Off time between restart attempts

_CS+– V_CS–voltage that trips OC fault function

6 × t_SS

ms

V

Factory default settings⁽⁵⁾, T_J= 25°C

27

30

33

mV

3 V ≤ V_VDD≤ 20 V,

30 mV ≤ V_ILIMTH≤ 110 mV, T_J= 25°C

–10%

10%

Threshold accuracy

V_ILIMTH

t_DLYOC

V_ILIMW

t_DLYOCW

3V ≤ V_VDD≤ 20 V, V_ILIMTH≤ 30 mV,

T_J= 25°C

–3

3

mV

Comparator offset

Temperature coefficient⁽⁴⁾

V_ILIMTH= 30 mV, T_J= 25°C

mV

ppm/°C

ns

4000

155

15

Overcurrent delay

3-mV overdrive, T_J= 25°C

V_CS+– V_CS–voltage that sets warning status

Factory default settings, T_J= 25°C

12

18

mV

3 V ≤ V_VDD≤ 20V,

1.9 mV ≤ V_ILIMTH≤ 120 mV, T_J= 25°C

–10%

10%

Threshold accuracy

3V ≤ V_VDD≤ 20 V, V_ILIMTH< 30 mV,

T_J= 25°C

–3

3

mV

Comparator offset

V_ILIMTH= 20 mV, T_J= 25°C

mV

ppm/°C

ns

Temperature coefficient⁽⁴⁾

Overcurrent warning delay⁽⁴⁾

4000

250

3-mV overdrive

(3) See applications section for more information regarding soft-start time setting.

(4) Ensured by design. Not production tested.

(5) The entire current ripple waveform must reside inside the linear range for current reading results to be accurate. DC current level must

be zero or greater for accurate results. Current sense does not support applications that sink current. Transient voltages (such as ripple)

are permitted to go below 0 V, but must be within the specified linear range.

4

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SLUS930B –APRIL 2011–REVISED OCTOBER 2011

ELECTRICAL CHARACTERISTICS (continued)

Unless otherwise stated, these specifications apply for –40°C ≤ T_J≤ 125°C, V_DD= 12 Vdc, FREQUENCY_SWITCH = 600 kHz

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

OUTPUT DRIVERS

R_HDHI

R_HDLO

(V_BOOT– V_SW) = 6.4 V, I_HDRV= –100 ,

T_J= 25°C

High-side driver pull up resistance

High-side driver pull down resistance

1.25

1.3

2.5

2.6

(V_BOOT– V_SW) = 6.4 V, I_HDRV= 100 mA,

T_J= 25°C

Ω

R_LDHI

R_LDLO

t_HRISE

t_HFALL

t_LRISE

t_LFALL

Low-side driver pull up resistance

Low-side driver pull down resistance

T_J= 25°C

1.25

0.8

6

2.5

1.5

(6)

High-side driver rise time

12.1

12.6

12.1

8

(6)

High-side driver fall time

6.3

6

C_LOAD= 2.2 nF

ns

(6)

Low-side driver rise time

(6)

Low-side driver fall time

4

MFR_SPECIFIC_00 bit 0 = 0,

(short dead time.)

t_DT

Anti-cross conduction time

20

50

1

ns

I_SW

SW pin leakage current (out of pin)

V_SW= 0 V

μA

BOOTSTRAP

V_BOOT

Internal diode voltage drop

BOOT diode leakage current⁽⁶⁾

I_BOOT= 5 mA

0.7

1

V

I_BOOT(lk)

UVLO

(V_BOOT– V_SW) = 6 V

μA

VDD UVLO turn on threshold⁽⁷⁾

Accuracy⁽⁷⁾

Factory default settings (minimum)

2.475

–10%

2.25

2.750

2.5

3.025

10%

2.75

10%

V_UVLO(on)

V

2.25 V ≤ V_VDD≤ 20 V,

2.75 V ≤ VIN_ON ≤ 18 V

VDD UVLO turn off threshold⁽⁷⁾

Accuracy⁽⁷⁾

Factory default settings (minimum)

V_UVLO(off)

2.25 V < V_VDD< 20 V,

2.75 V < VIN_OFF < 17.6 V

–10%

REMOTE VOLTAGE SENSE AMPLIFIER

V_IOFST

R_GAIN

Input offset voltage

Gain setting resistor⁽⁶⁾

–10

10

72

mV

48

60

kΩ

V_VDD> 6.5 V

0

6

V_DIFFO

Output voltage at DIFFO pin

V_VDD= 5 V

V_VDD= 3 V

0

4.5

V

0

2.5

K_DIFF

Differential gain of amplifier

Closed loop bandwidth⁽⁶⁾

Output source current

Output sink current

0.995

1.000

1.005

V/V

MHz

mA

V_AGBWP

I_VAOP

2

1

V_SNS+= V_DIFFO= 5 V, V_SNS–= 0 V

I_VAOM

V_SNS+= 0 V, V_SNS–= 4.5 V, V_DIFFO= 5 V

mA

POWERGOOD

FB pin voltage upper limit for power good on

FB pin voltage lower limit for power good on

Accuracy

648

552

Factory default settings

540 mV < V_PGON< 660 mV

Factory default settings

mV

V_PGON

–5%

5%

FB pin voltage upper limit for power good off

FB pin voltage lower limit for power good off

Accuracy

660

540

V_PGOFF

528 mV < V_PGOFF< 672 mV

–5%

5%

50

R_PGD

I_PGDLK

t_PGD

Pull down resistance of PGD pin

V_FB= 0, I_PGOOD= 5 mA

Ω

μA

μs

Factory default settings ,

550 mV < V_FB< 650 mV, V_PGOOD= 5 V

Leakage current

3

15

Delay filter from FB⁽⁶⁾

5

(6) Ensured by design. Not production tested.

(7) Although specifications appear to overlap, hysteresis is assured for UVLO turn on and turn off thresholds.

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ELECTRICAL CHARACTERISTICS (continued)

Unless otherwise stated, these specifications apply for –40°C ≤ T_J≤ 125°C, V_DD= 12 Vdc, FREQUENCY_SWITCH = 600 kHz

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

OUTPUT VOLTAGE MARGINING

(8)

VFB slope during margin voltage transition

Accuracy

Factory default settings

250

–15%

650

214

188

15%

670

548

758

455

V/s

MRG_SLP

3 V < V_VDD< 20 V, 600 μs < t_SS< 9 ms

Factory default settings

–40°C < T_J< 125°C

V_FBMH

FB pin voltage after margin high command

FB pin voltage after margin low command

Maximum FB pin voltage with Margin

Minimum FB pin voltage with Margin

Resolution of FB steps with margin

660

540

750

450

2.34

mV

V_FBML

532

V_FBM(max)

V_FBM(min)

V_FB(inc)

742

–40°C < T_J< 125°C

445

OVERVOLTAGE AND UNDERVOLTAGE DETECTION

FB pin overvoltage threshold (OV flag)

Factory default settings

638

–5%

502

672

528

705

5%

V_OV

mV

Accuracy

3 V < V_VDD< 20 V, 648 mV < V_OV< 690 mV

Factory default settings

FB pin undervoltage threshold (UV flag)

554

V_UV

3 V < V_VDD< 20 V,

510 mV < V_OV< 552 mV

Accuracy

–5%

5%

PMBus INTERFACE

V_IH

V_IL

High-level input voltage, CLK, DATA, CNTL

2.1

V

Low-level input voltage, CLK, DATA, CNTL

High-level input current, CLK, DATA, CNTL

CNTL

0.8

10

0.4

–10

–12

–10

–12

I_IH

μA

Low-level input current, CLK, DATA, CNTL

CNTL

I_IL

V_OL

I_OH

C_O

Low-level output voltage, DATA, SMBALRT

3.0 V ≤ V_VDD≤ 20 V, I_OUT= 2 mA

V

High-level open drain leakage current, DATA,

SMBALRT

V_OUT= 3.6 V

0

10

μA

(8)

Pin capacitance, CLK, DATA

0.7

pF

kHz

μs

f_PMB

PMBus operating frequency range

Bus free time between START and STOP⁽⁸⁾

Hold time after repeated START⁽⁸⁾

Repeated START setup time⁽⁸⁾

STOP setup time⁽⁸⁾

Slave mode

10

4.7

4.0

4.7

4.0

0

400

t_BUF

t_HD:STA

t_SU:STA

t_SU:STO

μs

Receive mode

Transmit mode

t_HD:DAT

Data hold time⁽⁸⁾

ns

300

250

25

t_SU:DAT

t_TIMEOUT

t_LOW:MEXT

t_LOW:SEXT

t_LOW

Data setup time⁽⁸⁾

Error signal/detect⁽⁸⁾

Cumulative clock low master extend time⁽⁸⁾

Cumulative clock low slave extend time⁽⁸⁾

Clock low time⁽⁸⁾

Clock high time⁽⁸⁾

CLK/DATA fall time⁽⁸⁾

CLK/DATA rise time⁽⁸⁾

ns

μs

ns

35

50

25

4.7

4.0

t_HIGH

t_FALL

300

t_RISE

1000

PMBus ADDRESSING

I_ADD

ADDX pin current

Address pin illegal low voltage threshold

8.23

9.75

11.21

0.055

μA

V_ADD(L)

V

(8) Ensured by design. Not production tested.

6

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SLUS930B –APRIL 2011–REVISED OCTOBER 2011

ELECTRICAL CHARACTERISTICS (continued)

Unless otherwise stated, these specifications apply for –40°C ≤ T_J≤ 125°C, V_DD= 12 Vdc, FREQUENCY_SWITCH = 600 kHz

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

MEASUREMENT SYSTEM

(9)

t_IDLY

Read delay time

153

192

122

231

μs

μV

mV

(10) (11)

I_RES

Current measurement resolution (LSB)

Current measurement range⁽¹¹⁾

Gain accuracy⁽¹³⁾

(12)

I_RNG

–45

–3%

–3

110

3%

3

I_ACC

I_OFST

Offset

mV

V

V_OUT(res)

V_OUT(rng)

V_OUT(gain)

V_{OUT(gain_adj)}

V_OUT(ofst)

V_{OUT(ofst_adj)}

V_IN(res)

VOUT measurement resolution (LSB)

VOUT voltage measurement range

Gain accuracy^(13)(14)

15.625

0

–2

14

2

LSB

Gain adjustment range through PMBus

Offset^(13)(14)

–10%

–3%

–125

10%

3%

124

Gain adjustment range through PMBus

V_INmeasurement resolution

V_INvoltage measurement range

Gain accuracy^(13)(14)

mV

V

32.5

V_IN(rng)

3.0

–2%

–10%

–5.5

–2

20

2%

V_IN(gain)

V_{IN(gain_adj)}

V_IN(offst)

V_{IN(offst_adj)}

Gain adjustment range through PMBus

Offset^(13)(14)

10%

1.4

–2

LSB

V

Offset adjustment range through PMBus

1.968

THERMAL SHUTDOWN

T_JSD

Junction OT shutdown temperature⁽¹⁴⁾

Shutdown hysteresis⁽¹⁴⁾

Junction OT warning threshold⁽¹⁴⁾

Junction OT warning temperature hysteresis⁽¹⁴⁾

135

25

145

30

155

35

°C

T_JSDH

T_JWRN

T_JWRNH

120

15

130

20

140

25

(9) All read backs are an average of 16 consecutive measurements – not a rolling average. Time is a delay between parameter updates.

(10) Constrained by the resolution of READ_IOUT command. This presents as the greater of 122 µV/ IOUT_CAL_GAIN or 62.5 mA, the

resolution of the READ_IOUT command

(11) Voltage is converted to current by dividing by IOUT_CAL_GAIN, the effective value of the resistance used to sense current in the

application. Maximum amount that can be reported via PMBus is 64A.

(12) Current reading is only supported to 0 average. Voltage transients to –45mV are taken into account when computing this average.

(13) PMBus commands provide for calibration of each device on an individual basis for improved overall system accuracy.

(14) Ensured by design. Not production tested.

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DEVICE INFORMATION

RHL PACKAGE

BOTTOM VIEW

DATA

CLK

24

1

SMBALRT

23

22

21

20

19

18

17

16

15

14

2

3

CNTL

ADDR1

ADDR0

VDD

PGOOD

SYNC

TRACK

COMP

FB

4

5

TPS40400

HDRV

6

BOOT

SW

7

TM

PowerPAD

8

DIFFO

VSNS+

VSNS–

ISNS–

SGND

LDRV

GND

9

10

11

BP6

13

12

BP3

ISNS+

PIN FUNCTIONS

NAME

I/O

DESCRIPTION

NO.

Low-order address pin for PMBus address configuration. One of eight resistor values must be connected from

this pin to SGND to select the low-order octal digit in the PMBus address.

ADDR0

ADDR1

BOOT

BP3

21

I

High-order address pin for PMBus address configuration. One of eight resistor values must be connected from

this pin to SGND to select the high-order octal digit in the PMBus address.

22

18

13

Gate drive voltage for the high-side N-channel MOSFET. A capacitor 100 nF typical must be connected between

this pin and SW.

I

Bypass pin for the internal regulator that supplies power to the internal controls of the device. Normal regulation

voltage is 3.3 V. Connect a 100 nF or larger capacitor from this pin to GND.

O

Bypass pin for the internal regulator that supplies power to the gate drivers. Normal regulation voltage is 6.5 V.

Connect a 1-μF or larger capacitor from this pin to GND.

BP6

14

1

O

I

CLK

Clock input for the PMBus interface

Logic level input that controls the startup and shutdown of the converter, Exact functionality is determined by

PMBus options.

CNTL

2

I

COMP

DATA

DIFFO

FB

6

24

8

O

Output of the error amplifier. Used for control loop compensation.

I/O Data I/O for the PMBus interface

O

I

Output of the unity gain remote voltage sense amplifier. Typically connected to the voltage divider on FB

Inverting input to the error amplifier. A voltage divider is connected here to sense the output voltage.

7

Common connection for the device. This pin should connect to the thermal pad under the device package and to

the power stage ground, preferably close to the source of the Low-side or rectifier FET. Connections should be

arranged so that no power level current slow across the pad connected to the thermal pad on the underside of

the device.

GND

15

–

HDRV

ISNS–

ISNS+

LDRV

19

11

12

16

O

I

Gate drive signal to the high-side FET

Inverting input to the current sense amplifier

Non-inverting input to the current sense amplifier

Output used to drive the gate of the low-side or rectifier FET.

I

O

Power good output. This is an open drain output that pulls low when any fault condition exists within the device

or when the device is not operating within a user selectable operating range of the nominal output voltage of the

converter.

PGOOD

3

O

8

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PIN FUNCTIONS (continued)

I/O

DESCRIPTION

NAME

NO.

Signal ground for the controller. Connect the ground of signal level circuits to this pin. Connections should be

arranged so that power level currents do not flow in the pad attached to the thermal plane or in the SGND

portion of the circuit.

SGND

PAD

-

SMBALRT

SW

23

17

O

I

Output used to signal that PMBus host that the controller needs attention.

This is the common connection for the flying high-side FET driver and also serve as a sense line for the adaptive

anti-cross-conduction circuitry

Logic level input to the oscillator inside the controller. The oscillator resets on the rising edge of a pulse train

applied to this pin and begin a new switching cycle.

SYNC

4

5

I

Analog input to the non inverting side of the control loop error amplifier. The error amplifier has three inputs

(voltage reference, TRACK and soft-start ramp) to it’s “+” side, and the lowest voltage applied to these three

inputs dominate and control the output voltage of the whole converter. This pin is to allow the user to configure a

voltage divider that allows the controller output follow an external reference voltage during startup.

TRACK

VDD

20

9

I

Input power connection for the device. 3.0 V to 20 V required.

Non-inverting input to the unity gain remote voltage sense amplifier.

Inverting input to the unity gain remote voltage sense amplifier.

VSNS+

VSNS–

10

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FUNCTIONAL BLOCK DIAGRAM

0 R D D A

1 R D D A

T R L A B M S

A T A D

K L C

L T N C

C N Y S

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TYPICAL CHARACTERISTICS

0.00

−0.05

−0.10

−0.15

−0.20

−0.25

−0.30

0.35

0.33

0.31

0.29

0.27

0.25

0.23

0.21

0.19

0.17

0.15

V_VDD= 3 V

V_VDD= 12 V

V_VDD= 20 V

Active Low

Active High

−40 −25 −10

5

20 35 50 65 80 95 110 125

−40 −25 −10

5

20 35 50 65 80 95 110 125

Junction Temperature (°C)

Figure 1. FB Pin Voltage Reference Variation

vs. Junction Temperature

Figure 2. CRTL Pin Hysteresis

vs. Junction Temperature

55

50

45

40

35

30

25

20

0.26

0.24

0.22

0.20

0.18

0.16

0.14

0.12

0.10

LDRV to HDRV (Short)

HDRV to LDRV

LDRV to HDRV (Long)

V_VDD= 12 V

−40 −25 −10

5

20 35 50 65 80 95 110 125

−40 −25 −10

5

20 35 50 65 80 95 110 125

Junction Temperature (°C)

Figure 3. Dead Time

vs. Junction Temperature

Figure 4. Remote Voltage Amplifier Offset

vs. Junction Temperature

1.0000

0.9999

0.9998

0.9997

0.9996

0.9995

0.3

0.2

0.1

0.0

−0.1

−0.2

−0.3

−0.4

−0.5

−0.6

−0.7

−40 −25 −10

5

20 35 50 65 80 95 110 125

−40 −25 −10

5

20 35 50 65 80 95 110 125

Junction Temperature (°C)

Figure 5. Remote Voltage Amplifier Gain

vs. Junction Temperature

Figure 6. TRACK Pin Offset Voltage

vs. Junction Temperature

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TYPICAL CHARACTERISTICS (continued)

180

160

140

120

100

80

60

50

40

30

20

10

0

V_FB= 450 mV

V_FB= 600 mV

V_FB= 750 mV

V_FB= 450 mV

V_FB= 600 mV

V_FB= 750 mV

60

−40 −25 −10

5

20 35 50 65 80 95 110 125

−40 −25 −10

5

20 35 50 65 80 95 110 125

Junction Temperature (°C)

Figure 7. TRACK Pin Input Bias Current

vs. Junction Temperature

Figure 8. FB pin Input Bias Current

vs. Junction Temperature

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

R_HDHI, V_VDD= 12 V

R_HDHI, V_VDD= 3 V

R_HDLO, V_VDD= 12 V

R_HDLO, V_VDD= 3 V

Sourcing

Sinking

−40 −25 −10

5

20 35 50 65 80 95 110 125

−40 −25 −10

5

20 35 50 65 80 95 110 125

Junction Temperature (°C)

Figure 9. Error Amplifier Output Current

vs. Junction Temperature

Figure 10. High-Side Driver Resistance

vs. Junction Temperature

MINIMUM ON-TIME

vs

JUNCTION TEMPERATURE

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

50

48

46

44

42

40

38

36

34

32

30

R_LDHI, V_VDD= 12 V

R_LDHI, V_VDD= 3 V

R_LDLO, V_VDD= 12 V

R_LDLO, V_VDD= 3 V

V_VDD= 12 V

f_SW=600 kHz

−40 −25 −10

5

20 35 50 65 80 95 110 125

−40 −25 −10

5

20 35 50 65 80 95 110 125

Junction Temperature (°C)

Figure 11. Low-Side Driver Resistance

vs. Junction Temperature

Figure 12. Minimum On-Time

vs. Junction Temperature

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TYPICAL CHARACTERISTICS (continued)

6

12

10

8

V_VDD= 12 V

FREQUENCY_SWITCH = 200 kHz

FREQUENCY_SWITCH = 600 kHz

FREQUENCY_SWITCH = 2 MHz

4

2

6

0

4

2

−2

−4

−6

0

FREQUENCY_SWITCH = 200 kHz

FREQUENCY_SWITCH = 600 kHz

FREQUENCY_SWITCH = 2 MHz

−2

V_VDD= 3 V

−4

−40 −25 −10

5

20 35 50 65 80 95 110 125

−40 −25 −10

5

20 35 50 65 80 95 110 125

Junction Temperature (°C)

Figure 13. Switching Frequency Change

vs. Junction Temperature

Figure 14. Switching Frequency Change

vs. Junction Temperature

12

10

8

13.0

12.5

12.0

11.5

11.0

10.5

10.0

9.5

6

4

2

V_PGOOD= 5 V

0

9.0

−40 −25 −10

5

20 35 50 65 80 95 110 125

−40 −25 −10

5

20 35 50 65 80 95 110 125

Junction Temperature (°C)

Figure 15. PGOOD Pin Current Leakage

vs. Junction Temperature

Figure 16. PGOOD Resistance to GND

vs. Junction Temperature

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APPLICATION INFORMATION

PMBus

General Description

Timing and electrical characteristics of the PMBus can be found in the PMB Power Management Protocol

Specification, Part 1, revision 1.1 available at http://pmbus.org. The TPS40400 supports both the 100 kHz and

400 kHz bus timing requirements. The TPS40400 does not stretch pulses on the PMBus when communicating

with the master device.

Communication over the TPS40400 device PMBus interface can either support the Packet Error Checking (PEC)

scheme or not. If the master supplies CLK pulses for the PEC byte, it is used. If the CLK pulses are not present

before a STOP, the PEC is not used.

The TPS40400 supports a subset of the commands in the PMBus 1.1 specification. Most all of the controller

parameters can be programmed using the PMBus and stored as defaults for later use. All commands that require

data input or output use the literal format. The exponent of the data words is fixed at a reasonable value for the

command and altering the exponent is not supported. Direct format data input or output is not supported by the

TPS40400. See the SUPPORTED COMMANDS section for specific details.

The TPS40400 also supports the SMBALERT response protocol. The SMBALERT response protocol is a

mechanism by which a slave (the TPS40400) can alert the bus master that it wants to talk. The master

processes this event and simultaneously accesses all slaves on the bus (that support the protocol) through the

alert response address. Only the slave that caused the alert acknowledges this request. The host performs a

modified receive byte operation to get the slave’s address. At this point, the master can use the PMBus status

commands to query the slave that caused the alert. For more information on the SMBus alert response protocol,

see the System Management Bus (SMBus) specification.

The TPS40400 contains non-volatile memory that is used to store configuration settings and scale factors. The

settings programmed into the device are not automatically saved into this non-volatile memory though. The

STORE_DEFAULT_ALL command must be used to commit the current settings to non-volatile memory as

device defaults. The settings that are capable of being stored in non-volatile memory are noted in their detailed

descriptions.

Setting up the Controller – Hardware Connections

The TPS 40400 is an analog controller, meaning that it uses traditional analog circuitry to control the output of

the converter. Many of the operating parameters are set using the PMBus interface. This section describes how

to set the controller parameters in an application.

Output voltage. The output voltage is set in a very similar to the way to a traditional analog controller using a

voltage divider from the output to the feedback (FB) pin. The output voltage must be divided down to the nominal

reference voltage of 600mV. Figure 17 shows the typical connections for the controller. The voltage at the load

can be sensed using the unity gain differential voltage sense amplifier. This provides better load regulation for

output voltages lower than 5V nominal (see electrical specifications for the maximum output voltage of the

differential sense amplifier). For output voltages above this level, connect the output voltage directly to the

junction of R1 and C1, leave DIFFO open do not connect the VSNS inputs to the output voltage. In this case, it is

also recommended to connect VSNS+ to BP3 and VSNS- to GND. If desired the differential amplifier may also

be used elsewhere in the overall system as a voltage buffer provided the electrical specifications are not

exceeded

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VSNS+

9

DIFFO

+

X1

To load supply

connections

8

C1

R3

10

R1

VSNS–

C3

R4

C2

6

7

COMP

FB

R2

UDG-09075

Figure 17. Setting the Output Voltage

The components in Figure 17 that determine the nominal output voltage are R1 and R2. R1 is normally chosen to

make the feedback compensation values (R3, R4, C1, C2 andC3) come close to readily available standard

values. R2 is then calculated in Equation 1.

æ

ç

è

ö

÷

ø

R1

- V_FB

R2 = V_FB

´

V

(

)

OUT

where

•

V_FBis the feedback voltage

V_OUTis the desired output voltage

R1 and R2 are in the same units

(1)

The feedback voltage can be changed ±25% from the nominal 600mV using PMBus commands. This allows the

output voltage to vary by the same percentage. See the PMBus Functionality and Additional Setup section for

further details. Once the output voltage is set and the values of R1 and R2 are known, the VOUT_SCALE LOOP

parameter can be calculated. This parameter is required for the PMBus interface to function properly when

making output voltage adjustments.

Voltage feed forward. The TPS40400 has input voltage feed forward that maintains a constant power stage

gain as input voltage varies and provides for very good response to input voltage transient disturbances. The

simple constant power stage gain of the controller greatly simplifies feedback loop design because loop

characteristics remains constant as the input voltage changes, unlike a buck converter without voltage feed

forward. For modeling purposes, the gain from the COMP pin to the average voltage at the input of the L-C filter

is 6V/V.

Output current limit and warning. The TPS40400 uses a differential current sense scheme to sense the output

current. The sense element can be either the series resistance of the power stage filter inductor or a separate

current sense resistor. When using the inductor series resistance as in Figure 18, a filter must be used to remove

the large AC component of voltage across the inductor and leave only the component of the voltage that appears

across the resistance of the inductor. The values of R5 and C4 for the ideal case can be found by Equation 2.

The time constant of the R-C filter should be equal to or greater than the time constant of the inductor itself. If the

time constants are equal, the voltage appearing across C4 is be the current in the inductor multiplied the inductor

resistance. The inductor ripple current is reflected in the voltage across C4 perfectly in this case and there is no

reason to have a shorter R-C time constant. The time constant of the R-C filter can be made longer than the

inductor time constant because this is a voltage mode controller and the current sensing is done for overcurrent

detection and output current reporting only. Extending the R-C filter time constant beyond the inductor time

constant lowers the AC ripple component of voltage present at the ISNS pins of the TPS40400 but leaves the

correct DC current information intact. This also delays slightly the response to an overcurrent event, but reduces

noise in the system leading to cleaner overcurrent performance and current reporting data over the PMBus

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æ

ç

è

ö

÷

ø

L

R5´ C4 ³

R

ESR

where (from Figure 18)

•

R5 and R_ESRare in Ω

C4 is in F (suggest 100 nF, 10^-7F)

L is in H

(2)

The maximum voltage that the TPS40400 is designed to accept across the ISNS pins is 110 mV. Because most

all inductors have a copper conductor and because copper has a fairly large temperature coefficient of

resistance, the resistance of the inductor and the current through the inductor should make a DC voltage less

than 110 mV when the inductor is at the maximum temperature for the converter. This also applies for the

external resistor in Figure 19. The full load output current multiplied by the sense resistor value, must be less that

110 mV at the maximum converter operating temperature.

There is also a constraint on the negative (reverse current) voltage that can be applied to the ISNS pins of the

TPS40400. The voltage differential from ISNS+ to ISNS- should not be less than –45 mV. If this condition is not

met, inaccurate results from the READ_IOUT command is the result. This is intended to be a ripple voltage

limitation. The net current through the inductor must flow towards the load from the input voltage. Current sinking,

while possible for the controller to accommodate, is not supported for overcurrent detection or for the

READ_IOUT command.

In all cases, C4 should be placed as close to the ISNS pins as possible to help avoid problems with noise.

V

IN

L

R

ISNS

C4

R5

To load

ISNS+

ISNS–

ISNS+

ISNS–

UDG-09076

UDG-09077

Figure 18. Current Sensing Using Inductor

Resistance

Figure 19. Current Sensing Using Sense Resistor

Once the current sensing method is chosen, the TPS40400 needs to be told what the resistance of the current

sense element is. This allows the proper calculation of thresholds for the overcurrent fault and warning, as well

as more accurate reporting of the actual output current. The IOUT_CAL_GAIN command is used to set the value

of the sense element resistence of the device. IOUT_OC_WARN_LIMIT and IOUT_OC_FAULT_LIMIT set the

levels for the overcurrent warning and fault levels respectively. (See the PMBus Functionality and Additional

Setup section for more details.)

Linear regulators. The TPS40400 has two on board linear regulators primarily intended to provide suitable

power for the internal circuitry of the device. These pins, BP3 and BP6 must be properly bypassed to function

properly. BP3 needs a minimum of 100nF connected to GND and BP6 should have approximately 1µF

connected to GND.

It is permissible to use the external regulator to power other circuits if desired, but care must be taken to ensure

that the loads placed on the regulators do not adversely affect operation of the controller. The main consideration

is to avoid loads with heavy transient currents that can affect the regulator outputs. Transient voltages on these

outputs could result in noisy or erratic operation of the TPS40400.

.

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Current limits must also be observed. Shorting the BP3 pin to GND damages the BP3 regulator. The BP3

regulator input comes from the BP6 regulator output. The current limit circuit on the BP6 regulator is 100 mA so

the total current drawn from both regulators must be less than that. This total current includes the TPS40400

operating current I_VDDplus the gate drive current required to drive the power FETs. The total available current

from two regulators is found in Equation 3 and Equation 4:

I

= I

- I

(

+ I

)

LIN

BP6

VDD GATE

(3)

I

_GATE= f_SW´ Q_gHIGH+ Q_gLOW

(

)

where

•

I_LINis the total current that can be drawn from BP3 and BP6 in aggregate

I_BP6is the current limit of the BP6 regulator – 100 mA minimum

I_VDDis the quiescent current of the TPS40400 – 15 mA maximum

I_GATEis the gate drive current required by the power FETs

f_SWis the switching frequency

Q_gHIGHis the total gate charge required by the high-side FET

Q_gLOWis the total gate charge required by the low-side FET

(4)

PMBus address. The PMBus specification requires that each device connected to the PMBus have a unique

address on the bus. The TPS40400 has 64 possible addresses (0 through 63 in decimal) that can be assigned

by connecting resistors from the ADDR0 and ADDR1 pins to SGND. The address is set in the form of two octal

(0-7) digits, one digit for each pin. ADDR1 is the high-order digit and ADDR0 is the low-order digit.

The E96 series resistors suggested for each digit value are shown in Table 1.

Table 1. E96 Series Resistors

DIGIT

RESISTANCE (kΩ)

0

1

2

3

4

5

6

7

10

15.4

23.7

36.5

54.9

84.5

130

200

The TPS40400 also detects values that are out of range on the ADDR0 and ADDR1 pins. If either pin is detected

as having an out of range resistance connected to it, the TPS40400 continues to respond to PMBus commands,

but at address 127, which is outside of the possible programmed addresses. It is possible but not recommended

to use the device in this condition, especially if other TPS40400 devices are present on the bus or if another

device could possibly occupy the 127 address.

PMBus connections. The TPS40400 supports both the 100 kHz and 400 kHz bus speeds. Connection for the

PMBus interface should follow the High Power DC specifications given in section 3.1.3 in the SMBus

specification V2.0 for the 400-kHz bus speed or the Low Power DC specifications in section 3.1.2. The complete

SMBus specification is available from the SMBus web site, smbus.org.

PMBus Functionality and Additional Setup

Data format.There are three data formats supported in PMBus form commands that require representation of a

literal number as their argument (commands that set thresholds, voltages or report such). A compatible device

needs to only support one of these formats. The TPS40400 supports the Linear data format only for these

commands. In this format, the data argument consists of two parts, a mantissa and an exponent. The number

represented by this argument can be expressed as shown in Equation 5.

exponent

Value = Mantissa´ 2

(5)

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Output voltage adjustment. The nominal output voltage of the converter can be adjusted using the

VOUT_TRIM command. See the VOUT_TRIM command description for the format of this command as used in

the TPS40400. The adjustment range is ±25% from the nominal output voltage. The VOUT_TRIM command is

typically used to trim the final output voltage of the converter without relying on high precision resistors being

used in Figure 17. The resolution of the adjustment is 7 bits, with a resulting minimum step size of approximately

0.4%. Note that the output margining is accomplished using this same 7 bit structure so the total combined

deviation from the nominal output for margining and VOUT_TRIM is still limited to ±25%. Exceeding this range

causes errors.

In order for the PMBus output voltage adjustments to function correctly, the VOUT_SCALE_LOOP parameter

must be set properly. VOUT_SCALE_LOOP is a PMBus command (see Supported PMBus Commands) that tells

the controller what the ratio of the voltage divider that sets the nominal output voltage is. The data for this

command is the ratio of the divider that is used to set the output voltage. From Figure 17, VOUT_SCALE_LOOP

parameter can be calculated using Equation 6.

V

FB

VOUT _SCALE _LOOP =

V

OUT(nom)

(6)

The resolution of the VOUT_SCALE_LOOP command is 0.00195, or slightly under 0.2% due to the data format

of the command (the linear data mode exponent is fixed at -9 for this command). This granularity affects the

accuracy of adjustments to the output voltage made using the PMBus (VOUT_TRIM, VOUT_MARGIN_HIGH and

VOUT_MARGIN_LOW) as well as setting the over and under voltage fault and warning levels. These commands

use the VOUT_SCALE_LOOP parameter to calculate what the reference voltage needs to be for the requested

output voltage or the thresholds referenced to the FB pin need to be for the requested warning and fault levels.

Once the VOUT_SCALE_LOOP parameter has been properly set, the commands that adjust the output voltage

functions properly. There are three possible states that the TPS4040 can be in when considering what the actual

output voltage is:

•

No output margin

Margin high

Margin low

These output states are set using the OPERATION command. The FB pin reference voltage is calculated as

follows in each of these states.

No margin voltage:

V_FB

=

VOUT _ TRIM´ VOUT _SCALE _LOOP + 0.6

(

)

(

)

(7)

(8)

Margin high voltage state:

V

=

VOUT _ MARGIN _ HIGH + VOUT _ TRIM ´ VOUT _ SCALE _ LOOP

(

)

FB

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Margin low state:

V_FB

=

VOUT _MARGIN_LOW + VOUT _ TRIM ´ VOUT _SCALE _LOOP

(

)

where

•

V_FBis the FB pin voltage

VOUT_TRIM is the offset voltage in volts to be applied to the output voltage

VOUT_SCALE_LOOP is the output voltage divider scale parameter

VOUT_MARGIN_HIGH is the requested margin high voltage

VOUT_MARGIN_LOW is the requested margin low voltage

(9)

For these conditions, the output voltage is shown in Equation 10.

æ

ç

è

ö

÷

ø

R2 + R1

(

)

V_OUT= V_FB

´

R2

where

•

V_FBis the pin voltage calculated in Equation 7

R2 and R1 are in consistent units from Figure 17

VOUT is the output voltage

(10)

NOTE

The sum of the margin and trim voltages cannot be more that ±25% from the nominal

output voltage. The FB pin voltage can deviate no more that this from the nominal 600

mV.

When using the margin commands, the transition rate between any two of the three states (margin high, no

margin and margin low) is determined by the soft start time (set by TON_RISE and the output voltage information

available to the controller using the VOUT_SCALE_LOOP command. The result is that the transition rate

between margin states is the same volts per second as the soft start ramp – assuming that the user has input the

correct value for VOUT_SCALE_LOOP.

Overcurrent thresholds. PMBus provides for adjustable overcurrent in the TPS40400. To function properly, the

TPS40400 must be given the current sensing element resistance value. This is accomplished by issuing the

IOUT_CAL_GAIN command with the argument set to the resistance of the sense element (see the

IOUT_CAL_GAIN command description). The resolution of this command is 30.5 µΩ and the range is 0 to

15.6 mΩ.

Another command, IOUT_CAL_OFFSET (see the command description) can be used to trim out offset errors in

the READ_IOUT command results, overcurrent warning and fault level thresholds. The resolution of this

command is 62.5 mA Offsets cannot be trimmed closer than half of this amount. The range for this command is

-4 A to 3.937 A. Calibrating offsets to a level greater than this is not possible.

Once these two parameters have been set the IOUT_OC_WARN_LIMIT and IOUT_OC_FAULT_LIMIT limit

commands can be used to set the overcurrent warning and fault thresholds for the converter. There are two

resolution limiting factors in setting the overcurrent thresholds. The first is the resolution available in the

IOUT_OC_WARN_LIMIT and IOUT_OC_FAULT_LIMIT commands. The resolution available here is 500 mA.

This is the absolute minimum adjustment that can be made to these thresholds. The other potential limit is the

resolution of the overcurrent DAC and can result in lower resolution. The overcurrent detection is done using a

DAC to set the threshold and a comparator to sense when the actual current level is above that threshold. The

resolution of the DAC is 1.875 mV. The resistance of the current sense element and this resolution determine the

minimum adjustment that can be made to the overcurrent warning and fault thresholds. That minimum

adjustment is given in Equation 11.

1.875mV

I

=

DOC

R

ISNS

where

•

I_ΔOCis the minimum change that can be made in the overcurrent warning or fault threshold

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•

R_ISNSis the resistance of the current sensing element, either the inductor DC resistance or the resistance of

the current sense resistor used

(11)

Combining these two resolution limits shows that for current sense elements with a resistance below 3.75 mΩ,

the overcurrent resolution is given by Equation 11. For current sense element resistances above 3.75 mΩ, the

overcurrent warning and fault resolution is 500 mA.

The TPS40400 has built in temperature correction for the temperature coefficient of resistance for copper wound

inductors used as current sense elements. As the temperature of a copper wound inductor increases, its

resistance increases, resulting in a higher DC component of voltage across it for a given current. This leads to a

decrease in the current that would actually trip the overcurrent thresholds. The voltages that the TPS40400 uses

to represent the overcurrent thresholds is automatically adjusted higher as the die temperature of the TPS40400

increases. The temperature coefficient for the increase of the thresholds is chosen close to the temperature

coefficient of copper at 4000 ppm/°C. The change in overcurrent threshold voltage from one temperature to

another is given in Equation 12.

V

- V

= T2 - T1 ´ 1+ TC

´ V

)

CU OC1

(

) (

OC2

OC1

where

•

V_OC1and V_OC2are the overcurrent threshold voltages

T1 and T2 are the corresponding temperatures in °C

T_CCUis the temperature coefficient, 0.004

(12)

The change in overcurrent threshold voltages given in Equation 12 maintains the actual overcurrent trip points

near constant only if the die temperature of the TPS40400 and the copper temperature of the inductor are closely

coupled. If the inductor copper temperature rises higher than the TPS40400 die temperature, the overcurrent

thresholds appears to decrease and vice versa.

Temperature compensation applied to the overcurrent thresholds must be considered. The threshold voltage

must not be or become greater (with the internal temperature compensation) than 110 mV referred to the voltage

at the ISNS pins. For instance, if a 10 mΩ resistance inductor was used as the current sense element, a current

of 10 A would cause a 100mV DC level at the current sense pins. At first this looks just fine and within the

bounds of the 110 mV limit of the controller. However, the temperature compensation of the threshold inside the

device raises the effective threshold as the TPS40100 die temperature increases. For 100°C increase in die

temperature, for example, the effective threshold crossed at the ISNS pins to trip an overcurrent is approximately

140 mV at the ISNS pins. The TPS40400 cannot respond this high and the result is a failure of the overcurrent

mechanism to respond at higher die temperatures. For a given maximum temperature defined by the

characteristics of the particular application, the maximum overcurrent setting that should be made for the

TPS40400 is calculated in Equation 13.

V

ISNS max

(

)

I_MAX

=

R_ISNS

´

T

- 25 ´ TC +1

(

) (

MAX CU

)

(

where

•

I_MAXis the maximum overcurrent threshold setting permissible (using the IOUT_OC_FAULT_LIMIT command)

in A

•

V_ISNS(max)is the maximum allowable voltage differential at the ISNS pins, 120 mV R_ISNSis the resistance of the

current sensing element – either inductor or current sense resistor

•

T_MAXis the maximum junction temperature expected for the TPS40400 in °C

TC_CUis the temperature coefficient of resistance for copper, 0.004

(13)

Equation 13 is illustrated in Figure 20. This figure shows the variation of the internal overcurrent threshold as the

die temperature increases. In this example, the designated maximum die temperature is 125°C. For the

overcurrent threshold to be valid at this temperature (110 mV or below), the maximum overcurrent threshold that

should be set using the IOUT_OC_FAULT or IOUT_OC_WARN commands should correspond to no more than

75.7 mV. The current level that achieves this is what is calculated in Equation 13. If the maximum expected die

temperature is less than 125°C, then the maximum 25°C overcurrent threshold increases accordingly.

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120

110

100

90

80

70

60

25

45

65

85

105

125

145

Junction Temperature (°C)

Figure 20. Internal Overcurrent Threshold Variation

Reading the output current. The average output current for the converter is readable using the READ_IOUT

command. The results of this command support only positive or current sourced from the converter. If the

converter is sinking current the result of this command is a reading of 0 A. Another consideration is the amount

of ripple voltage applied to the ISNS pins when the DC voltage level is low – i.e., low or no output current.

Because the TPS40400 averages out the ripple voltage when reporting the output current using the READ_IOUT

command. Excessive negative ripple voltage (V_ISNS+– V_ISNS–< 0) at the ISNS pins causes an error in the

reported output current. To ensure accurate readings the differential voltage at these pins should not be allowed

to exceed –45 mV.

Soft-start time. The TPS40400 supports several soft-start times from 600 μs to 9 ms selected by the TON_RISE

PMBus command. See the command description for full details on the levels and implementation. When

selecting the soft-start time, care must be taken to ensure that the charging current for the output capacitors is

considered. In some applications (e.g., those with large amounts of output capacitance) this current can lead to

problems with nuisance tripping of the overcurrent protection circuitry. To ensure that this does not happen, the

output capacitor charging current should be included when considering where to set the overcurrent threshold.

The output capacitor charging current can be found using Equation 14:

V

=

´ C

OUT

I

CAP

t

SS

where

•

I_CAPis the startup charging current of the output capacitance in A

V_OUTis the output voltage of the converter in V

C_OUTis the total output capacitance in F

t_SSis the selected soft-start time in seconds

(14)

With the charging current calculated, the overcurrent threshold can then be calibrated to the sum of the

maximum load current and the output capacitor charging current plus some margin. The amount of margin

required depends on the individual application, but 25% is a suggested starting point. More or less may be

required.

Power good. The TPS40400 has user selectable power good thresholds. These thresholds determine at what

voltage the PGOOD pin is allowed to go high and the associated PMBus flags are cleared. There are three

possible settings that can be had. See the POWER_GOOD_ON and POWER_GOOD_OFF command

descriptions for complete details. Note that these commands establish symmetrical values above and below the

nominal voltage. Values entered for each threshold should be the voltages corresponding to the threshold below

the nominal output voltage. For instance, if the nominal output voltage is 3.3 V, and the desired power good on

thresholds are ±5%, the POWER_GOOD_ON command is issued with 2.85 V as the desired threshold. The

POWER_GOOD_OFF command must be set to a lower value (higher percentage) than the POWER_GOOD_ON

command as well. The VOUT_SCALE_LOOP command must be set to approximately 0.1818 for these examples

to work correctly.

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The FB pin is used to sense the output voltage for the purposes of power good detection. Because of this there

is the inherent filtering action provided by the compensation network connected from COMP to FB. As the output

voltage rises or falls below the nominal value, the error amplifier attempts to force FB to match its reference

voltage. When the error amplifier is no longer able to do this, the FB pin begins to drift and trip the power good

threshold. For this reason the network from COMP to FB should have no purely resistive path.

Power good de-asserts during all startups, after any fault condition is detected or whenever the device is turned

off or in a disabled state (OPERATION command or CNTL pin put the device into a disabled or off state). The

PGOOD pin acts like a diode to GND when the device has no power applied to the VDD pin.

Undervoltage lockout. The TPS40400 provides flexible user adjustment of the undervoltage lockout threshold

and the hysteresis. Two PMBus commands VIN_ON and VIN_OFF allow the user to set these input voltage turn

on and turn off thresholds independently, with a 500-mV resolution from a minimum of 2.5-V turn off to a

maximum 18-V turn on. See the command descriptions for more details.

Output overvoltage and undervoltage thresholds. The TPS40400 has output overvoltage protection and

undervoltage protection capability. The comparators that look at the overvoltage conditions and undervoltage

conditions use the FB pin as the output sensing point so the filtering effect of the compensation network

connected from COMP to FB has an effect on the speed of detection. As the output voltage rises or falls below

the nominal value, the error amplifier attempts to force FB to match its reference voltage. When the error

amplifier is no longer able to do this, the FB pin begins to drift and trip the overvoltage threshold or the

undervoltage threshold. For this reason the network from COMP to FB should have no purely resistive path.

The VOUT_OV_FAULT_LIMIT and VOUT_UV_FAULT_LIMIT commands are used to set the output overvoltage

and undervoltage thresholds. There are four possible thresholds that can be set with the undervoltage and

overvoltage commands. See the command descriptions for complete details.

Programmable fault responses. For the various fault conditions, the TPS40400 allows the user to select the

fault response. The faults that have programmable responses with the TPS40400 are overcurrent (see the

IOUT_OC_FAULT_RESPONSE command description), overtemperature, (see the OT_FAULT_RESPONSE

command description), output overvoltage, (see the VOUT_OV_FAULT_RESPONSE command description) and

output undervoltage, (see the VOUT_UV_FAULT_RESPONSE command description). These commands

program the TPS40400 response to the corresponding fault condition. Possible responses include ignoring the

fault, latching off and requiring a reset (either VDD power cycle or a toggling of the CNTL pin and/or

OPERATION command status) for the converter to restart. See the individual fault response command

descriptions for details on what is available for the specific command.

User data and adjustable anti-cross conduction delay. The TPS 40400 provides

a command,

MFR_SPECIFIC_00, which can be used as a scratchpad to store 14 bits of arbitrary data. These bits can

represent anything that the user desires and can be stored in EEPROM for non-volatility. Bit 0 of this command

is used to select between two dead time settings for the controller. The particular setting required for a given

application depends upon several things, including total FET gate charge, FET gate resistance, PCB layout

quality, temperature, etc. It is not possible to give a hard and fast rule as to when to use which setting, but

generally, for FETs above 25 nC gate charge, the longer dead time setting should be looked at. The shorter dead

time setting allows higher efficiency in applications where the FETs are generally small and switch very quickly,

while may lead to minimum amounts of cross conduction in applications with larger, slower switching FETs.

Conversely, using the longer dead time setting with smaller, faster switching FETs leads to excessive body diode

conduction in the low-side FET, leading to a drop in converter efficiency. Bit 1 of this command permanently

locks certain parameters from being changed when set to 1. Use with caution. For more detail, see the

MFR_SPECIFIC_00 command description.

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SUPPORTED COMMANDS

The TPS40400 supports the following commands from the PMBus 1.1 specification.

OPERATION (01h)

The OPERATION command is used to turn the device output on or off in conjunction with the input from the

CONTROL pin. It is also used to set the output voltage to the upper or lower MARGIN voltages. The unit stays in

the commanded operating mode until a subsequent OPERATION command or a change in the state of the

CONTROL pin instructs the device to change to another mode.

Command

Format

OPERATION

Unsigned binary

Bit Position

Access

7

r/w

ON

0

6

r

5

4

3

2

1

r

0

r

r/w

Function

X

0

Margin

X

Default Value

0

On

This bit is an enable command to the converter.

•

0: output switching is disabled. Both drivers placed in an off or low state.

1: output switching is enabled. The device is allowed to begin power conversion assuming no fault conditions

exist.

Margin

If Margin Low is enabled, load the value from the VOUT_MARGIN_LOW command. If Margin High is enabled,

load the value from the VOUT_MARGIN_HIGH command. (See PMBus specification for more information)

•

00XX: Margin Off

0101: Margin Low (Ignore Fault)

0110: Margin Low (Act on Fault)

1001: Margin High (Ignore Fault)

1010: Margin High (Act on Fault)

Note that the reference voltage used for overvoltage, undervoltage detection and power good are derived from

the actual reference voltage in effect at the time. Setting a margin to test for one of these fault conditions does

not work. Testing for these conditions must be done by forcing the FB pin to a voltage that would trip these fault

conditions based on the current reference voltage and the percentage difference from this level set by the

threshold setting commands.

ON_OFF_CONFIG (02h)

The ON_OFF_CONFIG command configures the combination of CNTL pin input and serial bus commands

needed to turn the unit on and off. The contents of this register can be stored to non-volatile memory using the

STORE_DEFAULT_ALL or STORE_DEFAULT_CODE commands.

Command

Format

ON_OFF_CONFIG

Unsigned binary

Bit Position

Access

7

r

6

r

5

r

4

r/w

pu

1

3

r/w

cmd

0

2

r/w

cpr

1

0

r

r/w

pol

1

Function

X

cpa

1

Default Value

pu

The pu bit sets the default to either operate any time power is present or for the on/off to be controlled by CNTL

pin and PMBus OPERATION command. This bit is used in conjunction with the 'cp', 'cmd', and 'on' bits to

determine start up.

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Bit Value

ACTION

0

Device powers up any time power is present regardless of state of the CNTL pin.

Device does not power up until commanded by the CNTL pin and OPERATION

command as programmed in bits [2:0] of the ON_OFF_CONFIG register.

1

cmd

The cmd bit controls how the device responds to the OPERATION command.

Bit Value

ACTION

0

1

Device ignores the “on” bit in the OPERATION command.

Device responds to the “on” bit in the OPERATION command.

cpr

The cpr bit sets the CNTL pin response. This bit is used in conjunction with the 'cmd', 'pu', and 'on' bits to

determine start up.

Bit Value

ACTION

0

1

Device ignores the CNTL pin. On/off is controlled only by the OPERATION command.

Device requires the CNTL pin to be asserted to start the unit.

pol

The pol bit controls the polarity of the CONTROL pin. For a change to become effective, the contents of the

ON_OFF_CONFIG register must be stored to non-volatile memory using either the SOR_DEFAULT_ALL or

STORE_DEFAULT_CODE commands and the device power cycled. Simply writing a new value to this bit does

not change the polarity of the CNTL pin.

Bit Value

ACTION

0

1

CNTL pin is active low.

CNTL pin is active high.

cpa

The cpa bit sets the CNTL pin action when turning the controller off. This bit is read internally and cannot be

modified by the user.

Bit Value

ACTION

1

Turn off the output and stop transferring energy to the output as fast as possible.

CLEAR_FAULTS (03h)

The CLEAR_FAULTS command is used to clear any fault bits that have been set. This command clears all bits

in all status registers simultaneously. At the same time, the device negates (clears, releases) its SMBALERT

signal output if the device is asserting the SMBALERT signal. The CLEAR_FAULTS command does not cause a

unit that has latched off for a fault condition to restart. If the fault is still present when the bit is cleared, the fault

bit is immediately reset and the host notified by the usual means.

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WRITE_PROTECT (10h)

The WRITE_PROTECT command is used to control writing to the PMBus device. The intent of this command is

to provide protection against accidental changes. This command is not intended to provide protection against

deliberate or malicious changes to the device configuration or operation. All supported command parameters

may have their parameters read, regardless of the WRITE_PROTECT settings. The contents of this register can

be stored to non-volatile memory using the STORE_DEFAULT_ALL or STORE_DEFAULT_CODE commands.

Command

Format

WRITE_PROTECT

Unsigned binary

Bit Position

Access

7

r/w

bit7

0

6

r/w

bit6

0

5

r/w

bit5

0

4

X

3

X

2

X

1

X

0

X

Function

Default Value

bit5

bit6

bit7

Bit Value

ACTION

0

Enable all writes as permitted in bit6 or bit7

Disable all writes except the WRITE_PROTECT, OPERATION and ON_OFF_CONFIG.

(bit6 and bit7 must be 0 to be valid data)

1

Bit Value

ACTION

0

Enable all writes as permitted in bit5 or bit7

Disable all writes except for the WRITE_PROTECT and OPERATION commands. (bit5

and bit7 must be 0 to be valid data)

1

Bit Value

ACTION

0

Enable all writes as permitted in bit5 or bit6

Disable all writes except for the WRITE_PROTECT command. (bit5 and bit6 must be 0

to be valid data)

1

In any case, only one of the three bits may be set at any one time. Attempting to set more than one bit results in

an alert being generated and the cml bit is STATUS_WORD being set.

STORE_DEFAULT_ALL (11h)

The STORE_DEFAULT_ALL command stores all of the current storable register settings in the EEPROM

memory as the new defaults on power up.

It is permissible to use this command while the device is switching. Note however that the device continues to

switch but ignores all fault conditions until the internal store process has completed.

EEPROM programming faults cause the device to NACK and set the 'cml' bit in the STATUS_BYTE and the 'oth'

bit in the STATUS_CML registers.

RESTORE_DEFAULT_ALL (12h)

The RESTORE_DEFAULT_ALL command restores all of the storable register settings from EEPROM memory.

This command should not be used while the device is actively switching. If this is done, the device stops

switching the output drivers and the output voltage drops. Depending on loading conditions, the output voltage

could reach an undervoltage level and trigger an undervoltage fault response if programmed to do so. The

command can be used while the device is switching, but it is not recommended as it results in a restart that could

disrupt power sequencing requirements in more complex systems. It is strongly recommended that the device be

stopped before issuing this command.

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STORE_DEFAULT_CODE (13h)

The STORE_DEFAULT_CODE command instructs the PMBus core to store the contents of the programming

register whose Command Code matches the value in the data byte into memory as the new default value.

Command

Bit Position

STORE_DEFAULT_CODE

7

6

5

4

3

2

1

0

Access

w

Function

Command code

EEPROM programming faults cause the device to NACK and set the ‘cml’ bit in the STATUS_BYTE and the ‘oth’

bit in the STATUS_CML registers. It is permissible to use this command while the device is switching. Note

however that the device continues to switch but ignores all fault conditions until the internal store process has

completed.

It is permitted to use the STORE_DEFAULT_CODE command while the device is operating. However, the

device may be unresponsive during the copy operation with unpredictable, undesirable or even catastrophic

results. It is recommended to turn off the device output before issuing this command.

RESTORE_DEFAULT_CODE (14h)

The RESTORE_DEFAULT_CODE command instructs the PMBus core to overwrite the programming register

whose Command Code matches the value in the data byte, with the default value.

Command

Bit Position

STORE_DEFAULT_CODE

7

6

5

4

3

2

1

0

Access

w

Function

Command code

The RESTORE_DEFAULT_CODE command should not be used while the device is switching because the

device stops switching and restarts. During the restart, the low-side driver turns on for an extended time period

and could damage loads that are sensitive to the power rail sinking current. If this is of no concern then the

command may be used while the device is switching.

NOTE

A

VIN_UV fault may be triggered when RESTORE_DEFAULT_ALL or

RESTORE_DEFAULT_CODE command is set. The firmware workaround is accomplished

by verifying that, upon completion of RESTORE_DEFAULT_ALL or

a

RESTORE_DEFAULT_CODE command, the sole source asserting SMB_ALERT is

STATUS_BYTE[3] (VIN_UV). If so, issue a CLEAR_FAULTS command. Any other source

asserting

SMB_ALERT

under

these

circumstances

(i.e.

completion

of

RESTORE_DEFAULT_ALL or RESTORE_DEFAULT_CODE) would indicate an actual

fault condition.

VOUT_MODE (20h)

Description: The PMBus specification dictates that the data word for the VOUT_MODE command is one byte

that consists of a 3-bit mode and 5-bit exponent parameter, as shown below. The 3-bit mode sets whether the

device uses the Linear or Direct modes for output voltage related commands. The 5-bit parameter sets the

exponent value for the linear data mode. The mode and exponent parameters are set and do not permit the user

to change the values.

Command

Bit Position

VOUT_MODE

7

r

6

5

r

4

r

3

r

2

1

r

0

r

Access

r

Mode

0

r

Exponent

1

Function

Default Value

0

1

0

1

0

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Mode:

Value fixed at 000, linear mode.

Exponent

Value fixed at 11011, Exponent for Linear mode values is –10.

VOUT_TRIM (22h)

The VOUT_TRIM command is used to apply a fixed offset voltage to the output voltage command value. It is

most typically use by the end user to trim the output voltage at the time the PMBus device is assembled into the

end user system. It is vital that the VOUT_SCALE_LOOP comand is set correctly in order to obtaining correct

results. The contents of this register can be stored to non-volatile memory using the STORE_DEFAULT_ALL or

STORE_DEFAULT_CODE commands.

The effect of this command is determined by the settings of the VOUT_MODE command. In this device, the

VOUT_MODE is fixed to Linear with an exponent of –10 (decimal).

-10

OUT(offst)

V

= VOUT _ TRIM´ 2

(15)

The maximum value of V_OUT(offst)is ±25% of nominal VOUT. Nominal V_OUTis set by external resistors and the

600 mV error amplifier reference. The valid range in 2s complement for this command is –4000h to 3FFF. The

high order two bits of the high byte must both be either 0 or 1. They cannot have different values. If a value

outside of the ±25% is given with this command, the TPS40400 sets the output voltage to the upper or lower limit

depending on the direction of the setting, assert SMBALRT, set the CML bit in STATUS_BYTE and the invalid

data bit STATUS_CML.

Command

Format

VOUT_TRIM

Linear, two’s complement binary

Bit Position

Access

7

6

r

5

4

3

2

1

0

7

6

5

4

3

2

1

0

r/w

Function

High Byte

Low Byte

Default

Value

0

VOUT_MARGIN_HIGH (25h)

The VOUT_MARGIN_HIGH command sets the target voltage which the output changes to when the

OPERATION command is set to "Margin High". The contents of this register can be stored to non-volatile

memory using the STORE_DEFAULT_ALL or STORE_DEFAULT_CODE commands.

The effect of this command is determined by the settings of the VOUT_MODE command. In this device, the

VOUT_MODE is fixed to Linear with an exponent of –10 (decimal). The actual output voltage commanded by a

margin high command can be found by:

-10

V

=

VOUT _ MARGIN _ HIGH + VOUT _ TRIM ´ 2

( )

OUT MH

(

)

(16)

The maximum margin range is ±25% of nominal VOUT. Nominal VOUT is set by external resistors and a 600 mV

error amplifier reference and does not include the offset generated by VOUT_TRIM. It is critical that the correct

value be programmed into VOUT_SCALE_LOOP for the correct margin value to be calculated. Error checking is

not performed when the VOUT_MARGIN_HIGH command is issued. The error checking is done when the

OPERATION command is issued calling for a margin high state. At that time, values outside the ±25% range is

treated as invalid data and causes the set the CML bit in the STATUS_BYTE and the invalid data (ivd) bit in the

STATUS_CML registers. The output voltage is then set to to the upper or lower limit depending on the direction

of the setting. The device state can be restored to power up defaults by issuing either the

RESTORE_DEFAULT_ALL or RESTORE_DEFAULT_CODE commands.

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Command

VOUT_MARGIN_HIGH

Format

Linear, two's complement binary

Bit Position

Access

7

r

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

r/w

Function

High Byte

Low Byte

Default Value

0

1

0

1

0

1

0

1

The default value of VOUT_MARGIN_HIGH is 0x547 or 1351. This corresponds to a default margin high voltage

of 1.32 V with the default VOUT_SCALE_LOOP value of 0.5 and external resistor selection to give 1.2 V nominal

output voltage.

VOUT_MARGIN_LOW (26h)

The VOUT_MARGIN_LOW command sets the target voltage which the output changes to when the

OPERATION command is set to "Margin Low". The contents of this register can be stored to non-volatile

memory using the STORE_DEFAULT_ALL or STORE_DEFAULT_CODE commands.

The effect of this command is determined by the settings of the VOUT_MODE command. In this device, the

VOUT_MODE is fixed to Linear with an exponent of –10 (decimal). The actual output voltage commanded by a

margin high command can be found by:

-10

V

= VOUT _MARGIN_LOW + VOUT _ TRIM ´ 2

( )

OUT(ML)

(17)

The maximum margin range is ±25% of nominal VOUT. Nominal VOUT is set by external resistors and a 600 mV

error amplifier reference and does not include the offset generated by VOUT_TRIM. It is critical that the correct

value be programmed into VOUT_SCALE_LOOP for the correct margin value to be calculated. Error checking is

not performed when the VOUT_MARGIN_LOW command is issued. The error checking is done when the

OPERATION command is issued calling for a margin high state. At that time, values outside the ±25% range is

treated as invalid data and causes the device to set the CML bit in the STATUS_BYTE and the invalid data (ivd)

bit in the STATUS_CML registers. The output voltage is then set to the upper or lower limit depending on the

direction of the setting. The device state can be restored to power up defaults by issuing either the

RESTORE_DEFAULT_ALL or RESTORE_DEFAULT_CODE commands.

Command

Format

VOUT_MARGIN_LOW

Linear, two's complement binary

Bit Position

Access

7

r

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

r/w

Function

High Byte

Low Byte

Default Value

0

1

0

1

0

1

0

1

The default value of VOUT_MARGIN_LOW is 0x451 or 1105. This corresponds to a default margin high voltage

of 1.08 V with the default VOUT_SCALE_LOOP value of 0.5 and external resistor selection to give 1.2 V nominal

output voltage.

VOUT_SCALE_LOOP (29h)

VOUT_SCALE_LOOP is equal to the feedback resistor ratio. The nominal output voltage is set by a resistor

divider and the internal 600mV reference voltage. The default value of VOUT_SCALE_LOOP is 0.5 meaning that

the reference voltage is one half of the output voltage. The contents of this register can be stored to non-volatile

memory using the STORE_DEFAULT_ALL or STORE_DEFAULT_CODE commands.

The correct setting for the VOUT_SCALE_LOOP parameter is shown in Equation 18.

V

FB

VOUT _SCALE _LOOP =

V

OUT(nom)

(18)

It is important that this parameter is set correctly because it has an effect on several other parameters. Any

parameter that operates on or reports output voltage depends on the correct setting of this parameter for correct

results to be obtained.

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Command

VOUT_SCALE_LOOP

Linear, two's complement binary

Format

Bit Position

Access

7

r

6

r

5

r

4

r

3

r

2

r

1

0

7

6

5

4

3

2

1

0

r/w

Function

Exponent

Mantissa

Default Value

1

0

1

0

1

0

Exponent

Value fixed at –9 (dec).

Mantissa

Default value is 256 (dec). When combined with the exponent, the overall value of VOUT_SCALE_LOOP is 0.5

(dec). The maximum value for the mantissa is 512 for a VOUT_SCALE_LOOP value of 1.

FREQUENCY_SWITCH (33h)

The FREQUENCY_SWITCH command sets the switching frequency. Smarty Jones only supports frequencies

from 200 kHz to 2 MHz. Values written within the supported frequency range is rounded up to the nearest

supported increment. The contents of this register can be stored to non-volatile memory using the

STORE_DEFAULT_ALL or STORE_DEFAULT_CODE commands.

There are 14 distinct supported frequencies:

•

200 kHz

300 kHz

400 kHz

500 kHz

600 kHz (default)

700 kHz

800 kHz

900 kHz

1.0 MHz

1.2 MHz

1.4 MHz

1.6 MHz

1.8 MHz

1.9 MHz

The data word that accompanies this command is divided into a fixed 5-bit exponent and an 11-bit mantissa. The

5 most significant bits of the mantissa are fixed, while the lower six bits may be altered.

Command

Format

FREQUENCY_SWITCH

Linear, two's complement binary

Bit Position

Access

7

r

6

r

5

4

r

3

r

2

r

1

r

0

r

7

r

6

r

5

r/w

4

3

2

1

0

r

Exponent

1

r/w

Function

Mantissa

0

Default Value

0

1

0

1

0

1

Exponent

Fixed at 5(dec)

Mantissa

The upper five bits are fixed at 0.

The lower six bits are writeable with a default value of 19 (dec).

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VIN_ON (35h)

The VIN_ON command sets the value of the input voltage at which the unit should start operation assuming all

other required startup conditions are met. Values are mapped to the nearest supported increment. Values

outside the supported range are treated as invalid data and cause the device set the CML bit in the

STATUS_BYTE and the invalid data (ivd) bit in the STATUS_CML registers. The value of VIN_ON remains

unchanged on an out-of-range write attempt. The contents of this register can be stored to non-volatile memory

using the STORE_DEFAULT_ALL or STORE_DEFAULT_CODE commands.

SUPPORTED VIN_ON VALUES

2.75⁽¹⁾

3.00

3.50

4.00

4.50

5.00

5.50

6.00

6.50

7.00

7.50

8.00

8.50

9.00

9.50

10.00

10.50

11.00

11.50

12.00

12.50

13.00

13.50

14.00

14.50

15.00

15.50

16.00

16.50

17.00

17.50

18.00

(1) Default setting

VIN_ON must be set higher than VIN_OFF. Attempting to write either VIN_ON lower than VIN_OFF or VIN_OFF

higher than VIN_ON results in the new value being rejected, SMBALERT being asserted along with the CML bit

in STATUS_BYTE and the invalid data bit in STATUS_CML.

The data word that accompanies this command is divided into a fixed 5-bit exponent and an 11-bit mantissa. The

four most significant bits of the mantissa are fixed, while the lower 7 bits may be altered.

Command

Format

VIN_ON

Linear, two's complement binary

Bit Position

Access

7

r

6

r

5

4

r

3

r

2

r

1

r

0

r

7

r

6

5

r/w

4

3

2

1

0

r

Exponent

1

r/w

Function

Mantissa

0

Default Value

1

0

1

0

1

Exponent

–2 (dec), fixed.

Mantissa

The upper four bits are fixed at 0.

The lower seven bits are programmable with a default value of 11 (dec).

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VIN_OFF (36h)

The VIN_OFF command sets the value of the input voltage at which the unit should stop operation. Values are

mapped to the nearest supported increment. Values outside the supported range is treated as invalid data and

causes the device to set the CML bit in the STATUS_BYTE and the invalid data (ivd) bit in the STATUS_CML

registers. The value of VIN_ON remains unchanged during an out-of-range write attempt. The contents of this

register can be stored to non-volatile memory using the STORE_DEFAULT_ALL or STORE_DEFAULT_CODE

commands.

SUPPORTED VIN_OFF VALUES

2.50⁽¹⁾

3.00

3.50

4.00

4.50

5.00

5.50

6.00

6.50

7.00

7.50

8.00

8.50

9.00

9.50

10.00

10.50

11.00

11.50

12.00

12.50

13.00

13.50

14.00

14.50

15.00

15.50

16.00

16.50

17.00

17.50

(1) Default setting

VIN_ON must be set higher than VIN_OFF. Attempting to write either VIN_ON lower than VIN_OFF or VIN_OFF

higher than VIN_ON resultx in the new value being rejected, SMBALERT being asserted along with the CML bit

in STATUS_BYTE and the invalid data bit in STATUS_CML.

The data word that accompanies this command is divided into a fixed 5 bit exponent and an 11 bit mantissa. The

4 most significant bits of the mantissa are fixed, while the lower 7 bits may be altered.

Command

Format

VIN_OFF

Linear, two's complement binary

Bit Position

Access

7

r

6

r

5

4

r

3

r

2

r

1

r

0

r

7

r

6

5

r/w

4

3

2

1

0

r

Exponent

1

r/w

Function

Mantissa

0

Default Value

1

0

1

0

1

0

Exponent

–2 (dec), fixed.

Mantissa

The upper four bits are fixed at 0.

The lower seven bits are programmable with a default value of 10 (dec)

IOUT_CAL_GAIN (38h)

The IOUT_CAL_GAIN is the ratio of the voltage at the current sense element to the sensed current. The units

are Ohms (Ω). The effective current sense element can be the DC resistance of the inductor or a separate

current sense resistor. The default setting is 3 mΩ, and the resolution is 30.5 µΩ. The range is 0 to 15.6 mΩ. The

contents of this register can be stored to non-volatile memory using the STORE_DEFAULT_ALL or

STORE_DEFAULT_CODE commands.

Command

Format

IOUT_CAL_GAIN

Linear, two's complement binary

Bit Position

Access

7

r

6

r

5

4

r

3

r

2

r

1

r

0

7

6

5

r/w

4

3

2

1

0

r

Exponent

0

r/w

Function

Mantissa

1

Default Value

1

0

1

0

1

0

1

0

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Exponent

–15 (dec), fixed.

Mantissa

The upper four bits are fixed at 0.

The lower seven bits are programmable with a default value of 98 (dec)

IOUT_CAL_OFFSET (39h)

The IOUT_CAL_OFFSET is used to compensate for offset errors in the READ_IOUT results and the

IOUT_OC_FAULT_LIMIT and IOUT_OC_WARN_LIMIT thresholds. The units are amps. The default setting is 0

amps. The resolution of the argument for this command is 62.5 mA and the range is +3937.5mA to -4000 mA.

Values written outside of this range alias into the supported range. For example, 1110 0100 0000 0001 has an

expected value of –63.0625 amps, but results in 1110 0111 1111 0001 which is –0.9375 A. This occurs because

the read-only bits are fixed. The Exponent is always –4 and the 5 msb bits of the Mantissa are always equal to

the sign bit. The contents of this register can be stored to non-volatile memory using the STORE_DEFAULT_ALL

or STORE_DEFAULT_CODE commands.

Command

Format

IOUT_CAL_OFFSET

Linear, two's complement binary

Bit Position

Access

7

r

6

r

5

4

r

3

r

2

1

r

0

r

7

r

6

r

5

r/w

4

3

2

1

0

r

Exponent

1

r/w

Function

Mantissa

0

Default Value

1

0

Exponent

–4 (dec), fixed.

Mantissa

MSB is programmable with sign, next 4 bits are sign extend only.

Lower six bits are programmable with a default value of 0 (dec)

VOUT_OV_FAULT_LIMIT (40h)

The VOUT_OV_FAULT_LIMIT command sets the value of the output voltage that causes an output overvoltage

fault. The contents of this register can be stored to non-volatile memory using the STORE_DEFAULT_ALL or

STORE_DEFAULT_CODE commands.

The effective value of this command is determined by the settings of the VOUT_MODE command. In this device,

the VOUT_MODE is fixed to Linear with an exponent of –10 (decimal) so the effective overvoltage trip point

requested is:

-10

V

= VOUT _OV _FAULT _LIMIT ´ 2

OUT(OV _req)

(19)

The VOUT_OV_FAULT_LIMIT has two data bytes formatted as 2's complement binary integer. The actual values

for the VOUT_ OV_FAULT_LIMIT trip point are set to fixed percentages of nominal V_OUT. There are four fixed

percentages of the nominal V_OUTthat are supported for overvoltage trip points.

•

108%

110%

112% (default)

115%

For example, for a 1.2V nominal output, VOUT_OV_FAULT_LIMIT can be set to 1.296 V, 1.32 V, 1.344 V or

1.38 V. Values within the supported range is set to the nearest fixed percentage. It is critical that the correct

value be programmed into VOUT_SCALE_LOOP for the correct overvoltage fault trip point to be calculated.

Values outside the supported range results in the corresponding extreme value to be selected. No error

conditions are reported

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Command

VOUT_OV_FAULT_LIMIT

Linear, two's complement binary

Format

Bit Position

Access

7

r

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

r/w

Function

High Byte

Low Byte

Default Value

0

1

0

1

0

1

0

VOUT_OV_FAULT_RESPONSE (41h)

Description: The VOUT_OV_FAULT_RESPONSE command instructs the device on what action to take in

response to a VOUT_OV_FAULT_LIMIT fault. The device also:

•

Sets the VOUT_OV bit in the STATUS_BYTE

Sets the VOUT bit in the STATUS_WORD

Sets the VOUT OV fault bit in the STATUS_VOUT register, and

Notifies the host via SMBALRT pin

The contents of this register can be stored to non-volatile memory using the STORE_DEFAULT_ALL or

STORE_DEFAULT_CODE commands.

A one-byte unsigned binary data argument is used with this command:

Command

VOUT_OV_FAULT_RESPONSE

Format

Unsigned binary

Bit Position

Access

7

r/W

6

r/w

5

r/w

4

r/w

3

r/w

2

r

1

r

0

r

Function

RSP[1]

0

RSP[0]

0

RS[2]

0

RS[1]

0

RS[0]

0

X

1

X

0

X

0

Default Value

RSP[1:0]

Output voltage overvoltage response

00: The device continues operation without interruption.

01: The device continues operation for four switching cycles. If the fault is still present, the device shuts

down and responds according to RS[2:0].

10: The device shuts down and responds according to RS[2:0].

11: The device shuts down and attempts to restart.

RS[2:0]

Output voltage overvoltage retry setting

000: A zero value for the Retry Setting means that the unit does not attempt to restart. The output

remains disabled until the fault is cleared (See section 10.7 of the PMBus spec.)

111: A one value for the Retry Setting means that the unit goes through a normal startup (Soft start)

continuously, without limitation, until it is commanded off or bias power is removed or another fault

condition causes the unit to shutdown.

Any value other than 000 or 111 is not accepted.

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VOUT_UV_FAULT_LIMIT (44h)

The VOUT_UV_FAULT_LIMIT command sets the value of the output voltage that causes an output undervoltage

fault. The contents of this register can be stored to non-volatile memory using the STORE_DEFAULT_ALL or

STORE_DEFAULT_CODE commands.

The effective value of this command is determined by the settings of the VOUT_MODE command. In this device,

the VOUT_MODE is fixed to Linear with an exponent of –10 (decimal) so the effective overvoltage trip point

requested is:

-10

V

= VOUT _UV _FAULT _LIMIT ´ 2

OUT(UV _req)

(20)

The VOUT_UV_FAULT_LIMIT has two data bytes formatted as two's complement binary integer. The actual

values for VOUT_ UV_FAULT_LIMIT trip point are set to fixed percentages of nominal VOUT. There are four

fixed percentages of V_OUTthat are supported for overvoltage trip points.

•

92%

90%

88% (default)

85%

For example, for a 1.2 V nominal output, VOUT_UV_FAULT_LIMIT can be set to 1.104 V, 1.08 V, 1.056 V or

1.02 V. Values within the supported range are set to the nearest fixed percentage. It is critical that the correct

value be programmed into VOUT_SCALE_LOOP for the correct overvoltage fault trip point to be calculated.

Values outside the supported range results in the corresponding extreme value to be selected. No error

conditions are reported.

The VOUT_UV_FAULT_LIMIT command has two bytes formatted as a two’s compliment binary integer:

Command

Format

VOUT_UV_FAULT_LIMIT

Linear, two's complement binary

Bit Position

Access

7

r

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

r/w

Function

High Byte

Low Byte

Default Value

0

1

0

1

0

1

VOUT_UV_FAULT_RESPONSE (45h)

The VOUT_UV_FAULT_RESPONSE command instructs the device on what action to take in response to a

VOUT_UV_FAULT_LIMIT fault. The device also:

•

Sets the VOUT bit in the STATUS_WORD

Sets the VOUT UV Fault bit in the STATUS_VOUT register, and

Notifies the host via SMBALRT pin

The contents of this register can be stored to non-volatile memory using the STORE_DEFAULT_ALL or

STORE_DEFAULT_CODE commands.

A one-byte unsigned binary data word is used with this command:

Command

Format

VOUT_UV_FAULT_RESPONSE

Unsigned binary

Bit Position

Access

7

r/w

6

r/w

5

r/w

4

r/w

3

r/w

2

r

1

r

0

r

Function

RSP[1]

0

RSP[0]

0

RS[2]

0

RS[1]

0

RS[0]

0

X

1

X

0

X

0

Default Value

RSP[1:0]

Output voltage undervoltage response

00: The device continues operation without interruption.

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01: The device continues operation for four switching cycles. If the fault is still present, the device shuts

down and responds according to RS[2:0].

10: The device shuts down and responds according to RS[2:0].

11: The device shuts down and attempts to restart.

RS[2:0]

Output voltage undervoltage retry setting

000: A zero value for the Retry Setting means that the unit does not attempt to restart. The output

remains disabled until the fault is cleared (See section 10.7 of the PMBus spec.)

111: A one value for the Retry Setting means that the unit goes through a normal startup (Soft start)

continuously, without limitation, until it is commanded off or bias power is removed or another fault

condition causes the unit to shutdown.

Any value other than 000 or 111 is not accepted.

IOUT_OC_FAULT_LIMIT (46h)

The IOUT_OC_FAULT_LIMIT command sets the value of the output current, in amperes, that causes the

over-current detector to indicate an over-current fault condition. The IOUT_OC_FAULT_LIMIT should be set to

equal to or greater than the IOUT_OC_WARN_LIMIT. Writing a value to IOUT_OC_FAULT_LIMIT less than

IOUT_OC_WARN_LIMIT causea the device to set the CML bit in the STATUS_BYTE and the invalid data (ivd)

bit in the STATUS_CML registers as well as assert the SMBALRT signal. The contents of this register can be

stored to non-volatile memory using the STORE_DEFAULT_ALL or STORE_DEFAULT_CODE commands.

The IOUT_OC_FAULT_LIMIT takes a two-byte data word formatted as follows:

Command

Format

IOUT_OC_FAULT_LIMIT

Linear, two's complement binary

Bit Position

Access

7

r

6

r

5

4

r

3

r

2

r

1

r

0

r

7

r

6

r

5

r/w

4

3

2

1

0

r

Exponent

1

r/w

Function

Mantissa

0

Default Value

1

0

1

0

1

0

Exponent

–1 (dec), fixed.

Mantissa

The upper five bits are fixed at 0.

The lower six bits are programmable with a default value of 20 (dec)

The actual output current for a give mantissa and exponent is shown in Equation 21.

Mantissa

=

I_OUT(oc)= Mantissa´ 2^Exponent

2

(21)

The default output fault current setting is 10 A. Values of I_OUT(oc)can range between 0 A and 35 A in 500-mA

increments.

IOUT_OC_FAULT_RESPONSE (47h)

The IOUT_OC_FAULT_RESPONSE command instructs the device on what action to take in response to an

IOUT_OC_FAULT_LIMIT fault. The device also:

•

Sets the IOUT_OC bit in the STATUS_BYTE

Sets the IOUT/POUT bit in the STATUS_WORD

Sets the IOUT OC Fault bit in the STATUS_IOUT register, and

Notifies the host as described in section 10.2.2 of the PMBus Specification.

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The contents of this register can be stored to non-volatile memory using the STORE_DEFAULT_ALL or

STORE_DEFAULT_CODE commands.

Command

Format

IOUT_OC_FAULT_RESPONSE

Unsigned binary

Bit Position

Access

7

r/w

6

r/w

5

r/w

4

r/w

3

r/w

2

r

1

r

0

r

Function

RSP[1]

0

RSP[0]

0

RS[2]

0

RS[1]

0

RS[0]

0

X

1

X

0

X

0

Default Value

RSP[1:0]

00: The device continues operation without interruption

01: This is unsupported and causes a data error.

10: The device continues operation for four switching cycles. If the fault is still present, the device shuts

down and responds according to RS[2:0].

11: The device shuts down and attempts to restart.

RS[2:0]

000: A zero value for the Retry Setting means that the unit does not attempt to restart. The output

remains disabled until the fault is cleared (See section 10.7 of the PMBus spec.)

111: A one value for the Retry Setting means that the unit goes through a normal startup (Soft start)

continuously, without limitation, until it is commanded off or bias power is removed or another fault

condition causes the unit to shutdown.

Any value other than 000 or 111 is not accepted.

IOUT_OC_WARN_LIMIT (4Ah)

The IOUT_OC_WARN_LIMIT command sets the value of the output current, in amperes, that causes the

over-current detector to indicate an over-current warning. When this current level is exceeded the device:

•

Sets the OTHER bit in the STATUS_BYTE

Sets the OCW bit in the STATUS_WORD

Sets the IOUT overcurrent Warning (OCW) bit in the STATUS_IOUT register, and

Notifies the host by asserting SMBALRT

The IOUT_OC_WARN_LIMIT threshold should always be set to less than or equal to the

IOUT_OC_FAULT_LIMIT. Writing a value to IOUT_OC_WARN_LIMIT greater than IOUT_OC_FAULT_LIMIT

causes the device to set the CML bit in the STATUS_BYTE and the invalid data (ivd) bit in the STATUS_CML

registers as well as assert the SMBALRT signal. The contents of this register can be stored to non-volatile

memory using the STORE_DEFAULT_ALL or STORE_DEFAULT_CODE commands.

The IOUT_OC_WARN_LIMIT takes a two byte data word formatted as follows:

Command

Format

IOUT_OC_WARN_LIMIT

Linear, two's complement binary

Bit Position

Access

7

r

6

r

5

4

r

3

r

2

r

1

r

0

r

7

r

6

r

5

r/w

4

3

2

1

0

r

Exponent

1

r/w

Function

Mantissa

0

Default Value

1

0

1

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Exponent

–1 (dec), fixed

Mantissa

The upper five bits are fixed at 0.

Lower six bits are programmable with a default value of 15 (dec)

The actual output warning current level for a give mantissa and exponent is:

Mantissa

=

I_OUT(oc)= Mantissa´ 2^Exponent

2

(22)

The default output fault current setting is 10A. Values of I_OUT(oc)can range from 0A to 35A in 500mA increments.

The default output warning current setting is 7.5A.

OT_FAULT_RESPONSE (50h)

The OT_FAULT_RESPONSE command instructs the device on what action to take in response to an output over

temperature fault. The temperature sensed is the die temperature of the TPS40400 only. No other temperature

sensors are provided. The contents of this register can be stored to non-volatile memory using the

STORE_DEFAULT_ALL or STORE_DEFAULT_CODE commands. The OT_FAULT_LIMIT parameter is not

programmable and is therefore not supported in the PMBus command set. When an over temperature fault

condition is sensed, the device:

•

Sets the TEMPERATURE bit in the STATUS_BYTE

Sets the OT FAULT bit in the STATUS_TEMPERATURE register, and

Notifies the host by asserting the SMBALRT signal

A one-byte unsigned binary data word is used with this command:

Command

OT_FAULT_RESPONSE

Unsigned binary

Format

Bit Position

Access

7

r

6

r/w

5

r

4

r

3

r

2

r

1

r

0

r

Function

X

1

OTF_RS

1

X

0

X

0

X

0

X

0

X

0

X

0

Default Value

OTF_RS

Over temperature fault retry setting

0: A zero value for the Retry setting indicates that the unit does not attempt to restart.

1: A one value for the Retry setting indicates that the unit goes through a normal startup (soft-start)

when the die temperature falls below the hysteresis band limit. (See the Electrical Characteristics

table).

POWER_GOOD_ON (5Eh)

The POWER_GOOD_ON command sets the value of the output voltage at which the PGOOD output pin (open

drain) is asserted high. The contents of this register can be stored to non-volatile memory using the

STORE_DEFAULT_ALL or STORE_DEFAULT_CODE commands. The actual implementation is a window

comparator with symmetrical thresholds above and below the nominal. This command sets both the upper and

lower power good threshold at the same time. The parameter passed with this command is always the lower

threshold (less than the nominal output) and is mapped to the closest supported percentages of the nominal

output voltage inTable 2.

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Table 2. Supported POWER_GOOD_ON Levels

THRESHOLD

Low

95%

92%

90%

High

105%

108%

110%

For example, with a 1.2 V nominal output voltage, the POWER_GOOD_ON command can set the lower

threshold to 1.14 V, 1.104 V or 1.08 V. Doing this automatically sets the upper thresholds to 1.26 V, 1.296 V and

1.32 V respectively.

The effective value of this command is determined by the settings of the VOUT_MODE command. In this device,

the VOUT_MODE is fixed to Linear with an exponent of –10 (decimal) so the effective lower power good turn on

threshold requested is:

-10

V

= POWER _GOOD _ON´ 2

OUT(PGOOD _ON)

(23)

The nominal output voltage is set by external resistors and a 600-mV error amplifier reference. It is critical that

the correct value be programmed into VOUT_SCALE_LOOP in order to correctly select the desired

POWER_GOOD_ON threshold.

Normally, the POWER_GOOD_ON threshold is set higher than the POWER_GOOD_OFF threshold. If the

POWER_GOOD_ON threshold is set to a value equal to or less than the POWER_GOOD_OFF threshold, the

device:

•

Sets the CML bit in the STATUS_BYTE

Sets the Invalid data bit in STATUS_CML

Notifies the host via SMBALRT pin

It is the user's responsibility to ensure that the chosen POWER_GOOD_ON and POWER_GOOD_OFF

thresholds are reasonable with respect to each other. For values written outside the supported ranges are

ACK'ed but causes the SMBALRT line to assert and the CML bit to be set in the STATUS_WORD. The invalid

data bit is also set in the STATUS_CML results. The actual POWER_GOOD_ON threshold is set to the nearest

supported extreme value. For instance, with VOUT_SCALE_LOOP set to 0.5 for a typical 1.2-V output supply,

setting POWER_GOOD_ON to 0.5 results in the threshold being set to the 90% value.

The POWER_GOOD_ON command has two data bytes formatted as two’s complement binary integer:

Command

Format

POWER_GOOD_ON

Linear, two's complement binary

Bit Position

Access

7

r

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

r/w

Function

High Byte

Low Byte

Default Value

0

1

0

1

0

1

0

1

0

The default value sets the power good turn on threshold to 1.1035V which maps to the 92% low threshold and

108% high threshold.

POWER_GOOD_OFF (5Fh)

The POWER_GOOD_OFF command sets the value of the output voltage at which the PGOOD output pin (open

drain output) is de-asserted low. The contents of this register can be stored to non-volatile memory using the

STORE_DEFAULT_ALL or STORE_DEFAULT_CODE commands. The actual implementation is a window

comparator with symmetrical thresholds above and below the nominal. This command sets both the upper and

lower power good threshold at the same time. The parameter passed with this command is always the lower

threshold (less than the nominal output) and is mapped to the closest supported percentages of the nominal

output voltage below:

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Supported POWER_GOOD_OFF Levels

Low Threshold High Threshold

92% 108%

90%⁽¹⁾

110%

112%

88%

(1) Default value

For example, with a 1.2 V nominal output voltage, the POWER_GOOD_OFF command can set the lower

threshold to 1.104 V, 1.0 8V or 1.056 V. Doing this automatically sets the upper thresholds to 1.296 V, 1.32 V

and 1.344 V respectively.

The effective value of this command is determined by the settings of the VOUT_MODE command. In this device,

the VOUT_MODE is fixed to Linear with an exponent of –10 (decimal) so the effective lower power good turn on

threshold requested are:

-10

V

= POWER _GOOD _OFF´ 2

OUT(PGOOD _OFF)

(24)

The nominal output voltage is set by external resistors and a 600 mV error amplifier reference. It is critical that

the correct value be programmed into VOUT_SCALE_LOOP for the correct POWER_GOOD_ON threshold to be

selected.

Normally, the POWER_GOOD_ON threshold is set higher than the POWER_GOOD_OFF threshold. If the

POWER_GOOD_ON threshold is set to a value equal to or less than the POWER_GOOD_OFF threshold, the

device:

•

Sets the CML bit in the STATUS_BYTE

Sets the Invalid data bit in STATUS_CML

Notifies the host via SMBALRT pin

It is the user's responsibility to make sure that chsen POWER_GOOD_ON and POWER_GOOD_OFF thresholds

are reasonable with respect to each other. For values written outside the supported ranges are ACK'ed but

cause the SMBALRT line to assert and the CML bit to be set in the STATUS_WORD. The invalid data bit is also

set in the STATUS_CML results. The actual POWER_GOOD_OFF threshold is set to the nearest supported

extreme value. For instance, with VOUT_SCALE_LOOP set to 0.5 for a typical 1.2-V output supply, setting

POWER_GOOD_OFF to 0.5 results in the threshold being set to the 88% value.

The POWER_GOOD_OFF command has two data bytes formatted as two's complement binary integer:

Command

Format

POWER_GOOD_OFF

Linear, two's complement binary

Bit Position

Access

7

r

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

r/w

Function

High Byte

Low Byte

Default Value

0

1

0

1

0

1

0

1

0

The default value sets the power good turn off threshold to 1.08 V which maps to the 90% low threshold and

108% high threshold.

TON_RISE (61h)

The TON_RISE command sets the time in ms, from when the output starts to rise until the voltage has entered

the regulation band. There are several discreet settings that this command supports. Commanding a value other

than one of these values results in the nearest supported value being selected.

The supported TON_RISE times over PMBus are as follows. Note that the actual soft-start time is longer than

the entered value. Typically the nominal value seen in operation is approximately 15% longer that the time

entered.

•

600 µs

900 µs

1.2 ms

1.8 ms

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•

2.7 ms (default value)

4.2 ms

6.0 ms

9.0 ms

A value of 0 ms instructs the unit to bring its output voltage to the programmed regulation value as quickly as

possible. The contents of this register can be stored to non-volatile memory using the STORE_DEFAULT_ALL or

STORE_DEFAULT_CODE commands.

The TON_RISE command is formatted as a linear mode two’s complement binary integer.

Command

Format

TON_RISE

Linear, two's complement binary

Bit Position

Access

7

r

6

r

5

4

r

3

r

2

r

1

r

0

7

6

5

4

3

2

1

0

r

Exponent

1

r/w

Function

Mantissa

1

Default Value

1

0

1

0

1

Exponent

–4 (dec), fixed.

Mantissa

The upper two bits are fixed at 0.

The lower five bits are programmable with a default value of 43 (dec)

STATUS_BYTE (78h)

The STATUS_BYTE command returns one byte of information with a summary of the most critical device faults.

For TPS40400, 4 fault bits is flagged in this particular command: output over-voltage, output over-current,

over-temperature, and output under-voltage. The STATUS_BYTE reports communication faults in the CML bit.

Other communication faults set the NONE OF THE ABOVE bit.

Command

STATUS_BYTE

Format

Unsigned binary

Bit Position

Access

7

r

6

r

5

4

3

r

2

r

1

r

0

r

IOUT_OC

0

r

Function

X

0

OFF

0

VOUT_OV

0

VIN_UV

0

TEMPERATURE CML

NONE OF THE ABOVE

0

Default Value

0

A "1" in any of these bit positions indicates that:

OFF:

The device is not providing power to the output, regardless of the reason. In TPS40400, this flag

means that the converter is not enabled.

VOUT_OV:

An output overvoltage fault has occurred.

IOUT_OC:

An output over current fault has occurred.

VIN_UV:

An input undervoltage fault has occurred.

TEMPERATURE:

A temperature fault or warning has occurred.

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CML:

A Communications, Memory or Logic fault has occurred.

NONE OF THE ABOVE:

A fault or warning not listed in bit1 through bits 1-7 has occurred, for example an undervoltage

condition or an over current warning condition

STATUS_WORD (78h)

The STATUS_WORD command returns two bytes of information with a summary of the device's fault/warning

conditions. The low byte is identical to the STATUS_BYTE above. The additional byte reports the warning

conditions for output overvoltage and overcurrent, as well as the power good status of the converter.

Command

Format

STATUS_WORD (low byte)

Unsigned binary

Bit Position

Access

7

r

6

r

5

4

3

2

r

1

r

0

r

IOUT_OC

0

r

VIN_UV

0

r

Function

X

0

OFF

x

VOUT_OV

0

TEMPERATURE CML

NONE OF THE ABOVE

0

Default Value

0

A "1" in any of the low byte (STATUS_BYTE) bit positions indicates that:

OFF:

The device is not providing power to the output, regardless of the reason. In TPS40400, this flag

means that the converter is not enabled.

VOUT_OV:

An output overvoltage fault has occurred.

IOUT_OC:

An output over current fault has occurred.

VIN_UV:

An input undervoltage fault has occurred.

TEMPERATURE:

A temperature fault or warning has occurred.

CML:

A Communications, Memory or Logic fault has occurred.

NONE OF THE ABOVE:

A fault or warning not listed in bits 1-7 has occurred

Command

Format

STATUS_WORD (high byte)

Unsigned binary

Bit Position

Access

7

6

5

r

4

r

3

2

r

1

r

0

r

VOUT

0

r

Function

IOUT/POUT

0

X

0

X

0

POWER_GOOD

0

X

0

X

0

X

0

Default Value

A "1" in any of the high byte bit positions indicates that:

VOUT:

An output voltage fault or warning has occurred

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IOUT/POUT:

An output current warning or fault has occurred. The PMBus specification states that this also

applies to output power. TPS40400 does not support output power warnings or faults.

POWER_GOOD:

The power good signal is negated.

STATUS_VOUT (7Ah)

The STATUS_VOUT command returns one byte of information relating to the status of the converter's output

voltage related faults. The only bits of this register supported by TPS40400 are VOUT_OV Fault and VOUT_UV

Fault.

Command

Format

STATUS_VOUT

Unsigned binary

Bit Position

Access

7

6

r

5

r

4

r

3

r

2

r

1

r

0

r

Function

VOUT OV Fault

0

X

0

X

0

VOUT UV Fault

X

0

X

0

X

0

X

0

Default Value

0

A "1" in any of these bit positions indicates that:

VOUT OV Fault:

The device has seen the output voltage rise above the VOUT_OV_FAULT_LIMIT threshold.

VOUT UV Fault:

The device has seen the output voltage fall below the VOUT_UV_FAULT_LIMIT threshold.

STATUS_IOUT (7Bh)

The STATUS_IOUT command returns one byte of information relating to the status of the converter’s output

current related faults. The only bits of this register supported by TPS40400 are IOUT_OC Fault and IOUT_OC

Warning.

Command

Format

STATUS_IOUT

Unsigned binary

Bit Position

Access

7

6

r

5

4

r

3

r

2

r

1

r

0

r

Function

IOUT_OV Fault

0

X

0

IOUT OC Warning

0

X

0

X

0

X

0

X

0

X

0

Default Value

A "1" in any of these bit positions indicates that:

IOUT_OV Fault:

The device has seen the output current rise above the level set by IOUT_OC_FAULT_LIMIT.

VOUT_UV Fault:

The device has seen the output current rise relating to the level set by IOUT_OC_WARN_LIMIT.

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STATUS_TEMPERATURE (7Dh)

The STATUS_TEMPERATURE command returns one byte of information relating to the status of the converter

temperature related faults. The only bits of this register supported by TPS40400 are OT Fault and OT Warning.

Command

Format

STATUS_TEMPERATURE

Unsigned binary

Bit Position

Access

7

6

5

r

4

r

3

r

2

r

1

r

0

r

OT Fault

0

r

Function

OT Warning

0

X

0

X

0

X

0

X

0

X

0

X

0

Default Value

A "1" in any of these bit positions indicates that:

OT Fault:

The device die temperature has exceeded the preset fault threshold.

OT Warning:

The device die temperature has exceeded the preset warning threshold.

STATUS_CML (7Eh)

The STATUS_CML command returns one byte of information relating to the status of the converter’s

communication related faults. The bits of this register supported by TPS40400 are:

Invalid/Unsuppported Command, Invalid/Unsupported Data, Packet Error Check Failed and Other

Communication Fault.

Command

Format

STATUS_CML

Unsigned binary

Bit Position

Access

7

r

6

r

5

r

4

r

3

r

2

r

1

r

0

r

Invalid/Unsuppported

Command

Invalid/Unsupported Packet Error Check

Other Communication

Fault

Function

X

0

X

0

X

0

X

0

Data

Failed

Default Value

0

A "1" in any of these bit positions indicates that:

Invalid/Unsupported Command:

An invalid or unsupported command has been received.

Invalild/Unsupported Data

Invalid or unsupported data has been received

Packet Error Check Failed

A packet has failed the CRC error check.

Other Communication Fault

Some other communication fault or error has occurred

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READ_VIN (88h)

The READ_VIN commands returns two bytes of data in the linear data format that represent the input voltage

applied to the VDD pin of the controller. The data format is as follows:

Command

Format

READ_VIN

Linear, two's complement binary

Bit Position

Access

7

r

6

r

5

4

r

3

r

2

r

1

r

0

r

7

r

6

r

5

4

r

3

r

2

r

1

r

0

r

Exponent

0

r

Function

Mantissa

0

Default Value

1

0

The input voltage is scaled before it reaches the internal analog to digital converter so that resolution of the input

voltage read back is 31.25mV. The input voltage can be found using Equation 25.

V

= Mantissa´ 2^Exponent´ 1+ READ _ VIN_CAL _GAIN + READ _ VIN_CAL _OFFSET

(

)

IN

(25)

Exponent

Fixed at –5.

Mantissa

The lower 10 bits are the result of the ADC conversion of the input voltage. The 11^thbit is fixed at 0 because only

positive numbers are considered valid.

READ_VIN_CAL_GAIN comes from the MFR_SPECIFIC_06 command

READ_VIN_CAL_OFFSET comes from the MFR_SPECIFIC_07 command

READ_VOUT (8Bh)

The READ_VOUT commands returns two bytes of data in the linear data format that represent the output voltage

of the controller. The output voltage is sensed at the ISNS- pin so voltage drop to the load is not accounted for.

The data format is as follows:

Command

Format

READ_VOUT

Linear, two's complement binary

Bit Position

Access

7

r

6

r

5

r

4

r

3

r

2

r

1

r

0

r

7

6

r

5

r

4

r

3

r

2

r

1

r

0

r

Function

Mantissa

0

Default Value

0

The setting of the VOUT_MODE affects the results of this command as well. In the TPS40400, VOUT_MODE is

set to linear mode with an exponent of –10 and cannot be altered. The output voltage can be found by:

V_OUT= Mantissa´ 2^Exponent´ 1+ READ _ VOUT _CAL _GAIN + READ _ VOUT _CAL _OFFSET

(

)

(26)

Exponent

Fixed at -10 by VOUT_MODE

Mantissa

Bits 13 (bit 5 in high order byte) through 4 are the result of the ADC conversion of the ouput voltage. The

effective LSB using this scheme is 15.625 mV.

READ_VOUT_CAL_GAIN is derived from the MFR_SPECIFIC_05 command

READ_VOUT_CAL_OFFSET is derived from the MFR_SPECIFIC_04 command

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READ_IOUT (8Ch)

The READ_IOUT commands returns two bytes of data in the linear data format that represent the output current

of the controller. The output current is sensed at the ISNS+ and ISNS– pins. The data format is as follows:

Command

Format

READ_IOUT

Linear, two's complement binary

Bit Position

Access

7

r

6

r

5

4

r

3

r

2

r

1

r

0

r

7

r

6

r

5

4

r

3

r

2

r

1

r

0

r

Exponent

1

r

Function

Mantissa

0

Default Value

1

0

The output current is scaled before it reaches the internal analog to digital converter so that resolution of the

output current read is 62.5 mA, though resolution may be less depending on the setting of IOUT_CAL_GAIN.

The maximum value that can be reported is 64 A. It is mandatory that the IOUT_CAL_GAIN and

IOUT_CAL_OFFSET parameters are sset correctly in order to obtain accurate results. The output current can be

found by using Equation 27.

Exponent

I

= Mantissa´ 2

OUT

(27)

Exponent

Fixed at -4.

Mantissa

The lower 10 bits are the result of the ADC conversion of the input voltage. The 11^thbit is fixed at 0 because only

positive numbers are considered valid.

PMBUS_REVISION (98h)

The PMBUS_REVISION command returns a single, unsigned binary byte that indicates that the TPS40400 is

compliant with the 1.1 revision of the PMBus specification.

Command

Format

PMBUS_REVISION

Unsigned binary

Bit Position

Access

7

r

6

r

5

r

4

r

3

r

2

r

1

r

0

r

Default Value

0

1

0

1

MFR_VIN_MIN (A0h)

The MFR_VIN_MIN command returns a two-byte linear formatted result that indicates the minimum voltage from

which the TPS40400 is able to convert power. The data is formatted as follows:

Command

Format

MFR_VIN_MIN

Linear, two's complement binary

Bit Position

Access

7

r

6

r

5

4

r

3

r

2

r

1

r

0

r

7

r

6

r

5

4

r

3

r

2

r

1

r

0

r

Exponent

1

r

Function

Mantissa

0

Default Value

1

0

1

0

The minimum input voltage can be found using Equation 28.

Exponent

IN

V

= Mantissa´ 2

(28)

This equates to 3 V when evaluated with the default values. The TPS40400 begins to convert power at a

minimum input of 2.75-V.

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Exponent

Fixed at –2.

Mantissa

Fixed at 12.

MFR_VIN_MAX (A1h)

The MFR_VIN_MAX returns a two-byte linear formatted result that represents the maximum voltage that the

TPS40400 is specified to operate at. The data is formatted as follows:

Command

Format

MFR_VIN_MAX

Bit Position

Access

7

r

6

r

5

4

r

3

r

2

r

1

r

0

r

7

r

6

r

5

4

r

3

r

2

r

1

r

0

r

Exponent

1

r

Function

Mantissa

0

Default Value

1

0

1

0

The maximum input voltage can be found from:

Exponent

IN(min)

V

= Mantissa´ 2

(29)

This equals 20 V when evaluated with the default values.

Exponent

Fixed at –2.

Mantissa

Fixed at 80.

MFR_VOUT_MIN (A4h)

This command returns a two byte result that represents the minimum output voltage the TPS40400 supports.

Command

Format

MFR_VOUT_MIN

Linear, two's complement binary

Bit Position

Access

7

r

6

r

5

r

4

r

3

r

2

r

1

r

0

r

7

6

r

5

r

4

r

3

r

2

r

1

r

0

r

Function

Mantissa

0

Default Value

0

1

0

1

0

1

0

The setting of the VOUT_MODE affects the results of this command as well. In the TPS40400, VOUT_MODE is

set to linear mode with an exponent of -10 and cannot be altered. The minimum nominal output voltage can be

found by:

Exponent

V

= Mantissa´ 2

OUT(max)

(30)

This equals to 600 mV using the pre-set values. Using VOUT_TRIM, it is possible to adjust this voltage down to

approximately 450 mV.

Exponent

Fixed at –10.

Mantissa

Fixed at 614.

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MFR_VOUT_MAX (A5h)

The command returns a two-byte result that represents the maximum output voltage that the TPS40400

supports.

Command

Format

MFR_VOUT_MAX

Linear, two's complement binary

Bit Position

Access

7

r

6

r

5

r

4

r

3

r

2

r

1

r

0

r

7

6

r

5

r

4

r

3

r

2

r

1

r

0

r

Function

Mantissa

0

Default Value

0

1

0

The setting of the VOUT_MODE affects the results of this command as well. In the TPS40400, VOUT_MODE is

set to linear mode with an exponent of –10 and cannot be altered. The maximum nominal output voltage can be

found by:

Exponent

V

= Mantissa´ 2

OUT(max)

(31)

This evaluates to 12 V using the pre-set values.

Exponent

Fixed at –10.

Mantissa

Fixed at 12288

MFR_SPECIFIC_00 (D0h)

The MFR_SPECIFIC_00 command is used for storing arbitrary user data and for selecting a dead time or

anti-cross conduction time for the TPS40400. The contents of this register can be stored to non-volatile memory

using the STORE_DEFAULT_ALL or STORE_DEFAULT_CODE commands.

This command take a two byte unsigned binary argument as follows.

Command

Format

MFR_SPECIFIC_00

Unsigned binary

Bit Position

Access

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

r/w

WPE

0

r/w

DTC

0

r/w

Function

USER_DATA

Default Value

0

Dead Time Control setting (DTC)

•

0: Fast. Dead time = ~25 ns

1: Slow. Dead time = ~ 50 ns

WPE

Write protect extension. Writing a 1 to this bit position permanently locks the following parameters:

•

IOUT_CAL_GAIN

IOUT_CAL_OFFSET

FREQUENCY_SWITCH

IOUT_OC_FAULT_LIMIT

MFR_SPECIFIC_00

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NOTE

Subsequent to setting the WPE bit, either

a

STORE_DEFAULT_ALL or

STORE_DEFAULT_CODE (for MFR_SPECIFIC_00) PMBus command must be issued in

order to prevent the WPE bit from being cleared when the device is subjected to a

reset-restart operation.

MFR_SPECIFIC_01 (D1h)

This command is used for trimming internal components of the TPS40400 and is not recommended for general

use.

MFR_SPECIFIC_02 (D2h)

This command is used for trimming internal components of the TPS40400 and is not recommended for general

use.

MFR_SPECIFIC_03 (D3h)

This command is used for trimming internal components of the TPS40400 and is not recommended for general

use.

MFR_SPECIFIC_04 (D4h)

This command applies an offset to the READ_VOUT command results to calibrate out offset errors in the on

board measurement system. The contents of this register can be stored to non-volatile memory using the

STORE_DEFAULT_ALL or STORE_DEFAULT_CODE commands.

Command

Format

MFR_SPECIFIC_04

Linear, two's compliment binary

Bit Position

Access

7

6

r⁽¹⁾

5

r⁽¹⁾

4

r⁽¹⁾

3

r⁽¹⁾

2

r⁽¹⁾

1

r⁽¹⁾

0

r⁽¹⁾

7

6

5

4

3

2

1

0

r/w

r⁽¹⁾

Mantissa

0

r/w

Function

Default Value

0

(1) Bits are sign extension only and are not otherwise programmable.

Default value: 0

Exponent

READ _ VOUT _CAL _OFFSET = Mantissa ´ 2

•

Exponent is fixed at 2^-10by VOUT_MODE

LSB value is 975 µV

Range -125 mV to 124 mV

(32)

MFR_SPECIFIC_05 (D5h)

This command applies a gain correction to the READ_VOUT command results to calibrate out gain errors in the

on board measurement system. The contents of this register can be stored to non-volatile memory using the

STORE_DEFAULT_ALL or STORE_DEFAULT_CODE commands.

Command

Format

MFR_SPECIFIC_05

Linear, two's compliment binary

Bit Position

Access

7

r⁽¹⁾

6

r⁽¹⁾

5

r⁽¹⁾

4

r⁽¹⁾

3

r⁽¹⁾

2

r⁽¹⁾

1

r⁽¹⁾

0

r⁽¹⁾

7

r⁽¹⁾

6

r⁽¹⁾

5

r⁽¹⁾

4

3

2

1

0

r/w

Function

Exponent

0

Mantissa

0

Default Value

1

0

1

0

(1) Bits are sign extension only and are not otherwise programmable.

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Default value: 0

Exponent

READ _ VOUT _CAL _GAIN = Mantissa ´ 2

•

Exponent is fixed at -8

LSB value is 0.4%

Range -0.125 to 0.121

(33)

MFR_SPECIFIC_06 (D6h)

This command applies an offset to the READ_VIN command results to calibrate out offset errors in the on board

measurement system. The contents of this register can be stored to non-volatile memory using the

STORE_DEFAULT_ALL or STORE_DEFAULT_CODE commands.

Command

Format

MFR_SPECIFIC_06

Linear, two's compliment binary

Bit Position

Access

7

r⁽¹⁾

6

r⁽¹⁾

5

r⁽¹⁾

4

r⁽¹⁾

3

r⁽¹⁾

2

1

r⁽¹⁾

0

r⁽¹⁾

7

r⁽¹⁾

6

r⁽¹⁾

5

4

3

2

1

0

r/w

Function

Exponent

0

Mantissa

0

Default Value

1

0

(1) Bits are sign extension only and are not otherwise programmable.

Default value: 0

Exponent

READ _ VIN_CAL _OFFSET = Mantissa ´ 2

•

Exponent is fixed at -5

LSB value is 32vmV

Range -2vV to 1.968vV

(34)

MFR_SPECIFIC_07 (D7h)

This command applies a gain correction to the READ_VIN command results to calibrate out gain errors in the on

board measurement system. The contents of this register can be stored to non-volatile memory using the

STORE_DEFAULT_ALL or STORE_DEFAULT_CODE commands.

Command

Format

MFR_SPECIFIC_07

Linear, two's compliment binary

Bit Position

Access

7

r

6

r

5

4

r

3

r

2

1

r⁽¹⁾

0

r⁽¹⁾

7

r⁽¹⁾

6

r⁽¹⁾

5

r⁽¹⁾

4

3

2

1

0

r

Exponent

0

r/w

Function

Mantissa

0

Default Value

1

0

(1) Bits are sign extension only and are not otherwise programmable.

Default value: 0

Exponent

READ _ VIN_CAL _GAIN = Mantissa ´ 2

•

Exponent is fixed at -8

LSB value is 0.4%

Range -0.125V to 10.121

(35)

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MFR_SPECIFIC_44 (FCh)

This command returns a two byte unsigned binary 12-bit device identifier code and 4-bit revision code in the

following format.

Command

Format

MFR_SPECIFIC_44

Linear, two's complement binary

Bit Position

Access

7

r

6

r

5

r

4

r

3

r

2

r

1

r

0

r

7

r

6

r

5

r

4

r

3

r

2

r

1

r

0

r

Function

Identifier Code

Revision Code

Default Value

0

1

0

1

0

1

This command is oriented toward providing similar information to the DEVICE_ID command but for devices that

do not support block read and write functions.

Identifier Code

Fixed at 1 (dec)

Revision Code

Starts at 0 and increments as revisions progress.

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DESIGN EXAMPLES

Design Example 1: 12-V Input, 1.2-V Output, 20-A (max) Output Current

Design Parameters

The following example illustrates the design process and component selection for a synchronous buck converter

using the TPS40400 controller. The design goal parameters are listed in Table 3.

Table 3. Design Electrical Parameters

PARAMETER

INPUT CHARACTERISTICS

NOTES AND CONDITIONS

MIN

NOM

MAX UNITS

V_IN

I_IN

Input voltage

8

12

3.6

60

7

14

V

A

Input current

V_IN= 8 V, I_OUT= 20 A

V_IN= 12 V, I_OUT= 0 A

No load input current

V_INstart voltage

V_INstop voltage

mA

V

V_IN(start)

V_IN(stop)

5

V

OUTPUT CHARACTERISTICS

V_OUT

Output voltage

V_IN= 12 V, I_OUT= 20 A

8 ≤ V_IN≤ 14 V, I_OUT= 20 A

V_IN= 12 V, 0 A ≤ I_OUT≤ 20 A

V_IN= 12 V, I_OUT= 20 A

8 ≤ V_IN≤ 14

1.08

1.2

1.32

0.5%

V

Line regulation

Load regulation

Output ripple voltage

Output current

Vout_ripple

Iout

50 mV_P-P

0

20

29

A

I_OCP

Output over current inception point

Soft-start time

V_IN= 12 V

21

25

SS

(default)

2.8

ms

Transient response

Load step

ΔI

10 A ≤ I_OUT≤ 20 A

10

1

A

A/μS

mV

μs

Load slew rate

Overshoot

120

20

Settling time

SYSTEM CHARACTERISTICS

f_SW

η_PK

η

Switching frequency

Peak efficiency

300

90%

85%

kHz

V_IN= 12 V, 0 A ≤ I_OUT≤ 20 A

V_IN= 12 V, I_OUT= 20 A

Full load efficiency

T_OPER

Operating temperature range

8 ≤ V_IN≤ 14 V, 0 A ≤ I_OUT≤ 20 A

–40

60

°C

Design Procedure

The following design example is for an output of 1.2 V at 20-A maximum, with an input range of 8 V to 14 V.

Selecting a Switching Frequency

This design example is calculated for a switching frequency of 300 kHz to improve efficiency. The switching

frequency can be changed with the Fusion GUI, but some components may need to be revised at other switching

frequencies.

Output Inductor, L_OUT

The output inductor value is determined by the peak-to-peak ripple at high line, and in this case a value of 30%

of output current maximum is used.

V

- V_OUT

IN max

(

V_OUT

)

1

14 -1.2

1

L_OUT

=

´

=

f_SW0.3´ 20 300kHz

´

= 610nH

0.3´I_OUT

V

IN max

(

)

(36)

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For this design a 750-nH inductor from Pulse (PG0077.801) was selected. The actual ripple current should now

be recalculated using the actual inductance value.

V

1.2

L

I

= di = dt ´

= 3.05m ´

= 4.88A

P-P

RIPPLE

L

0.75m

(37)

With this ripple current, the inductor RMS and peak current values can be calculated.

The RMS value of a zero-average triangular wave is given by Equation 38.

æ

ç

è

ö²

÷

4.88

12

2

(_DC) (_AC)

2

I_RMS

=

I

+ I

=

20

( )

+

= 20.05A_RMS

ø

(38)

(39)

At maximum load and maximum line, the peak inductor current is given by Equation 39.

I_P-P

4.88

I_PEAK= I_DC

+

= 20 +

= 22.44A_PEAK

2

The DCR of the selected inductor (from the data sheet) is 1.2 mΩ. Inductor conduction losses are described in

Equation 40.

P = I²´R = I

²´DCR = 20.05 ²´1.2mW = 0.482W

(

)

(

)

RMS

(40)

Output Capacitance, C_OUT

The selection of the output capacitor is typically affected by the output transient response requirement.

Equation 41 and Equation 42 can be used to over-estimate the voltage deviation to account for delays in the loop

bandwidth and can be used to determine the required output capacitance. The estimate of C_OUTbased on

overshoot is shown in Equation 41.

2

DI

´L

O

DI

´L

O

(

)

´C

OUT

V

<

´ Dt =

´

=

OVERSHOOT

C

V

OUT

OUT OUT

(41)

The estimate of C_OUTbased on undershoot is shown in Equation 42.

2

)

DI

(

´L

O

DI

´L

O

OUT

V

<

´ Dt =

´

=

_OUT) (

UNDERSHOOT

C

V

- V

V

- V

´ C

(

)

OUT OUT

OUT

IN

(42)

When V_IN(min)> 2 x V_OUT, use the overshoot equation (V_Overshoot)to calculate minimum output capacitance.

When V_IN(min)< 2 x V_OUTuse the undershoot equation (V_Undershoot). In this design example, V_IN(min)is much larger

than 2 x V_OUTso Equation 43 is used to determine the required minimum output capacitance.

2

)

2

10 ´750nH

( )

1.2´120mV

DI

´L

(

OUT

C

=

= 520mF

OUT

V

´ V

OUT

OVERSHOOT

(43)

The Resistive Component of Output Ripple

With a minimum capacitance, the maximum allowable ESR is determined by the maximum ripple voltage and is

approximated by Equation 44.

æ

ç

è

ö

÷

ø

I

æ

ç

è

ö

÷

ø

4.88

8´ 521mF´300kHz

4.88

RIPPLE

V

-

50mV -

SPEC

V

- V

RIPPLE cap

8´ C

´ f

SW

SPEC

(

)

OUT

RIPPLE

ESR

=

= 9.45mW

(44)

MAX

I

RIPPLE

The factor of 8 in the equation above results from the calculation of capacitor voltage resulting from a triangular

current. For this design, a 680-µF, 45-mΩ ESR, 5-nH ESL tantalum and two, 47-µF, 3-mΩ ESR, 0.9-nH ESL

ceramic capacitors were selected for a total capacitance of 780 µF.

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Peak Current Rating of the Inductor

With the output capacitance known, it is possible to calculate the charge current during start-up and determine

the minimum saturation current rating for the inductor. The start-up charging current is shown in Equation 45 and

the resulting peak inductor current is shown in Equation 46 .

1.2´ 680m + 2´ 47m

(

3.1m

V

´ C

)

OUT

I

=

= 0.3A

CHARGE

t

SS

(45)

(46)

I

æ

ö

÷

4.88

2

æ

ö

RIPPLE

I_{L1 peak}= I_{OUT max}

+

+ I_CHARGE= 20 +

+ 0.3 = 23.04A

ç

è

ç

÷

(

)

(

)

2

è

ø

Input Capacitance, C_IN

The input capacitor is selected to limit the input ripple voltage to 20% or less of V_IN. The ripple voltage is due to

the current flowing in the input capacitor’s ESR as well as capacitance charging and discharging. To simplify the

calculations, an infinitely large series input inductance is assumed. With an infinite inductor, the input capacitor

current is calculated to be 5.6 Arms.

For reasons of availability, consider the capacitor EEVFC1E331P, which is an electrolytic, 330-µF, 25-V

capacitor with 150-mΩ of ESR and 100-nH ESL. This capacitor has an rms current rating of 670 mA. With the

calculated rms value of the capacitor current of 5.6 Arms, this implies that needs to be additional capacitance

with a much lower ESR across the input bus in order to divert most of the AC current to this low ESR capacitor.

Another readily available capacitor is selected. A 22-µF, ceramic, 25-V, 10-mΩ ESR, 0.9-nH ESL device, two in

parallel. With these capacitors in parallel, the ripple in the electrolytic is well within its rating with a value of

329 mA_rms

.

Switching MOSFETs, Q_HSand Q_LS

The high-side and low-side FETs, Q_HSand Q_LS, are selected based on several factors including:

•

Vds, the drain to source voltage rating. This design requires a 25-V device

Vgs, the gate to source voltage rating. For the TPS40400 this voltage is 6.5 V

Conduction losses, based on I²×R_DS(on)

Gate charge, must be low enough to be driven by the PWM controller

These devices are selected:

VOLTAGE RATING

(V)

R_DS(on)

(mΩ)

GATE CHARGE

Q_G(nC)

LOCATION

PART NUMBER

QTY

High-side

Low-side

CSD16404Q5A

CSD16325Q5

25

4.1

1.7

8

1

2

25

Since the selected FETs are very fast, the controller is programmed to have the shorter dead-time of 25 ns.

General Component Selection

Refer to the schematic in Figure 21 for device reference designators and connections for the TPS40400 Design

Example 1.

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Figure 21. Schematic

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Device Addressing, R_ADDR0and R_ADDR1

The PMBus address for the device must be read from the ADDR0 and ADDR1 pins. Each pin has an internal

fixed current source and the resulting developed voltage is read and converted to the desired device address.

The external resistors R_ADDR0and R_ADDR1from the address pins to ground set eight possible states for a total of

64 possible addresses. The address states are determined by voltages on the address pins per Table 4.

Table 4. Address

Configuration

DIGIT

RESISTANCE (kΩ)

0

1

2

3

4

5

6

7

10

15.4

23.7

36.5

54.9

84.5

130

200

For this design, the address of 34 octal, or 28 decimal is selected arbitrarily. In order to achieve this address, the

ADDR0 resistor R5 would be 54.9 kΩ and the ADDR1 resistor R4 would be 36.5 kΩ.

Current Sense Flter, R16 and C17

Current sensing for the TPS40400 is typically done by sensing the voltage drop across the output inductor’s (L1)

DC resistance. In order to do this, the large AC switching voltage forced across L1 must be filtered out so that

the measured voltage is only the DC drop. This is done by placing an R-C filter directly across the output choke

(high-frequency filter) L1. The R-C combination is chosen such that it provides enough filtering for the application

and the time constant is chosen to match that of the output inductor and its ESR, which is shown in Equation 47.

L1

t =

DCR

(47)

Usually a capacitor value is chosen between 10 nF and 1 µF for this location. A value of 100 nF is arbitrarily

chosen, which yields Equation 48.

L1

1

750nH

R16 =

´

=

= 6.25kW

DCR

C

1.2mW ´100nF

(48)

Choose a standard value of 6.19 kΩ.

The capacitor C17 should be placed as close to the ISNS+ and ISNS– pins as possible to provide good bypass

filtering. R16 should be placed close to the inductor to prevent traces with the switch node voltage from being

propagated across the PCB and getting close to sensitive pins of the TPS40400.

Voltage Decoupling Capacitors, C_BP3, C_BP6, and C_VDD

Three pins on the TPS40400 have DC bias voltages. It is necessary to add small decoupling capacitors to these

pins. Table 5 shows the recommended minimum values.

Table 5. Voltage Decoupling Capacitor Values

RECOMMENDED

DEVICE LOCATION

FUNCTION

SELECTED VALUE

MINIMUM VALUE

0.1-µF low ESR

1-µF low ESR

V_CCfor internal controls of the

device

C_BP3, (C18)

C_BP6, (C15)

1-µF ceramic

V_CCfor gate drivers

2 x 100 nF, with additional series 10-Ω filter

resistor R3 to filter out switching noise from the

power FETs

C_VDD, (C1) and (C2)

0.1-µF low ESR

V_CCfor input power to the device

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Bootstrap Capacitor, C9

Selection of the bootstrap capacitor is based on the total gate charge of the high-side FET and the allowable

ripple on the BOOT pin. A ripple of 0.2 V is chosen as maximum for this design. This yields a value described in

Equation 49.

Q_GHS

8nC

C_BOOT= C9 ³

´

V_{BOOT ripple}0.2V

= 40nF

(

)

(49)

Choose a standard value of 100 nF. Additionally, a series resistor R9 is added in order to reducing the turn-on

speed of the high-side FET, Q1.

Snubber R12 and C16

For this design, the snubber function is designed based on an allowable snubber power dissipation. A target

value of between 0.25% and 0.5% of the rated output power (P_OUT) is used as the starting point for the

calculation of the snubber values. Once the snubber values are determined and real hardware is obtained, the

snubber values can be adjusted to achieve better results.

Energy

E

1

= 2 events ´ ´C´ V ´300kHz

2

=

seconds cycle

´ f

(

)

SW

2

(50)

(51)

60mW

C =

=

= 1.02nF

V²´ 300kHz

196´300kHz

Shortest Pulse Width

28.6n 28.6n

=

10

R =

=

= 5.72W

5´ C

5´1n

(52)

Loop Compensaton Components

Using the Texas Instruments SwitcherPro™ design tool and the resulting plant (system) bode plot, a crossover

frequency of 20 kHz is selected with 45° of phase margin. The resulting compensation components are listed in

Table 6.

Table 6. Deisgn Example 1 Component Summary

COMPONENT LOCATION

VALUE

4.99 kΩ

2.74 kΩ

680 pF

2.2 nF

R6

R8

C6

C7

C8

820 pF

Output Voltage Set Point, R_BIAS

The output voltage can be set by choosing and calculating R1 and R_BIAS. The V_OUTset point is shown in

Equation 53.

V

´R1

REF

R

=

BIAS

V

- V

REF

OUT

(53)

In this design R1 was chosen to be 10 kΩ. R_BIASis calculated to be 10 kΩ.

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Remote Sensing

Remote sensing can be accomplished with the differential amplifier as shown in Figure 22. Resistors RS1 and

RS2 (R7 and R18 in the schematic above) are used if the sense connections fail or get damaged. The values of

RS1 and RS2 are bound by an upper value such that the voltage drop across them does not introduce

appreciable voltage regulation error from the bias current, and a lower value such that the voltage drop in the

load wires which appears across these resistors does not dissipate appreciable power. Values between 10 Ω to

50 Ω are usually chosen.

U1

TPS40400

1

2

3

4

5

6

7

8

9

CLK

24

23

22

21

20

DATA

SMBALT

ADDR1

ADDR0

VDD

CNTL

PG

C2

SYNC

TRACK

COMP

FB

R2

C3

C1

Rbias

R3

R1

HDRV 19

BOOT 18

SW 17

LDRV 16

GND 15

BP6 14

BP3 13

+SENSE

DIFFO

VSNS+

VOUT

PGND

Rs1

LOAD

10 VSNS-

11 ISNS-

12 ISNS+

-SENSE

Rs2

SGND

PAD

Figure 22. Remote Sense Schematic

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Typical Performance Characteristics

70

60

140

120

96

Gain

Phase

f_SW= 300 kΩ

94

50

Reference 100

92

90

88

86

84

82

80

40

80

60

40

20

0

30

20

10

0

−10

−20

−30

−20

−40

I_OUT= 20 A

V_IN= 14 V

V_IN= 8 V

V_IN= 12 V

V_IN= 14 V

−60

100000

100

1000

10000

Frequency (Hz)

0

2

4

6

8

10

12

14

16

18

20

G000

Output Current (A)

G000

Figure 23. Efficiency

Figure 24. Plant (System) Bode

Figure 25. Switching Waveform

Figure 26. Ripple Waveform

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Design Example 1 List of Materials

Table 7 lists of materials for Design Example 1.

Table 7. List of Materials

REFERENCE

DESIGNATOR

QTY

VALUE

100 nF

DESCRIPTION

Ceramic, 25 V, X7R, 10%

SIZE

0603

PART NUMBER

Std

MFR

C1, C2, C9, C17

C11

4

1

Std

TPSE687K006R004

5

680 µF

Tantalum, 6.3 V, 10%

7343 (D)

AVX

C13, C14

C15, C18

C16

2

1

2

1

2

47 µF

1 µF

Ceramic, 6.3 V, X7R, 10%

Ceramic, 16 V, X7R, 10%

Ceramic, 25 V, X7R, 10%

Ceramic, 50 V, X7R, 10%

Ceramic, 25 V, X7R, 10%

Aluminum, 25 V, 150 mΩ, FC series

Ceramic, 50 V, X7R, 10%

LED, Red, 20-mA, 6-mcd

1210

0805

Std

1.0 nF

10 nF

1.0 µF

22 µF

330 µF

680 pF

2.2 nF

820 pF

RED

0603

Std

C20

0603

Std

C21

1206

Std

C3, C4

C5

1210

Std

10 mm x 12 mm

0603

EEVFC1E331P

Panasonic

Std

C6

Std

C7

0603

Std

C8

0603

Std

D1, D2

0603

LTST-C190CKT

Lite On

0.40 inch x 0.35

inch

On Shore

Technology

J1, J2

J3, J4

J6

2

1

D120/2DS

L35

Terminal block, 2-pin, 15-A, 5.1mm

ED120/2DS

L35

Type L - copper single conductor, one-hole

mount

0.813 inch x 0.375

inch

Thomas and Betts

AMP

0.607 inch x 0.484

inch

86479-3

Male right angle 2 x 5-pin, 100mil spacing

86479-3

JP1, JP2

L1

2

1

PEC02SAAN Header, 2-pin, 100 mil Spacing

0.100 inch x 2

PEC02SAAN

Sullins

Pulse

0.75 µH

Inductor, SMT, 0.75 µH, 1.2 mΩ, 31A

0.512 x 0.571 inch PG0077.801

CSD16404Q5

A

Q1

1

MOSFET, N-channel, 25 V, 20 A, 4.1 mΩ

QFN5X6mm

CSD16404Q5A

TI

Q2, Q3

R1, R2

R10, R17, R19

R12

2

3

1

2

1

3

1

CSD16325Q5 MOSFET, N-channel, 25 V, 33 A, 1.7 mΩ

QFN-8 POWER

0603

CSD16325Q5

TI

1 kΩ

Resistor, 1/16-W, 5%

Resistor, 1/16W, 1%

Resistor, 1/8W, 1%

Resistor, 1/16W, 1%

Std

10 kΩ

0603

2.74 kΩ

100 kΩ

200 Ω

0 Ω

1206

R13

0603

R14

0603

R15

0603

R16

6.19 kΩ

10 Ω

0603

R3, R9

R4

0603

36.5 kΩ

54.9 kΩ

4.99 kΩ

49.9 Ω

2.74 kΩ

0603

R5

0603

R6

0603

R7, R11, R18

R8

0603

TPS40400RH 3.0 V to 20 V PMBus synchronous buck

controller

U1

1

QFN-24

TPS40400RHL

TI

L

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Internal Configuration

Internal configuration of the TPS40400 is handled via the PMBus (pins CLK and DATA) and the Fusion Digital

Power Designer (GUI interface). An example of the configuration window that is used to make internal

configuration changes to the TSP40400 is shown below in Figure 27.

Figure 27. Advanced Configuration Window

Figure 27 shows are the user changeable parameters of the TPS40400 and these consist of the following

sections.

•

Calibration

Configuration

Limits

On/Off Configuration

The status section is read only, and consists of data read from the TPS40400 such as V_OUT, I_OUT, V_IN, and status

words. A full description of each command and status word is available in the SUPPORTED COMMANDS

section of the TPS40400 datasheet.

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Configuration changes can be implemented by changing the value in the Value/Edit box of each parameter.

Most boxes allow direct parameter changes such as voltage or current, but some boxes such as

IOUT_OC_FAULT_RESPONSE provide a pop-up configuration window as shown in Figure 28, and others

provide a pull-down menu. Select the appropriate radio buttons to make the desired changes.

To implement the changes to the device, click on the [Write to Hardware] button. This stores the changes to the

device in volatile memory, so these changes are lost when input power is cycled. To permanently make changes

and commit those changes to non-volatile memory, click on the [Store RAM to Flash] button.

Figure 28. IOUT_OC_FAULT_RESPONE Configuration Window

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Design Example 2: 12-V Input, 5-V Output, 5-A (max) Output Current

Design Example 2 Parameters

The following example illustrates the design process and component selection for a synchronous buck converter

using the TPS40400 controller. The design goal parameters are listed in Table 8.

Table 8. Design Example 2 Electrical Parameters

PARAMETER

INPUT CHARACTERISTICS

NOTES AND CONDITIONS

MIN

NOM

MAX UNITS

V_IN

I_IN

Input voltage

8

12

3.5

60

7

14

V

A

Input current

V_IN= 8 V, I_OUT= 5 A

No load input current

V_INstart voltage

V_INstop voltage

V_IN= 12 V, I_OUT= 0 A

mA

V

V_IN(start)

V_IN(stop)

6

V

OUTPUT CHARACTERISTICS

V_OUT

Output voltage

V_IN= 12 V, I_OUT= 5 A

8 ≤ V_IN≤,14 V, I_OUT= 5 A

V_IN= 12 V, 0 A ≤ I_OUT≤ 5 A

V_IN= 12 V, I_OUT= 5 A

8 ≤ V_IN≤ 14

4.75

5.00

5.25

0.5%

V

Line regulation

Load regulation

Output ripple voltage

Output current

Vout_ripple

Iout

50 mV_P-P

0

5

A

I_OCP

Output over current inception point

Soft-start time

V_IN= 12 V

6.7

8.0

5

9.3

SS

(default)

ms

Transient response

Load step

ΔI

2 A ≤ I_OUT≤ 5 A

3

1

A

A/μS

mV

μs

Load slew rate

Overshoot

500

50

Settling time

SYSTEM CHARACTERISTICS

f_SW

η_PK

η

Switching frequency

Peak efficiency

300

90%

85%

kHz

V_IN= 12 V, 0 A ≤ I_OUT≤ 5 A

V_IN= 12 V, I_OUT= 5 A

Full load efficiency

T_OPER

Operating temperature range

8 ≤ V_IN≤ 14 V, 0 A ≤ I_OUT≤ 5 A

–40

60

°C

62

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SLUS930B –APRIL 2011–REVISED OCTOBER 2011

General Component Selection

Refer to the schematic below for device reference designators and connections.

Figure 29. Design Example 2 Schematic

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TPS40400

SLUS930B –APRIL 2011–REVISED OCTOBER 2011

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Design Example 2 List of Materials

Table 9 lists of materials for Design Example 2.

Table 9. Design Example 2 List of Materials

REFERENCE

DESIGNATOR

QTY

VALUE

0.1 µF

DESCRIPTION

Ceramic, X7R, 25 V, 20%

SIZE

0603

PART NUMBER

MFR

C1, C2, C9, C17

4

2

1

2

1

2

1

Standard

Panasonic

Standard

Pulse

C3, C4

C5

22 µF

Ceramic, X7R, 25 V, 10%

Aluminum, 25 V, 20%

1210

Standard

330 µF

2700 pF

470 pF

2700 pF

680 µF

47 µF

10x12mm

0603

EEVFC1E331P

Standard

C6

Ceramic, X7R, 10 V, 20%

Tantalum, 6.3 V, 20%

C7

0603

Standard

C8

0603

Standard

C11

C13, C14

C15, C18

C16

L1

7343 (D)

1210

TPSE6870060045

GRM32ER60J476M

Standard

Ceramic, X7R, 6.3 V, 20%

Ceramic, X7R, 16 V, 20%

Ceramic, X7R, 25 V, 20%

Inductor, 6.8 µH, 12 mΩ

1 µF

0603

1000 pF

6.8 µH

0603

Standard

PF0553.682NL

CSD16325Q5

Standard

Q1

CSD16325Q5

10 Ω

Transistor, N-channel FET, 25 V, 100 A, 10 Ω QFN 5x6

TI

Q2

Transistor, N-channel, 25 V, 100 A, 10 Ω

Resistor, 1/16W, 5%

Resistor, 1/16W, 1%

Resistor, 1/16W, 5%

Resistor, 1/16W, 1%

QFN 5x6

0603

TI

R3

Standard

Texas Instruments

R4

39.2 kΩ

64.9 kΩ

10.7 kΩ

49.9 Ω

Standard

R5

Standard

R6

Standard

R7, R18

R8

Standard

1.62 kΩ

10 kΩ

Standard

R10

R12

R14

R16

R17

U1

Standard

2.7 Ω

Standard

0.0 Ω

Standard

5.71 kΩ

1.33 kΩ

TPS40400

Standard

3.0V-20V PMBus synchronous buck controller 24-pin QFN

TPS40400RHL

64

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SLUS930B –APRIL 2011–REVISED OCTOBER 2011

Design Characterization

Figure 30. Switching Voltage and Inductor Current Figure 31. Switching Voltage and Inductor Current

Waveform Waveform

5.140

5.139

5.138

5.137

5.136

5.135

5.134

5.133

5.132

5.140

5.139

5.138

5.137

5.136

5.135

5.134

5.133

5.132

I_OUT= 5 A

I_OUT= 2 A

I_OUT= 0 A

V_IN= 14 V

V_IN= 11 V

V_IN= 8 V

I_OUT= 5 A

8

9

10

11

12

13

14

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

Output Current (A)

Input Voltage (V)

G000

Figure 32. Design Example 2 Line Regulation

Figure 33. Design Example 2 Load Regulation

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REVISION HISTORY

Changes from Revision A (JULY 2011) to Revision B

Page

•

Changed corrected default values in ON_OFF_CONFIG table. ......................................................................................... 23

Added Design Example 1 ................................................................................................................................................... 51

Added Design Example 2 ................................................................................................................................................... 62

66

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PACKAGE MATERIALS INFORMATION

www.ti.com

19-Aug-2011

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TPS40400RHLR

TPS40400RHLT

QFN

RHL

24

3000

250

330.0

180.0

12.4

3.8

5.8

1.2

8.0

12.0

Q1

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

19-Aug-2011

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

TPS40400RHLR

TPS40400RHLT

QFN

RHL

24

3000

250

346.0

190.5

346.0

212.7

29.0

31.8

Pack Materials-Page 2

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型号：	TPS40400
厂家：	TEXAS INSTRUMENTS
描述：	3.0-V TO 20-V PMBus SYNCHRONOUS BUCK CONTROLLER 3.0 V至20 V的PMBus同步降压控制器控制器
文件：	总72页 (文件大小：1956K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TPS40400 [TI]

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