TPS43061 [TI]
具有宽输入电压和用于标准 Low Qg NexFET 的 5.5V 闸极驱动器的低 Iq 同步升压控制器;
| 型号： | TPS43061 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有宽输入电压和用于标准 Low Qg NexFET 的 5.5V 闸极驱动器的低 Iq 同步升压控制器 驱动 控制器 驱动器 |
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TPS43060
TPS43061
www.ti.com
SLVSBP4A –DECEMBER 2012–REVISED DECEMBER 2012
Low Quiescent Current Synchronous Boost DC-DC Controller with Wide V Range
IN
Check for Samples: TPS43060, TPS43061
1
FEATURES
APPLICATIONS
2
•
58 V Maximum Output Voltage
•
•
•
•
•
•
•
Thunderbolt Port for PCs
•
•
4.5 V to 38 V (40 V Abs Max) VIN Range
Automotive Power Systems
Synchronous Flyback
TPS43060: 7.5 V Gate Drive Optimized for
Standard Threshold MOSFETs
GaN RF Power Amplifiers
•
•
TPS43061: 5.5 V Gate Drive Optimized for Low
Qg NexFETs™
Tablet Computer Accessories
Battery Powered Systems
5 V, 12 V, and 24 V DC Bus Power Systems
Current-Mode Control with Internal Slope
Compensation
•
•
•
•
•
•
•
•
•
•
Adjustable Frequency from 50kHz to 1MHz
Synchronization Capability to External Clock
Adjustable Soft-Start Time
DESCRIPTION
The TPS43060 and TPS43061 are low IQ current-
mode synchronous boost controllers with wide input
voltage range from 4.5 V to 38 V (40 V abs max) and
boosted output range up to 58 V. Synchronous
rectification enables high efficiency for high current
applications, and lossless inductor DCR sensing
further improves efficiency. The resulting low power
losses combined with a 3 mm x 3 mm QFN-16
package with PowerPad™ supports high power-
density and high reliability boost converter solutions
over extended (-40°C to 150°C) temperature range.
Inductor DCR or Resistor Current Sensing
Output Voltage Power-Good Indicator
±0.8% Feedback Reference Voltage
5 µA Shutdown Supply Current
600 µA Operating Quiescent Current
Integrated Bootstrap Diode (TPS43061)
Cycle-by-Cycle Current Limit and Thermal
Shutdown
The TPS43060 includes a 7.5 V gate drive supply
which is suitable to drive a broad range of MOSFETs.
The TPS43061 has a 5.5 V gate drive supply and
driver strength optimized for low Qg NexFET™. In
addition, TPS43061 provides an integrated bootstrap
diode for the high side gate driver to reduce external
parts count.
•
•
•
Adjustable UVLO and Output Overvoltage
Protection
Small 16-Pin QFN (3 mm x 3 mm) Package with
PowerPAD™
-40°C to 150°C Operating TJ Range
SIMPLIFIED SCHEMATIC
L
VOUT
VIN
RSENSE
QH
CBOOT
TPS43060/61
CI
CO
ISNS-
BOOT
DBOOT
(Note1)
ISNS+
VIN
QL
VCC
CVCC
EN
PGND
LDRV
PGOOD
COMP
RC
CC
RT/CLK
SW
RT
HDRV
SS
FB
CSS
AGND
RSL
RSH
Note 1: DBOOT is required for TPS43060, but optional for TPS43061.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
NexFETs, PowerPAD are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2012, Texas Instruments Incorporated
TPS43060
TPS43061
SLVSBP4A –DECEMBER 2012–REVISED DECEMBER 2012
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
DEVICE INFORMATION
(1)
Table 1. Ordering Information
TJ
PACKAGE
QFN-16
PART NUMBER(2)
TPS43060RTE
TPS43061RTE
-40˚C to 150˚C
-40˚C to 150˚C
QFN-16
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) The RTE package is available in large and small reel packaging. Add an R suffix to the device type (TPS43061RTER) for the large reel,
or T (TPS43061RTET) for the small reel.
QFN-16 PACKAGE
(TOP VIEW)
16 15 14 13
1
2
3
4
12 SW
RT/CLK
SS
BOOT
11
10
9
PowerPAD
(17)
VCC
COMP
FB
PGND
5
6
7
8
PIN FUNCTIONS
PIN
DESCRIPTION
NAME
NO.
Resistor Timing and External Clock. An external resistor from this pin to the AGND pin programs the
switching frequency between 50 kHz and 1MHz. Driving the pin with an external clock between 300
kHz to 1 MHz will synchronize the switching frequency to the external clock.
RT/CLK
1
SS
2
3
Soft-start programming pin. A capacitor between the SS pin and AGND pin sets soft-start time.
Output of the internal transconductance error amplifier. The feedback loop compensation network is
connected from this pin to AGND.
COMP
Error amplifier input and feedback pin for voltage regulation. Connect this pin to the center tap of a
resistor divider to set the output voltage.
FB
4
5
6
Inductor current sense comparator inverting input pin. This pin is normally connected to the inductor
side of the current sense resistor.
ISNS-
ISNS+
Inductor current sense comparator non-inverting input pin. This pin is normally connected to the VIN
side of the current sense resistor.
The input supply pin to the IC. Connect VIN to a supply voltage between 4.5 V and 38 V. It is
acceptable for the voltage on the VIN pin to be different from the boost power stage input, ISNS+ and
ISNS- pins.
VIN
7
Low side gate driver output. Connect this pin to the gate of the low side N-channel MOSFET. When
VIN bias is removed, an internal 200 kΩ resistor pulls LDRV to PGND.
LDRV
PGND
8
9
Power ground of the IC. Connect this pin to the source of the low-side MOSFET. PGND should be
connected to AGND via a single point on printed circuit board.
2
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TPS43061
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SLVSBP4A –DECEMBER 2012–REVISED DECEMBER 2012
PIN FUNCTIONS (continued)
PIN
DESCRIPTION
NAME
NO.
Output of an internal LDO and power supply for internal control circuits and gate drivers. VCC is
typically 7.5V for the TPS43060 and 5.5 V for the TPS43061. Connect a low ESR ceramic capacitor
from this pin to PGND. The recommended capacitance range is from 0.47 µF to 10µF.
VCC
10
Bootstrap capacitor node for high-side MOSFET gate driver. Connect the bootstrap capacitor from this
pin to the SW pin. For the TPS43060, also connect a bootstrap diode from VCC to BOOT.
BOOT
SW
11
12
13
14
Switching node of the boost converter. Connect this pin to the junction of the drain of the low side
MOSFET, the source of high side synchronous MOSFET and the inductor.
High side gate driver output. Connect this pin to the gate of the high side synchronous rectifier
MOSFET. When VIN bias is removed, this pin is connected to SW through an internal 200 kΩ resistor.
HDRV
PGOOD
Power good indicator. This pin is an open-drain output. A 10 kΩ pull-up resistor is recommended
between PGOOD and VCC or an external logic supply pin.
Enable pin with internal pull-up current source. Floating this pin will enable the IC. Pull below 1.2 V to
enter low current standby mode. Pull below 0.4 V to enter shutdown mode. The EN pin can be used to
implement adjustable undervoltage lockout (UVLO) using two resistors.
EN
15
Analog signal ground of the IC. AGND should be connected to PGND at a single point on printed circuit
board.
AGND
16
17
The PowerPAD should be connected to AGND. If possible, use thermal vias to connect to an internal
ground plane for improved power dissipation.
PowerPAD
FUNCTIONAL BLOCK DIAGRAM
VIN
ISNS- ISNS+
5.5V or 7.5V
LDO
ILIM
TPS43061
only
BOOT
HDRV
5µA
Reverse
Current
Detect
Slope
Compensation
1.22V
SS
SW
R
S
LOGIC
and
CONTROL
FB
VCC
COMP
LDRV
OVP
PGND
OSC/PLL
RT/CLK
3.2µA
1.342V
PGOOD
1.8µA
O
FB
EN
1.21V
1.098V
AGND
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SLVSBP4A –DECEMBER 2012–REVISED DECEMBER 2012
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ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
VALUE
UNIT
MIN
-0.3
-0.6
-2
MAX
40
Input: VIN, EN, ISNS+,ISNS-
DC Voltage: SW
V
V
60
Transient Voltage (10ns max): SW
60
V
Voltage
FB, RT/CLK, COMP, SS
-0.3
3.6
65
V
BOOT, HDRV Voltage with Respect to Ground
BOOT, HDRV Voltage with Respect to SW Pin
VCC, PGOOD, LDRV
V
8
V
-0.3
8
V
(HBM) QSS 009-105 (JESD22-A114A)
(CDM) QSS 009-147 (JESD22-C101B.01)
2
kV
V
Electrostatic Discharge
500
+150
+150
Operating Junction Temperature Range
Storage Temperature Range
-40
-65
°C
°C
THERMAL CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
QFN
(1)
THERMAL METRIC
UNIT
(16-PINS)
65.7
42.3
18
θJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
θJCtop
θJB
°C/W
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.9
ψJB
17.9
22.7
θJCbot
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
4.5
VIN
0
NOM
MAX
38
UNIT
V
VIN
Input voltage range
VOUT
VEN
VCLK
TJ
Output voltage range
58
V
EN voltage range
38
V
External switching frequency logic input range
Operating junction temperature
0
3.6
V
-40
+150
°C
4
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TPS43061
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SLVSBP4A –DECEMBER 2012–REVISED DECEMBER 2012
ELECTRICAL CHARACTERISTICS
VIN = 4.5 to 38 V, TJ = -40ºC to +150ºC, unless otherwise noted. Typical values are at TA = 25ºC
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY AND ENABLE
VIN
Input voltage range
4.5
3.7
3.9
38
4
V
V
Input undervoltage threshold
VIN falling
VIN rising
3.9
4.1
VUV
4.3
V
Vhys
IQ
Undervoltage lockout hysteresis
200
mV
Device non-switching,
RT = 115 kΩ, VFB = 2 V
Operating quiescent current into VIN
600
800
µA
ISD
Shutdown current
VEN = 0.4V
1.5
0.7
5
0.9
µA
V
EN pin voltage threshold to standby
EN pin voltage threshold to enable the device
EN pin voltage threshold to disable the device
EN pin pull-up current
VEN ramping down
VEN ramping up
VEN ramping down
VEN = 1 V
0.4
1.12
1
VEN
1.21
1.14
1.8
1.29
1.28
V
V
µA
µA
µs
IEN
tEN
EN pin hysteresis current
VEN = 1. 3V
3.2
4.6
EN to start switching time
CVCC = 0.47 µF
125
VIN = 12 - 38 V,
IVCC = 0 µA
7.5
4.5
5.5
4.5
V
V
V
TPS43060
VIN = 4.5 V,
IVCC = 0 µA
VCC
VCC voltage
VIN = 12 - 38 V,
IVCC = 0 µA
TPS43061
VIN = 4.5 V,
IVCC = 0 µA
V
IVCC
VCC pin maximum output current
50
mA
VOLTAGE REFERENCE AND ERROR AMPLIFIER
TJ = 25°C
1.21
1.22
1.22
20
1.23
V
VREF
IFB
Feedback Voltage Reference
TJ = -40°C to 150°C
1.195
1.244
Error Amplifier input bias current
COMP pin sink current
nA
µA
VFB = VREF + 250 mV,
VCOMP = 1.5 V
160
160
ICOMP
VFB = VREF - 250 mV,
VCOMP = 1.5 V
COMP pin source current
COMP pin clamp voltage
µA
V
High clamp, VFB = 1V
Low clamp, VFB = 1.5 V
Duty cycle = 0%
2.1
0.7
1
VCLAMP
COMP pin threshold
V
Gea
Rea
Fea
Error amplifier transconductance
Error amplifier output resistance
Error amplifier crossover frequency
1.1
10
2
m-mho
MΩ
MHz
CURRENT SENSE
Maximum current sense threshold
At 0% Duty Cycle
At Max Duty Cycle
64
50
73
61
3.8
70
70
82
72
mV
mV
mV
µA
VCSmax
Maximum current sense threshold
Reverse current sense threshold
Sense+ pin current
VRCsns
ISNS+
ISNS-
Sense- pin current
µA
RT/CLK
Operating frequency range
using resistor timing mode
50
1000
kHz
fSW
Switching frequency
RT/CLK pin voltage
RT = 115 kΩ
RT = 75 kΩ
450
675
500
750
0.5
550
825
kHz
kHz
V
VRT/CLK
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SLVSBP4A –DECEMBER 2012–REVISED DECEMBER 2012
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ELECTRICAL CHARACTERISTICS (continued)
VIN = 4.5 to 38 V, TJ = -40ºC to +150ºC, unless otherwise noted. Typical values are at TA = 25ºC
PARAMETER
tCLK-min Minimum input clock pulse width
vCLK-H
TEST CONDITIONS
MIN
TYP
14
MAX
60
UNIT
ns
PLL = 500 kHz
RT/CLK high threshold
RT/CLK low threshold
PLL frequency sync range
PLL lock in time
1.78
1.35
2
V
0.4
V
fCLK
300
1000
250
kHz
µs
tPLLIN
100
140
tPLLEXIT
Last RT/CLK falling edge to return to resistor timing mode if CLK is not present
250
µs
POWER SWITCH DRIVERS
VIN = 12 V - 40 V
VIN = 4.5 V
2
3
TPS43060
TPS43061
TPS43060
TPS43061
TPS43060
TPS43061
TPS43060
TPS43061
Ω
Ω
LDRV pull-up resistance
VIN = 12 V - 40 V
VIN = 4.5 V
2.5
3
RLDRV
VIN = 12 V - 40 V
VIN = 4.5 V
1.2
2
Ω
LDRV pull-down resistance
HDRV pull-up resistance
HDRV pull-down resistance
VIN = 12 V - 40 V
VIN = 4.5 V
1.6
2
Ω
VIN = 12 V - 40 V
VIN = 4.5 V
2
Ω
2.8
5
VIN = 12 V - 40 V
VIN = 4.5 V
Ω
5.5
1.2
1.9
3
RHDRV
VIN = 12 V - 40 V
VIN = 4.5 V
Ω
VIN = 12 V - 40 V
VIN = 4.5 V
Ω
3.7
15
20
10
15
15
20
10
15
TPS43060
TPS43061
TPS43060
TPS43061
TPS43060
TPS43061
TPS43060
TPS43061
High side gate rise time, 10% to
90%
CLOAD = 2.2 nF,
VIN = 12 V - 40 V
tHR
tHF
tLR
ns
ns
ns
High side gate fall time, 90% to
10%
CLOAD = 2.2 nF,
VIN = 12 V - 40 V
Low side gate rise time, 10% to
90%
CLOAD = 2.2 nF,
VIN = 12 V - 40 V
Low side gate fall time, 90% to
10%
CLOAD = 2.2 nF,
VIN = 12 V - 40 V
tLF
VF
ns
V
BOOT diode forward voltage
drop
TPS43061
TPS43061
IF = 10 mA, TA = 25ºC
0.75
IBOOT
tON
BOOT pin leakage current
Vr = 60 V
0.1
100
250
65
µA
ns
ns
ns
LDRV minimum on pulse width
LDRV minimum off pulse width
fSW = 500 kHz
fSW = 500 kHz
VIN = 12V
tOFF
TPS43060,
CLOAD = open,
fSW = 500 kHz
Time delay between LDRV
fall(50%) to HDRV rise (50%),
tnon-overlap1
VIN = 4.5V
75
ns
TPS43061,
CLOAD = open,
fSW = 500 kHz
VIN = 12V
VIN = 4.5V
65
75
ns
ns
tdelay
TPS43060,
CLOAD = open,
fSW = 500 kHz
VIN = 12V
VIN = 4.5V
65
75
ns
ns
Time delay between HDRV fall
(50%) to LDRV rise (50%), tnon-
TPS43061,
CLOAD = open,
fSW = 500 kHz
VIN = 12V
VIN = 4.5V
65
75
ns
ns
overlap2
6
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SLVSBP4A –DECEMBER 2012–REVISED DECEMBER 2012
ELECTRICAL CHARACTERISTICS (continued)
VIN = 4.5 to 38 V, TJ = -40ºC to +150ºC, unless otherwise noted. Typical values are at TA = 25ºC
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER GOOD, SS AND OVP
VFB with respect to
Feedback Voltage
Reference, VFB falling
PGOOD low threshold
PGDL
86%
90%
2%
93%
VFB with respect to
Feedback Voltage
Reference
PGOOD low hysteresis
VFB with respect to
Feedback Voltage
Reference, VFB rising
PGOOD high threshold
PGDH
107%
1.8
110%
2%
114%
VFB with respect to
Feedback Voltage
Reference
PGOOD high hysteresis
PGDSC
PGDLK
VIN_PGD
ISS
PGOOD sink current
VPGOOD = 0.4 V
VPGOOD = 7 V
4
100
2.5
5
mA
nA
V
PGOOD pin leakage current
Minimum VIN for valid PGOOD
Soft-start bias current
4.3
VSS = 0 V
µA
Ω
RSS
Soft-start discharge resistance
250
VFB with respect to
Feedback Voltage
Reference, VFB rising
OVP threshold
OVP hysteresis
104%
107%
2%
110%
VOVP
VFB with respect to
Feedback Voltage
Reference
THERMAL SHUTDOWN
TSD
Thermal shutdown set threshold
Thermal shutdown hysteresis
165
15
°C
°C
Thyst
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TYPICAL CHARACTERISTICS
VIN = 12 V, fSW = 500 kHz, TA = 25ºC (unless otherwise noted)
4.5
4.4
4.3
4.2
4.1
4.0
3.9
3.8
3.7
3.6
3.5
6
V
= 4.5 V
VIN Rising
IN
V
= 12 V
VIN Falling
IN
5
V
= 24 V
IN
V
= 40 V
IN
4
3
2
1
0
œ50
œ25
0
25
50
75
100
125
150
œ50
œ25
0
25
50
75
100
125
150
C002
C003
Temperature (°C)
Temperature (°C)
Figure 1. Input Start and Stop Voltage vs Temperature
Figure 2. Shutdown Supply Current vs Temperature
680
600
VIN =4.5V
RT = 115 kꢀ
580
560
540
520
500
480
460
440
420
400
VIN =12V
= 24 V
660
640
620
600
580
560
540
520
V
IN
V
= 40 V
IN
œ50
œ25
0
25
50
75
100
125
150
œ50
œ25
0
25
50
75
100
125
150
C004
C005
Temperature ( C)
Temperature (°C)
Figure 3. Non-Switching Supply Current vs Temperature
Figure 4. Frequency vs Temperature
1.240
1.235
1.230
1.225
1.220
1.215
1.210
1.205
1.200
3.0
2.5
2.0
1.5
1.0
0.5
0.0
COMP Pin Clamp High
COMP Pin Clamp Low
œ50
œ25
0
25
50
75
100
125
150
œ50
œ25
0
25
50
75
100
125
150
C006
C007
Temperature ( °C)
Temperature (°C)
Figure 5. Feedback Voltage Reference vs Temperature
Figure 6. COMP Clamp Voltage vs Temperature
8
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SLVSBP4A –DECEMBER 2012–REVISED DECEMBER 2012
TYPICAL CHARACTERISTICS (continued)
VIN = 12 V, fSW = 500 kHz, TA = 25ºC (unless otherwise noted)
3.0
7
6
5
4
3
2
1
0
2.5
2.0
1.5
1.0
0.5
0.0
œ50
œ25
0
25
50
75
100
125
150
œ50
œ25
0
25
50
75
100
125
150
C008
C009
Temperature (°C)
Temperature (°C)
Figure 7. EN Pull-Up Current vs Temperature
Figure 8. EN Hysteresis Current vs Temperature
1.26
1.24
1.22
1.20
1.18
1.16
1.14
1.12
1300
1200
1100
1000
900
EN Voltage Rising
EN Voltage Falling
800
700
600
œ50
œ25
0
25
50
75
100
125
150
œ50
œ25
0
25
50
75
100
125
150
C010
C011
Temperature (°C)
Temperature (°C)
Figure 9. Enable Threshold vs Temperature
Figure 10. Error Amplifier Transconductance vs
Temperature
7
6
5
4
3
2
1
0
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
œ50
œ25
0
25
50
75
100
125
150
œ50
œ25
0
25
50
75
100
125
150
C012
C013
Temperature (°C)
Temperature (°C)
Figure 11. SS Charge Current vs Temperature
Figure 12. Gate Driver Output Resistance vs Temperature
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TYPICAL CHARACTERISTICS (continued)
VIN = 12 V, fSW = 500 kHz, TA = 25ºC (unless otherwise noted)
110
100
80
60
40
20
0
0% Duty Cycle
Max Duty Cycle
FB Rising
108
106
104
102
100
VIN = 12 V
fsw = 500 kHz
œ50
œ25
0
25
50
75
100
125
150
œ50
œ25
0
25
50
75
100
125
150
C014
C015
Temperature (°C)
Temperature (°C)
Figure 13. OVP Threshold vs Temperature
Figure 14. Maximum Current Sense Threshold vs
Temperature
5
4
3
2
1
0
10
TPS43060
TPS43061
9
8
7
6
5
4
3
2
1
0
VIN = 12 V
IVCC = 0 µA
œ50
œ25
0
25
50
75
100
125
150
œ50
œ25
0
25
50
75
100
125
150
C016
C017
Temperature (°C)
Temperature (°C)
Figure 15. Reverse Current Sense Threshold vs
Temperature
Figure 16. VCC Voltage vs Temperature
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DETAILED DESCRIPTION
OPERATION
The TPS43060 and TPS43061 are high-performance wide input range synchronous boost controllers that accept
a 4.5 V to 38 V (40 V abs max) input and support output voltages up to 58 V. The devices have gate drivers for
both the low side N-channel MOSFET and the high side synchronous rectifier N-channel MOSFET. Voltage
regulation is achieved employing constant frequency current mode pulse width modulation (PWM) control. The
switching frequency is set either by an external timing resistor or by synchronizing to an external clock signal.
The switching frequency is programmable from 50 kHz to 1 MHz in the resistor programmed mode or can be
synchronized to an external clock between 300 kHz to 1 MHz.
The PWM control circuitry turns on the low side MOSFET at the beginning of each oscillator clock cycle, as the
error amplifier compares the output voltage feedback signal at the FB pin to the internal 1.22 V reference
voltage. The low side MOSFET is turned-off when the inductor current reaches a threshold level set by the error
amplifier output. After the low side MOSFET is turned off, the high side synchronous MOSFET is turned on until
the beginning of the next oscillator clock cycle or until the inductor current reaches the reverse current sense
threshold. The input voltage is applied across the inductor and stores the energy as inductor current ramps up
during the portion of the switching cycle when the low side MOSFET is on. Meanwhile the output capacitor
supplies load current. When the low side MOSFET is turned off by the PWM controller, the inductor transfers
stored energy via the synchronous MOSFET to replenish the output capacitor and supply the load current. This
operation repeats every switching cycle.
The devices feature internal slope compensation to avoid sub-harmonic oscillation that is intrinsic to peak current
mode control at duty cycles higher than 50%. They also feature adjustable soft-start time, optional lossless
inductor DCR current sensing, an output power good indicator, cycle-by-cycle current limit and over-temperature
protection.
SWITCHING FREQUENCY
The switch frequency is set by a resistor (RT) connected to the RT/CLK pin of the TPS43060 and TPS43061.
The relationship between the timing resistance RT and frequency is shown in the Figure 17. The resistor value
required for a desired frequency can be calculated using Equation 1.
57500
RT (kW) =
fsw (kHz)
(1)
1200
1000
800
600
400
200
0
30
100
Resistance (kΩ)
900
G001
Figure 17. Frequency vs RT Resistance
The device switching frequency can be synchronized to an external clock that is applied to the RT/CLK pin. The
external clock should be in the range of 300 kHz to 1 MHz. The required logic levels of the external clock are
shown in the specification table. The pulse width of the external clock should be greater than 20ns to ensure
proper synchronization. A resistor between 57.5 kΩ and 1150 kΩ must always be connected from the RT/CLK
pin to ground when the converter is synchronized to an external clock. Do not leave this pin open.
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LOW DROPOUT REGULATOR
The TPS43060 and TPS43061 contain a low dropout regulators that provides bias supply for the controller and
the gate driver. The output of the LDO of TPS43060 and TPS43061 are regulated to 7.5 V and 5.5 V,
respectively. When the input voltage is below the VCC regulation level the VCC output tracks VIN with a small
dropout voltage. The output current of the VCC regulator should not exceed 50 mA. The value of the VCC
capacitance depends on the total system design, and its startup characteristics. The recommended range of
values for the VCC capacitor is from 0.47 µF to 10 µF.
INPUT UNDERVOLTAGE (UV)
An undervoltage detection circuit prevents mis-operation of the device at input voltages below 3.9 V (typical).
When the input voltage is below the VIN UV threshold, the internal PWM control circuitry and gate drivers are
turned off. The threshold is set below minimum operating voltage of 4.5 V to ensure that a transient VIN dip will
not cause the device to reset. For input voltages between the UV threshold and 4.5 V, the device attempts to
operate, but the electrical specifications are not ensured. The EN pin can be used to achieve adjustable UVLO if
the desired start-up threshold is higher than 3.9 V. Details are provided in the following section.
ENABLE AND ADJUSTABLE UNDERVOLTAGE LOCKOUT (UVLO)
The EN pin voltage must be greater than 1.21 V (typical) to enable TPS43060 and TPS43061. The device enters
a shutdown mode when the EN voltage is less than 0.4 V. In shutdown mode, the input supply current for the
device is less than 5 µA. The EN pin has an internal 1.8 μA pull-up current source that provides the default
enabled condition when the EN pin floats. When the EN pin voltage is higher than the shutdown threshold but
less than 1.21 V, the devices are in standby mode.
Adjustable input UVLO can be accomplished using the EN pin. As shown in Figure 18, a resistor divider from the
VIN pin to AGND sets the UVLO level. Once EN pin voltage crosses the 1.21 V (typical) threshold voltage an
additional 3.2 μA hysteresis current is sourced out of the EN pin. When EN pin voltage falls below 1.14 V
(typical), the hysteresis current is removed. The addition of hysteresis current at the EN threshold facilitates
adjustable input voltage hysteresis. RUVLO_H and RUVLO_L are calculated using Equation 2 and Equation 3
respectively.
VIN
RUVLO_H
3.2 µA
1.8 µA
EN
1.21 V
RUVLO_L
AGND
Figure 18. Adjustable UVLO using EN pin
æ
ö
VEN _ DIS
VSTART
´
æ
-V
ç
÷
STOP
ç
÷
VEN _ON
è
ø
RUVLO _ H
=
ö
VEN _ DIS
IEN _ pup ´ 1-
+ I
EN _ hys
ç
÷
ç
è
÷
VEN _ON
ø
REN _ H ´VEN _ DIS
(2)
(3)
RUVLO _ L
=
VSTOP -VEN _ DIS + REN _ H ´ IEN _ pup + IEN _ hys + I
)
(
EN _ hys
Where
•
VSTART is the desired turn-on voltage at the VIN pin
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•
•
•
•
•
VSTOP is the desired turn-off voltage at the VIN pin
VEN_ON is EN pin voltage threshold to enable the device, 1.21V (typical)
VEN_DIS is EN pin voltage threshold to disable the device, 1.14V (typical)
IEN_hys is the hysteresis current inside the device, 3.2μA (typical)
IEN_pup is the internal pull-up current at EN pin, 1.8μA (typical)
VOLTAGE REFERENCE AND SETTING OUTPUT VOLTAGE
An internal voltage reference provides a precise 1.22 V voltage reference at the error amplifier non-inverting
input. To set the output voltage, select the FB pin resistor RSH and RSL according to Equation 4.
æ
ç
è
ö
÷
ø
RSH
RSL
VOUT =1.22V ´
+1
(4)
MINIMUM ON-TIME AND PULSE SKIPPING
The TPS43060 and TPS43061 also feature a minimum on-time of 100 ns for the low-side gate driver. This
minimum on-time determines the minimum duty cycle of the PWM for any set switching frequency. When the
voltage regulation loop requires a minimum on-time pulse width less than 100 ns, the controller enters pulse-
skipping mode. In this mode, the devices hold the power switch off for multiple switching cycles to prevent the
output voltage from rising above the desired regulated voltage. This operation typically occurs in light load
conditions when the DC-DC converter operates in discontinuous conduction mode. Pulse skipping increases the
output ripple as shown in Figure 27.
ZERO-CROSS-DETECTION and DUTY CYCLE
The TPS43060 and TPS43061 feature zero-cross-detection which turns off high side driver when the sensed
current falls below the reverse current sense threshold (3.8 mV typical), then the converter runs in discontinuous
conduction mode (DCM). The duty cycle is dependent on the mode in which the converter is operating. The duty
cycle in DCM varies widely with changes of the load. In CCM, where the inductor maintains a minimum dc
current, the duty cycle is related primarily to the input and output voltages as computed in Equation 5.
VOUT -VIN
D =
VOUT
(5)
When the converter operates in DCM, the duty cycle is a function of the load, input and output voltages,
inductance and switching frequency in Equation 6.
2´VOUT ´ IOUT ´ L´ fSW
D =
2
VIN
(6)
Equation 5 and Equation 6 provide an estimation of the duty cycle. A more accurate duty cycle can be calculated
by including the voltage drops of the external MOSFETs, sense resistor and DCR of the inductor.
MINIMUM OFF-TIME and MAXIMUM DUTY CYCLE
The low side driver LDRV of TPS43060 and TPS43061 has a minimum off-time of 250 ns or 5% of the switching
cycle period whichever is longer. Figure 19 shows Maximum duty cycle vs. Switching Frequency. The maximum
duty cycle limits the maximum achievable step-up ratio in a Boost converter. When the converter operates in
CCM, the step-up ratio of the boost converter can be calculated using Equation 7.
VOUT
1
=
VIN
1- D
(7)
For instance, if the maximum duty cycle is 90%, the achievable maximum output voltage to input voltage ratio is
limited to:
VOUT
1
=
=10
VIN
1-90%
(8)
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100
95
90
85
80
75
70
50 150 250 350 450 550 650 750 850 950 1050
C019
Frequency (kHz)
Figure 19. Maximum Duty Cycle vs Frequency
SOFT-START
The TPS43060 and TPS43061 have a built-in soft-start circuit which significantly reduces the start-up current
spike and output voltage overshoot. When the IC is enabled, an internal bias current source (5 µA typical)
charges the capacitor (CSS) on the SS pin. When the SS pin voltage is less than the internal 1.22 V reference,
the device regulates the FB pin voltage to the SS pin voltage rather than the internal 1.22 V reference voltage.
Once the SS pin voltage exceeds the reference voltage the device regulates the FB pin voltage to 1.22V. The
soft-start time of the output voltage can be calculated using Equation 9.
1.22V
t = C
ss
ss
5mA
(9)
POWER GOOD
The TPS43060 and TPS43061 PGOOD pin indicates when the output voltage is within pre-determined limits of
the desired regulated output voltage by monitoring the FB pin voltage. The PGOOD pin is driven by the open-
drain signal of an internal MOSFET. When the output voltage of the power converter is not within ±10% of the
output voltage set point, the PGOOD MOSFET turns on and pulls the PGOOD pin low. Otherwise, the PGOOD
MOSFET stays off and the PGOOD pin can be pulled up by an external resistor to a voltage supply up to 8V.
OVERVOLTAGE PROTECTION
The TPS43060 and TPS43061 integrate an overvoltage protection (OVP) circuit that turns off the low side
MOSFET when the output voltage reaches the OVP threshold which is internally fixed to 107% of the output
voltage set point. The low side MOSFET resumes normal PWM control when the output voltage drops below
105% of the output voltage set point. The OVP circuit protects the power MOSFETs and minimizes the output
voltage overshoot during transients or fault conditions.
OVERCURRENT PROTECTION AND CURRENT SENSE RESISTOR SELECTION
The TPS43060 and TPS43061 provide cycle-by-cycle current limit protection that turns off the low side MOSFET
when the inductor current reaches the current limit threshold. The cycle-by-cycle current limit circuitry is reset at
the beginning of the next switching cycle. During an overcurrent event, the output voltage begins to droop as a
function of the load on the output.
A slope compensation ramp is added to the current sense ramp to prevent sub-harmonic oscillations at high duty
cycle. The slope compensation reduces the overcurrent limit threshold (maximum current sense threshold) with
increasing duty cycle as detailed in Figure 20.
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78
74
70
66
62
58
54
50
0
10
20
30
40
50
60
70
80
90 100
C020
Duty Cycle (%)
Figure 20. OverCurrent Limit Threshold with Respect to Duty Cycle
The maximum current sense threshold VCSmax sets the maximum peak inductor current which is the sum of
maximum average inductor (input) current Iave_max and half the peak-to-peak inductor ripple ΔIL. The sense
resistor value should be chosen based on the desired maximum input current and the ripple current, and can be
calculated using Equation 10.
VCS max
RSENSE
=
DIL
Iave_ max
+
(10)
GATE DRIVERS
The TPS43060 and TPS43061 contain powerful high-side and low-side gate drivers supplied by the VCC bias
regulator. The nominal VCC voltage of the TPS43060 and TPS43061 is 7.5 V and 5.5 V respectively. The
TPS43061 gate drivers operate from a 5.5 V VCC supply, with drive strength optimized for low Qg NexFETs™. It
also features an integrated bootstrap diode for the high side gate driver to reduce the external part count. The
TPS43060 gate drivers operate from a 7.5 V VCC supply, which is suitable to drive a wide range of standard
MOSFETs. The TPS43060 requires an external bootstrap diode from VCC to BOOT to charge the bootstrap
capacitor. It also requires a 2Ω resistor connected in series with the VCC pin to limit the peak current drawn
through the internal circuitry when the external bootstrap diode is conducting. See the ELECTRICAL
CHARACTERISTICS table for typical rise and fall times and the output resistance of the gate drivers.
The LDRV and HDRV outputs are controlled with an adaptive dead-time control that ensures that both the
outputs are never high at the same time. This minimizes any cross conduction and protects the power converter.
The typical dead-time from LDRV fall to HDRV rise is 65 ns.
LAYOUT CONSIDERATIONS
As with all switching power supplies, especially those with high frequency and high switch current, printed circuit
board (PCB) layout is an important design step. If layout is not carefully designed, the regulator could suffer from
instability as well as noise problems. To maximize efficiency, switch rise and fall times are made as short as
possible. To prevent radiation and high frequency resonance problems, proper layout of the high frequency
switching path is essential. Minimize the length and area of all traces connected to the SW pin and always use a
ground plane under the switching regulator to minimize inter-plane coupling. The high current path including the
low side MOSFET, high side MOSFET, and output capacitor, experience nanosecond rise and fall times and
should be kept as short as possible. The input capacitor must be located close to the VIN pin and the AGND pin
to reduce the input supply ripple to the controller.
THERMAL SHUTDOWN
An internal thermal shutdown turns off the TPS43060 and TPS43061 when the junction temperature exceeds the
thermal shutdown threshold (165°C typical). The device will restart when the junction temperature drops by 15°C.
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THERMAL CONSIDERATIONS
The maximum IC junction temperature should be restricted to 150°C under normal operating conditions. This
restriction limits the power dissipation of the TPS43060 and TPS43061. The devices are packaged in a thermally
enhanced QFN package which includes a PowerPAD™ that improves the thermal capabilities. The thermal
resistance of the QFN package in any application greatly depends on the PCB layout and the PowerPAD
connection. The PowerPAD must be soldered to the analog ground on the PCB. Use thermal vias underneath
the PowerPAD to achieve good thermal performance.
DESIGN GUIDE – TPS43061 STEP-BY-STEP DESIGN PROCEDURE
The following section provides a step-by-step design guide of a high-frequency, high-power-density synchronous
boost converter with the TPS43061 controller combined with a NexFET™ power block. This design procedure is
also applicable to the TPS43060. A few parameters must be known in order to start the design process. These
requirements are typically determined at the system level. For this example, we will start with the following known
parameters.
Table 2. Key Parameters of the Boost Converter Example
Input voltage (VIN
Output voltage (VOUT
Maximum output current (IOUT
Transient response to 0.5 A to 1.5 A load step (ΔVOUT
Output voltage ripple (VRIPPLE
Start input voltage (VSTART
Start input voltage (VSTOP
)
6 V to 12.6 V, 9 V nominal
)
15 V
)
2 A
)
4% of VOUT = 0.6 V
0.5% of VOUT = 0.075 V
5.34 V
)
)
)
4.3 V
Figure 21. The Schematic of Synchronous Boost Converter using TPS43061
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SELECTING THE SWITCHING FREQUENCY
The first step is to determine the switching frequency of the power converter. There are tradeoffs to consider
when selecting a higher or lower switching frequency. Typically, the designer uses the highest switching
frequency possible since this results in the smallest solution size. A higher switching frequency allows for lower
value inductors and smaller output capacitors compared to a power converter that switches at a lower frequency.
A lower switching frequency will produce a larger solution size but typically has a better efficiency. Setting the
frequency for the minimum tolerable efficiency will produce the optimum solution size for the application.
The switching frequency can also be limited by the minimum on-time and off-time of the controller based on the
input voltage and the output voltage of the application. To determine the maximum allowable switching
frequency, first estimate the continuous conduction mode (CCM) duty cycle using Equation 11 with the minimum
and maximum input voltages. Equation 12 and Equation 13 should then be used to calculate the upper limit of
switching frequency for the regulator. Choose the lower value result from these two equations. Switching
frequencies higher than the calculated values will result in either pulse skipping if the minimum on-time restricts
the duty cycle or insufficient boost output voltage if the PWM duty cycle is limited by the minimum off-time.
VOUT - V
IN
D =
VOUT
(11)
Dmin
20%
fSW ontime =
=
= 2MHz
min 100
Dmin 60%
=
(12)
f
SW offtime =
= 2.4MHz
offmin 250
(13)
The typical minimum on-time and off-time of the device are 100 ns and 250 ns respectively. For this design, the
duty cycle is estimated at 20% and 60% with the maximum input voltage and minimum input voltage respectively.
When operating at switching frequencies less than 200 kHz the minimum off time starts to increase and is equal
to 5% the switching period. The estimated allowed maximum switching frequency based on Equation 12 and
Equation 13 is 2 MHz. When operating near the estimated maximum duty cycle more accurate estimations of the
duty cycle should be made by including the voltage drops of the external MOSFETs, sense resistor and DCR of
the inductor.
A switching frequency of 750 kHz is chosen as a compromise between efficiency and small solution size. To
determine the timing resistance for a given switching frequency use either Equation 14 or the curve in Figure 17.
The switching frequency is set by resistor R5 shown in Figure 21. For 750 kHz operation, the closest standard
value resistor is 76.8 kΩ.
57500
57500
RT (kW) =
=
fSW (kHz) 750(kHz)
= 76.7kW
(14)
INDUCTOR SELECTION
The selection of the inductor affects the steady-state operation as well as transient behavior and loop stability.
These factors make it an important component in a switching power supply design. The three most important
inductor specifications to consider are inductor value, DC resistance (DCR), and saturation current rating. Let the
parameter KIND represent the ratio of inductor peak-peak ripple current to the average inductor current. In a boost
topology the average inductor current is equal to the input current. The current delivered to the output is the input
current modulated at the duty cycle of the PWM. The inductor ripple current contributes to the output current
ripple that must be filtered by the output capacitor. Therefore, choosing high inductor ripple currents impacts the
selection of the output capacitor. The value of KIND in the design using low ESR output capacitors, such as
ceramics, can be relatively higher than that in the design using higher ESR output capacitors. Higher values of
KIND lead to discontinuous mode (DCM) operation at moderate to light loads.
To calculate the minimum value of the output inductor, use Equation 16 or Equation 17. In a boost topology
maximum current ripple occurs at 50% duty cycle. Use Equation 16 if the design will operate with 50% duty
cycle. If not, use Equation 17. In Equation 17, use the input voltage value that is nearest to 50% duty cycle
operation.
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For this design example, Equation 15 produces the estimated maximum input current (IIN) of 5 A. In reality this
will be higher because the simplified equations do not include the efficiency losses of the power supply. Using
KIND = 0.3 with Equation 16, the minimum inductor value is calculated to be 3.33µH. The nearest standard value
of 3.3 µH is chosen. It is important that the RMS current and saturation current ratings of the inductor not be
exceeded. The RMS and peak inductor current can be found from Equation 18 and Equation 19, respectively.
The calculated RMS inductor current is 5.0A and the peak inductor current is 5.73 A. The chosen inductor is a
Vishay IHLP2525CZER3R3M1 which has an RMS current rating of 6 A, a saturation current rating of 10 A and
30 mΩ DCR.
IOUT
2A
IIN
=
=
) (
= 5A
1- Dmax
1- 60%
(
)
(15)
(16)
(17)
VOUT
1
15V
1
L ³
L ³
´
=
´
IIN ´ KIND 4´ fSW 5A´ 0.3 4´750kHz
= 3.33mH
VIN
D
´
IIN ´ KIND fSW
ö2
÷
÷
ø
æ
ö2
æ
ö2
æ
ç
ç
è
IOUT
V
IN min´ Dmax
2A
1- 60%
6V ´ 60%
æ
ö2
÷
ø
ILrms =
+
=
+
= 5A
ç
ç
÷
÷
ç
ç
è
÷
1- Dmax
12 ´ L ´ fSW
12 ´3.3mH ´750kHz
ø
è
è
ø
(18)
(19)
IOUT
V
IN min´ Dmax
2A
6V ´ 60%
IL peak =
+
=
+
1- 60% 2´3.3mH ´750kHz
= 5.73A
1- Dmax
2´ L ´ fSW
Selecting higher ripple currents will increase the output voltage ripple of the regulator but allow for a lower
inductance value.
The current flowing through the inductor is the inductor ripple current plus the average input current. During
power up, load faults or transient load conditions the inductor current can increase above the peak inductor
current calculated above. The above equations also do not include the efficiency of the regulator. For this reason
a more conservative design approach is to choose an inductor with a saturation current rating greater than the
typical switch current limit set by the current sense resistor or the inductor DC resistance if lossless DCR sensing
is used.
SELECTING THE CURRENT SENSE RESISTOR
The external current sense resistor sets the cycle-by-cycle peak current limit. The peak current limit should be
set to assure the maximum load current can be supported at the minimum input voltage. The typical over current
threshold voltage (VCS) with respect to duty cycle is shown in Figure 20. In this design example, the typical
current limit threshold voltage at the 60% maximum duty cycle is 68 mV.
When selecting the current limit for the design, a 20% margin is recommended from the calculated peak current
limit in Equation 19 to allow for load and line transients and the efficiency loss of the design. The recommended
current sense resistance is calculated with Figure 20. In this example the minimum resistance is calculated at
9.89 mΩ and two 20 mΩ resistors in parallel are used. The sense resistors must be rated for the power
dissipation calculated in Equation 22. Using the maximum current limit threshold of 82 mV according to the
electrical specification table, the maximum power loss in the current sense resistor is 0.672 W. Two 0.5 W rated
sense resistors are used in parallel in this design.
VCS maxtyp = 68mV
(20)
VCS maxtyp
68mV
RCS
=
=
1.2´ IL peak 1.2´5.73A
= 9.89mW
= 0.672W
(21)
(VCS max max)2
(82mV )2
10mW
P
=
=
RCS
RCS
(22)
The 10 Ω series resistors R13 and R15 with the 100 pF capacitor C12 filter high frequency switching noise from
the ISNS pins.
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OUTPUT CAPACITOR SELECTION
In a boost topology the current supplied to the output capacitor is discontinuous and proper selection of the
output capacitor is important for filtering the high di/dt path of the supply. There are two primary considerations
for selecting the value of the output capacitor. The output capacitor determines the output voltage ripple, and
how the supply responds to a large change in load current. The output capacitance needs to be selected based
on the more stringent of these two criteria.
The desired response to a large change in load current is the first criteria. A PWM controller cannot immediately
respond to a fast increase or decrease in the load current. The response time is determined by the loop
bandwidth. The output capacitor must supply the increased load current or absorb the excess inductor current
until the controller responds. Equation 23 estimates the minimum output capacitance needed for the desired
ΔVOUT for a given ΔIOUT. The loop bandwidth (ƒBW) is typically limited by the Right Half Plane Zero (RHPZ) of the
boost topology. The maximum recommended bandwidth can be calculated from Equation 41 and Equation 42.
See the compensation section for more information. In this example, to limit the voltage deviation to 600 mV from
a 1 A load step with a 14.5 kHz maximum bandwidth, a minimum of 18.3 µF output capacitance is needed. This
value does not take into account the ESR of the output capacitor which can typically be ignored when using
ceramic capacitors.
The output capacitor absorbs the ripple current through the synchronous switch to limit the output voltage ripple.
Equation 24 calculates the minimum output capacitance needed to meet the output voltage ripple specification.
In this example, a minimum of 21.3 µF is needed. Again this value does not take into account the ESR of the
output capacitor.
DITRAN
2p´ fBW ´ DVTRAN 2p´14.5kHz ´ 0.6V
Dmax´ IOUT
1A
COUT
>
=
= 18.3mF
(23)
60%´5A
fSW ´VRIPPLE 750kHz ´ 0.075V
COUT
>
=
= 21.3mF
(24)
The most stringent criteria for the output capacitor is 21.3 µF required to limit the output voltage ripple. When
using ceramic capacitors for switching power supplies, high quality type X5R or X7R are recommended. They
have a high capacitance to volume ratio and are fairly stable over temperature. Capacitance de-ratings for aging,
temperature and dc bias increase the minimum value required. The voltage rating must be greater than the
output voltage with some tolerance for output voltage ripple and overshoot in transient conditions. For this
example 4 x 10 µF, 25 V ceramic capacitors with 5 mΩ of ESR are used. The estimated derated capacitance is
22 µF, approximately equal to the calculated minimum.
MOSFET SELECTION - NexFET™ POWER BLOCK
The TPS43061 5.5V gate drive is optimized for low Qg NexFET power devices. NexFET power blocks with both
the high-side and low-side MOSFETs integrated are ideal for high power density designs. This design example
uses the CSD86330Q3D. Two primary considerations when selecting the power MOSFETs are the average gate
drive current required and the estimated MOSFET power losses.
The average gate drive current must be less than the 50 mA (minimum) VCC supply current limit. This current is
calculated using Equation 25. With the selected power block and 5.5V VCC, the low-side FET has a total gate
charge of 11 nC and the high-side FET has a total gate charge of 5 nC. The required gate drive current is 12
mA.
IGD = (QgHS + QgLS )´ fSW = (5nC +11nC)´750kHz = 12mA
(25)
The target efficiency of the design dictates the acceptable power loss in the MOSFETs. The two largest
components of power loss in the low-side FET are switching and conduction losses. Both losses are highest at
the minimum input voltage when low-side FET current is maximum. The conduction power loss in the low-side
FET can be calculated with Equation 26. Switching losses occur during the turn-off and turn-on time of the
MOSFET. During these transitions, the low-side FET experiences both the input current and output voltage. The
switching loss can be estimated with Equation 27. The low-side FET of the CSD86330Q3D has RDS(on)LS = 4.2
mΩ, gate to drain charge Qgd = 1.6 nC, output capacitance COSS = 680 pF, series gate resistance RG = 1.2 Ω,
and gate to source voltage threshold VGS(th) = 1.1 V. The conduction power losses are estimated at 0.042 W and
the switching losses are estimated at 0.070 W.
P
= Dmax´ ILrms2 ´ RdsonLS = 60%´5.0A2 ´ 4.2mW = 0.042W
CONDLS
(26)
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æ
ö
÷
Qgd ´ RG
fSW
IOUT
2
ç
P
=
´ COSS ´VOUT +VOUT
´
´
SW
ç
è
÷
ø
2
1- Dmax VCC -VGS th
( )
ö
750kHz
2A
1.6nC ´1.2W
æ
=
´ 680pF ´15V 2 +15V ´
´
= 0.070W
ç
÷
2
1- 60% 5.5V -1.1V
è
ø
(27)
Two power losses in the high-side FET to consider are the dead time body diode loss and the FET conduction
loss. The conduction loss is highest at the minimum PWM duty cycle. The conduction power loss in the high-side
FET can be calculated with Equation 28. Dead time losses are caused by conduction in the body diode of the
high-side FET during the delay time between the LDRV and HDRV signals. The dead time loss varies mainly
with switching frequency. The dead time losses are estimated with Equation 29. The high-side FET of the
CSD86330Q3D has RDS(ON)HS = 8 mΩ and body diode forward voltage drop VSD = 0.75 V. The conduction power
losses are estimated at 0.080 W and the dead time losses are estimated at 0.366 W. For designs targeting
highest efficiency, dead time losses can be reduced by adding a Schottky diode in parallel with the high-side FET
to reduce the diode forward voltage drop during the dead time.
P
= 1- Dmax ´ I rms2 ´ R
= 1- 60% ´5.0A2 ´8mW = 0.080W
(
)
(
)
CONDHS
L
DS(on)LS
(28)
PDT = VSD ´ I rms ´ tnon-overlap1 + tnon-overlap2 ´ f
(
)
= 0.75V ´5A´ 60ns + 65ns ´750kHz = 0.366W
L
SW
(
)
(29)
BOOTSTRAP CAPACITOR SELECTION
A capacitor must be connected between the BOOT and SW pins for proper operation. This capacitor provides
the instantaneous charge and gate drive voltage needed to turn on the high-side FET. A ceramic with X5R or
better grade dielectric is recommended. Use Equation 30 to calculate the minimum bootstrap capacitance to limit
the BOOT capacitor ripple voltage to 250 mV. In this example with the selected high-side FET the minimum
calculated capacitance is 0.042 µF and a 0.1 µF capacitor is used. The capacitor should have a 10 V or higher
voltage rating.
QgHS
5nC
CBOOT
=
=
DVBOOT 250mV
= 0.042mF
(30)
VCC CAPACITOR
An X5R or better grade ceramic bypass capacitor is required for the internal VCC regulator at the VCC pin with a
recommended range of 0.47 µF to 10 µF. A capacitance of 4.7 µF is used in this example. The capacitor should
have a 10 V or higher voltage rating.
INPUT CAPACITOR
The TPS43060 and TPS43061 require a high quality 0.1 µF or higher ceramic type X5R or X7R bypass capacitor
at the VIN pin for proper decoupling. Based on the application requirements additional bulk capacitance may be
needed to meet input voltage ripple and, or transient requirements. The minimum capacitance for a specified
input voltage ripple is calculated using Equation 31. The voltage rating of the input capacitor must be greater
than the maximum input voltage. The capacitor must also have a ripple current rating greater than the RMS
current calculated with Equation 32. If ceramic input capacitors are used they should be high quality ceramic,
type X5R or X7R.
For this example design, the capacitors must be rated for at least 12 V to support the maximum input voltage.
Designing for a 45 mV input voltage ripple (0.5% the nominal input voltage), the minimum input capacitance is
10.8 µF. The input capacitor must also be rated for 0.42 A RMS current. The capacitors selected are 2 x 10 µF,
25 V ceramic capacitors with 5 mΩ of ESR. The estimated voltage de-rated total capacitance is 15 µF.
IRIPPLE
1.46A
CIN
>
=
4´ fSW ´VINRIPPLE 4´ 750kHz ´ 0.045V
= 10.8mF
(31)
(32)
IRIPPLE
1.46A
ICIN rms =
=
= 0.42A
12
12
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OUTPUT VOLTAGE AND FEEDBACK RESISTORS SELECTION
The voltage divider of R8 and R9 sets the output voltage. To balance power dissipation and noise sensitivity, R9
should be selected between 10 kΩ and 100 kΩ. For the example design, 11 kΩ was selected for R9. Using
Equation 33, R8 is calculated as 124.2 kΩ. The nearest standard 1% resistor 124 kΩ is used.
VOUT -VFB
15V -1.22V
RHS = RLS
´
= 11.0kW ´
= 124.2kW
VFB
1.22V
(33)
Where RLS = R9 and RHS = R8.
SETTING THE SOFT-START TIME
The soft-start capacitor determines the amount of time allowed for the output voltage to reach its nominal
programmed value during power up. This is especially useful if a load requires a controlled voltage slew rate. A
controlled start-up time is necessary with large output capacitance to limit the current into the capacitor during
start-up. Large currents to charging the capacitor during start-up could trigger the devices current limit. Excessive
current draw from the input power supply may also cause the input voltage rail to sag. The soft-start capacitor
can be sized to limit in-rush current or output voltage overshoot during startup. Use Equation 34 to calculate the
required capacitor for a desired soft-start time. In this example application for a desired soft-start time of 20 ms, a
0.082 µF capacitance is calculated, and the nearest standard value of 0.1 µF capacitor is chosen.
tSS ´ ISS
20ms ´5mA
CSS
=
=
= 0.082mF
VREF
1.22V
(34)
UNDERVOLTAGE LOCKOUT SET POINT
The undervoltage lockout (UVLO) can be adjusted using an external voltage divider connected to the EN pin of
the TPS43060 and TPS43061. The UVLO has two thresholds, one for power up when the input voltage is rising
and one for power down or brown outs when the input voltage is falling. The necessary voltage divider resistors
are calculated with Equation 35 and Equation 36. If the application does not require an adjustable UVLO, the EN
pin can be left floating or tied to the VIN pin.
For the example design, the supply should start switching once the input voltage increases to 5.34 V (VSTART).
After start-up, it should continue to operate until the input voltage falls to 4.3 V (VSTOP). To produce the desired
start and stop voltages, resistor divider values R3 = 221 kΩ between VIN and EN and a R4 = 59 kΩ between EN
and GND are used.
æ
ö
VEN _ DIS
1.14V
1.21V
1.14V
æ
ö
VSTART
´
-V
ç
ç
è
÷
÷
ø
STOP
5.34V ´
- 4.3V
ç
è
÷
VEN _ ON
ø
ö
RUVLO_ H
=
=
= 221.26kW
æ
ö
æ
VEN _ DIS
1.8mA´ 1-
+ 3.2mA
÷
ç
IEN _ pus ´ 1-
+ I
EN _ hys
ç
÷
÷
ø
1.21V
ç
è
è
ø
VEN _ ON
(35)
(36)
RUVLO_ H ´VEN _ DIS
221kW ´1.14V
4.3V -1.14V + 221kW ´ 1.8mA + 3.2mA
RUVLO_ L
=
=
(
)
VSTOP -VEN _ DIS + RUVLO _ H ´ I
(
+ I
)
EN _ pup
EN _ hys
59
POWER GOOD RESISTOR SELECTION
The PGOOD pin is an open drain output requiring a pull-up resistor connected to a voltage supply of no more
than 8 V. A value between 10 kΩ and 100 kΩ is recommended. If the Power Good indicator feature is not
needed, this pin can be grounded or left floating.
THE CONTROL LOOP COMPENSATION
There are several methods to design compensation for DC-DC regulators. The method presented here is easy to
calculate and ignores the effects of the slope compensation internal to the device. Since the slope compensation
is ignored, the actual crossover frequency will be lower than the crossover frequency used in the calculations.
This method assumes the crossover frequency is between the modulator pole and ESR zero of the output
capacitor. In this simplified model, the DC gain (Adc), modulator pole (ƒPmod), and the ESR zero (ƒZmod) are
calculated with Equation 37 to Equation 39. Use the de-rated value of COUT, which is 22 µF in this example. In a
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boost topology the maximum crossover frequency is typically limited by the right-half plane zero (RHPZ). The
RHPZ can be estimated with Equation 40. The compensation design should be done at the minimum input
voltage when the RHPZ is at the lowest frequency. The crossover frequency should also be limited to less than
1/5 of the switching frequency. Equation 41 and Equation 42 are used to calculate the maximum recommended
crossover frequency. For this example design, Adc = 11.3 V/V, ƒPmod = 1.93 kHz, ƒZmod = 1.45 MHz, ƒRHPZ = 57.9
kHz, ƒco1 = 14.5 kHz, and ƒco2 = 150 kHz. The target fco is 14.5 kHz.
VIN min
3
3
6V
V
Adc =
´
=
´
40 2´ RSENSE ´ IOUT 40 2´10mW ´ 2A
= 11.3
V
(37)
1
VOUT
IOUT
1
fPmod
=
=
=
=
= 1.93kHz
15V
2p´
´ 22mF
2p´
´ COUT
2A
(38)
(39)
1
1
fZ mod
=
2p´ ESR ´ COUT 2p´ 5mW ´ 22mF
= 1.45MHz
VOUT
15V
æ
ç
ö2
÷
ö2
IOUT
VIN
6V
æ
2A
2p´ 3.3mH
fRHPZ
´
=
´
= 57.9kHz
ç
è
÷
ø
2p´ L VOUT ø
15V
è
(40)
(41)
(42)
fRHPZ
57.9kHz
fco1<
fco2 <
=
= 14.5kHz
= 150kHz
4
4
fSW
750kHz
=
5
5
The compensation components can now be calculated. A resistor in series with a capacitor creates a
compensating zero. A capacitor in parallel to these two components can be added to form a compensating pole.
To determine the compensation resistor (R7) use Equation 43. R7 is calculated to be 7.44 kΩ and a standard 1%
value of 7.50 kΩ is selected. Use Equation 44 to set the compensation zero to 1/10 the target crossover
frequency. C9 is calculated at 0.0147 µF and a standard value of 0.015 µF is used.
2p´ COUT ´ RSENSE ´ VOUT ´ fco ´(RSH + RSL
)
40
3
R7 = RCOMP
=
´
3
RSL ´ VIN min´ Gea ´
40
40 2p´ 21mF´ 20mW´15V ´19.3kHz ´(124kW +11kW)
=
´
= 7.44kW
mA
3
3
11kW ´ 6V ´1100
´
V
40
(43)
(44)
1
1
C9 = CCOMP
=
=
= 0.0147mF
fco
14.5kHz
2p´
´ RCOMP 2p´
´ 7.50kW
10
10
A compensation pole can be implemented if desired with capacitor C8 in parallel with the series combination of
R7 and C9. Use the larger value calculated from Equation 45 and Equation 46. The selected value of C8 is 150
pF for this example.
COUT ´ ESR
22mF ´5mW
CHF
=
=
= 14.7pF
RCOMP
7.50kW
(45)
(46)
1
1
CHF
=
=
20p´ fco ´ RCOMP 20p´14.5kHz ´7.50kW
= 150pF
22
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DISCONTINUOUS CONDUCTION MODE, PULSE-SKIP MODE AND NO LOAD INPUT CURRENT
The reverse current sensing of the TPS43060/61 allows the power supply to operate discontinuous conduction
mode (DCM) at light loads for higher efficiency. The supply enters DCM when the inductor current ramps to zero
at the end of a PWM cycle and the reverse current sense turns off the high-side FET for the remainder of the
cycle. In DCM the duty cycle is a function of the load, input and output voltages, inductance and switching
frequency as computed in Equation 47. The load current at which the inductor current falls to zero and the
converter enters DCM can be calculated using Equation 48. Additionally after the converter enters DCM,
decreasing the load further reduce the duty cycle. If the DCM on-time reaches the minimum on-time of the
TPS43060 and TPS43061, the converter begins pulse skipping to maintain output voltage regulation. Pulse
skipping can increase the output voltage ripple.
In this example with the 9 V nominal input voltage, the estimated load current where the converter enters DCM
operation is 0.44 A. The measured boundary is 0.36 A. In most designs the converter enters DCM at lower load
currents because Equation 48 does not account for the efficiency losses.. The design example power supply
enters pulse-skip mode when the output current is lower than 12 mA and the input current draw is 1.3 mA with
no load.
2´ V
(
-VIN ´ L ´ I
´ fSW
OUT
)
VIN
OUT
D =
(47)
(48)
2
V
(
-VIN ´V
)
15V - 9V ´ 9V 2
(
)
OUT
IN
IOUT crit =
=
= 0.44A
2´VOUT 2 ´ fSW ´ L 2´15V 2 ´ 750kHz ´ 3.3mH
LAYOUT
Layout is a critical portion of a good power converter design. There are several signal paths conducting fast
changing currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise
or degrade performance. Guidelines are as follows and the EVM layouts can be used as reference.
•
The high speed switching current path includes the high-side FET, low-side FET and output capacitors. This
is a critical loop to minimize to reduce noise and achieve best performance.
•
Components connected to noise sensitive circuitry should be located as close to the TPS43060 and
TPS43061 as possible, and be connected the AGND pin. This includes components connected to FB, COMP,
SS, RT/CLK, and VCC pins.
•
•
The PowerPAD should be connected to the quiet analog ground for the AGND pin to limit internal noise. For
thermal performance, multiple vias directly under the device should be used to connect to any internal ground
planes.
Components in the power conversion path should be connected to the PGND. This includes the bulk input
capacitors, output capacitors, low-side FET and EN UVLO resistors.
•
•
A single connection must connect the quiet AGND to the noisy PGND near the PGND pin.
The low ESR ceramic bypass capacitor for the VIN pin should be connected to the quiet AGND as close as
possible to the TPS43060 and TPS43061.
•
•
•
The distance between the inductor, low-side FET and high-side FET should be minimized to reduce noise.
This connection is the high speed switching voltage node.
The high-side and low-side FETs should be placed close to the device to limit the trace length required for the
HDRV and LDRV gate drive signals.
The bypass capacitor between the ISNS+ and ISNS- pins should be placed next to the TPS43060 and
TPS43061. Minimize the distance between the device and the sense resistors.
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THERMAL CONSIDERATIONS
The TPS43060 and TPS43061 junction temperature should not exceed 150°C under normal operating
conditions. This restriction limits the power dissipation of the device. Power dissipation of the controller includes
gate drive power loss and bias power loss of the internal VCC regulator. The TPS43060 and TPS43061 are
packaged in a thermally enhanced QFN package which includes a PowerPAD™ that improves the thermal
capabilities. The thermal resistance of the QFN package depends on the PCB layout and the PowerPAD
connection. As mentioned in the layout considerations, the PowerPAD must be soldered to the analog ground on
the PCB with thermal vias underneath the PowerPAD to achieve good thermal performance.
For best thermal performance pcb copper area should be sized to improve thermal capabilities of the
components in the power path dissipating the most power. This includes the sense resistors, inductor, low-side
FET and high-side FET. Manufacturer guidelines for the selected external FETs should be followed.
CHARACTERISTICS OF THE TPS43061 BOOST CONVERTER EXAMPLE
Vout (ac coupled)
200mV/div
VIN
5V/div
VCC
5V/div
VCC
5V/div
VOUT
Iout
5V/div
1A/div
PGOOD
5V/div
Time - 200 ms/div
Time – 5ms/div
Figure 22. Load Transient
Figure 23. Start-up with VIN
VOUT(ac coupled)
100mV/div
EN
5V/div
IL
1A/div
VCC
5V/div
Vout
SW
5V/div
10V/div
PGood
5V/div
Time - 5 ms/div
Time – 1µs/div
Figure 24. Start-up with EN
Figure 25. Output Ripple in CCM
VOUT(ac coupled)
100mV/div
VOUT(ac coupled)
100mV/div
IL
IL
1A/div
1A/div
SW
SW
10V/div
10V/div
Time – 1µs/div
Time – 500µs/div
Figure 26. Output Ripple in DCM
Figure 27. Output Ripple in Pulse-Skipping Mode
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SLVSBP4A –DECEMBER 2012–REVISED DECEMBER 2012
CHARACTERISTICS OF THE TPS43061 BOOST CONVERTER EXAMPLE (continued)
VIN(ac coupled)
VOUT(ac coupled)
50mV/div
100mV/div
IL
IL
1A/div
1A/div
SW
SW
10V/div
10V/div
Time – 1µs/div
Time – 1µs/div
Figure 28. Input Ripple in CCM
Figure 29. Input Ripple in DCM
60
50
180
120
60
100
95
90
85
80
75
70
65
60
55
50
Gain
Phase
40
30
20
10
0
0
−10
−20
−30
−40
−50
−60
−60
−120
−180
V
= 6 V
IN
V
= 9 V
IN
V
= 12 V
IN
100
1k
10k
100k
1M
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
Frequency (Hz)
G030
C030
Output Current (A)
Figure 30. Efficiency vs Output Current
Figure 31. Loop Gain and Phase
0.05
0.04
0.03
0.02
0.01
0
0.1
0.08
0.06
0.04
0.02
0
-0.01
-0.02
-0.03
-0.04
-0.05
-0.02
-0.04
-0.06
-0.08
-0.1
0
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
2
6
6.5
7
7.5
8
8.5
9
9.5 10 10.5 11 11.5 12
C031
C033
Output Current (A)
Input Voltage (V)
Figure 32. Load Regulation
Figure 33. Line Regulation
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HIGH EFFICIENCY 40V SYNCHRONOUS BOOST CONVERTER USING TPS43060
Figure 34. High Voltage Synchronous Boost Converter using TPS43060
100
95
90
VOUT = 40 V
fsw = 300 kHz
85
80
10 VIN
75
70
24 VIN
38 VIN
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
C001
Output Current (A)
Figure 35. The Efficiency of High Voltage Boost Converter Using TPS43060
The design procedure of TPS43061 is also applicable to the TPS43060; however, several difference should be
noted. Unlike the TPS43061, which has 5.5 V gate drive supply and is optimized for low Qg NexFETs™, the
TPS43060 has a 7.5 V gate drive supply and is suitable to drive standard threshold MOSFETs. The TPS43060
requires an external bootstrap diode (D1 as shown in Figure 34) from VCC to BOOT to charge the bootstrap
capacitor, and the external diode should have a breakdown voltage rating greater than the output voltage. In
addition, the TPS43060 also requires a 2Ω resistor (R19 shown in Figure 34) connected in series with the VCC
pin to limit the peak current drawn through the internal circuitry when the external bootstrap diode is conducting.
26
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SLVSBP4A –DECEMBER 2012–REVISED DECEMBER 2012
REVISION HISTORY
Changes from Original (December 2012) to Revision A
Page
•
Changed the devices From: Preview To: Production ........................................................................................................... 1
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2012
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package Qty
Eco Plan Lead/Ball Finish
MSL Peak Temp
Samples
Drawing
(1)
(2)
(3)
(Requires Login)
TPS43060RTER
PREVIEW
PREVIEW
ACTIVE
WQFN
WQFN
WQFN
WQFN
RTE
RTE
RTE
RTE
16
16
16
16
3000
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
TPS43060RTET
Green (RoHS
& no Sb/Br)
TPS43061RTER
3000
250
Green (RoHS
& no Sb/Br)
TPS43061RTET
ACTIVE
Green (RoHS
& no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
IMPORTANT NOTICE
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Copyright © 2012, Texas Instruments Incorporated
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