TPS50601A-SP [TI]

Radiation Hardened 3-V to 6.3-V Input, 6-A Synchronous Buck Converter;
TPS50601A-SP
型号: TPS50601A-SP
厂家: TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述:

Radiation Hardened 3-V to 6.3-V Input, 6-A Synchronous Buck Converter

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TPS50301-HT  
TPS50601-SP  
www.ti.com  
SLVSA94D DECEMBER 2012REVISED JANUARY 2013  
1.6-V TO 6.3-V INPUT, 3-A/6-A SYNCHRONOUS STEP DOWN SWIFT™ CONVERTER  
Check for Samples: TPS50301-HT, TPS50601-SP  
1
FEATURES  
2
Peak Efficiency: 95% (VO = 3.3 V)  
Integrated 55-m/50-mMOSFETs  
Split Power Rail: 1.6 V to 6.3 V on PVIN  
Power Rail: 3 V to 6.3 V on VIN  
TPS50301-HT: 3 A  
Power Good Output Monitor for Undervoltage  
and Overvoltage  
Adjustable Input Undervoltage Lockout  
For SWIFT™ Documentation, Visit  
http://www.ti.com/swift  
TPS50601-SP: 6 A  
APPLICATIONS  
TPS50601-SP:  
Point of Load Regulation  
SEL Latchup Immune to LET = 85 MeV-cm2/mg  
TPS50601-SP: Rad Tolerant Applications  
TPS50301-HT: Down-Hole Drilling  
Supports Harsh Environment Applications  
TPS50601-SP:  
Total Dose (TID) tolerance = 100kRad (Si)  
Flexible Switching Frequency Options:  
TPS50301-HT Available in Extreme  
(–55°C to 210°C) Temperature Range  
TPS50601-SP Available in Military  
100-kHz to 1-MHz Adjustable Internal  
Oscillator  
External Sync Capability from 100 kHz  
to 1 MHz  
(1)  
(–55°C to 125°C) Temperature Range  
TPS50301-HT: Texas Instruments' high  
temperature products utilize highly optimized  
silicon (die) solutions with design and process  
enhancements to maximize performance over  
extended temperatures.  
Sync Pin Can Be Configured as a 500-kHz  
Output for Master/Slave Applications  
0.795-V ±1.258% Voltage Reference at 25°C  
Monotonic Start-Up into Pre-Biased Outputs  
Adjustable Slow Start and Power Sequencing  
(1) Custom temperature ranges available  
DESCRIPTION  
The TPS50301 is a 6.3-V, 3-A and the TPS50601 is a 6.3-V, 6-A synchronous step down converter which is  
optimized for small designs through high efficiency and integrating the high-side and low-side MOSFETs. Further  
space savings are achieved through current mode control, which reduces component count, and a high switching  
frequency, reducing the inductor's footprint. The devices are offered in a thermally enhanced 20-pin ceramic,  
dual in-line flatpack package.  
Efficiency vs. Load Current Vin=5V  
Current Sharing vs. Load Current  
1.00  
0.95  
0.90  
0.85  
0.80  
0.75  
0.70  
0.65  
0.60  
0.55  
0.50  
0.45  
0.40  
0.35  
0.30  
0.25  
0.20  
0.15  
0.10  
0.05  
0.00  
60.00  
58.00  
56.00  
54.00  
52.00  
50.00  
48.00  
46.00  
44.00  
42.00  
40.00  
Vo = 3.3V  
Vo = 1.2V  
POL # 2  
POL # 1  
0.00  
1.00  
2.00  
3.00  
4.00  
5.00  
6.00  
0.00  
2.00  
4.00  
6.00  
8.00  
10.00  
12.00  
IL- Load Current -A  
IL-Current Load_A  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
SWIFT is a trademark of Texas Instruments.  
2
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2012–2013, Texas Instruments Incorporated  
TPS50301-HT  
TPS50601-SP  
SLVSA94D DECEMBER 2012REVISED JANUARY 2013  
www.ti.com  
DESCRIPTION (CONTINUED)  
The output voltage startup ramp is controlled by the SS/TR pin which allows operation as either a stand alone  
power supply or in tracking situations. Power sequencing is also possible by correctly configuring the enable and  
the open drain power good pins.  
Cycle by cycle current limiting on the high-side FET protects the device in overload situations and is enhanced  
by a low-side sourcing current limit which prevents current runaway. There is also a low-side sinking current limit  
which turns off the low-side MOSFET to prevent excessive reverse current. Thermal shutdown disables the part  
when die temperature exceeds thermal shutdown temperature.  
SIMPLIFIED SCHEMATIC  
PVIN  
VIN  
VIN  
Cboot  
TPS50x01  
BOOT  
Cin  
VOUT  
Lo  
EN  
PH  
Co  
PWRGD  
SYNC  
R1  
VSENSE  
SS/TR  
RT  
R2  
GND  
COMP  
RRT  
R3  
C1  
Thermal  
Pad  
Css  
C2  
2
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Copyright © 2012–2013, Texas Instruments Incorporated  
Product Folder Links: TPS50301-HT TPS50601-SP  
TPS50301-HT  
TPS50601-SP  
www.ti.com  
SLVSA94D DECEMBER 2012REVISED JANUARY 2013  
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with  
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.  
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more  
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.  
Table 1. ORDERING INFORMATION(1)  
ORDERABLE PART  
TJ  
PACKAGE(2)  
TOP-SIDE MARKING  
NUMBER  
–55°C to 210°C  
–55°C to 125°C  
25°C  
TPS50301SHKH  
TPS50301SHKH  
TPS50601MHKHV  
20-pin ceramic flatpack (HKH)  
TPS50601MHKHV  
TPS50601HKHMPR(3)  
TPS50601HKH/EM (EVAL ONLY)  
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI  
web site at www.ti.com.  
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.  
(3) These units are intended for engineering evaluation only. They are processed to a non-compliant flow (e.g. no burn-in, etc.) and are  
tested to temperature rating of 25°C only. These units are not suitable for qualification, production, radiation testing or flight use. Parts  
are not warranted for performance on full MIL specified temperature range of -55°C to 125°C or operating life.  
ABSOLUTE MAXIMUM RATINGS(1)  
over operating temperature range (unless otherwise noted)  
VALUE  
-0.3 to 7  
-0.3 to 7  
-0.3 to 5.5  
-0.3 to 14  
-0.3 to 3.3  
-0.3 to 3.3  
-0.3 to 5.5  
-0.3 to 5.5  
-0.3 to 7  
0 to 7  
UNIT  
V
VIN  
PVIN  
V
EN  
V
BOOT  
V
Input Voltage  
VSENSE  
COMP  
V
V
PWRGD  
SS/TR  
V
V
SYNC  
V
BOOT-PH  
PH  
V
Output Voltage  
Output current  
-1 to 7  
V
PH 10ns Transient  
TPS50301  
TPS50601  
-3 to 7  
V
3
A
6
A
Vdiff  
-0.2 to 0.2  
V
(GND to exposed thermal pad)  
PH  
Current Limit  
±100  
A
µA  
A
Source Current  
Sink Current  
RT  
PH  
Current Limit  
Current Limit  
±200  
PVIN  
COMP  
PWRGD  
A
µA  
mA  
kV  
kV  
–0.1 to 5  
1
Electrostatic Discharge (HBM) QSS 009-105 (JESD22-A114A)  
Electrostatic Discharge (CDM) QSS 009-147 (JESD22-C101B.01)  
1
TPS50301  
Operating Junction Temperature  
TPS50601  
–55 to 220  
-55 to 150  
–65 to 220  
-65 to 150  
°C  
°C  
TPS50301  
Storage Temperature  
TPS50601  
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings  
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating  
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.  
Copyright © 2012–2013, Texas Instruments Incorporated  
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Product Folder Links: TPS50301-HT TPS50601-SP  
TPS50301-HT  
TPS50601-SP  
SLVSA94D DECEMBER 2012REVISED JANUARY 2013  
www.ti.com  
PACKAGE DISSIPATION RATINGS(1)(2)(3)(4)(5)  
θJA THERMAL IMPEDANCE  
JUNCTION TO AMBIENT  
θJC THERMAL IMPEDANCE  
JUNCTION TO CASE (THERMAL PAD)  
θJB THERMAL IMPEDANCE  
JUNCTION TO BOARD  
PACKAGE  
HKH  
39.9°C/W  
0.52°C/W  
43.1°C/W  
(1) Maximum power dissipation may be limited by overcurrent protection  
(2) Power rating at a specific ambient temperature TA should be determined with a junction temperature of 150°C. This is the point where  
distortion starts to substantially increase. Thermal management of the PCB should strive to keep the junction temperature at or below  
150°C for best performance and long-term reliability. See power dissipation estimate in application section of this data sheet for more  
information.  
(3) Test board conditions:  
(a) 2.5 inches × 2.5 inches, 4 layers, thickness: 0.062 inch  
(b) 2 oz. copper traces located on the top of the PCB  
(c) 2 oz. copper ground planes on the 2 internal layers and bottom layer  
(d) 4 0.010 inch thermal vias located under the device package  
(4) For information on thermal characteristics see SPRA953A  
(5) For TPS50301-HT, use polyimide PCB and thermal management to ensure operation below maximum TJ operation.  
TPS50301 ELECTRICAL CHARACTERISTICS  
TJ = –55°C to 210°C, VIN = 3 V to 6.3 V, PVIN = 1.6 V to 6.3 V (unless otherwise noted)  
DESCRIPTION  
SUPPLY VOLTAGE (VIN AND PVIN PINS)  
PVIN operating input voltage  
VIN operating input voltage  
VIN internal UVLO threshold  
VIN internal UVLO hysteresis  
VIN shutdown supply current  
VIN operating – non switching supply current  
ENABLE AND UVLO (EN PIN)  
Enable threshold  
CONDITIONS  
MIN  
TYP  
MAX UNIT  
1.6  
3
6.3  
6.3  
3
V
V
VIN rising  
EN = 0 V  
2.75  
50  
V
mV  
mA  
mA  
2.5  
5
8
VSENSE = VBG  
10  
Rising  
1.13  
1.03  
3.2  
3
1.19  
V
V
Enable threshold  
Falling  
0.97  
Input current  
EN = 1.1 V  
EN = 1.3 V  
μA  
μA  
Hysteresis current  
VOLTAGE REFERENCE  
-55°C  
25°C  
0.767  
0.785  
0.785  
0.795  
0.795  
0.795  
0.805  
0.805  
0.830  
Voltage reference  
0 A Iout 3 A  
V
210°C  
MOSFET  
High-side switch resistance  
High-side switch resistance(1) (2)  
Low-side switch resistance(1) (2)  
ERROR AMPLIFIER  
BOOT-PH = 2.2 V  
BOOT-PH = 6.3 V  
VIN = 3 V  
55  
50  
50  
mΩ  
mΩ  
mΩ  
Error amplifier transconductance (gm)(2)  
Error amplifier dc gain(2)  
Error amplifier source/sink(2)  
Start switching threshold(2)  
COMP to Iswitch gm(2)  
–2 μA < ICOMP < 2 μA, V(COMP) = 1 V  
VSENSE = 0.8 V  
1300  
39000  
±125  
0.25  
μMhos  
V/V  
μA  
V(COMP) = 1 V, 40 mV input overdrive  
V
18  
A/V  
CURRENT LIMIT  
High-side switch current limit threshold  
Low-side switch sourcing current limit  
Low-side switch sinking current limit  
VIN = 6.3 V  
VIN = 6.3 V  
VIN = 6.3 V  
7.8  
6
11  
10  
3
A
A
A
(1) Measured at pins  
(2) Ensured by design only. Not tested in production.  
4
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Copyright © 2012–2013, Texas Instruments Incorporated  
Product Folder Links: TPS50301-HT TPS50601-SP  
 
TPS50301-HT  
TPS50601-SP  
www.ti.com  
SLVSA94D DECEMBER 2012REVISED JANUARY 2013  
TPS50301 ELECTRICAL CHARACTERISTICS (continued)  
TJ = –55°C to 210°C, VIN = 3 V to 6.3 V, PVIN = 1.6 V to 6.3 V (unless otherwise noted)  
DESCRIPTION  
INTERNAL SWITCHING FREQUENCY  
Internally set frequency  
CONDITIONS  
MIN  
TYP  
MAX UNIT  
RT = Open  
395  
500  
480  
585  
kHz  
kHz  
RT = 100 kΩ (1%)  
RT = 485 kΩ (1%)  
RT = 47 kΩ (1%)  
Externally set frequency  
100  
1000  
EXTERNAL SYNCHRONIZATION  
SYNC out low-to-high rise time (10%/90%)  
SYNC out high-to-low fall time (90%/10%)  
Falling edge delay time(3)  
Cload = 25 pF  
Cload = 25 pF  
25  
3
126  
15  
ns  
ns  
°
180  
SYNC out high level threshold  
SYNC out low level threshold  
IOH = 50 µA  
IOL = 50 µA  
2
V
600  
mV  
mV  
V
SYNC in low level threshold  
800  
SYNC in high level threshold  
1.85  
5
% of program frequency  
-5  
%
SYNC in frequency range  
100  
1000  
kHz  
PH (PH PIN)  
Measured at 90% to 90% of VIN,  
25°C, IPH = 2A  
Minimum on time  
94  
236  
ns  
ns  
Minimum off time  
BOOT-PH 2.2 V  
500  
BOOT (BOOT PIN)  
BOOT-PH UVLO  
2.2  
3
V
SLOW START AND TRACKING (SS/TR PIN)  
SS charge current  
2.5  
30  
μA  
SS/TR to VSENSE matching  
POWER GOOD (PWRGD PIN)  
V(SS/TR) = 0.4 V  
90  
mV  
VSENSE falling (Fault)  
VSENSE rising (Good)  
VSENSE rising (Fault)  
91  
94  
% Vref  
% Vref  
% Vref  
% Vref  
µA  
VSENSE threshold  
109  
106  
0.03  
VSENSE falling (Good)  
VSENSE = Vref, V(PWRGD) = 5 V  
I(PWRGD) = 2 mA  
Output high leakage  
2.9  
0.3  
1
Output low  
V
Minimum VIN for valid output  
Minimum SS/TR voltage for PWRGD  
V(PWRGD) < 0.5V at 100 μA  
0.6  
V
1.4  
V
(3) Bench verified. Not tested in production.  
Copyright © 2012–2013, Texas Instruments Incorporated  
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Product Folder Links: TPS50301-HT TPS50601-SP  
TPS50301-HT  
TPS50601-SP  
SLVSA94D DECEMBER 2012REVISED JANUARY 2013  
www.ti.com  
TPS50601 ELECTRICAL CHARACTERISTICS  
TJ = –55°C to 125°C, VIN = 3 V to 6.3 V, PVIN = 1.6 V to 6.3 V (unless otherwise noted)  
DESCRIPTION  
SUPPLY VOLTAGE (VIN AND PVIN PINS)  
PVIN operating input voltage  
VIN operating input voltage  
VIN internal UVLO threshold  
VIN internal UVLO hysteresis  
VIN shutdown supply current  
VIN operating – non switching supply current  
ENABLE AND UVLO (EN PIN)  
Enable threshold  
CONDITIONS  
MIN  
TYP  
MAX UNIT  
1.6  
3
6.3  
6.3  
3
V
V
VIN rising  
2.75  
50  
V
mV  
mA  
mA  
EN = 0 V  
2.5  
5
5.9  
10  
VSENSE = VBG  
Rising  
1.13  
1.09  
3.2  
3
1.18  
V
Enable threshold  
Falling  
1.05  
Input current  
EN = 1.1 V  
EN = 1.3 V  
μA  
μA  
Hysteresis current  
VOLTAGE REFERENCE  
-55°C  
0.767  
0.785  
0.785  
0.795  
0.795  
0.795  
0.804  
0.804  
0.815  
Voltage reference  
0 A Iout 6 A  
25°C  
V
125°C  
MOSFET  
High-side switch resistance  
High-side switch resistance(1)  
Low-side switch resistance(1)  
ERROR AMPLIFIER  
BOOT-PH = 2.2 V  
BOOT-PH = 6.3 V  
VIN = 6.3 V  
55  
50  
50  
mΩ  
mΩ  
mΩ  
Error amplifier transconductance (gm)(2)  
Error amplifier dc gain(2)  
Error amplifier source/sink(2)  
Start switching threshold(2)  
COMP to Iswitch gm(2)  
–2 μA < ICOMP < 2 μA, V(COMP) = 1 V  
VSENSE = 0.792 V  
1300  
39000  
±125  
0.25  
μMhos  
V/V  
μA  
V(COMP) = 1 V, 40 mV input overdrive  
V
18  
A/V  
CURRENT LIMIT  
High-side switch current limit threshold  
Low-side switch sourcing current limit  
Low-side switch sinking current limit  
VIN = 6.3 V  
VIN = 6.3 V  
VIN = 6.3 V  
8
7
11  
10  
3
A
A
A
(1) Measured at pins  
(2) Ensured by design only. Not tested in production.  
6
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Copyright © 2012–2013, Texas Instruments Incorporated  
Product Folder Links: TPS50301-HT TPS50601-SP  
 
TPS50301-HT  
TPS50601-SP  
www.ti.com  
SLVSA94D DECEMBER 2012REVISED JANUARY 2013  
TPS50601 ELECTRICAL CHARACTERISTICS (continued)  
TJ = –55°C to 125°C, VIN = 3 V to 6.3 V, PVIN = 1.6 V to 6.3 V (unless otherwise noted)  
DESCRIPTION  
THERMAL SHUTDOWN  
CONDITIONS  
MIN  
TYP  
MAX UNIT  
Thermal shutdown  
175  
10  
°C  
°C  
Thermal shutdown hysteresis  
INTERNAL SWITCHING FREQUENCY  
Internally set frequency  
RT = Open  
395  
500  
480  
585  
kHz  
kHz  
RT = 100 kΩ (1%)  
RT = 485 kΩ (1%)  
RT = 47 kΩ (1%)  
Externally set frequency  
100  
1000  
EXTERNAL SYNCHRONIZATION  
SYNC out low-to-high rise time (10%/90%)  
SYNC out high-to-low fall time (90%/10%)  
Falling edge delay time(3)  
Cload = 25 pF  
Cload = 25 pF  
25  
3
111  
15  
ns  
ns  
°
180  
SYNC out high level threshold  
SYNC out low level threshold  
IOH = 50 µA  
IOL = 50 µA  
2
V
600  
mV  
mV  
V
SYNC in low level threshold  
800  
SYNC in high level threshold  
1.85  
5
% of program frequency  
-5  
%
SYNC in frequency range  
100  
1000  
kHz  
PH (PH PIN)  
Measured at 90% to 90% of VIN,  
25°C, IPH = 2A  
94  
Minimum on time  
175  
ns  
ns  
Minimum off time  
BOOT-PH 3 V  
500  
BOOT (BOOT PIN)  
BOOT-PH UVLO  
2.2  
3
V
SLOW START AND TRACKING (SS/TR PIN)  
SS charge current  
2.5  
30  
μA  
SS/TR to VSENSE matching  
POWER GOOD (PWRGD PIN)  
V(SS/TR) = 0.4 V  
90  
mV  
VSENSE falling (Fault)  
VSENSE rising (Good)  
VSENSE rising (Fault)  
91  
94  
% Vref  
% Vref  
% Vref  
% Vref  
nA  
VSENSE threshold  
109  
106  
30  
VSENSE falling (Good)  
VSENSE = Vref, V(PWRGD) = 5 V  
I(PWRGD) = 2 mA  
Output high leakage  
181  
0.3  
1
Output low  
V
Minimum VIN for valid output  
Minimum SS/TR voltage for PWRGD  
V(PWRGD) < 0.5V at 100 μA  
0.6  
V
1.4  
V
(3) Bench verified. Not tested in production.  
Copyright © 2012–2013, Texas Instruments Incorporated  
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Product Folder Links: TPS50301-HT TPS50601-SP  
TPS50301-HT  
TPS50601-SP  
SLVSA94D DECEMBER 2012REVISED JANUARY 2013  
www.ti.com  
1000000  
100000  
10000  
1000  
Duty Cycle  
100  
80  
60  
40  
20  
110  
130  
150  
170  
190  
210  
Operating Junction Temperature ( °C)  
A. See datasheet for absolute maximum and minimum recommended operating conditions.  
B. Silicon operating life design goal is 10 years at 125°C junction temperature (does not include package interconnect  
life).  
C. The predicted operating lifetime vs. junction temperature is based on reliability modeling using electromigration as the  
dominant failure mechanism affecting device wearout for the specific device process and design characteristics.  
D. This device is rated for 1000 hours of continuous operation at maximum rated temperature at 210°C.  
Figure 1. TPS50301-HT 3-A Continuous Current Estimated Device Life  
10000000  
1000000  
Duty Cycle  
100  
80  
60  
40  
20  
100000  
10000  
1000  
95  
105  
115  
125  
135  
145  
Operating Junction Temperature ( °C)  
A. See datasheet for absolute maximum and minimum recommended operating conditions.  
B. Product operating life design goal is > 15 years for 65°C TJ 95°C based on silicon technology characterization per  
MIL-PRF-38535.  
C. The predicted operating lifetime vs. junction temperature is based on reliability modeling using electromigration as the  
dominant failure mechanism affecting device wearout for the specific device process and design characteristics.  
Figure 2. TPS50601-SP 6-A Continuous Current Estimated Device Life  
8
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Product Folder Links: TPS50301-HT TPS50601-SP  
TPS50301-HT  
TPS50601-SP  
www.ti.com  
SLVSA94D DECEMBER 2012REVISED JANUARY 2013  
DEVICE INFORMATION  
PIN ASSIGNMENTS  
1
2
3
4
5
GND  
20  
PWRGD  
EN  
RT  
19  
18  
17  
SS/TR  
COMP  
VSENSE  
SYNC  
Thermal Pad  
(Bottom Side)  
21  
VIN  
PVIN  
PVIN  
16  
15  
14  
13  
12  
11  
BOOT  
PH  
6
7
PH  
PH  
8
PGND  
PGND  
PGND  
9
PH  
PH  
10  
Table 2. PIN FUNCTIONS  
PIN  
DESCRIPTION  
NAME  
GND  
EN  
No.  
1
Return for control circuitry/Thermal pad(1)  
2
Enable pin. Float to enable. Adjust the input undervoltage lockout with two resistors.  
In internal oscillation mode, a resistor is connected between the RT pin and GND to set the switching  
frequency.  
RT  
3
4
Optoinal 1-MHz external system clock input. The device operates with an internal oscillator if this pin is left  
open.  
SYNC  
VIN  
5
Supplies the power to the output FET controllers.  
Power input. Supplies the power switches of the power converter.  
Return for low side Power MOSFET  
PVIN  
PGND  
6, 7  
8, 9, 10  
11, 12, 13,  
14, 15  
PH  
The switch node  
A bootstrap cap is required between BOOT and PH. The voltage on this cap carries the gate drive voltage for  
the high-side MOSFET.  
BOOT  
16  
17  
18  
VSENSE  
COMP  
Inverting input of the gm error amplifier  
Error amplifier output, and input to the output switch current comparator. Connect frequency compensation to  
this pin.  
Slow-start and tracking. An external capacitor connected to this pin sets the internal voltage reference rise  
time. The voltage on this pin overrides the internal reference. It can be used for tracking and sequencing.  
SS/TR  
19  
20  
Power Good fault pin. Asserts low if output voltage is low due to thermal shutdown, dropout, over-voltage, EN  
shutdown or during slow start.  
PWRGD  
(1) Thermal pad (analog ground) must be connected to PGND external to the package.  
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FUNCTIONAL BLOCK DIAGRAM  
VIN  
PVIN PVIN  
PWRGD  
EN  
Thermal  
Shutdown  
UVLO  
Shutdown  
Enable  
Comparator  
Ip  
Ih  
Shutdown  
Shutdown  
Logic  
UV  
OV  
Logic  
Enable  
Threshold  
Boot  
Charge  
Current  
Sense  
Minimum Clamp  
Pulse Skip  
ERROR  
AMPLIFIER  
VSENSE  
SS/TR  
BOOT  
Boot  
UVLO  
V/I  
HS MOSFET  
Current  
Comparator  
Voltage  
Reference  
Power Stage  
& Deadtime  
Control  
PH  
PH  
Logic  
Slope  
Compensation  
VIN  
Regulator  
Overload Recovery  
and  
RT Bias  
Oscillator  
LS MOSFET  
Current Limit  
Clamp  
Current  
Sense  
PGND  
PGND  
SYNC  
Detect  
COMP  
Thermal Pad/GND  
RT  
SYNC  
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TYPICAL CHARACTERISTICS  
OVERVIEW  
The device is a 6.3-V, 3-A or 6-A, synchronous step-down (buck) converter with two integrated n-channel  
MOSFETs. To improve performance during line and load transients the device implements a constant frequency,  
peak current mode control which also simplifies external frequency compensation. The wide switching frequency,  
100 kHz to 1 MHz, allows for efficiency and size optimization when selecting the output filter components.  
The device has been designed for safe monotonic startup into pre-biased loads. The default start up is when VIN  
is typically 3 V. The EN pin has an internal pull-up current source that can be used to adjust the input voltage  
under voltage lockout (UVLO) with two external resistors. In addition, the EN pin can be floating for the device to  
operate with the internal pull-up current. The total operating current for the device is approximately 5 mA when  
not switching and under no load. When the device is disabled, the supply current is typically less than 2.5 mA.  
The integrated MOSFETs allow for high efficiency power supply designs with continuous output currents up to 6  
amperes. The MOSFETs have been sized to optimize efficiency for lower duty cycle applications.  
The device reduces the external component count by integrating the boot recharge circuit. The bias voltage for  
the integrated high-side MOSFET is supplied by a capacitor between the BOOT and PH pins. The boot capacitor  
voltage is monitored by a BOOT to PH UVLO (BOOT-PH UVLO) circuit allowing PH pin to be pulled low to  
recharge the boot capacitor. The device can operate over duty cycle range per Equation 2 and Equation 3 as  
long as the boot capacitor voltage is higher than the preset BOOT-PH UVLO threshold which is typically 2.2 V.  
The output voltage can be stepped down to as low as the 0.795 V voltage reference (Vref).  
The device has a power good comparator (PWRGD) with hysteresis which monitors the output voltage through  
the VSENSE pin. The PWRGD pin is an open drain MOSFET which is pulled low when the VSENSE pin voltage  
is less than 91% or greater than 109% of the reference voltage Vref and asserts high when the VSENSE pin  
voltage is 94% to 106% of the Vref.  
The SS/TR (slow start/tracking) pin is used to minimize inrush currents or provide power supply sequencing  
during power up. A small value capacitor or resistor divider should be coupled to the pin for slow start or critical  
power supply sequencing requirements.  
The device is protected from output overvoltage, overload and thermal fault conditions. The device minimizes  
excessive output overvoltage transients by taking advantage of the overvoltage circuit power good comparator.  
When the overvoltage comparator is activated, the high-side MOSFET is turned off and prevented from turning  
on until the VSENSE pin voltage is lower than 106% of the Vref. The device implements both high-side MOSFET  
overload protection and bidirectional low-side MOSFET overload protections which help control the inductor  
current and avoid current runaway. The device also shuts down if the junction temperature is higher than thermal  
shutdown trip point. The device is restarted under control of the slow start circuit automatically when the junction  
temperature drops 10°C typically below the thermal shutdown trip point.  
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TYPICAL CHARACTERISTICS (continued)  
VOLTAGE REFERENCE  
vs  
OSCILLATOR FREQUENCY  
vs  
TEMPERATURE  
TEMPERATURE  
0.83  
0.82  
0.81  
0.80  
0.79  
0.78  
0.77  
0.76  
1250  
1000  
750  
500  
250  
0
Nom  
Min  
Max  
VIN = 3 V  
VIN = 6.3 V  
œ75 œ50 œ25  
0
25 50 75 100 125 150 175 200 225  
œ75 œ50 œ25  
0
25 50 75 100 125 150 175 200 225  
C003  
C004  
Junction Temperature (°C)  
Junction Temperature (°C)  
Figure 3.  
Figure 4.  
SHUTDOWN QUIESCENT CURRENT  
EN PIN HYSTERESIS CURRENT  
vs  
vs  
TEMPERATURE  
TEMPERATURE  
6000  
5000  
4000  
3000  
2000  
1000  
0
5
4
3
2
1
0
VIN = 3 V  
VIN = 3 V  
VIN = 6.3 V  
VIN = 6.3 V  
œ75 œ50 œ25  
0
25 50 75 100 125 150 175 200 225  
œ75 œ50 œ25  
0
25 50 75 100 125 150 175 200 225  
C005  
Junction Temperature (°C)  
C006  
Junction Temperature (°C)  
Figure 5.  
Figure 6.  
EN PIN PULL-UP CURRENT  
EN PIN UVLO THRESHOLD  
vs  
vs  
TEMPERATURE  
TEMPERATURE  
œ5  
œ6  
1.170  
1.165  
1.160  
1.155  
1.150  
1.145  
1.140  
1.135  
1.130  
VIN = 3 V  
VIN = 3 V  
VIN = 6.3 V  
VIN = 6.3 V  
œ7  
œ8  
œ9  
œ10  
œ75 œ50 œ25  
0
25 50 75 100 125 150 175 200 225  
œ75 œ50 œ25  
0
25 50 75 100 125 150 175 200 225  
C007  
C008  
Junction Temperature (°C)  
Junction Temperature (°C)  
Figure 7.  
Figure 8.  
12  
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TYPICAL CHARACTERISTICS (continued)  
NON-SWITCHING OPERATING QUIESCENT CURRENT (VIN)  
SLOW START CHARGE CURRENT  
vs  
vs  
TEMPERATURE  
TEMPERATURE  
8000  
7500  
7000  
6500  
6000  
5500  
5000  
4500  
4000  
3500  
3000  
3.2  
3.0  
2.8  
2.6  
2.4  
2.2  
VIN = 3 V  
VIN = 6.3 V  
VIN = 6.3 V  
œ75 œ50 œ25  
0
25 50 75 100 125 150 175 200 225  
œ75 œ50 œ25  
0
25 50 75 100 125 150 175 200 225  
C009  
C010  
Junction Temperature (°C)  
Junction Temperature (°C)  
Figure 9.  
Figure 10.  
(SS-VSENSE) OFFSET  
vs  
TEMPERATURE  
HIGH-SIDE CURRENT LIMIT THRESHOLD  
vs  
TEMPERATURE  
12  
0.05  
0.04  
0.03  
0.02  
0.01  
0.00  
VIN = 3 V  
11  
10  
9
VIN = 6.3 V  
8
7
VIN = 6.3 V  
6
-75 -50 -25  
0
25 50 75 100 125 150 175 200 225  
œ75 œ50 œ25  
0
25 50 75 100 125 150 175 200 225  
C012  
Junction Temperature (°C)  
C011  
Junction Temperature (°C)  
Figure 11.  
Figure 12.  
LOW-SIDE RDS(ON)  
vs  
HIGH-SIDE RDS(ON)  
vs  
TEMPERATURE  
TEMPERATURE  
170  
150  
130  
110  
90  
180  
VIN = 3 V  
VIN = 3 V  
160  
140  
120  
100  
80  
VIN = 6.3 V  
VIN = 6.3 V  
70  
50  
60  
30  
40  
10  
20  
œ75 œ50 œ25  
0
25 50 75 100 125 150 175 200 225  
œ75 œ50 œ25  
0
25 50 75 100 125 150 175 200 225  
C002  
C001  
Junction Temperature (°C)  
Junction Temperature (°C)  
Figure 13.  
Figure 14.  
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TYPICAL CHARACTERISTICS (continued)  
MINIMUM CONTROLLABLE ON TIME  
MINIMUM CONTROLLABLE DUTY RATIO  
vs  
vs  
TEMPERATURE  
TEMPERATURE  
250  
200  
150  
100  
50  
15  
10  
5
VIN = 3 V  
VIN = 3 V  
VIN = 6.3 V  
VIN = 6.3 V  
0
œ75 œ50 œ25  
0
25 50 75 100 125 150 175 200 225  
œ75 œ50 œ25  
0
25 50 75 100 125 150 175 200 225  
C013  
C014  
Junction Temperature (°C)  
Junction Temperature (°C)  
Figure 15.  
Figure 16.  
14  
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DETAILED DESCRIPTION  
Fixed Frequency PWM Control  
The device uses fixed frequency, peak current mode control. The output voltage is compared through external  
resistors on the VSENSE pin to an internal voltage reference by an error amplifier which drives the COMP pin.  
An internal oscillator initiates the turn on of the high-side power switch. The error amplifier output is converted  
into a current reference which compares to the high-side power switch current. When the power switch current  
reaches current reference generated by the COMP voltage level the high-side power switch is turned off and the  
low-side power switch is turned on.  
Continuous Current Mode Operation (CCM)  
As a synchronous buck converter, the device normally works in CCM (Continuous Conduction Mode) under all  
load conditions.  
VIN and Power VIN Pins (VIN and PVIN)  
The device allows for a variety of applications by using the VIN and PVIN pins together or separately. The VIN  
pin voltage supplies the internal control circuits of the device. The PVIN pin voltage provides the input voltage to  
the power converter system.  
If tied together, the input voltage for VIN and PVIN can range from 3 V to 6.3 V. If using the VIN separately from  
PVIN, the VIN pin must be between 3 V and 6.3 V, and the PVIN pin can range from as low as 1.6 V to 6.3 V. A  
voltage divider connected to the EN pin can adjust the input voltage UVLO appropriately. Adjusting the input  
voltage UVLO on the PVIN pin helps to provide consistent power up behavior.  
PVIN vs Frequency  
With VIN tied to PVIN minimum off-time determines what output voltage is achievable over frequency range.  
Voltage Reference  
The voltage reference system produces a precise voltage reference as indicated in TPS50301 ELECTRICAL  
CHARACTERISTICS and TPS50601 ELECTRICAL CHARACTERISTICS.  
Adjusting the Output Voltage  
The output voltage is set with a resistor divider from the output (VOUT) to the VSENSE pin. It is recommended to  
use 1% tolerance or better divider resistors. Start with a 10 kΩ for R15 (top resistor) and use Equation 1 to  
calculate R38 (bottom reisitor divider). To improve efficiency at light loads consider using larger value resistors. If  
the values are too high the regulator is more susceptible to noise and voltage errors from the VSENSE input  
current are noticeable.  
Vref  
R38 =  
R15  
Vo - Vref  
(1)  
Where Vref = 0.795 V  
The minimum output voltage and maximum output voltage can be limited by the minimum on time of the high-  
side MOSFET and bootstrap voltage (BOOT-PH voltage) respectively. More discussion is located in Bootstrap  
Voltage (BOOT) and Low Dropout Operation.  
Maximum Duty Cycle Limit  
The TPS50601 can operate at duty cycle per Equation 2 and Equation 3 as long as the boot capacitor voltage is  
higher than the preset BOOT-PH UVLO threshold which is typically 2.2 V.  
Duty cycle can be calculated based on Equation 2:  
VOUT + IOUT_max ·RTesr + IOUT_max ·Rds_low  
D(VIN) =  
VIN - IOUT_max ·Rds_high + IOUT_max ·Rds_low  
(2)  
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Where  
RTesr = Rdcr + Rtrace  
Rdcr is the DC resistance of the inductor.  
Rtrace is the DC trace resistance (miscellaneous drop).  
Rds_high is the maximum RDS of the high side MOSFET.  
Rds_low is the maximum RDS of the low side MOSFET.  
PVIN vs Frequency  
With VIN tied to PVIN minimum off-time will determine the output voltage that is achievable over frequency range.  
For VIN = PVIN must be greater than or equal to 3 V. For VIN = 3 V, PVIN can vary from 1.6 V to 6.3 V as  
highlighted in Electrical Characteristics.  
This is given by equation below.  
V
O
+ I  
O(Rds _ onLS + Rmisc)  
PVin _ min(fSW) =  
1- Toff _ min· fSW  
(3)  
Where  
Rds_onLS - low side Rds-on  
Rmisc - Miscellaneous trace drops  
Toff_min – minimum off time  
Using the above approach one can calculate minimum PVIN required for specific VOUT as indicated below as an  
example.  
PVin_min(100 kHz = 1.889 V)  
VO = 1.5 V  
PVin_min(1000 kHz = 3.396 V)  
f
- Switching Frequency - Hz  
sw  
Figure 17. PVIN vs Frequency  
Safe Start-up into Pre-Biased Outputs  
The device has been designed to prevent the low-side MOSFET from discharging a pre-biased output. During  
monotonic pre-biased startup, the low-side MOSFET is not allowed to sink current until the SS/TR pin voltage is  
higher than 1.4 V.  
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Error Amplifier  
The device uses a transconductance error amplifier. The error amplifier compares the VSENSE pin voltage to the  
lower of the SS/TR pin voltage or the internal 0.795 V voltage reference. The transconductance of the error  
amplifier is 1300 μA/V during normal operation. The frequency compensation network is connected between the  
COMP pin and ground. Error amplifier DC gain is typically 39000 V/V with minimum value of 22000 V/V per  
design.  
Slope Compensation  
The device adds a compensating ramp to the switch current signal. This slope compensation prevents sub-  
harmonic oscillations. The available peak inductor current remains constant over the full duty cycle range.  
Enable and Adjusting Under-Voltage Lockout  
The EN pin provides electrical on/off control of the device. Once the EN pin voltage exceeds the threshold  
voltage, the device starts operation. If the EN pin voltage is pulled below the threshold voltage, the regulator  
stops switching and enters low Iq state. If an external Schottky diode is used from VIN to Boot, then a bleeder  
may be required < 1 mA to ensure output is low when unit is disabled via Enable pin.  
The EN pin has an internal pull-up current source, allowing the user to float the EN pin for enabling the device. If  
an application requires controlling the EN pin, use open drain or open collector output logic to interface with the  
pin.  
The device implements internal UVLO circuitry on the VIN pin. The device is disabled when the VIN pin voltage  
falls below the internal VIN UVLO threshold. The internal VIN UVLO threshold has a hysteresis of 150 mV.  
If an application requires either a higher UVLO threshold on the VIN pin or a secondary UVLO on the PVIN, in  
split rail applications, then the EN pin can be configured as shown in Figure 18, Figure 19 and Figure 20. When  
using the external UVLO function it is recommended to set the hysteresis to be greater than 500 mV.  
The EN pin has a small pull-up current Ip which sets the default state of the pin to enable when no external  
components are connected. The pull-up current is also used to control the voltage hysteresis for the UVLO  
function since it increases by Ih once the EN pin crosses the enable threshold. The UVLO thresholds can be  
calculated using Equation 4 and Equation 5.  
TPS50x01  
VIN  
ip  
i
h
R 1  
R 2  
EN  
Figure 18. Adjustable VIN Under Voltage Lock Out  
TPS50x01  
PVIN  
ip  
i
h
R 1  
R 2  
EN  
Figure 19. Adjustable PVIN Under Voltage Lock Out, VIN 3 V  
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TPS50x01  
PVIN  
VIN  
ip  
i
h
R 1  
R 2  
EN  
Figure 20. Adjustable VIN and PVIN Under Voltage Lock Out  
æ
ç
è
ö
VENFALLING  
VSTART  
- VSTOP  
÷
VENRISING  
ø
R1 =  
æ
ö
÷
ø
VENFALLING  
Ip 1-  
+I  
ç
h
VENRISING  
R1´ VENFALLING  
VSTOP - VENFALLING + R1(Ip + Ih )  
è
(4)  
(5)  
R2 =  
Where Ih = 3 μA, Ip = 3.2 μA, VENRISING = 1.131 V, VENFALLING = 1.09 V  
Adjustable Switching Frequency and Synchronization (SYNC)  
The switching frequency of the device supports three modes of operations. The modes of operation are set by  
the conditions on the RT and Sync pins. At a high level these modes can be described as master, internal  
oscillator and external synchronization modes.  
In master mode, the RT pin should be left floating, the internal oscillator is set to 500 kHz and the Sync pin is set  
as an output clock. The Sync output is in phase with respect to the internal oscillator. Sync out signal level is  
same as VIN level with 50% duty cycle. Sync signal feeding the slave module which is in phase with the master  
clock gets internally inverted (180 degrees out of phase with the master clock) internally in the slave module.  
In internal oscillator mode, a resistor is connected between the RT pin and GND. The Sync pin requires a 10-kΩ  
resistor to GND for this mode to be effective. The switching frequency of the device is adjustable from 100 kHz to  
1 MHz by placing a maximum of 510 kΩ and a minimum of 47 kΩ respectively. To determine the RT resistance  
for a given switching frequency, use Equation 6 or the curve in Figure 21. To reduce the solution size one would  
set switching frequency as high as possible, but tradeoffs of supply efficiency and minimum controllable on time  
should be considered.  
-1.0549  
RT(FSW) = 67009 x FSW  
(6)  
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3
1.2x10  
3
1.08x10  
RT(FSW  
)
960  
840  
720  
600  
480  
360  
240  
120  
0
RT = 500 kW  
3
0
100  
200  
300  
400  
500  
600  
700  
800  
900 1x10  
Switching Frequency (FSW) - kHz  
Figure 21. RT vs Switching Frequency  
When operating the converter in internal oscillator mode (internal oscillator determines the switching frequency  
(500 kHz) default), the synchronous pin becomes the output and there is a phase inversion. When trying to  
parallel with another converter, the RT pin of the second (slave) converter must have its RT pin populated such  
that the converter frequency of the slave converter must be within ±5% of the master converter. This is required  
because the RT pin also sets the proper operation of slope compensation.  
In external synchronization mode, a resistor is connected between the RT pin and GND. The Sync pin requires a  
toggling signal for this mode to be effective. The switching frequency of the device goes 1:1 with that of Sync pin.  
External system clock-user supplied sync clock signal determines the switching frequency. If no external clock  
signal is detected for 20 µs, then TPS50601-SP transitions to its internal clock which is typically 500 kHz. An  
external synchronization using an inverter to obtain phase inversion is necessary. RT values of master and slave  
converter must be within ±5% of the external synchronization frequency. This is necessary for proper slope  
compensation. A resistance in the RT pin required for proper operation of the slope compensation circuit. To  
determine the RT resistance for a given switching frequency, use Equation 6 or the curve in Figure 21. To reduce  
the solution size one would set switching frequency as high as possible, but tradeoffs of supply efficiency and  
minimum controllable on time should be considered.  
These modes are described in Table 3.  
Table 3. Switching Frequency, SYNC and RT Pins Usage Table  
SWITCHING  
FREQUENCY  
RT PIN  
SYNC PIN  
DESCRIPTION/NOTES  
Sync pin behaves as an output. Sync output signal is  
180° out of phase to the internal 500-kHz switching  
frequency.  
Float  
Generates an output signal  
10-kΩ resistor to AGND  
500 kHz  
Internally generated switching frequency is based  
upon the resistor value present at the RT pin.  
100 kHz to 1 MHz  
47-kΩ to 485-kΩ  
resistor to AGND  
User supplied sync clock or  
TPS50601 master device  
sync output  
Internally synchronized  
to external clock  
Set value of RT that corresponds to the externally  
supplied sync frequency.  
Slow Start (SS/TR)  
The device uses the lower voltage of the internal voltage reference or the SS/TR pin voltage as the reference  
voltage and regulates the output accordingly. A capacitor on the SS/TR pin to ground implements a slow start  
time. The device has an internal pull-up current source of 5 mA that charges the external slow start capacitor.  
The calculations for the slow start time (Tss, 10% to 90%) and slow start capacitor (Css) are shown in  
Equation 7. The voltage reference (Vref) is 0.795 V and the slow start charge current (Iss) is 2.5 μA.  
Css(nF) ´ Vref(V)  
Tss(ms) =  
Iss(mA)  
(7)  
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When the input UVLO is triggered, the EN pin is pulled below 1.032 V, or a thermal shutdown event occurs the  
device stops switching and enters low current operation. At the subsequent power up, when the shutdown  
condition is removed, the device does not start switching until it has discharged its SS/TR pin to ground ensuring  
proper soft start behavior.  
Power Good (PWRGD)  
The PWRGD pin is an open drain output. Once the VSENSE pin is between 94% and 106% of the internal  
voltage reference the PWRGD pin pull-down is de-asserted and the pin floats. It is recommended to use a pull-  
up resistor between the values of 10 kand 100 kto a voltage source that is 5.5 V or less. The PWRGD is in a  
defined state once the VIN input voltage is greater than 1 V but with reduced current sinking capability. The  
PWRGD achieves full current sinking capability once the VIN input voltage is above 3 V.  
The PWRGD pin is pulled low when VSENSE is lower than 91% or greater than 109% of the nominal internal  
reference voltage. Also, the PWRGD is pulled low, if the input UVLO or thermal shutdown are asserted, the EN  
pin is pulled low or the SS/TR pin is below 1.4 V.  
Bootstrap Voltage (BOOT) and Low Dropout Operation  
The device has an integrated boot regulator, and requires a small ceramic capacitor between the BOOT and PH  
pins to provide the gate drive voltage for the high-side MOSFET. The boot capacitor is charged when the BOOT  
pin voltage is less than VIN and BOOT-PH voltage is below regulation. The value of this ceramic capacitor  
should be 0.1 μF. A ceramic capacitor with an X7R or X5R grade dielectric with a voltage rating of 10 V or higher  
is recommended because of the stable characteristics over temperature and voltage.  
To improve drop out, the device is designed to operate at a high duty cycle as long as the BOOT to PH pin  
voltage is greater than the BOOT-PH UVLO threshold which is typically 2.1 V. When the voltage between BOOT  
and PH drops below the BOOT-PH UVLO threshold the high-side MOSFET is turned off and the low-side  
MOSFET is turned on allowing the boot capacitor to be recharged. In applications with split input voltage rails,  
high duty cycle operation can be achieved as long as (VIN – PVIN) > 4 V.  
Maximum switching frequency is also limited by minimum on time (specified in Electrical Characteristics table) as  
indicated by Equation 8. Switching frequency will be worse case at no load conditions.  
1
VO + Rds_on · (IO)  
FSW =  
=
T
VIN · (Ton_max)  
(8)  
Sequencing (SS/TR)  
Many of the common power supply sequencing methods can be implemented using the SS/TR, EN and PWRGD  
pins.  
The sequential method is illustrated in Figure 22 using two TPS50601 devices. The power good of the first  
device is coupled to the EN pin of the second device which enables the second power supply once the primary  
supply reaches regulation.  
TPS50x01  
TPS50x01  
PWRGD  
EN  
EN  
SS/TR  
SS/TR  
PWRGD  
Figure 22. Sequential Start Up Sequence  
Figure 23 shows the method implementing ratio-metric sequencing by connecting the SS/TR pins of two devices  
together. The regulator outputs ramp up and reach regulation at the same time. When calculating the slow start  
time the pull-up current source must be doubled in Equation 7.  
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TPS50x01  
EN  
SS/TR  
PWRGD  
TPS50x01  
EN  
SS/TR  
PWRGD  
Figure 23. Ratiometric Start Up Sequence  
Ratio-metric and simultaneous power supply sequencing can be implemented by connecting the resistor network  
of R1 and R2 shown in Figure 24 to the output of the power supply that needs to be tracked or another voltage  
reference source. Using Equation 9 and Equation 10, the tracking resistors can be calculated to initiate the Vout2  
slightly before, after or at the same time as Vout1. Equation 11 is the voltage difference between Vout1 and  
Vout2.  
To design a ratio-metric start up in which the Vout2 voltage is slightly greater than the Vout1 voltage when Vout2  
reaches regulation, use a negative number in Equation 9 and Equation 10 for ΔV. Equation 11 results in a  
positive number for applications where the Vout2 is slightly lower than Vout1 when Vout2 regulation is achieved.  
The ΔV variable is zero volt for simultaneous sequencing. To minimize the effect of the inherent SS/TR to  
VSENSE offset (Vssoffset, 29 mV) in the slow start circuit and the offset created by the pull-up current source  
(Iss, 2 μA) and tracking resistors, the Vssoffset and Iss are included as variables in the equations.  
To ensure proper operation of the device, the calculated R1 value from Equation 9 must be greater than the  
value calculated in Equation 12.  
Vout2 + DV  
Vssoffset  
R1 =  
´
Vref  
Iss  
(9)  
Vref ´ R1  
Vout2 + DV - Vref  
R2 =  
(10)  
(11)  
(12)  
DV = Vout1 - Vout2  
R1> 2800´ Vout1-180´DV  
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TPS50x01  
EN  
VOUT1  
SS/TR  
PWRGD  
TPS50x01  
VOUT2  
EN  
R1  
R2  
SS/TR  
PWRGD  
R3  
R4  
Figure 24. Ratiometric and Simultaneous Startup Sequence  
Output Overvoltage Protection (OVP)  
The device incorporates an output overvoltage protection (OVP) circuit to minimize output voltage overshoot. For  
example, when the power supply output is overloaded the error amplifier compares the actual output voltage to  
the internal reference voltage. If the VSENSE pin voltage is lower than the internal reference voltage for a  
considerable time, the output of the error amplifier demands maximum output current. Once the condition is  
removed, the regulator output rises and the error amplifier output transitions to the steady state voltage. In some  
applications with small output capacitance, the power supply output voltage can respond faster than the error  
amplifier. This leads to the possibility of an output overshoot. The OVP feature minimizes the overshoot by  
comparing the VSENSE pin voltage to the OVP threshold. If the VSENSE pin voltage is greater than the OVP  
threshold the high-side MOSFET is turned off preventing current from flowing to the output and minimizing output  
overshoot. When the VSENSE voltage drops lower than the OVP threshold, the high-side MOSFET is allowed to  
turn on at the next clock cycle.  
Overcurrent Protection  
The device is protected from overcurrent conditions by cycle-by-cycle current limiting on both the high-side  
MOSFET and the low-side MOSFET.  
High-side MOSFET overcurrent protection  
The device implements current mode control which uses the COMP pin voltage to control the turn off of the high-  
side MOSFET and the turn on of the low-side MOSFET on a cycle by cycle basis. Each cycle the switch current  
and the current reference generated by the COMP pin voltage are compared, when the peak switch current  
intersects the current reference the high-side switch is turned off.  
Low-side MOSFET overcurrent protection  
While the low-side MOSFET is turned on its conduction current is monitored by the internal circuitry. During  
normal operation the low-side MOSFET sources current to the load. At the end of every clock cycle, the low-side  
MOSFET sourcing current is compared to the internally set low-side sourcing current limit. If the low-side  
sourcing current is exceeded the high-side MOSFET is not turned on and the low-side MOSFET stays on for the  
next cycle. The high-side MOSFET is turned on again when the low-side current is below the low-side sourcing  
current limit at the start of a cycle.  
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The low-side MOSFET may also sink current from the load. If the low-side sinking current limit is exceeded the  
low-side MOSFET is turned off immediately for the rest of that clock cycle. In this scenario both MOSFETs are  
off until the start of the next cycle.  
When the low-side MOSFET turns off, switch node increases and forward biases the high-side MOSFET parallel  
diode (high-side MOSFET is still off at this stage).  
TPS50601 Thermal Shutdown  
The internal thermal shutdown circuitry forces the device to stop switching if the junction temperature exceeds  
175°C typically. The device reinitiates the power up sequence when the junction temperature drops below 165°C  
typically.  
Turn-On Behavior  
Minimum on-time specification determines the maximum operating frequency of the design. As the unit starts up  
and goes through its soft start process, the required duty-cycle is less than the minimum controllable on-time.  
This can cause the converter to skip pulses. Thus, instantaneous output pulses can be higher or lower than the  
desired voltage. This behavior is shown in and is only evident when operating at high frequency with high  
bandwidth. Once the minimum on-pulse is greater than the minimum controllable on-time, the turn-on behavior is  
normal. When operating at low frequencies (100 kHz or less), the turn-on behavior does not exhibit any ringing at  
initial startup.  
Small Signal Model for Loop Response  
Figure 25 shows an equivalent model for the device control loop which can be modeled in a circuit simulation  
program to check frequency response and transient responses. The error amplifier is a transconductance  
amplifier with a gm of 1300 μA/V. The error amplifier can be modeled using an ideal voltage controlled current  
source. The resistor Roea (30 M) and capacitor Coea (20.7 pF) model the open loop gain and frequency  
response of the error amplifier. The 1-mV ac voltage source between the nodes a and b effectively breaks the  
control loop for the frequency response measurements. Plotting a/c and c/b show the small signal responses of  
the power stage and frequency compensation respectively. Plotting a/b shows the small signal response of the  
overall loop. The dynamic loop response can be checked by replacing the RL with a current source with the  
appropriate load step amplitude and step rate in a time domain analysis.  
PH  
VOUT  
Power Stage  
18 A/V  
a
b
RESR  
R1  
RL  
COMP  
c
C
O
VSENSE  
R2  
0.8V  
Coea  
Roea  
R3  
C1  
gm  
1300 mA/V  
C2  
Figure 25. Small Signal Model for Loop Response  
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Simple Small Signal Model for Peak Current Mode Control  
Figure 26 is a simple small signal model that can be used to understand how to design the frequency  
compensation. The device power stage can be approximated to a voltage controlled current source (duty cycle  
modulator) supplying current to the output capacitor and load resistor. The control to output transfer function is  
shown in Equation 13 and consists of a dc gain, one dominant pole and one ESR zero. The quotient of the  
change in switch current and the change in COMP pin voltage (node c in Figure 25) is the power stage  
transconductance (gmps) which is 18 A/V for the device. The DC gain of the power stage is the product of gmps  
and the load resistance RL) as shown in Equation 14 with resistive loads. As the load current increases, the DC  
gain decreases. This variation with load may seem problematic at first glance, but fortunately the dominant pole  
moves with load current (see Equation 15). The combined effect is highlighted by the dashed line in Figure 27.  
As the load current decreases, the gain increases and the pole frequency lowers, keeping the 0-dB crossover  
frequency the same for the varying load conditions which makes it easier to design the frequency compensation.  
VOUT  
VC  
RESR  
RL  
gm  
ps  
CO  
Figure 26. Simplified Small Signal Model for Peak Current Mode Control  
VOUT  
Adc  
VC  
RESR  
fp  
RL  
gm  
ps  
CO  
fz  
Figure 27. Simplified Frequency Response for Peak Current Mode Control  
æ
ç
è
s
ö
÷
ø
1+  
2p ´ ¦z  
VOUT  
VC  
= Adc ´  
æ
ö
÷
ø
s
1+  
ç
è
2p ´ ¦p  
(13)  
(14)  
Adc = gmps ´ RL  
1
¦p =  
C
´ R ´ 2p  
L
O
(15)  
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1
¦z =  
C
´ R  
´ 2p  
ESR  
O
(16)  
Where  
gmea is the GM amplifier gain ( 1300 μA/V)  
gmps is the power stage gain (18 A/V).  
RL is the load resistance  
CO is the output capacitance.  
RESR is the equivalent series resistance of the output capacitor.  
Small Signal Model for Frequency Compensation  
The device uses a transconductance amplifier for the error amplifier and readily supports two of the commonly  
used frequency compensation circuits shown in Figure 28. In Type 2A, one additional high frequency pole is  
added to attenuate high frequency noise.  
The design guideline below are provided for advanced users who prefer to compensate using the general  
method. The step-by-step design procedure described in the application section may also be used.  
VOUT  
R1  
VSENSE  
Type 2A  
Type 2B  
COMP  
Coea  
Vref  
R3  
C1  
gm  
C2  
R3  
C1  
ea  
Roea  
R2  
Figure 28. Types of Frequency Compensation  
The general design guidelines for device loop compensation are as follows  
1. Determine the crossover frequency fc. A good starting point is 1/10th of the switching frequency, fSW  
2. R3 can be determined by  
.
2p ´ ¦c ´ VOUT ´ Co  
R3 =  
gm  
´ Vref ´ gm  
ps  
ea  
(17)  
Where  
gmea is the GM amplifier gain ( 1300 μA/V)  
gmps is the power stage gain (18 A/V).  
Vref is the reference voltage (0.795 V)  
æ
ç
è
ö
÷
ø
1
¦p =  
CO ´ RL ´ 2p  
3. Place a compensation zero at the dominant pole  
C1 can be determined by  
RL ´ Co  
.
C1 =  
R3  
(18)  
4. C2 is optional. It can be used to cancel the zero from the ESR (Equivalent Series Resistance) of the output  
capacitor Co.  
RESR ´ Co  
C2 =  
R3  
(19)  
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PACKAGE OPTION ADDENDUM  
www.ti.com  
24-Jan-2013  
PACKAGING INFORMATION  
Orderable Device  
Status Package Type Package Pins Package Qty  
Eco Plan Lead/Ball Finish  
MSL Peak Temp  
Op Temp (°C)  
Top-Side Markings  
Samples  
Drawing  
(1)  
(2)  
(3)  
(4)  
TPS50301SHKH  
ACTIVE  
CFP  
CFP  
HKH  
20  
20  
1
1
TBD  
TBD  
AU  
AU  
N / A for Pkg Type  
N / A for Pkg Type  
-55 to 210 TPS50301SHKH  
-55 to 125 TPS50601MHKHV  
TPS50601MHKHV  
ACTIVE  
HKH  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability  
information and additional product content details.  
TBD: The Pb-Free/Green conversion plan has not been defined.  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that  
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between  
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight  
in homogeneous material)  
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.  
(4) Only one of markings shown within the brackets will appear on the physical device.  
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Addendum-Page 1  
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