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TPS51116RGETG4 [TI]

COMPLETE DDR, DDR2 AND DDR3 MEMORY POWER SOLUTION SYNCHRONOUS BUCK CONTROLLER, 3-A LDO, BUFFERED REFERENCE; 完整的DDR ， DDR2和DDR3内存的电源解决方案同步降压控制器， 3 -A LDO ，缓冲基准
TPS51116RGETG4
型号： TPS51116RGETG4
厂家： TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述：

COMPLETE DDR, DDR2 AND DDR3 MEMORY POWER SOLUTION SYNCHRONOUS BUCK CONTROLLER, 3-A LDO, BUFFERED REFERENCE
完整的DDR ， DDR2和DDR3内存的电源解决方案同步降压控制器， 3 -A LDO ，缓冲基准

稳压器 开关式稳压器或控制器 电源电路 开关式控制器 双倍数据速率
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TPS51116  
www.ti.com................................................................................................................................................................ SLUS609H–MAY 2004–REVISED JULY 2009  
COMPLETE DDR, DDR2 AND DDR3 MEMORY POWER SOLUTION  
SYNCHRONOUS BUCK CONTROLLER, 3-A LDO, BUFFERED REFERENCE  
1
FEATURES  
DESCRIPTION  
2
•
Synchronous Buck Controller (VDDQ)  
–
–
Wide-Input Voltage Range: 3.0-V to 28-V  
The TPS51116 provides a complete power supply for  
DDR/SSTL-2, DDR2/SSTL-18, and DDR3 memory  
systems. It integrates a synchronous buck controller  
with a 3-A sink/source tracking linear regulator and  
buffered low noise reference. The TPS51116 offers  
the lowest total solution cost in systems where space  
D−CAP™ Mode with 100-ns Load Step  
Response  
–
Current Mode Option Supports Ceramic  
Output Capacitors  
is at  
a premium. The TPS51116 synchronous  
–
–
–
Supports Soft-Off in S4/S5 States  
controller runs fixed 400kHz pseudo-constant  
frequency PWM with an adaptive on-time control that  
can be configured in D-CAP™ Mode for ease of use  
and fastest transient response or in current mode to  
support ceramic output capacitors. The 3-A  
sink/source LDO maintains fast transient response  
only requiring 20-µF (2 × 10 µF) of ceramic output  
capacitance. In addition, the LDO supply input is  
available externally to significantly reduce the total  
power losses. The TPS51116 supports all of the  
sleep state controls placing VTT at high-Z in S3  
(suspend to RAM) and discharging VDDQ, VTT and  
VTTREF (soft-off) in S4/S5 (suspend to disk).  
TPS51116 has all of the protection features including  
thermal shutdown and is offered in both a 20-pin  
HTSSOP PowerPAD™ package and 24-pin 4
״
 QFN.  
Current Sensing from RDS(on) or Resistor  
2.5-V (DDR), 1.8-V (DDR2), Adjustable to  
1.5-V (DDR3) or Output Range 0.75-V to  
3.0-V  
–
Equipped with Powergood, Overvoltage  
Protection and Undervoltage Protection  
•
3-A LDO (VTT), Buffered Reference (VREF)  
–
–
Capable to Sink and Source 3 A  
LDO Input Available to Optimize Power  
Losses  
–
Requires only 20-µF Ceramic Output  
Capacitor  
–
–
–
–
Buffered Low Noise 10-mA VREF Output  
Accuracy 20 mV for both VREF and VTT  
Supports High-Z in S3 and Soft-Off in S4/S5  
Thermal Shutdown  
APPLICATIONS  
•
DDR/DDR2/DDR3/LPDDR3 Memory Power  
Supplies  
•
SSTL-2 SSTL-18 and HSTL Termination  
M1  
Ceramic  
IRF7821  
L1  
0.1 µF  
C1  
1 µH  
VDDQ  
1.8 V  
10 A  
VTT  
0.9 V  
2 A  
24  
23  
22  
21  
20  
19  
M2  
IRF7832  
C6  
SP−CAP  
2y150 µF  
VTT VLDOIN VBST DRVH LL  
VTTGND  
DRVL  
PGND  
1
2
3
4
5
6
18  
VREF  
0.9 V  
10 mA  
VIN  
C5  
Ceramic  
VTTSNS  
CS_GND 17  
CS 16  
R1  
5.1 kΩ  
2y10 µF  
GND  
TPS51116RGE  
MODE  
V5IN 15  
5V_IN  
R3  
5.1 Ω  
VTTREF  
COMP  
V5FILT 14  
PGOOD 13  
C2  
Ceramic  
1 µF  
C7  
Ceramic  
1 µF  
R2  
100 kΩ  
C3  
Ceramic  
2y10 µF  
NC VDDQSNS VDDQSET S3 S5 NC  
7
8
9
10  
11  
12  
C4  
PGOOD  
S3  
S5  
Ceramic  
0.033 µF  
UDG−04153  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
2
D-CAP, PowerPAD are trademarks of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2004–2009, Texas Instruments Incorporated  
TPS51116  
SLUS609H–MAY 2004–REVISED JULY 2009................................................................................................................................................................ www.ti.com  
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam  
during storage or handling to prevent electrostatic damage to the MOS gates.  
ORDERING INFORMATION(1)  
MINIMUM  
ORDER  
QUANTITY  
ORDERABLE PART  
NUMBER  
OUTPUT  
SUPPLY  
TA  
PACKAGE  
PINS  
TPS51116PWP  
TPS51116PWPR  
TPS51116PWPRG4  
TPS51116RGE  
Tube  
70  
2000  
2000  
90  
PLASTIC HTSSOP  
PowerPAD (PWP)  
20  
Tape-and-reel  
Tape-and-reel  
Tube  
-40°C to 85°C  
Large  
tape-and-reel  
PLASTIC QUAD FLAT  
PACK (QFN)  
TPS51116RGER  
TPS51116RGET  
3000  
250  
24  
Small  
tape-and-reel  
(1) All packaging options have Cu NIPDAU lead/ball finish.  
ABSOLUTE MAXIMUM RATINGS(1)  
over operating free-air temperature range unless otherwise noted  
TPS51116  
UNITS  
VBST  
-0.3 to 36  
-0.3 to 6  
VBST wrt LL  
VIN  
Input voltage range  
V
CS, MODE, S3, S5, VTTSNS, VDDQSNS, V5IN, VLDOIN, VDDQSET,  
V5FILT  
-0.3 to 6  
PGND, VTTGND, CS_GND  
DRVH  
-0.3 to 0.3  
-1.0 to 36  
-1.0 to 30  
-0.3 to 6  
VOUT Output voltage range LL  
COMP, DRVL, PGOOD, VTT, VTTREF  
Operating ambient temperature range  
Storage temperature  
V
TA  
-40 to 85  
-55 to 150  
°C  
Tstg  
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings  
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating  
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage  
values are with respect to the network ground terminal unless otherwise noted.  
DISSIPATION RATINGS  
DERATING FACTOR ABOVE TA  
=
TA < 25°C POWER RATING  
(W)  
TA = 85°C POWER RATING  
(W)  
PACKAGE  
25°C  
(mW/°C)  
20-pin PWP  
24-pin RGE  
2.53  
2.20  
25.3  
22.0  
1.01  
0.88  
2
Submit Documentation Feedback  
Copyright © 2004–2009, Texas Instruments Incorporated  
Product Folder Link(s): TPS51116  
TPS51116  
www.ti.com................................................................................................................................................................ SLUS609H–MAY 2004–REVISED JULY 2009  
RECOMMENDED OPERATING CONDITIONS  
MIN  
4.75  
-0.1  
-0.6  
-0.1  
-0.1  
-0.1  
MAX  
5.25  
34  
UNIT  
Supply voltage, V5IN, V5FILT  
V
VBST, DRVH  
LL  
28  
VLDOIN, VTT, VTTSNS, VDDQSNS  
VTTREF  
3.6  
1.8  
0.1  
Voltage range  
V
PGND, VTTGND, CS_GND  
S3, S5, MODE, VDDQSET, CS, COMP, PGOOD,  
DRVL  
-0.1  
-40  
5.25  
85  
Operating free-air temperature, TA  
°C  
Copyright © 2004–2009, Texas Instruments Incorporated  
Submit Documentation Feedback  
3
Product Folder Link(s): TPS51116  
TPS51116  
SLUS609H–MAY 2004–REVISED JULY 2009................................................................................................................................................................ www.ti.com  
ELECTRICAL CHARACTERISTICS  
over operating free-air temperature range, VV5IN = 5 V(1), VLDOIN is connected to VDDQ output (unless otherwise noted)  
PARAMETER  
SUPPLY CURRENT  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
TA = 25°C, No load, VS3 = VS5 = 5 V,  
COMP connected to capacitor  
IV5IN1  
IV5IN2  
IV5IN3  
Supply current 1, V5IN(1)  
Supply current 2, V5IN(1)  
Supply current 3, V5IN(1)  
0.8  
300  
240  
2
600  
500  
mA  
TA = 25°C, No load, VS3 = 0 V, VS5 = 5 V,  
COMP connected to capacitor  
TA = 25°C, No load, VS3 = 0 V, VS5 = 5 V,  
VCOMP = 5 V  
Shutdown current, V5IN(1)  
Supply current 1, VLDOIN  
Supply current 2, VLDOIN  
Standby current, VLDOIN  
TA = 25°C, No load, VS3 = VS5 = 0 V  
TA = 25°C, No load, VS3 = VS5 = 5 V  
TA = 25°C, No load, VS3 = 5 V, VS5 = 0 V,  
TA = 25°C, No load, VS3 = VS5 = 0 V  
0.1  
1
1.0  
10  
µA  
IV5INSDN  
IVLDOIN1  
IVLDOIN2  
IVLDOINSDN  
0.1  
0.1  
10  
1.0  
VTTREF OUTPUT  
VVTTREF  
Output voltage, VTTREF  
VVDDQSNS/2  
V
-10 mA < IVTTREF < 10 mA, VVDDQSNS = 2.5 V,  
Tolerance to VVDDQSNS/2  
-20  
-18  
-15  
–12  
20  
18  
15  
12  
-10 mA < IVTTREF < 10 mA, VVDDQSNS = 1.8 V,  
Tolerance to VVDDQSNS/2  
VVTTREFTOL  
Output voltage tolerance  
mV  
-10 mA < IVTTREF < 10 mA, VVDDQSNS = 1.5 V,  
Tolerance to VVDDQSNS/2  
-10 mA < IVTTREF < 10 mA, VVDDQSNS = 1.2 V,  
Tolerance to VVDDQSNS/2  
VVTTREFSRC  
VVTTREFSNK  
VDDQ OUTPUT  
Source current  
VVDDQSNS = 2.5 V, VVTTREF = 0 V  
VVDDQSNS = 2.5 V, VVTTREF = 2.5 V  
-20  
20  
-40  
40  
-80  
80  
mA  
Sink current  
TA = 25°C, VVDDQSET = 0 V, No load  
2.465  
2.457  
2.440  
1.776  
1.769  
1.764  
2.500  
2.500  
2.500  
1.800  
1.800  
1.800  
2.535  
2.543  
2.550  
1.824  
1.831  
1.836  
(2)  
0°C ≤ TA≤ 85°C, VVDDQSET = 0 V, No load  
(2)  
-40°C ≤ TA ≤ 85°C, VVDDQSET = 0 V, No load  
TA = 25°C, VVDDQSET = 5 V, No load(2)  
0°C ≤ TA≤ 85°C, VVDDQSET = 5V, No load(2)  
-40°C ≤ TA ≤ 85°C, VVDDQSET = 5V, No load(2)  
VVDDQ  
Output voltage, VDDQ  
V
-40°C ≤ TA ≤ 85°C, Adjustable mode, No  
0.75  
3.0  
load(2)  
TA = 25°C, Adjustable mode  
742.5  
740.2  
738.0  
750.0  
750.0  
750.0  
215  
757.5  
759.8  
762.0  
mV  
VVDDQSET  
VDDQSET regulation voltage 0°C ≤ TA≤ 85°C, Adjustable mode  
-40°C ≤ TA ≤ 85°C, Adjustable mode  
VVDDQSET = 0 V  
kΩ  
RVDDQSNS  
Input impedance, VDDQSNS VVDDQSET = 5 V  
180  
Adjustable mode  
460  
VVDDQSET = 0.78 V, COMP = Open  
VVDDQSET = 0.78 V, COMP = 5 V  
-0.04  
-0.06  
IVDDQSET  
Input current, VDDQSET  
µA  
VS3 = VS5 = 0 V, VVDDQSNS = 0.5 V,  
VMODE = 0 V  
IVDDQDisch  
Discharge current, VDDQ  
Discharge current, VLDOIN  
10  
40  
mA  
mA  
VS3 = VS5 = 0 V, VVDDQSNS = 0.5 V,  
VMODE = 0.5 V  
IVLDOINDisch  
700  
(1) V5IN references to PWP packaged devices should be interpreted as V5FILT references to RGE packaged devices.  
(2) Specified by design.  
4
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Copyright © 2004–2009, Texas Instruments Incorporated  
Product Folder Link(s): TPS51116  
TPS51116  
www.ti.com................................................................................................................................................................ SLUS609H–MAY 2004–REVISED JULY 2009  
ELECTRICAL CHARACTERISTICS (continued)  
over operating free-air temperature range, VV5IN = 5 V, VLDOIN is connected to VDDQ output (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
VTT OUTPUT  
VS3 = VS5 = 5 V, VVLDOIN = VVDDQSNS = 2.5 V  
VS3 = VS5 = 5 V, VVLDOIN = VVDDQSNS = 1.8 V  
VS3 = VS5 = 5 V, VVLDOIN = VVDDQSNS = 1.5 V  
1.25  
0.9  
VVTTSNS  
Output voltage, VTT  
V
0.75  
VVDDQSNS = VVLDOIN = 2.5 V, VS3 = VS5 = 5 V,  
IVTT = 0 A  
-20  
-30  
-40  
-20  
-30  
-40  
-20  
-30  
-40  
-20  
-30  
-40  
20  
30  
40  
20  
30  
40  
20  
30  
40  
20  
30  
40  
VTT output voltage tolerance VVDDQSNS = VVLDOIN = 2.5 V, VS3 = VS5 = 5 V,  
VVTTTOL25  
VVTTTOL18  
VVTTTOL15  
VVTTTOL12  
mV  
mV  
mV  
mV  
to VTTREF  
|IVTT| < 1.5 A  
VVDDQSNS = VVLDOIN = 2.5 V, VS3 = VS5 = 5 V,  
|IVTT| < 3 A  
VVDDQSNS = VVLDOIN = 1.8 V, VS3 = VS5 = 5 V,  
IVTT = 0 A  
VTT output voltage tolerance VVDDQSNS = VVLDOIN = 1.8 V, VS3 = VS5 = 5 V,  
to VTTREF  
|IVTT| < 1 A  
VVDDQSNS = VVLDOIN = 1.8 V, VS3 = VS5 = 5 V,  
|IVTT| < 2 A  
VVDDQSNS = VVLDOIN = 1.5 V, VS3 = VS5 = 5 V,  
IVTT = 0 A  
VTT output voltage tolerance VVDDQSNS = VVLDOIN = 1.5 V, VS3 = VS5 = 5 V,  
to VTTREF  
|IVTT| < 1 A  
VVDDQSNS = VVLDOIN = 1.5 V, VS3 = VS5 = 5 V,  
|IVTT| < 2 A  
VVDDQSNS = VVLDOIN = 1.2 V, VS3 = VS5 = 5 V,  
IVTT = 0 A  
VTT output voltage tolerance VVDDQSNS = VVLDOIN = 1.2 V, VS3 = VS5 = 5 V,  
to VTTREF  
|IVTT| < 1 A  
VVDDQSNS = VVLDOIN = 1.2 V, VS3 = VS5 = 5 V,  
|IVTT| < 1.5 A  
VVLDOIN = VVDDQSNS = 2.5 V, VVTT = VVTTSNS  
1.19 V, PGOOD = HI  
=
3.0  
1.5  
3.0  
3.8  
2.2  
3.6  
2.2  
6.0  
3.0  
6.0  
IVTTTOCLSRC  
Source current limit, VTT  
Sink current limit, VTT  
VVLDOIN = VVDDQSNS = 2.5 V, VVTT = 0 V  
A
VVLDOIN = VVDDQSNS = 2.5 V, VVTT = VVTTSNS  
1.31 V, PGOOD = HI  
=
IVTTTOCLSNK  
VVLDOIN = VVDDQSNS = 2.5 V, VVTT = VVDDQ  
VS3 = 0 V, VS5 = 5 V, VVTT = VVDDQSNS /2  
VS3 = 5 V, VVTTSNS = VVDDQSNS /2  
1.5  
-10  
-1  
3.0  
10  
1
IVTTLK  
Leakage current, VTT  
IVTTBIAS  
IVTTSNSLK  
Input bias current, VTTSNS  
Leakage current, VTTSNS  
-0.1  
17  
µA  
VS3 = 0 V, VS5 = 5 V, VVTT = VVDDQSNS /2  
-1  
1
TA = 25°C, VS3 = VS5 = VVDDQSNS = 0 V,  
VVTT = 0.5 V  
IVTTDisch  
Discharge current, VTT  
10  
mA  
TRANSCONDUCTANCE AMPLIFIER  
gm  
Gain  
TA = 25°C  
240  
300  
13  
360  
µS  
µA  
COMP maximum sink  
current  
VS3 = 0 V, VS5 = 5 V, VVDDQSET = 0 V,  
VVDDQSNS = 2.7 V, VCOMP = 1.28 V  
ICOMPSNK  
COMP maximum source  
current  
VS3 = 0 V, VS5 = 5 V, VVDDQSET = 0 V,  
VVDDQSNS = 2.3 V, VCOMP = 1.28 V  
ICOMPSRC  
VCOMPHI  
VCOMPLO  
-13  
1.34  
1.21  
VS3 = 0 V, VS5 = 5 V, VVDDQSET = 0 V,  
VVDDQSNS = 2.3 V, VCS = 0 V  
COMP high clamp voltage  
COMP low clamp voltage  
1.31  
1.18  
1.37  
1.24  
V
VS3 = 0 V, VS5 = 5 V, VVDDQSET = 0 V,  
VVDDQSNS = 2.7 V, VCS = 0 V  
Copyright © 2004–2009, Texas Instruments Incorporated  
Submit Documentation Feedback  
5
Product Folder Link(s): TPS51116  
TPS51116  
SLUS609H–MAY 2004–REVISED JULY 2009................................................................................................................................................................ www.ti.com  
ELECTRICAL CHARACTERISTICS (continued)  
over operating free-air temperature range, VV5IN = 5 V, VLDOIN is connected to VDDQ output (unless otherwise noted)  
PARAMETER  
DUTY CONTROL  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
TON  
Operating on-time  
Startup on-time  
VIN = 12 V, VVDDQSET = 0 V  
520  
125  
100  
350  
TON0  
VIN = 12 V, VVDDQSNS = 0 V  
ns  
(3)  
TON(min)  
TOFF(min)  
Minimum on-time  
Minimum off-time  
TA = 25°C  
TA = 25°C(3)  
ZERO CURRENT COMPARATOR  
Zero current comparator  
offset  
VZC  
-6  
0
6
mV  
OUTPUT DRIVERS  
Source, IDRVH = -100 mA  
Sink, IDRVH = 100 mA  
Source, IDRVL = -100 mA  
Sink, IDRVL = 100 mA  
LL-low to DRVL-on(3)  
DRVL-off to DRVH-on(3)  
3
0.9  
3
6
3
6
3
RDRVH  
RDRVL  
TD  
DRVH resistance  
DRVL resistance  
Dead time  
Ω
0.9  
10  
20  
ns  
INTERNAL BST DIODE  
VFBST  
Forward voltage  
VV5IN-VBST , IF = 10 mA, TA = 25°C  
0.7  
0.8  
0.1  
0.9  
1.0  
V
VVBST = 34 V, VLL = 28 V, VVDDQ = 2.6 V,  
TA = 25°C  
IVBSTLK  
VBST leakage current  
µA  
PROTECTIONS  
VPGND-CS , PGOOD = HI, VCS < 0.5 V  
VPGND-CS , PGOOD = LO, VCS < 0.5 V  
TA = 25°C, VCS > 4.5 V, PGOOD = HI  
TA = 25°C, VCS > 4.5 V, PGOOD = LO  
50  
20  
9
60  
30  
10  
5
70  
40  
11  
6
VOCL  
Current limit threshold  
mV  
ITRIP  
Current sense sink current  
µA  
4
TRIP current temperature  
coefficient  
RDS(on) sense scheme, On the basis  
of TA = 25°C(3)  
TCITRIP  
VOCL(off)  
VR(trip)  
4500  
0
ppm/°C  
Overcurrent protection  
COMP offset  
(VV5IN-CS - VPGND-LL), VV5IN-CS = 60 mV,  
VCS > 4.5 V(3)  
-5  
5
mV  
Current limit threshold setting  
range  
(3)(4)  
VV5IN-CS  
30  
150  
POWERGOOD COMPARATOR  
PG in from lower  
92.5%  
95.0%  
97.5%  
VTVDDQPG  
VDDQ powergood threshold PG in from higher  
102.5%  
105.0% 107.5%  
PG hysteresis  
5%  
7.5  
IPG(max)  
TPG(del)  
PGOOD sink current  
PGOOD delay time  
VVTT = 0 V, VPGOOD = 0.5 V  
Delay for PG in  
2.5  
80  
mA  
130  
200  
µs  
(3) Specified by design.  
(4) V5IN references to PWP packaged devices should be interpreted as V5FILT references to RGE packaged devices.  
6
Submit Documentation Feedback  
Copyright © 2004–2009, Texas Instruments Incorporated  
Product Folder Link(s): TPS51116  
TPS51116  
www.ti.com................................................................................................................................................................ SLUS609H–MAY 2004–REVISED JULY 2009  
ELECTRICAL CHARACTERISTICS (continued)  
over operating free-air temperature range, VV5IN = 5 V, VLDOIN is connected to VDDQ output (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
UNDERVOLTAGE LOCKOUT/LOGIC THRESHOLD  
Wake up  
3.7  
0.2  
4.7  
4.0  
0.3  
4.3  
0.4  
V5IN UVLO threshold  
voltage  
VUVV5IN  
Hysteresis  
No discharge  
VTHMODE  
MODE threshold  
Non-tracking discharge  
2.5 V output  
1.8 V output  
S3, S5  
0.1  
0.25  
4.5  
0.08  
3.5  
0.15  
4.0  
V
VTHVDDQSET  
VDDQSET threshold voltage  
VIH  
High-level input voltage  
Low-level input voltage  
Hysteresis voltage  
2.2  
VIL  
S3, S5  
0.3  
VIHYST  
VINLEAK  
VINVDDQSET  
S3, S5  
0.2  
Logic input leakage current  
Input leakage/ bias current  
S3, S5, MODE  
VDDQSET  
-1  
-1  
1
1
µA  
µs  
UNDERVOLTAGE AND OVERVOLTAGE PROTECTION  
OVP detect  
Hysteresis  
110%  
115%  
5%  
120%  
VDDQ OVP trip threshold  
voltage  
VOVP  
VDDQ OVP propagation  
delay  
TOVPDEL  
VUVP  
TUVPDEL  
TUVPEN  
1.5  
(5)  
UVP detect  
Hysteresis  
70%  
10%  
Output UVP trip threshold  
Output UVP propagation  
delay(5)  
Output UVP enable delay(5)  
32  
cycle  
°C  
1007  
THERMAL SHUTDOWN  
Shutdown temperature  
Hysteresis  
160  
10  
(5)  
TSDN  
Thermal SDN threshold  
(5) Specified by design.  
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DEVICE INFORMATION  
TERMINAL FUNCTIONS  
TERMINAL  
NO.  
I/O  
DESCRIPTION  
NAME  
PWP  
RGE  
Output of the transconductance amplifier for phase compensation. Connect to V5IN to disable  
gm amplifier and use D-CAP™ mode.  
COMP  
8
6
I/O  
I/O  
Current sense comparator input (-) for resistor current sense scheme. Or overcurrent trip  
voltage setting input for RDS(on) current sense scheme if connected to V5IN (PWP), V5FILT  
(RGE) through the voltage setting resistor.  
CS  
15  
16  
DRVH  
DRVL  
19  
17  
5
21  
19  
3
O
O
-
Switching (top) MOSFET gate drive output.  
Rectifying (bottom) MOSFET gate drive output.  
GND  
Signal ground. Connect to minus terminal of the VTT LDO output capacitor.  
Current sense comparator input (+) and ground for powergood circuit.  
CS_GND  
-
17  
Switching (top) MOSFET gate driver return. Current sense comparator input (-) for RDS(on)  
current sense.  
LL  
18  
20  
I/O  
I
MODE  
NC  
6
-
4
Discharge mode setting pin. See VDDQ and VTT Discharge Control section.  
7,12  
No connect.  
Ground for rectifying (bottom) MOSFET gate driver (PWP, RGE). Also current sense  
comparator input(+) and ground for powergood circuit (PWP).  
PGND  
16  
13  
18  
13  
-
Powergood signal open drain output, In HIGH state when VDDQ output voltage is within the  
target range.  
PGOOD  
O
S3  
11  
12  
14  
10  
11  
15  
I
I
I
S3 signal input.  
S5  
S5 signal input.  
V5IN  
5-V power supply input for internal circuits (PWP) and MOSFET gate drivers (PWP, RGE).  
Filtered 5-V power supply input for internal circuits. Connect R-C network from V5IN to  
V5FILT.  
V5FILT  
-
14  
I
VBST  
20  
10  
22  
9
I/O  
I
Switching (top) MOSFET driver bootstrap voltage input.  
VDDQSET  
VDDQ output voltage setting pin. See VDDQ Output Voltage Selection section.  
VDDQ reference input for VTT and VTTREF. Power supply for the VTTREF. Discharge  
current sinking terminal for VDDQ Non-tracking discharge. Output voltage feedback input for  
VDDQ output if VDDQSET pin is connected to V5IN or GND.  
VDDQSNS  
9
8
I/O  
VLDOIN  
VTT  
1
2
3
7
23  
24  
1
I
Power supply for the VTT LDO.  
Power output for the VTT LDO.  
Power ground output for the VTT LDO.  
VTTREF buffered reference output.  
O
-
VTTGND  
VTTREF  
5
O
Voltage sense input for the VTT LDO. Connect to plus terminal of the VTT LDO output  
capacitor.  
VTTSNS  
4
2
I
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RGE PACKAGE  
(BOTTOM VIEW)  
PWP PACKAGE  
(TOP VIEW)  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
1
2
3
4
5
6
VLDOIN  
VTT  
VTTGND  
VTTSNS  
GND  
MODE  
VTTREF  
COMP  
VBST  
DRVH  
LL  
DRVL  
PGND  
CS  
V5IN  
PGOOD  
S5  
VTT  
VLDOIN  
VBST  
DRVH  
LL  
24  
7
8
9
NC  
23  
22  
21  
20  
19  
VDDQSNS  
VDDQSET  
S3  
10  
11  
12  
S5  
DRVL  
NC  
VDDQSNS  
VDDQSET  
18 17 16 15 14 13  
S3  
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FUNCTIONAL BLOCK DIAGRAM (PWP)  
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FUNCTIONAL BLOCK DIAGRAM (RGE)  
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TPS51116  
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DETAILED DESCRIPTION  
The TPS51116 is an integrated power management solution which combines a synchronous buck controller, a  
10-mA buffered reference and a high-current sink/source low-dropout linear regulator (LDO) in a small 20-pin  
HTSSOP package or a 24-pin QFN package. Each of these rails generates VDDQ, VTTREF and VTT that  
required with DDR/DDR2/DDR3 memory systems. The switch mode power supply (SMPS) portion employs  
external N-channel MOSFETs to support high current for DDR/DDR2/DDR3 memory’s VDD/VDDQ. The preset  
output voltage is selectable from 2.5 V or 1.8 V. User defined output voltage is also possible and can be  
adjustable from 0.75 V to 3 V. Input voltage range of the SMPS is 3 V to 28 V. The SMPS runs an adaptive  
on-time PWM operation at high-load condition and automatically reduces frequency to keep excellent efficiency  
down to several mA. Current sensing scheme uses either RDS(on) of the external rectifying MOSFET for a  
low-cost, loss-less solution, or an optional sense resistor placed in series to the rectifying MOSFET for more  
accurate current limit. The output of the switcher is sensed by VDDQSNS pin to generate one-half VDDQ for the  
10-mA buffered reference (VTTREF) and the VTT active termination supply. The VTT LDO can source and sink  
up to 3-A peak current with only 20-µF (two 10-µF in parallel) ceramic output capacitors. VTTREF tracks VDDQ/2  
within 1% of VDDQ. VTT output tracks VTTREF within 20 mV at no load condition while 40 mV at full load. The  
LDO input can be separated from VDDQ and optionally connected to a lower voltage by using VLDOIN pin. This  
helps reducing power dissipation in sourcing phase. TheTPS51116 is fully compatible to JEDEC DDR/DDR2  
specifications at S3/S5 sleep state (see Table 2). The part has two options of output discharge function when  
both VTT and VDDQ are disabled. The tracking discharge mode discharges VDDQ and VTT outputs through the  
internal LDO transistors and then VTT output tracks half of VDDQ voltage during discharge. The non-tracking  
discharge mode discharges outputs using internal discharge MOSFETs which are connected to VDDQSNS and  
VTT. The current capability of these discharge FETs are limited and discharge occurs more slowly than the  
tracking discharge. These discharge functions can be disabled by selecting non-discharge mode.  
VDDQ SMPS, Dual PWM Operation Modes  
The main control loop of the SMPS is designed as an adaptive on-time pulse width modulation (PWM) controller.  
It supports two control schemes which are a current mode and a proprietary D-CAP™ mode. D-CAP™ mode  
uses internal compensation circuit and is suitable for low external component count configuration with an  
appropriate amount of ESR at the output capacitor(s). Current mode control has more flexibility, using external  
compensation network, and can be used to achieve stable operation with very low ESR capacitor(s) such as  
ceramic or specialty polymer capacitors.  
These control modes are selected by the COMP terminal connection. If the COMP pin is connected to V5IN,  
TPS51116 works in the D-CAP™ mode, otherwise it works in the current mode. VDDQ output voltage is  
monitored at a feedback point voltage. If VDDQSET is connected to V5IN or GND, this feedback point is the  
output of the internal resistor divider inside VDDQSNS pin. If an external resistor divider is connected to  
VDDQSET pin, VDDQSET pin itself becomes the feedback point (see VDDQ Output Voltage Selection section).  
At the beginning of each cycle, the synchronous top MOSFET is turned on, or becomes ON state. This MOSFET  
is turned off, or becomes OFF state, after internal one shot timer expires. This one shot is determined by VIN and  
VOUT to keep frequency fairly constant over input voltage range, hence it is called adaptive on-time control (see  
PWM Frequency and Adaptive On-Time Control section). The MOSFET is turned on again when feedback  
information indicates insufficient output voltage and inductor current information indicates below the overcurrent  
limit. Repeating operation in this manner, the controller regulates the output voltage. The synchronous bottom or  
the rectifying MOSFET is turned on each OFF state to keep the conduction loss minimum. The rectifying  
MOSFET is turned off when inductor current information detects zero level. This enables seamless transition to  
the reduced frequency operation at light load condition so that high efficiency is kept over broad range of load  
current.  
In the current mode control scheme, the transconductance amplifier generates a target current level  
corresponding to the voltage difference between the feedback point and the internal 750 mV reference. During  
the OFF state, the PWM comparator monitors the inductor current signal as well as this target current level, and  
when the inductor current signal comes lower than the target current level, the comparator provides SET signal  
to initiate the next ON state. The voltage feedback gain is adjustable outside the controller device to support  
various types of output MOSFETs and capacitors. In the D-CAP™ mode, the transconductance amplifier is  
disabled and the PWM comparator compares the feedback point voltage and the internal 750 mV reference  
during the OFF state. When the feedback point comes lower than the reference voltage, the comparator provides  
SET signal to initiate the next ON state.  
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VDDQ SMPS, Light Load Condition  
TPS51116 automatically reduces switching frequency at light load condition to maintain high efficiency. This  
reduction of frequency is achieved smoothly and without increase of VOUTripple or load regulation. Detail  
operation is described as follows. As the output current decreases from heavy load condition, the inductor current  
is also reduced and eventually comes to the point that its valley touches zero current, which is the boundary  
between continuous conduction and discontinuous conduction modes. The rectifying MOSFET is turned off when  
this zero inductor current is detected. As the load current further decreased, the converter runs in discontinuous  
conduction mode and it takes longer and longer to discharge the output capacitor to the level that requires next  
ON cycle. The ON-time is kept the same as that in the heavy load condition. In reverse, when the output current  
increase from light load to heavy load, switching frequency increases to the constant 400 kHz as the inductor  
current reaches to the continuous conduction. The transition load point to the light load operation IOUT(LL) (i.e. the  
threshold between continuous and discontinuous conduction mode) can be calculated in Equation 1:  
(V * V  
 
)   V  
IN  
OUT  
OUT  
1
I
+
OUT(LL)  
2   L   f  
V
IN  
(1)  
where  
•
f is the PWM switching frequency (400 kHz)  
Switching frequency versus output current in the light load condition is a function of L, f, VIN and VOUT, but it  
decreases almost proportional to the output current from the IOUT(LL) given above. For example, it is 40 kHz at  
IOUT(LL)/10 and 4 kHz at IOUT(LL)/100.  
Low-Side Driver  
The low-side driver is designed to drive high-current, low-RDS(on), N-channel MOSFET(s). The drive capability is  
represented by its internal resistance, which are 3 Ω for V5IN to DRVL and 0.9 Ω for DRVL to PGND. A  
dead-time to prevent shoot through is internally generated between top MOSFET off to bottom MOSFET on, and  
bottom MOSFET off to top MOSFET on. 5-V bias voltage is delivered from V5IN supply. The instantaneous drive  
current is supplied by an input capacitor connected between V5IN and GND. The average drive current is equal  
to the gate charge at VGS = 5 V times switching frequency. This gate drive current as well as the high-side gate  
drive current times 5 V makes the driving power which needs to be dissipated from TPS51116 package.  
High-Side Driver  
The high-side driver is designed to drive high-current, low-RDS(on) N-channel MOSFET(s). When configured as a  
floating driver, 5-V bias voltage is delivered from V5IN supply. The average drive current is also calculated by the  
gate charge at VGS = 5V times switching frequency. The instantaneous drive current is supplied by the flying  
capacitor between VBST and LL pins. The drive capability is represented by its internal resistance, which are 3 Ω  
for VBST to DRVH and 0.9 Ω for DRVH to LL.  
Current Sensing Scheme  
In order to provide both good accuracy and cost effective solution, TPS51116 supports both of external resistor  
sensing and MOSFET RDS(on) sensing. For resistor sensing scheme, an appropriate current sensing resistor  
should be connected between the source terminal of the bottom MOSFET and PGND. CS pin is connected to the  
MOSFET source terminal node. The inductor current is monitored by the voltage between PGND pin and CS pin.  
For RDS(on) sensing scheme, CS pin should be connected to V5IN (PWP), or V5FILT (RGE) through the trip  
voltage setting resistor, RTRIP. In this scheme, CS terminal sinks 10-µA ITRIP current and the trip level is set to the  
voltage across the RTRIP. The inductor current is monitored by the voltage between PGND pin and LL pin so that  
LL pin should be connected to the drain terminal of the bottom MOSFET. ITRIP has 4500ppm/°C temperature  
slope to compensate the temperature dependency of the RDS(on). In either scheme, PGND is used as the positive  
current sensing node so that PGND should be connected to the proper current sensing device, i.e. the sense  
resistor or the source terminal of the bottom MOSFET.  
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PWM Frequency and Adaptive On-Time Control  
TPS51116 employs adaptive on-time control scheme and does not have a dedicated oscillator on board.  
However, the device runs with fixed 400-kHz pseudo-constant frequency by feed-forwarding the input and output  
voltage into the on-time one-shot timer. The on-time is controlled inverse proportional to the input voltage and  
proportional to the output voltage so that the duty ratio is kept as VOUT/VIN technically with the same cycle time.  
Although the TPS51116 does not have a pin connected to VIN, the input voltage is monitored at LL pin during  
the ON state. This helps pin count reduction to make the part compact without sacrificing its performance. In  
order to secure minimum ON-time during startup, feed-forward from the output voltage is enabled after the output  
becomes 750 mV or larger.  
VDDQ Output Voltage Selection  
TPS51116 can be used for both of DDR (VVDDQ = 2.5 V) and DDR2 (VVDDQ = 1.8 V) power supply and adjustable  
output voltage (0.75 V < VVDDQ < 3 V) by connecting VDDQSET pin as shown in Table 1. Use adjustable output  
voltage scheme for DDR3 application.  
Table 1. VDDQSET and Output Voltages  
VDDQSET  
GND  
VDDQ (V)  
2.5  
VTTREF and VTT  
VVDDQSNS/2  
NOTE  
DDR  
V5IN  
1.8  
VVDDQSNS/2  
DDR2  
DDR3  
FB Resistors  
1.5  
VVDDQSNS/2  
RUP= RDOWN=75 kΩ  
FB Resistors  
Adjustable  
VVDDQSNS/2  
0.75 V < VVDDQ < 3 V(1)  
VTT Linear Regulator and VTTREF  
TPS51116 integrates high performance low-dropout linear regulator that is capable of sourcing and sinking  
current up to 3 A. This VTT linear regulator employs ultimate fast response feedback loop so that small ceramic  
capacitors are enough to keep tracking the VTTREF within 40 mV at all conditions including fast load transient.  
To achieve tight regulation with minimum effect of wiring resistance, a remote sensing terminal, VTTSNS, should  
be connected to the positive node of VTT output capacitor(s) as a separate trace from VTT pin. For stable  
operation, total capacitance of the VTT output terminal can be equal to or greater than 20 µF. It is recommended  
to attach two 10-µF ceramic capacitors in parallel to minimize the effect of ESR and ESL. If ESR of the output  
capacitor is greater than 2 mΩ, insert an RC filter between the output and the VTTSNS input to achieve loop  
stability. The RC filter time constant should be almost the same or slightly lower than the time constant made by  
the output capacitor and its ESR. VTTREF block consists of on-chip 1/2 divider, LPF and buffer. This regulator  
also has sink and source capability up to 10 mA. Bypass VTTREF to GND by a 0.033-µF ceramic capacitor for  
stable operation.  
Outputs Management by S3, S5 Control  
In the DDR/DDR2/DDR3 memory applications, it is important to keep VDDQ always higher than VTT/VTTREF  
including both start-up and shutdown. TPS51116 provides this management by simply connecting both S3 and  
S5 terminals to the sleep-mode signals such as SLP_S3 and SLP_S5 in the notebook PC system. All of VDDQ,  
VTTREF and VTT are turned on at S0 state (S3 = S5 = high). In S3 state (S3 = low, S5 = high), VDDQ and  
VTTREF voltages are kept on while VTT is turned off and left at high impedance (high-Z) state. The VTT output  
is floated and does not sink or source current in this state. In S4/S5 states (S3 = S5 = low), all of the three  
outputs are disabled. Outputs are discharged to ground according to the discharge mode selected by MODE pin  
(see VDDQ and VTT Discharge Control section). Each state code represents as follow; S0 = full ON, S3 =  
suspend to RAM (STR), S4 = suspend to disk (STD), S5 = soft OFF. (See Table 2)  
Table 2. S3 and S5 Control  
STATE  
S0  
S3  
HI  
S5  
HI  
VDDQ  
VTTREF  
VTT  
On  
On  
On  
On  
On  
S3  
LO  
LO  
HI  
Off (Hi-Z)  
Off (Discharge)  
S4/S5  
LO  
Off (Discharge)  
Off (Discharge)  
(1)  
14  
V
VDDQ≥ 1.2 V when used as VLDOIN.  
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Soft-Start and Powergood  
The soft start function of the SMPS is achieved by ramping up reference voltage and two-stage current clamp. At  
the starting point, the reference voltage is set to 650 mV (87% of its target value) and the overcurrent threshold  
is set half of the nominal value. When UVP comparator detects VDDQ become greater than 80% of the target,  
the reference voltage is raised toward 750 mV using internal 4-bit DAC. This takes approximately 85 µs. The  
overcurrent threshold is released to nominal value at the end of this period. The powergood signal waits another  
45 µs after the reference voltage reaches 750 mV and the VDDQ voltage becomes good (above 95% of the  
target voltage), then turns off powergood open-drain MOSFET.  
The soft-start function of the VTT LDO is achieved by current clamp. The current limit threshold is also changed  
in two stages using an internal powergood signal dedicated for LDO. During VTT is below the powergood  
threshold, the current limit level is cut into 60% (2.2 A).This allows the output capacitors to be charged with low  
and constant current that gives linear ramp up of the output. When the output comes up to the good state, the  
overcurrent limit level is released to normal value (3.8 A). TPS51116 has an independent counter for each  
output, but the PGOOD signal indicates only the status of VDDQ and does not indicate VTT powergood  
externally. See Figure 1.  
100%  
87%  
80%  
V
VDDQ  
V
OCL  
V
PGOOD  
V
S5  
85 µs  
45 µs  
UDG−04066  
Figure 1. VDDQ Soft-Start and Powergood Timing  
Soft-start duration, TVDDQSS, TVTTSS are functions of output capacitances.  
2   CVDDQ   VVDDQ   0.8  
TVDDQSS  
+
) 85 ms  
IVDDQOCP  
(2)  
(3)  
where IVDDQOCP is the current limit value for VDDQ switcher calculated by Equation 5.  
C
+
  V  
VTT  
VTT  
T
VTTSS  
I
VTTOCL  
where, IVTTOCL = 2.2 A (typ). In each of the two previous calculations, no load current during start-up are  
assumed. Note that both switchers and the LDO do not start up with full load condition.  
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VDDQ and VTT Discharge Control  
TPS51116 discharges VDDQ, VTTREF and VTT outputs during S3 and S5 are both low. There are two different  
discharge modes. The discharge mode can be set by connecting MODE pin as shown in Table 3.  
Table 3. Discharge Selection  
MODE  
V5IN  
DISCHARGE MODE  
No discharge  
VDDQ  
GND  
Tracking discharge  
Non-tracking discharge  
When in tracking-discharge mode, TPS51116 discharges outputs through the internal VTT regulator transistors  
and VTT output tracks half of VDDQ voltage during this discharge. Note that VDDQ discharge current flows via  
VLDOIN to LDOGND thus VLDOIN must be connected to VDDQ output in this mode. The internal LDO can  
handle up to 3 A and discharge quickly. After VDDQ is discharged down to 0.2 V, the internal LDO is turned off  
and the operation mode is changed to the non-tracking-discharge mode.  
When in non-tracking-discharge mode, TPS51116 discharges outputs using internal MOSFETs which are  
connected to VDDQSNS and VTT. The current capability of these MOSFETs are limited to discharge slowly.  
Note that VDDQ discharge current flows from VDDQSNS to PGND in this mode. In case of no discharge mode,  
TPS51116 does not discharge output charge at all.  
Current Protection for VDDQ  
The SMPS has cycle-by-cycle overcurrent limiting control. The inductor current is monitored during the OFF state  
and the controller keeps the OFF state during the inductor current is larger than the overcurrent trip level. The  
trip level and current sense scheme are determined by CS pin connection (see Current Sensing Scheme  
section). For resistor sensing scheme, the trip level, VTRIP, is fixed value of 60 mV.  
For RDS(on) sensing scheme, CS terminal sinks 10 µA and the trip level is set to the voltage across this RTRIP  
resistor.  
VTRIP (mV) + RTRIP (kW)   10 (mA)  
(4)  
As the comparison is done during the OFF state, VTRIP sets valley level of the inductor current. Thus, the load  
current at overcurrent threshold, IOCP, can be calculated as shown in Equation 5.  
ǒ
V
Ǔ
IN * VOUT   VOUT  
VTRIP  
IRIPPLE  
VTRIP  
+ )  
1
IOCP  
+
)
 
2
RDS(on)  
RDS(on) 2   L   f  
VIN  
(5)  
In an overcurrent condition, the current to the load exceeds the current to the output capacitor thus the output  
voltage tends to fall down. If the output voltage becomes less than Powergood level, the VTRIP is cut into half and  
the output voltage tends to be even lower. Eventually, it crosses the undervoltage protection threshold and  
shutdown.  
Current Protection for VTT  
The LDO has an internally fixed constant overcurrent limiting of 3.8 A while operating at normal condition. This  
trip point is reduced to 2.2 A before the output voltage comes within 5% of the target voltage or goes outside of  
10% of the target voltage.  
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Overvoltage and Undervoltage Protection for VDDQ  
TPS51116 monitors a resistor divided feedback voltage to detect overvoltage and undervoltage. If VDDQSET is  
connected to V5IN or GND, the feedback voltage is made by an internal resistor divider inside VDDQSNS pin. If  
an external resistor divider is connected to VDDQSET pin, the feedback voltage is VDDQSET voltage itself.  
When the feedback voltage becomes higher than 115% of the target voltage, the OVP comparator output goes  
high and the circuit latches as the top MOSFET driver OFF and the bottom MOSFET driver ON.  
Also, TPS51116 monitors VDDQSNS voltage directly and if it becomes greater than 4 V TPS51116 turns off the  
top MOSFET driver. When the feedback voltage becomes lower than 70% of the target voltage, the UVP  
comparator output goes high and an internal UVP delay counter begins counting. After 32 cycles, TPS51116  
latches OFF both top and bottom MOSFETs. This function is enabled after 1007 cycles of SMPS operation to  
ensure startup.  
V5IN (PWP), V5FILT (RGE) Undervoltage Lockout (UVLO) Protection  
TPS51116 has 5-V supply undervoltage lockout protection (UVLO). When the V5IN (PWP) voltage or V5FILT  
(RGE) voltage is lower than UVLO threshold voltage, SMPS, VTTLDO and VTTREF are shut off. This is a  
non-latch protection.  
V5IN (PWP), V5FILT (RGE) Input Capacitor  
Add a ceramic capacitor with a value between 1.0 µF and 4.7 µF placed close to the V5IN (PWP) pin or V5FILT  
(RGE) pin to stabilize 5 V from any parasitic impedance from the supply.  
Thermal Shutdown  
TPS51116 monitors the temperature of itself. If the temperature exceeds the threshold value, 160°C (typ),  
SMPS, VTTLDO and VTTREF are shut off. This is a non-latch protection and the operation is resumed when the  
device is cooled down by about 10°C.  
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APPLICATION INFORMATION  
Loop Compensation and External Parts Selection  
Current Mode Operation  
A buck converter using TPS51116 current mode operation can be partitioned into three portions, a voltage  
divider, an error amplifier and a switching modulator. By linearizing the switching modulator, we can derive the  
transfer function of the whole system. Since current mode scheme directly controls the inductor current, the  
modulator can be linearized as shown in Figure 2.  
Figure 2. Linearizing the Modulator  
Here, the inductor is located inside the local feedback loop and its inductance does not appear in the small signal  
model. As a result, a modulated current source including the power inductor can be modeled as a current source  
with its transconductance of 1/RS and the output capacitor represent the modulator portion. This simplified model  
is applicable in the frequency space up to approximately a half of the switching frequency. One note is, although  
the inductance has no influence to small signal model, it has influence to the large signal model as it limits slew  
rate of the current source. This means the buck converter’s load transient response, one of the large signal  
behaviors, can be improved by using smaller inductance without affecting the loop stability.  
Total open loop transfer function of the whole system is given by Equation 6.  
H(s) + H1(s)   H2(s)   H3(s)  
(6)  
Assuming RL>>ESR, RO>>RC and CC>>CC2, each transfer function of the three blocks is shown starting with  
Equation 7.  
R2  
R2 ) R1  
H (s) +  
1
(
)
(7)  
ǒ
CǓ  
R
1 ) s   C   R  
O
C
H (s) + * gm   
2
ǒ
Ǔ ǒ  
CǓ  
1 ) s   C   R  
1 ) s   C   R  
C
O
C2  
(8)  
(9)  
(1 ) s   CO   ESR)  
RL  
 
H3(s) +  
RS  
ǒ
Ǔ
1 ) s   CO   RL  
There are three poles and two zeros in H(s). Each pole and zero is given by the following five equations.  
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1
w
w
w
w
w
+
+
+
+
+
P1  
P2  
P3  
Z1  
Z2  
ǒ
ǒ
ǒ
OǓ  
C   R  
C
(10)  
(11)  
(12)  
(13)  
(14)  
1
Ǔ
C
  RL  
O
1
  R  
CǓ  
C
C2  
1
ǒ
CǓ  
C   R  
C
1
ǒ
C
Ǔ
  ESR  
O
Usually, each frequency of those poles and zeros is lower than the 0 dB frequency, f0. However, the f0 should be  
kept under 1/3 of the switching frequency to avoid effect of switching circuit delay. The f0 is given by Equation 15.  
R
R
gm  
gm  
C
S
0.75  
C
S
1
2p  
R1  
R1 ) R2  
1
2p  
f +  
 
 
 
+
 
 
 
0
C
R
V
C
R
O
OUT  
O
(15)  
Based on small signal analysis above, the external components can be selected by following manner.  
1. Choose the inductor. The inductance value should be determined to give the ripple current of  
approximately 1/4 to 1/2 of maximum output current.  
ǒ
Ǔ
ǒ
Ǔ
V
IN(max) * VOUT   VOUT  
V
IN(max) * VOUT   VOUT  
1
2
L +  
 
+
 
IIND(ripple)   f  
VIN(max)  
IOUT(max)   f  
VIN(max)  
(16)  
The inductor also needs to have low DCR to achieve good efficiency, as well as enough room above peak  
inductor current before saturation. The peak inductor current can be estimated as shown in Equation 17.  
ǒ
Ǔ
V
IN(max) * VOUT   VOUT  
VTRIP  
1
IIND(peak)  
+
)
 
RDS(on) L   f  
VIN(max)  
(17)  
2. Choose rectifying (bottom) MOSFET. When RDS(on) sensing scheme is selected, the rectifying MOSFET’s  
on-resistance is used as this RS so that lower RDS(on) does not always promise better performance. In order  
to clearly detect inductor current, minimum RS recommended is to give 15 mV or larger ripple voltage with  
the inductor ripple current. This promises smooth transition from CCM to DCM or vice versa. Upper side of  
the RDS(on) is of course restricted by the efficiency requirement, and usually this resistance affects efficiency  
more at high-load conditions. When using external resistor current sensing, there is no restriction for low  
RDS(on). However, the current sensing resistance RS itself affects the efficiency  
3. Choose output capacitor(s). In cases of organic semiconductor capacitors (OS-CON) or specialty polymer  
capacitors (SP-CAP), ESR to achieve required ripple value at stable state or transient load conditions  
determines the amount of capacitor(s) need, and capacitance is then enough to satisfy stable operation. The  
peak-to-peak ripple value can be estimated by ESR times the inductor ripple current for stable state, or ESR  
times the load current step for a fast transient load response. In case of ceramic capacitor(s), usually ESR is  
small enough to meet ripple requirement. On the other hand, transient undershoot and overshoot driven by  
output capacitance becomes the key factor to determine the capacitor(s).  
4. Determine f0 and calculate RC using Equation 18. Note that higher RC shows faster transient response in  
cost of unstableness. If the transient response is not enough even with high RC value, try increasing the out  
put capacitance. Recommended f0 is fOSC/4. Then RC can be derived by Equation 19.  
VOUT CO  
RC v 2p   f0   
 
  RS  
gm  
0.75  
(18)  
(19)  
R
C + 2.8   VOUT   CO [mF]   RS [mW]  
5. Calculate CC2. Purpose of this capacitance is to cancel zero caused by ESR of the output capacitor. In case  
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of ceramic capacitor(s) is used, no need for CC2  
.
1
1
w
+
+ w  
+
z2  
p3  
ǒ
C
Ǔ
ǒ
C
CǓ  
  R  
  ESR  
O
C2  
(20)  
(21)  
ǒ
Ǔ
CO   ESR  
CC2  
+
RC  
6. Calculate CC. The purpose of CC is to cut DC component to obtain high DC feedback gain. However, as it  
causes phase delay, another zero to cancel this effect at f0 frequency is need. This zero, ωz1, is determined  
by Cc and Rc. Recommended ωz1 is 10 times lower to the f0 frequency.  
f
0
1
f
+
+
z1  
10  
2p   C   R  
C
C
(22)  
(23)  
7. When using adjustable mode, determine the value of R1 and R2. .  
* 0.75  
V
OUT  
R1 +  
  R2  
0.75  
D-CAP™ Mode Operation  
A buck converter system using D-CAP™ Mode can be simplified as below.  
Figure 3. Linearizing the Modulator  
The VDDQSNS voltage is compare with internal reference voltage after divider resistors. The PWM comparator  
determines the timing to turn on top MOSFET. The gain and speed of the comparator is high enough to keep the  
voltage at the beginning of each on cycle (or the end of off cycle) substantially constant. The DC output voltage  
may have line regulation due to ripple amplitude that slightly increases as the input voltage increase.  
For the loop stability, the 0-dB frequency, f0, defined below need to be lower than 1/3 of the switching frequency.  
f
SW  
3
1
f +  
v
0
2p   ESR   C  
O
(24)  
As f0 is determined solely by the output capacitor’s characteristics, loop stability of D-CAP™ mode is determined  
by the capacitor’s chemistry. For example, specialty polymer capacitors (SP-CAP) have CO in the order of  
several 100 µF and ESR in range of 10 mΩ. These makes f0 in the order of 100 kHz or less and the loop is then  
stable. However, ceramic capacitors have f0 at more than 700 kHz, which is not suitable for this operational  
mode.  
Although D-CAP™ mode provides many advantages such as ease-of-use, minimum external components  
configuration and extremely short response time, due to not employing an error amplifier in the loop, sufficient  
amount of feedback signal needs to be provided by external circuit to reduce jitter level.  
The required signal level is approximately 15 mV at comparing point. This gives VRIPPLE = (VOUT/0.75) x 15 (mV)  
at the output node. The output capacitor’s ESR should meet this requirement.  
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The external components selection is much simple in D-CAP™ mode.  
1. Choose inductor. This section is the same as the current mode. Please refer to the instructions in the  
Current Mode Operation section.  
2. Choose output capacitor(s).Organic semiconductor capacitor(s) or specialty polymer capacitor(s) are  
recommended. Determine ESR to meet required ripple voltage above. A quick approximation is shown in  
Equation 25.  
VOUT   0.015  
IRIPPLE   0.75  
VOUT  
IOUT(max)  
ESR +  
[
  60 [mW]  
(25)  
Thermal Design  
Primary power dissipation of TPS51116 is generated from VTT regulator. VTT current flow in both source and  
sink directions generate power dissipation from the part. In the source phase, potential difference between  
VLDOIN and VTT times VTT current becomes the power dissipation, WDSRC  
.
+ ǒV  
Ǔ
W
* V  
  I  
DSRC  
VLDOIN  
VTT VTT  
(26)  
In this case, if VLDOIN is connected to an alternative power supply lower than VDDQ voltage, power loss can be  
decreased.  
For the sink phase, VTT voltage is applied across the internal LDO regulator, and the power dissipation, WDSNK  
is calculated by Equation 27:  
,
W
+ V  
  I  
VTT VTT  
DSNK  
(27)  
Since this device does not sink AND source the current at the same time and IVTT varies rapidly with time, actual  
power dissipation need to be considered for thermal design is an average of above value. Another power  
consumption is the current used for internal control circuitry from V5IN supply and VLDOIN supply. V5IN  
supports both the internal circuit and external MOSFETs drive current. The former current is in the VLDOIN  
supply can be estimated as 1.5 mA or less at normal operational conditions.  
These powers need to be effectively dissipated from the package. Maximum power dissipation allowed to the  
package is calculated by Equation 28,  
T
J(max) * TA(max)  
WPKG  
+
qJA  
(28)  
where  
•
•
•
TJ(max) is 125°C  
TA(max) is the maximum ambient temperature in the system  
θJA is the thermal resistance from the silicon junction to the ambient  
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This thermal resistance strongly depends on the board layout. TPS51116 is assembled in a thermally enhanced  
PowerPAD™ package that has exposed die pad underneath the body. For improved thermal performance, this  
die pad needs to be attached to ground trace via thermal land on the PCB. This ground trace acts as a heat  
sink/spread. The typical thermal resistance, 39.6°C/W, is achieved based on a 6.5 mm × 3.4 mm thermal land  
with eight vias without air flow. It can be improved by using larger thermal land and/or increasing vias number.  
Further information about PowerPAD™ and its recommended board layout is described in (SLMA002). This  
document is available at http:\\www.ti.com.  
Layout Considerations  
Certain points must be considered before designing a layout using the TPS51116.  
•
•
•
•
PCB trace defined as LL node, which connects to source of switching MOSFET, drain of rectifying MOSFET  
and high-voltage side of the inductor, should be as short and wide as possible.  
Consider adding a small snubber circuit, consists of 3 Ω and 1 nF, between LL and PGND in case a  
high-frequency surge is observed on the LL voltage waveform.  
All sensitive analog traces such as VDDQSNS, VTTSNS and CS should placed away from high-voltage  
switching nodes such as LL, DRVL or DRVH nodes to avoid coupling.  
VLDOIN should be connected to VDDQ output with short and wide trace. If different power source is used for  
VLDOIN, an input bypass capacitor should be placed to the pin as close as possible with short and wide  
connection.  
•
•
The output capacitor for VTT should be placed close to the pin with short and wide connection in order to  
avoid additional ESR and/or ESL of the trace.  
VTTSNS should be connected to the positive node of VTT output capacitor(s) as a separate trace from the  
high current power line and is strongly recommended to avoid additional ESR and/or ESL. If it is needed to  
sense the voltage of the point of the load, it is recommended to attach the output capacitor(s) at that point.  
Also, it is recommended to minimize any additional ESR and/or ESL of ground trace between GND pin and  
the output capacitor(s).  
•
•
Consider adding LPF at VTTSNS in case ESR of the VTT output capacitor(s) is larger than 2 mΩ.  
VDDQSNS can be connected separately from VLDOIN. Remember that this sensing potential is the reference  
voltage of VTTREF. Avoid any noise generative lines.  
•
•
Negative node of VTT output capacitor(s) and VTTREF capacitor should be tied together by avoiding  
common impedance to the high current path of the VTT source/sink current.  
GND (Signal GND) pin node represents the reference potential for VTTREF and VTT outputs. Connect GND  
to negative nodes of VTT capacitor(s), VTTREF capacitor and VDDQ capacitor(s) with care to avoid  
additional ESR and/or ESL. GND and PGND (power ground) should be connected together at a single point.  
•
Connect CS_GND (RGE) to source of rectifying MOSFET using Kevin connection. Avoid common trace for  
high-current paths such as the MOSFET to the output capacitors or the PGND to the MOSFET trace. In case  
of using external current sense resistor, apply the same care and connect it to the positive side (ground side)  
of the resistor.  
•
PGND is the return path for rectifying MOSFET gate drive. Use 0.65 mm (25mil) or wider trace. Connect to  
source of rectifying MOSFET with shortest possible path.  
•
•
Place a V5FILT filter capacitor (RGE) close to the TPS51116, within 12 mm (0.5 inches) if possible.  
The trace from the CS pin should avoid high-voltage switching nodes such as those for LL, VBST, DRVH,  
DRVL or PGOOD.  
•
In order to effectively remove heat from the package, prepare thermal land and solder to the package’s  
thermal pad. Wide trace of the component-side copper, connected to this thermal land, helps heat spreading.  
Numerous vias with a 0.33-mm diameter connected from the thermal land to the internal/solder-side ground  
plane(s) should be used to help dissipation. Do NOT connect PGND to this thermal land underneath the  
package.  
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Figure 4. D-CAP™ Mode, PWP Package  
Figure 5. D-CAP™ Mode, RGE Package  
Table 4. D-CAP™ Mode Schematic Components  
SYMBOL  
R1  
SPECIFICATION  
5.1 kΩ  
MANUFACTURER  
PART NUMBER  
-
-
-
-
R2  
100 kΩ  
R3  
75 kΩ  
R4  
(100 × VVDDQ – 75) kΩ  
5.1 Ω  
R5  
M1  
30 V, 13 mΩ  
30 V, 5 mΩ  
International Rectifier  
International Rectifier  
IRF7821  
IRF7832  
M2  
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Figure 6. Current Mode, PWP Package  
Figure 7. Current Mode, RGE Package  
Table 5. Current Mode Schematic Components  
SYMBOL  
R1  
SPECIFICATION  
6 mΩ, 1%  
100 kΩ  
MANUFACTURER  
PART NUMBER  
Vishay  
-
WSL-2521 0.006  
-
R2  
R5  
5.1 Ω  
M0  
30 V, 13 mΩ  
30 V, 5 mΩ  
International Rectifier  
International Rectifier  
IRF7821  
IRF7832  
M1  
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TYPICAL CHARACTERISTICS  
All data in the following graphs are measured from the PWP packaged device.  
V5IN SUPPLY CURRENT  
vs  
JUNCTION TEMPERATURE  
V5IN SHUTDOWN CURRENT  
vs  
JUNCTION TEMPERATURE  
1.0  
0.9  
0.8  
0.7  
0.6  
0.5  
2.0  
1.8  
1.6  
1.4  
1.2  
1.0  
0.8  
0.4  
0.3  
0.2  
0.6  
0.4  
0.1  
0
0.2  
0
−50  
0
50  
100  
150  
−50  
0
50  
100  
150  
T − Junction Temperature − °C  
J
T − Junction Temperature − °C  
J
Figure 8.  
Figure 9.  
V5IN SUPPLY CURRENT  
vs  
VLDOIN SUPPLY CURRENT  
vs  
LOAD CURRENT  
TEMPERATURE  
10  
9
1.0  
DDR2  
= 0.9 V  
V
VTT  
0.9  
0.8  
0.7  
8
7
6
0.6  
0.5  
0.4  
5
4
3
2
0.3  
0.2  
1
0
0.1  
0
−2  
−1  
0
1
2
−50  
0
50  
100  
150  
I
− VTT Current − A  
T − Junction Temperature − °C  
J
VTT  
Figure 10.  
Figure 11.  
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TYPICAL CHARACTERISTICS (continued)  
CS CURRENT  
vs  
JUNCTION TEMPERATURE  
VDDQ DISCHARGE CURRENT  
vs  
JUNCTION TEMPERATURE  
16  
14  
12  
10  
8
80  
70  
60  
50  
PGOOD = HI  
40  
30  
6
PGOOD = LO  
4
20  
10  
2
0
−50  
0
50  
100  
150  
−50  
0
50  
100  
150  
T − Junction Temperature − °C  
J
T − Junction Temperature − °C  
J
Figure 12.  
Figure 13.  
VTT DISCHARGE CURRENT  
vs  
JUNCTION TEMPERATURE  
OVERVOLTAGE AND UNDERVOLTAGE THRESHOLD  
vs  
JUNCTION TEMPERATURE  
30  
25  
20  
15  
10  
140  
120  
100  
80  
V
OVP  
V
UVP  
60  
−50  
−50  
0
50  
100  
150  
0
50  
100  
150  
T − Junction Temperature − °C  
J
T − Junction Temperature − °C  
J
Figure 14.  
Figure 15.  
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TYPICAL CHARACTERISTICS (continued)  
SWITCHING FREQUENCY  
vs  
SWITCHING FREQUENCY  
vs  
INPUT VOLTAGE  
OUTPUT CURRENT  
430  
420  
410  
450  
400  
D-CAP Mode  
= 7 A  
DDR2  
I
VDDQ  
350  
300  
250  
DDR  
400  
390  
380  
200  
150  
100  
50  
DDR2  
DDR  
D−CAP Mode  
= 12 V  
V
IN  
370  
0
4
8
12  
16  
20  
24  
28  
0
2
4
6
8
10  
I
− VDDQ Output Current − A  
V
IN  
− Input Voltage − V  
VDDQ  
Figure 16.  
Figure 17.  
VDDQ OUTPUT VOLTAGE  
vs  
OUTPUT CURRENT (DDR)  
VDDQ OUTPUT VOLTAGE  
vs  
INPUT VOLTAGE (DDR2)  
1.820  
1.815  
1.810  
1.805  
1.800  
1.795  
1.790  
1.785  
1.780  
1.820  
1.815  
1.810  
1.805  
1.800  
1.795  
1.790  
1.785  
1.780  
D−CAP Mode  
I
= 0 A  
VDDQ  
I
= 10 A  
VDDQ  
D−CAP Mode  
V
IN  
= 12 V  
0
2
4
6
8
10  
4
8
12  
16  
20  
24  
30  
I
− VDDQ Output Current − A  
VDDQ  
V
IN  
− Input Voltage − V  
Figure 18.  
Figure 19.  
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TYPICAL CHARACTERISTICS (continued)  
VTT OUTPUT VOLTAGE  
vs  
OUTPUT CURRENT (DDR)  
VTT OUTPUT VOLTAGE  
vs  
OUTPUT CURRENT (DDR2)  
0.94  
0.93  
0.92  
0.91  
0.90  
0.89  
0.88  
0.87  
0.86  
1.30  
1.29  
1.28  
1.27  
1.26  
1.25  
1.24  
V
= 1.8 V  
VLDOIN  
V
= 2.5 V  
VLDOIN  
1.23  
1.22  
V
= 1.5 V  
= 1.2 V  
VLDOIN  
V
VLDOIN  
V
= 1.8 V  
0
VLDOIN  
1.21  
1.20  
−3  
−2  
−1  
0
1
2
3
−5 −4 −3 −2 −1  
1
2
3
4
5
I
− VTT Output Current − A  
I
− VTT Output Current − A  
VTT  
VTT  
Figure 20.  
Figure 21.  
VTTREF OUTPUT VOLTAGE  
vs  
OUTPUT CURRENT (DDR)  
VTTREF OUTPUT VOLTAGE  
vs  
OUTPUT CURRENT (DDR2)  
1.252  
1.251  
1.250  
1.249  
1.248  
0.904  
0.903  
0.902  
0.901  
0.900  
DDR2  
DDR  
1.247  
1.246  
0.899  
0.898  
1.245  
1.244  
0.897  
0.896  
−10  
−5  
0
5
10  
−10  
−5  
0
5
10  
I
− VTTREF Current − mA  
I
− VTTREF Current − mA  
VTTREF  
VTTREF  
Figure 22.  
Figure 23.  
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TYPICAL CHARACTERISTICS (continued)  
VTTREF OUTPUT VOLTAGE  
vs  
OUTPUT CURRENT (DDR3)  
VTT OUTPUT VOLTAGE  
vs  
OUTPUT CURRENT (DDR3)  
0.765  
0.76  
0.79  
0.78  
0.77  
0.76  
0.75  
0.74  
0.73  
0.72  
0.71  
DDR3  
V
= 1.5 V  
VLDOIN  
0.755  
0.75  
0.745  
0.74  
0.735  
-10  
-5  
0
- VTTREF Current - mA  
10  
5
-3  
-2  
-1  
1
2
0
3
I
VTTREF  
I
- VTT Output Current - A  
VTT  
Figure 24.  
Figure 25.  
VDDQ EFFICIENCY (DDR)  
vs  
VDDQ EFFICIENCY (DDR2)  
vs  
VDDQ CURRENT  
VDDQ CURRENT  
100  
100  
V
IN  
= 8 V  
V
IN  
= 8 V  
V
VDDQ  
= 2.5 V  
V
VDDQ  
= 1.8 V  
90  
80  
90  
80  
V
IN  
= 12 V  
V
IN  
= 20 V  
V
IN  
= 12 V  
V
IN  
= 20 V  
70  
60  
70  
60  
50  
50  
0.001  
0.01  
0.1  
1
10  
0.001  
0.01  
0.1  
1
10  
I
− VDDQ Current − A  
I
− VDDQ Current − A  
VDDQ  
VDDQ  
Figure 26.  
Figure 27.  
Copyright © 2004–2009, Texas Instruments Incorporated  
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29  
Product Folder Link(s): TPS51116  
TPS51116  
SLUS609H–MAY 2004–REVISED JULY 2009................................................................................................................................................................ www.ti.com  
TYPICAL CHARACTERISTICS (continued)  
V
VDDQ  
(50 mV/div)  
I
(2 A/div)  
VDDQ  
V
(10 mV/div)  
(10 mV/div)  
VTTREF  
V
VTT  
t − Time − 2 µs/div  
Figure 28. Ripple Waveforms - Heavy Load Condition  
(50 mV/div)  
t − Time − 20 µs/div  
Figure 29. VDDQ Load Transient Response  
V
VDDQ  
V
VTT  
(20 mV/div)  
S5  
VDDQ  
V
VTTREF  
(20 mV/div)  
VTTREF  
PGOOD  
I
VTT  
(2 A/div)  
I
= I  
VTTREF  
= 0 A  
VDDQ  
t − Time − 100 µs/div  
t − Time − 20 µs/div  
Figure 30. VTT Load Transient Response  
Figure 31. VDDQ, VTT, and VTTREF Start-Up Waveforms  
30  
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Copyright © 2004–2009, Texas Instruments Incorporated  
Product Folder Link(s): TPS51116  
TPS51116  
www.ti.com................................................................................................................................................................ SLUS609H–MAY 2004–REVISED JULY 2009  
TYPICAL CHARACTERISTICS (continued)  
VDDQ  
VDDQ  
VTTREF  
VTTREF  
VTT  
VTT  
S5  
S5  
I
= I  
VTT  
= I  
VTTREF  
= 0 A  
VDDQ  
I
= I  
VTT  
= I  
VTTREF  
= 0 A  
VDDQ  
t − Time − 1 ms/div  
t − Time − 200 µs/div  
Figure 32. Soft-Start Waveforms Tracking Discharge  
Figure 33. Soft-Stop Waveforms Non-Tracking Discharge  
VDDQ BODE PLOT (CURRENT MODE)  
VTT BODE PLOT, SOURCE (DDR2)  
GAIN AND PHASE  
vs  
GAIN AND PHASE  
vs  
FREQUENCY  
FREQUENCY  
80  
60  
180  
80  
60  
180  
135  
135  
Phase  
Phase  
90  
90  
45  
0
40  
40  
20  
45  
0
20  
0
0
Gain  
−45  
−20  
−40  
−60  
−80  
−20  
−40  
−60  
−80  
−45  
Gain  
−90  
−90  
−135  
−135  
I
= −1 A  
VTT  
I
= 7 A  
VDDQ  
−180  
10 M  
−180  
10 k  
1 M  
100 k  
100  
1 k  
10 k  
100 k  
1 M  
f − Frequency − Hz  
f − Frequency − Hz  
Figure 34.  
Figure 35.  
Copyright © 2004–2009, Texas Instruments Incorporated  
Submit Documentation Feedback  
31  
Product Folder Link(s): TPS51116  
TPS51116  
SLUS609H–MAY 2004–REVISED JULY 2009................................................................................................................................................................ www.ti.com  
TYPICAL CHARACTERISTICS (continued)  
VTT BODE PLOT, SINK (DDR2)  
GAIN AND PHASE  
vs  
FREQUENCY  
80  
60  
180  
135  
90  
40  
Phase  
Gain  
20  
45  
0
0
−20  
−40  
−60  
−80  
−45  
−90  
−135  
−180  
I
= 1 A  
VTT  
10 k  
1 M  
100 k  
10 M  
f − Frequency − Hz  
Figure 36.  
32  
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Copyright © 2004–2009, Texas Instruments Incorporated  
Product Folder Link(s): TPS51116  
PACKAGE OPTION ADDENDUM  
www.ti.com  
16-Jul-2009  
PACKAGING INFORMATION  
Orderable Device  
TPS51116PWP  
Status (1)  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
Package Package  
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)  
Qty  
Type  
Drawing  
HTSSOP  
PWP  
20  
20  
20  
20  
24  
24  
24  
24  
70 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR  
no Sb/Br)  
TPS51116PWPG4  
TPS51116PWPR  
TPS51116PWPRG4  
TPS51116RGER  
TPS51116RGERG4  
TPS51116RGET  
TPS51116RGETG4  
HTSSOP  
HTSSOP  
HTSSOP  
VQFN  
PWP  
PWP  
PWP  
RGE  
RGE  
RGE  
RGE  
70 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR  
no Sb/Br)  
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR  
no Sb/Br)  
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR  
no Sb/Br)  
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR  
no Sb/Br)  
VQFN  
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR  
no Sb/Br)  
VQFN  
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR  
no Sb/Br)  
VQFN  
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR  
no Sb/Br)  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in  
a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2)  
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check  
http://www.ti.com/productcontent for the latest availability information and additional product content details.  
TBD: The Pb-Free/Green conversion plan has not been defined.  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements  
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered  
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and  
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS  
compatible) as defined above.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame  
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)  
(3)  
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder  
temperature.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is  
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the  
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take  
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on  
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited  
information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI  
to Customer on an annual basis.  
Addendum-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
14-Jul-2012  
TAPE AND REEL INFORMATION  
*All dimensions are nominal  
Device  
Package Package Pins  
Type Drawing  
SPQ  
Reel  
Reel  
A0  
B0  
K0  
P1  
W
Pin1  
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant  
(mm) W1 (mm)  
TPS51116PWPR  
TPS51116RGER  
TPS51116RGET  
TPS51116RGET  
HTSSOP PWP  
20  
24  
24  
24  
2000  
3000  
250  
330.0  
330.0  
180.0  
180.0  
16.4  
12.4  
12.4  
12.4  
6.95  
4.25  
4.3  
7.1  
4.25  
4.3  
1.6  
1.15  
1.1  
8.0  
8.0  
8.0  
8.0  
16.0  
12.0  
12.0  
12.0  
Q1  
Q2  
Q2  
Q2  
VQFN  
VQFN  
VQFN  
RGE  
RGE  
RGE  
250  
4.25  
4.25  
1.15  
Pack Materials-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
14-Jul-2012  
*All dimensions are nominal  
Device  
Package Type Package Drawing Pins  
SPQ  
Length (mm) Width (mm) Height (mm)  
TPS51116PWPR  
TPS51116RGER  
TPS51116RGET  
TPS51116RGET  
HTSSOP  
VQFN  
PWP  
RGE  
RGE  
RGE  
20  
24  
24  
24  
2000  
3000  
250  
367.0  
367.0  
195.0  
210.0  
367.0  
367.0  
200.0  
185.0  
38.0  
35.0  
45.0  
35.0  
VQFN  
VQFN  
250  
Pack Materials-Page 2  
IMPORTANT NOTICE  
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