TPS51120RHBRG4 [TI]
DUAL CURRENT MODE, SYNCHRONOUS STEP-DOWN CONTROLLER WITH 100-mA STANDBY REGULATORS FOR NOTEBOOK SYSTEM POWER; 双路电流模式，具有100mA待机稳压器笔记本系统功率同步降压型控制器
| 型号： | TPS51120RHBRG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | DUAL CURRENT MODE, SYNCHRONOUS STEP-DOWN CONTROLLER WITH 100-mA STANDBY REGULATORS FOR NOTEBOOK SYSTEM POWER |
| 文件： | 总34页 (文件大小：615K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS51120
www.ti.com
SLUS670A–JULY 2005–REVISED AUGUST 2005
DUAL CURRENT MODE, SYNCHRONOUS STEP-DOWN CONTROLLER WITH 100-mA
STANDBY REGULATORS FOR NOTEBOOK SYSTEM POWER
FEATURES
DESCRIPTION
•
3.3-V and 5-V 100-mA Bootstrapped Standby
The TPS51120 is a highly sophisticated dual current
mode synchronous step-down controller. It is a full
featured controller designed to run directly off a three-
or four-cell Li-ion battery and provide high-power and
5-V and/or 3.3-V standby regulation for all the down-
stream circuitry in a notebook computer system. High
current, 100-mA, 5-V or 3.3-V on-board linear regu-
lators have glitch-free switch over function to SMPS
and can be kept alive independently during standby
state. The pseudo-constant frequency adaptive
on-time control scheme supports full range of current
mode operation including simplified loop compen-
sation, ceramic output capacitors as well as seamless
transition to reduced frequency operation at light-load
condition. Optional D-CAP™ mode operation
optimized for SP-CAP or POSCAP output capacitors
allows further reduction of external compensation
parts. Dynamic UVP supports VIN line sag without
latch off by hitting 5V UVP. No negative voltage
appears at output voltage node during UVLO, UVP,
and OCP, OTP or loss of VIN.
Regulators with Independent Enables
Selectable D-CAP® Mode Enables Fast
Transient Response Less than 100 ns
•
•
•
•
•
•
•
Selectable Low Ripple Current Mode
Less than 1% Internal Reference Accuracy
Selectable PWM-only/Auto-skip Modes
Low-side RDS(on) Loss-less Current Sensing
RSENSE Accurate Current Sense Option
Internal Soft-start and Integrated VOUT
Discharge Transistors
Integrated 2-V Reference
Adaptive Gate Drivers with Integrated Boost
Diode
Power Good for Each Channel with Delay
Timer
•
•
•
•
•
Fault Disable Mode
Supply Input Voltage Range: 4.5 V to 28 V
The TPS51120 32-pin QFN package is specified from
–40°C to 85°C ambient temperature.
APPLICATIONS
•
Notebook Computers System Bus and I/O
V5FILT
C31
1 nF
R11
100 kΩ
R21
100 kΩ
GND
8
7
6
5
4
3
2
1
EN_LDO5
P_GOOD2
9
32
SKIPSEL
P_GOOD1
EN5
GND
10 EN3
TONSEL 31
PGOOD1 30
EN1 29
EN_LDO3
VBAT
VBAT
11 PGOOD2
12 EN2
TPS51120RHB
(QFN−32)
EN_2
EN_1
C10
20 µF
C10
20 µF
13 VBST2
14 DRVH2
15 LL2
VBST1 28
DRVH1 27
LL1 26
C11
0.1 µF
Q3
Q1
IRF7821
C21
0.1 µF
IRF7821
L1
4.7 µH
L2
2.2 µH
VO2
3.3V/6A
VO1
5V/6A
+
+
C2A
150 µF
PowerPAD
C2B
150 µF
C1A
150 µF
C1B
150 µF
Q4
IRF7832
Q2
IRF7832
DRVL1
25
DRVL2
16
17
18
19
20
21
22
23
24
VO1_GND
−
VO2_GND
−
PGND1
R22
3.3 kΩ
R50
5.1
PGND2
R12
3.6 kΩ
W
VBAT
C30
NA
C30
10 µF
C51
1 µF
C50
10 µF
UDG−05074
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
D-CAP is a registered trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2005, Texas Instruments Incorporated
TPS51120
www.ti.com
ECO PLAN
SLUS670A–JULY 2005–REVISED AUGUST 2005
ORDERING INFORMATION(1)(2)
ORDERABLE
OUTPUT
MINIMUM
ORDER
QUANTITY
TA
PACKAGE
PART
NUMBER
PINS
SUPPLY
TPS51120RHBT
TPS51120RHBR
Tape-and-reel
Tape-and-reel
250
PLASTIC QUAD
FLAT PACK (QFN)
Green
(RoHS and no Sb/Br)
-40°C to 85°C
32
3000
(1) All packaging options have Cu NIPdAu lead/ball finish.
(2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
ABSOLUTE MAXIMUM RATINGS(1)
over operating free-air temperature range unless otherwise noted
TPS51120
-0.3 to 36
-0.3 to 6
UNITS
VBST1, VBST2
VBST1, VBST2 wrt LL
VIN, EN5
Input voltage range
V
-0.3 to 30
SKIPSEL, TONSEL, EN1, EN2, CS1, CS2, V5FILT, VFB1, VFB2, EN3, VO1,
VO2
-0.3 to 6
DRVH1, DRVH2
DRVH1, DRVH2 (wrt LL)
LL1, LL2
-1 to 36
-0.3 to 6
-1 to 30
Output voltage range
Source/sink current
V
VREF2, VREG3, VREG5, PGOOD1, PGOOD2, DRVL1, DRVL2, COMP1,
COMP2
-0.3 to 6
PGND1, PGND2
VREF2
-0.3 to 0.3
1
VBST
100
mA
VREG5, VREG3 (source only)
200
TA
Operating ambient temperature range
Storage temperature
-40 to 85
-55 to 150
-40 to 125
255
Tstg
TJ
°C
Junction temperature
Lead temperature 1.6 mm (1/16 inch) from case for 10 seconds
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage
values are with respect to the network ground terminal unless otherwise noted.
DISSIPATION RATINGS
DERATING FACTOR
ABOVE TA = 25°C
(W/°C)
TA = 85°C
POWER RATING
(W)
TA < 25°C POWER RATING
PACKAGE
(W)
32-pin QFN(1)
32-pin QFN(2)
2.6
2.9
0.026
0.029
1.0
1.2
(1) JEDEC standard PCB.
(2) Enhanced thermal conductance by 3 x 3 thermal vias beneath thermal pad.
2
TPS51120
www.ti.com
SLUS670A–JULY 2005–REVISED AUGUST 2005
RECOMMENDED OPERATING CONDITIONS
MIN
4.5
MAX
5.5
34
UNIT
Input voltage, V5FILT
VBST1, VBST2
V
-0.1
-0.1
-0.1
-0.1
-0.1
-0.8
-0.1
-0.8
VBST1, VBST2 wrt LL
5.5
28
Input voltage range
VIN, EN5
V
V
SKIPSEL, TONSEL, EN1, EN2, CS1, CS2, V5FILT, VFB1, VFB2, EN3
5.5
5.5
34
VO1, VO2
DRVH1, DRVH2
DRVH1, DRVH2 (wrt LL)
LL1, LL2
5.5
28
Output voltage range
Source/sink current
VREF2, VREG5, VREG3, PGOOD1, PGOOD2, DRVL1, DRVL2, COMP1,
COMP2
-0.1
-0.1
5.5
PGND1, PGND2
VREF2
0.1
0.08
50
VBST
mA
VREG5, VREF3 (source only)
100
85
Operating ambient temperature range, TA
-40
°C
3
TPS51120
www.ti.com
SLUS670A–JULY 2005–REVISED AUGUST 2005
ELECTRICAL CHARACTERISTICS
over operating free-air temperature range, VVIN = 12 V, VVREG5 = VV5FILT = 5 V (unless otherwise noted)
PARAMETER
SUPPLY CURRENT
TEST CONDITIONS
MIN
TYP
MAX UNIT
VIN current, VREG5=VREG3=No
Load, EN3=EN5=FLOAT,
EN1=EN2=5V, CS=5V, COMP
connected to Cap
IINCCAP
Supply current
Current mode
750
1500
1400
VIN current, VREG5=VREG3=No
Load, EN3=EN5=FLOAT;
EN1=EN2=5V, CS=5V, COMP=5V
IINNOCAP
IIN5(STBY)
IIN3(STBY)
Supply current
Stand-by current
Stand-by current
D-CAP mode
5-V only
700
30
VIN current, VREG5=No Load
EN3=0V, EN5=FLOAT,
EN1=EN2=0
µA
45
20
VIN current, VREG3=No Load
EN3=FLOAT, EN5=0,
EN1=EN2=0
3.3-V only
12
VIN current, VREG5=VREG3=VREF2=No Load
EN3=EN5=FLOAT, EN1=EN2=0
IIN532(STBY) Stand-by current
100
10
150
20
IIN(SHDN)
Shut down current
VIN current, EN3=EN5=EN1=EN2=0V
VOUT and VREF2 VOLTAGES
VFB2=5V, TA= 25°C, No Load
VFB2=5V, TA= 0 to 85°C, No Load
VFB2=5V, TA= -40 to 85°C, No Load
VFB1=5V, TA= 25°C, No Load
VFB1=5V, TA= 0 to 85°C, No Load
VFB1=5V, TA= -40 to 85°C, No Load
Adjustable mode output range
Adjustable mode
3.255
3.241
3.234
4.935
4.910
4.900
1.0
3.300
3.300
3.300
5.000
5.000
5.000
3.345
3.359
3.366
5.065
5.090
5.100
5.5
VOUT
Output voltage
V
V
VADJ
Output regulation voltage
1.00
Adjustable mode, TA= 25°C
-0.9%
-1.3%
-1.6%
1.97
0.9%
1.3%
1.6%
2.03
2.04
2.05
Output regulation voltage toler-
ance
VADJ T
Adjustable mode, TA= 0 to 85°C
Adjustable mode, TA= -40 to 85°C
VVREF2
2-V output regulation voltage
I
I
I
VREF2± 50 µA, TA= 25°C
2.00
VREF2± 50 µA, TA= 0 to 85°C
VREF2± 50 µA, TA= -40 to 85°C
1.96
V
2-V output regulation voltage toler-
ance
VVREF2T
1.95
VFBx=1.02V, COMPx=open
VFBx=1.02V, COMPx=5V
VOx=0.5V, TA= 25°C
0.02
0.02
10
IVFB
VFB input current
µA
RDISCHARG Discharge switch resistance
20
Ω
4
TPS51120
www.ti.com
SLUS670A–JULY 2005–REVISED AUGUST 2005
ELECTRICAL CHARACTERISTICS (continued)
over operating free-air temperature range, VVIN = 12 V, VVREG5 = VV5FILT = 5 V (unless otherwise noted)
PARAMETER
VREG3 VOLTAGE
TEST CONDITIONS
MIN
TYP
MAX UNIT
VVREG3
VREG3 Output Regulation Voltage IVREG3 = 20 mA, 6V < VIN < 28V, TA= 25°C
IVREG3 = 1 - 50 mA , 6V < VIN < 28V, TA= 0 to 85°C
3.25
3.21
3.30
3.35
3.37
V
VVREG3T
VREG3 Output Voltage Tolerance
IVREG3 = 1 - 100 mA , 6V < VIN < 28V, TA= -40 to
3.16
3.39
85°C
(1)
IVREG3
VREG3 Output Current
TA = 25°C, VREG3=3.14V
170
mA
Rising edge of VO2, VREG3 drops to VO2 voltage
Hysteresis
2.85
3.10
3.0
V
VREG3 Bootstrap Switch
Threshold
VLDO3SW
120
1.3
mV
VREG3 Bootstrap Switch Resist-
ance
RLDO3SW
Ω
VREG5 VOLTAGE
VVREG5
VREG5 Output Regulation Voltage IVREG5 = 20 mA, 6V < VIN < 28V, TA= 25°C
4.925
4.89
5.00
5.075
5.11
VVREG5T
VREG5 Output Voltage Tolerance IVREG5 = 1 - 50 mA , 6V < VIN < 28V, TA= 0 to 85°C
V
IVREG5 = 1 - 100 mA , 6V < VIN < 28V, TA= -40 to
4.80
5.15
4.85
3.0
85°C
IVREG5
VREG5 Output Current
TA = 25°C, VREG5=4.75 V(1)
Rising edge of VO1, VREG5 drops to VO1 voltage
Hysteresis
200
mA
V
4.30
VREG5 Bootstrap Switch
Threshold
VLDO5SW
140
1.3
mV
VREG5 Bootstrap Switch Resist-
ance
RLDO5SW
Ω
TRANSCONDUCTANCE AMPLIFIER
Gm Gain
ICOMPSINK COMP Maximum Sink Current
TA = 25°C
280
12
µS
µA
VFBx=1.05V, COMPx=1.28V
8
-15
16
-7
ICOMPSRC
VCOMPHI
VCOMPLO
COMP Maximum Source Current VFBx=0.95V, COMPx=1.28V
-11
COMP High Clamp Voltage
COMP Low Clamp Voltage
CSx=0V, VFBx=0.95V
CSx=0V, VFBx=1.05V
1.26
1.08
1.34
1.12
1.42
1.20
V
OUTPUT DRIVER
Source, VVBST-DRVH = 1V
Sink, VDRVH-LL = 1V
3.5
1.5
3.5
1.5
20
60
2
7
3
7
3
RDRVH
RDRVL
TD
DRVH resistance
Ω
Source, VVREG5-DRVL = 1V
Sink, VDRVL-PGND = 1V
DRVH-off to DRVL-on, TA= 25°C
DRVL-off to DRVH-on, TA= 25°C
LL to GND(1)
DRVL resistance
Dead time
ns
V
30
VDTH
VDTL
DRVH-off threshold
DRVL-off threshold
(1)
DRVL to GND
1.1
INTERNAL BST DIODE
VFBST Forward Voltage
IRBST Reverse Current
VVREG5-VBST, IF = 10 mA, TA= 25°C
VBST = 34 V, VREG5=5V
0.7
0.8
0.1
0.1
0.9
1.0
1.0
V
µA
IBST(LEAK) VBST Leakage current
VBST=34V, LL=28V, EN3=EN5=EN1=EN2=0V
(1) Ensured by design. Not production tested.
5
TPS51120
www.ti.com
SLUS670A–JULY 2005–REVISED AUGUST 2005
ELECTRICAL CHARACTERISTICS (continued)
over operating free-air temperature range, VVIN = 12 V, VVREG5 = VV5FILT = 5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
ON-TIME TIMER, INTERNAL SOFT-START and HOUSEKEEPING CLOCK
TON1a
TON1b
TON1c
TON1d
TON2a
On time, 5V, 180 kHz
On time, 5V, 220 kHz
On time, 5V, 280 kHz
On time, 5V, 380 kHz
On time, 3.3V, 270 kHz
VLL1=12V, VOUT1=5V, TONSEL=5V, TA= 25°C
VLL1=12V, VOUT1=5V, TONSEL=FLOAT, TA= 25°C
VLL1=12V, VOUT1=5V, TONSEL=2V, TA= 25°C
VLL1=12V, VOUT1=5V, TONSEL=GND, TA= 25°C
VLL2=12V, VOUT2=3.3V, TONSEL=5V, TA= 25°C
2150
1790
1370
1020
940
2340
1950
1490
1110
1030
2530
2110
1610
1200
1120
VLL2==12V, VOUT1=3.3V, TONSEL=FLOAT, TA=
25°C
TON2b
On time, 3.3V, 330 kHz
780
850
920
ns
TON2c
On time, 3.3V, 430 kHz
On time, 3.3V, 580 kHz
Minimum on time, 5V
Minimum on time, 3.3V
Minimum off time
VLL2==12V, VOUT1=3.3V, TONSEL=2V, TA= 25°C
VLL2==12V, VOUT1=3.3V, TONSEL=GND, TA= 25°C
TA = 25°C, TONSEL=GND, VLL1=28V, VO1=1V
TA = 25°C, TONSEL=GND, VLL2=28V, VO2=1V
TA = 25°C, VFB=0.9V, LL=0.5V
580
430
650
480
70
720
530
TON2d
TON(MIN)1
TON(MIN)2
TOFF(MIN)
TSS
45
480
772
0.3
290
Internal Soft Start Timer
Internal Soft Start Slope
HK clock frequency
TA = 25°C, ENx>3V
clks
(2)
SLSS
TA = 25°C, ENx>3V, Slope wrt. VFB
V/ms
FCLK
230
0.4
350 kHz
UVLO/LOGIC THRESHOLD
EN3, EN5, low to high
Hysteresis
EN3 = FLOAT (OPEN)(2)
EN5= FLOAT (OPEN)(2)
VENx < 0.5V
0.6
0.2
1.7
3.3
1.5
4.0
200
0.8
VENLDOH
LDO enable threshold
V
VENLDOFL3 EN3 pullup voltage
VENLDOFL5 EN5 pullup voltage
IENLDOFL
EN3, EN5 pullup current
4.0
4.2
µA
Wake up
3.8
100
0
V
VUV(VREG5) VREG5 UVLO threshold
Hysteresis
300 mV
0.7
Auto-SKIP Mode Enabled
Auto-SKIP Mode Enabled, Faults Off
PWM-Only Mode Enabled
Fast Switching Frequency
Medium Switching Frequency #2
Medium Switching Frequency #1
Slow Switching Frequency
SKIPSEL, TONSEL=0V
SKIPSEL, TONSEL=5V
BJT Base input, Switcher begins to Track ENx
VSKIPSEL
SKIPSEL threshold
1.3
2.7
0
2.2
5.5
0.7
2.2
3.0
5.5
3
V
1.3
2.7
4.5
VTONSEL
TONSEL threshold
1
1
ISEL
SKIPSEL/TONSEL input current
µA
2
VENSWSTAT EN1, EN2 SS Start Voltage
VENSWEND EN1, EN2 SS End Voltage
0.5
0.9
1.2
V
‘Logic High’ Level for Switcher Enable when using
Internal Softstart, 0°C ≤ TA≤ 85°C
2.75
2
2.90
3
IENSW1,2
VTHVFB1
VTHVFB2
EN1, EN2 Pullup Current
VFB1 threshold
EN1, EN2=0.6V
1
µA
5.0V preset output
3.3V preset output
V5FILT -0.3
V5FILT -0.3
V
VFB2 threshold
CURRENT SENSE
Resistor sense scheme , VPGND - VCS voltage,
PGOOD=Hi
VOCL
Current limit threshold
67
9
80
10
93 mV
ITRIP
CS Sink Current
RDS(ON) sense scheme, PGOOD=Hi, TA= 25°C
11
µA
ppm/°
C
TCITRIP
ITRIP temperature Coefficient
RDS(ON) sense scheme, On the basis of 25°C
4500
(2) Ensured by design. Not production tested.
6
TPS51120
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SLUS670A–JULY 2005–REVISED AUGUST 2005
ELECTRICAL CHARACTERISTICS (continued)
over operating free-air temperature range, VVIN = 12 V, VVREG5 = VV5FILT = 5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
(VVREG5-CS-VPGND-LL) voltage, VVREG5-CS = 80mV,
RDS(ON) sense
VOCLoff
VR(trip)
VZC
OCP Comparator Offset
-10
0
10
Current limit threshold setting
range
VV5FILT-VCS voltage
30
-5
150 mV
5
Zero cross detection Comparator
offset
VPGNDx-VLLx voltage, SKIPSEL=0V
1
POWERGOOD COMPARATOR
Power Bad Threshold
Hysteresis
±7%
±10%
±5%
5.0
±13%
VTH(PG)
PGOOD Threshold
IPG(MAX
TPGDEL
PGOOD Sink Current
PGOOD Delay Timer
PGOOD=0.5 V
2.5
mA
Delay for PGOOD in, ‘clks’=HK Clock
256
clks
UNDERVOLTAGE and OVERVOLTAGE PROTECTION
VOVP
VFBx OVP Trip Threshold
VFBx OVP Delay Time
OVP detect
110%
65%
115%
2
120%
ms
TOVPDEL
UVP detect
Hysteresis
70%
6%
75%
VUVP
VFBx UVP Trip Threshold
TUVPDEL
VFBx UVP Delay Timer
‘clks’=HK Clock
128
clks
THERMAL SHUTDOWN
Shutdown temperature
Hysteresis
145
10
TSDN1 Thermal shutdown threshold
°C
7
TPS51120
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SLUS670A–JULY 2005–REVISED AUGUST 2005
DEVICE INFORMATION
TERMINAL FUNCTIONS
TERMINAL
I/O DESCRIPTION
NAME
COMP1
COMP2
CS1
NO.
2
O
O
I
Loop compensation pin (error amplifier output). Connect RC from this pin to GND for proper loop compensation
with current mode operation. Tie this pin to V5FILT for D-CAP™ mode operation.
7
23
18
27
14
25
16
29
12
Current sense comparator input (-) for resistor sensing scheme. Or, overcurrent trip setting input for RDS(on)
current sense scheme if connected to V5FILT through the threshold setting resistor.
CS2
I
DRVH1
DRVH2
DRVL1
DRVL2
EN1
O
O
O
O
I
High-side MOSFET gate drive output. Source 3.5 Ω, sink 1.5 Ω, LL-node referenced floating driver. Drive
voltage corresponds to VBST to LL voltage.
Rectifying (low-side) MOSFET gate drive output. Source 3.5 Ω, sink 1.5 Ω, PGND referenced driver. Drive
voltage is VREG5 voltage.
Channel 1 and Channel 2 SMPS enable pins. Connect to 5 V to turn on with internal 3-ms soft-start. Slower
soft-start is possible by applying an external capacitor from each of these pins to ground to program ramp rate.
EN2
I
VREG3, 3.3-V low dropout linear regulator enable pin. Connect to GND to disable. Float or tie to enabled
VREG5 to turn on the regulator.
EN3
EN5
10
9
I
I
VREG5, 5-V low dropout linear regulator enable pin. Connect to GND to disable. Float or tie to VBAT to turn on
the regulator.
GND
LL1
5
I
Signal ground pin.
26
15
24
I/O
I/O
High-side MOSFET gate driver return. Also serve as current sense comparator input (-) for RDS(on) sensing, and
input voltage monitor for on-time control circuitry
LL2
PGND1
I/O Ground return for rectifying MOSFET gate driver. Connect PGND2, PGND1 and GND strongly together near
the source of the rectifying FET or the GND connection of the current sense resistor. Also serve as current
PGND2
17
30
11
I/O
O
sense comparator input (+).
PGOOD1
PGOOD2
Power-good window comparator open drain output. Pull up with resistor to V5FILT or appropriate signal
voltage. Current capability is 5-mA. PGOOD goes high 1-ms after VFB is within specified limits. Power bad
(terminal goes low) is within 10 µs.
O
SKIPSEL
TONSEL
V5FILT
32
31
20
28
I
I
I
I
Skip and fault mode selection pin. Refer to Table 2
On-time selection pin. Refer to Table 1 and Table 2.
5-V supply input for the entire control circuit. Should be provided from VREG5 via RC filter.
VBST1
Supply Input for High-side MOSFET Driver. Connect capacitor from this pin to respective LL terminal. An
internal PN diode is connected between VREG5 to each of these pins. User can add external schottky diode if
forward drop is critical to drive the power MOSFET.
VBST2
13
I
VFB1
VFB2
VIN
3
6
I
I
I
I
SMPS feedback input. Connect the feedback resistor divider here for adjustable outputs. Tie these pins to
V5FILT or for fixed output option. Refer to Table 2
22
1
Supply Input for 5-V and 3.3-V linear regulator. Typically connected to VBAT.
VO1
These terminals serve four functions: on-time adjustment, output discharge, VREG5, VREG3 switchover input
and feedback inputs for 5-V, 3.3-V fixed-output option. Connect to positive terminal of respective switch mode
power supply’s output capacitor.
VO2
8
4
I
2-V reference output. Capable of ±50-µA, ±2% over 0 - 85°C temperature range. Bypass to GND by 1-nF
ceramic capacitor. Tie this pin to GND disables both SMPS.
VREF2
O
3.3-V, 100-mA low dropout linear regulator output. Bypass to PGND by 10-µF ceramic capacitor. Runs from
VREG3
VREG5
19
21
O
O
VIN supply. Shuts off with EN3. Switches over to VO2 when 3.1 V or above is provided.
5-V, 100-mA low dropout linear regulator output. Bypass to PGND by 10-µF ceramic capacitor. Runs from VIN
supply. Internally connected to VBST and DRVL. Shuts off with EN5. Switches over to VO1 when 4.8 V or
above is provided.
8
TPS51120
www.ti.com
SLUS670A–JULY 2005–REVISED AUGUST 2005
QFN PACKAGE
(BOTTOM VIEW)
1
2
3
4
5
6
7
8
SKIPSEL
TONSEL
PGOOD1
EN1
32
9
EN5
31
30
29
28
27
26
25
10
11
12
13
14
15
16
EN3
PGOOD2
EN2
VBST1
DRVH1
LL1
VBST2
DRVH2
LL2
DRVL1
DRVL2
24 23 22 21 20 19 18 17
9
TPS51120
www.ti.com
SLUS670A–JULY 2005–REVISED AUGUST 2005
BLOCK DIAGRAM (One Channel Only Shown)
10
TPS51120
www.ti.com
SLUS670A–JULY 2005–REVISED AUGUST 2005
DETAILED DESCRIPTION
PWM Operation
The switching mode power supply (SMPS) block of TPS51120 supports an adaptive on time control
pulse-width-modulation (PWM). Switching frequency is selectable from four choices for maximum efficiency
(5 V/180 kHz, 3.3 V/270 kHz), minimum component size (5 V/380 kHz, 3.3 V/580 kHz) or the other two
intermediates. The TPS51120 supports both true current mode control and D-CAP™ mode control, selectable up
to the requirements from system design. All N-channel MOSFET totem-pole architecture is employed for external
switches. The synchronous top (high-side) MOSFET is turned on, or is “SET”, at the beginning of each cycle.
This MOSFET is turned off, or is “RESET” after a constant “on-time” period which is defined by the frequency of
customer’s choice and input and output voltage ratio. The top MOSFET is turned on again if inductor current is
reduced to meet both conditions of,
1. the current level corresponds to the error amount of output voltage and,
2. below the overcurrent limit level
Repeating operation in this manner, the controller regulates the output voltage. The synchronous bottom
(low-side) or the rectifying MOSFET is turned on each cycle in the negative phase to the top MOSFET to keep
the conduction loss minimum. The rectifying MOSFET turns off on the event reverse inductor current flow is
detected. This enables seamless transition to skip mode function so that high efficiency is kept over a broad
range of load current. At the beginning of the soft start period, the rectifying MOSFET remains in the off state
until the top MOSFET is turned on for at least once.
Current Mode
The current mode scheme is a sequence of feedback control described as follows. The output voltage is
monitored at the middle point of voltage divider resistors and fed back to a transconductance amplifier. The
amplifier outputs target current level proportional to error amount between the feedback voltage and the internal
1 V reference voltage. The inductor current level is monitored during the off-cycle, when rectifying MOSFET is
turned on. The PWM comparator compares the inductor current signal with this target current level that is
indicated at the COMP pin voltage. When both signals are equal (at the valley of the current sense signal), the
comparator provides the “SET” signal to the gate driver latch. The current mode option has relatively higher
flexibility by the external compensation network provided to the COMP pin. And it is suitable for lowest ripple
design with output capacitor(s) having ultra-low ESR. More detail information about loop compensation and
parameter design can be found in the Loop Compensation and External Parts section. When sensing the
inductor current, accuracy and cost always trades off. In order to give the circuit designer a choice between
these two, TPS51120 supports both of external resistor sensing and MOSFET RDS(on) sensing. Please contact
factory for current mode EVM with RSENSE capability.
D-CAP™ Mode
The D-CAP™ mode operation is enabled by tying the COMP pin to V5FILT. In this mode, the PWM comparator
monitors the feedback voltage directly and compares the voltage with the internal 1-V reference. When both
signals are equal at the valley of the voltage sense signal, the comparator provides the “SET” signal to the top
MOSFET gate driver. Because the compensation network is implemented on the part and the output waveform
itself is used as the error signal, external circuit design is largely simplified. Another advantage of the D-CAP™
mode is its inherent fast transient response. A trade-off is a sufficient amount of ESR required in the output
capacitor. SPCAP or POSCAP is recommended. The inductor current information is still used in the D-CAP™
mode for over current protection and light load operation. Do NOT neglect current sensing design in this mode.
To summarize, the D-CAP™ mode is suitable for the lowest external component count with the fastest transient
response, but with relatively large ripple voltage. It is easy to design the loop once appropriate output capacitor
and inductor current ripple is selected. Please refer to loop compensation and parameter design in the Loop
Compensation and External Parts section for more information.
11
TPS51120
www.ti.com
SLUS670A–JULY 2005–REVISED AUGUST 2005
DETAILED DESCRIPTION (continued)
Adaptive On-Time Control
The TPS51120 employs adaptive on time control scheme and does not have a dedicated oscillator on board.
However, it works almost constant frequency over the entire input voltage range (pseudo-constant frequency) by
feed-forwarding the input and output voltage into the on-time one-shot timer. The on-time is controlled inverse
proportional to the input voltage and proportional to the output voltage so that the duty ratio is kept as VOUT/VIN
technically with the same cycle time. The input voltage monitoring is accomplished through sensing the LL node,
not at VIN node, during the ‘ON’ state. This eliminates the influence of the voltage drop across the top MOSFET
to the frequency especially in heavy load condition. The VIN pin is not used for the on-time control but used only
for the 5 V and 3.3 V regulators’ supply. The switching frequency is selectable from four combinations shown in
the table below by setting TONSEL pin voltage. This allows the system design to pursue highest efficiency (5
V/180 kHz, 3.3 V/270 kHz), smallest components size (5 V/380 kHz, 3.3 V/580 kHz) or a good balance of both in
the medium. Also shown in the table are the typical on-time for each frequency and 5 V, 3.3 V outputs at
VIN=12. Output voltage feed-forward is enabled after the output voltage exceeds 1.0 V in order to achieve stable
start up.
Table 1. Frequency Selection and Typical On-Time
TONSEL CONNECTION
CH1(LL1=VIN=12 V)
CH2 (LL2=VIN=12 V)
FREQUENCY (kHz)
ON-TIME @ 5 V (ns)
FREQUENCY (kHz)
ON-TIME @ 3.3 V (ns)
V5FILT
FLOAT (OPEN)
VREF2
180
220
280
380
2340
1950
1490
1111
270
330
430
580
1030
850
650
480
GND
Programming Table
The TPS51120 has varieties of configurations choice. It is important to tailor appropriately with regard to the
system design requirements. Table below shows programming table for the control scheme selection, frequency
selection, output voltage selection and skip selection. Faults-off disables UVP, OVP and UVLO. This is mainly
intended for debugging purpose. Enable states and possible connections for the LDO’s EN3, EN5 pins and
SMPS’s EN1, EN2 pins are also shown.
Table 2. Function Programming Table
PIN
GND
VREF2
FLOAT
V5FILT
COMP
N/A
N/A
Current Mode
(apply R-C network)
D-CAP™ Mode
TONSEL (CH1/CH2) [kHz]
VFB1
380 / 580
280 / 430
220 / 330
180 / 270
5V fixed output
3.3 V fixed output
PWM
Adjustable output (connect to the resistor divider)
Adjustable output (connect to the resistor divider)
VFB2
SKIPSEL
AUTO-SKIP
Switcher Off
LDO Off
AUTO-SKIP (FAULTS OFF)
Not used
PWM
Switcher on
LDO on
EN1, EN2
Switcher on
EN3, EN5
Not used
LDO on (EN3 only)
12
TPS51120
www.ti.com
SLUS670A–JULY 2005–REVISED AUGUST 2005
DETAILED DESCRIPTION (continued)
Light Load Operation
TPS51120 automatically reduces switching frequency at light load condition to maintain high efficiency. This
reduction of frequency is achieved smoothly and without an increase in load regulation. Detail operation is
described as follows. As the output current decreases from heavy load condition, the inductor current is also
reduced and eventually comes to the point that its ‘valley’ touches zero current, which is the boundary between
continuous conduction and discontinuous conduction modes. The rectifying MOSFET is turned off when this zero
inductor current is detected. The on-time is kept the same as that in the heavy load condition. As the load current
further decreases, the converter runs in discontinuous conduction mode and it takes longer and longer to
discharge the output capacitor to the level that requires next ‘ON’ cycle. This results in reducing the switching
frequency. In reverse, when the output current increases from light load to heavy load, switching frequency
increases to the constant predetermined frequency as the inductor current reaches to the continuous conduction.
The transition load point to the light load operation IOUT(LL) (i.e. the threshold between continuous and
discontinuous conduction mode) can be calculated as shown in Equation 1.
ǒV
Ǔ
V
* V
IN
OUT
OUT
1
I
+
OUT(LL)
2 L f
V
IN
(1)
where f is the PWM switching frequency which is determined by TONSEL pin. Switching frequency versus output
current in the light load condition is a function of L, f, VIN and VOUT, but it decreases almost proportional to the
output current from the IOUT(LL) given in Equation 1.
Forced PWM Operation
Tying SKIPSEL to V5FILT or leaving it float force the part to operate in continuous conduction mode for entire
load range by disabling zero inductor current detection. Switching frequency is kept at the frequency selected by
TONSEL input. System designers may want to use this mode to avoid certain frequency in light load condition
with the cost of low efficiency. However, please be aware the output has a capability to both sink and source
current in this mode. If the output terminal is connected to a voltage source higher than the regulated voltage, the
converter sinks current from the output and boosts the charge into the input capacitor. This may cause
unexpected high voltage at VIN and may damage the part.
5V, 100 mA, LDO and Switchover (VREG5)
A 5-V, 100-mA linear regulator is integrated in the TPS51120. This low drop-out (LDO) regulator services the
main analog supply rail for the IC and provides the current for the gate drivers. The regulator is a PMOS type
with transconductance control and the pole is determined by the value of output capacitance. Typically, the value
of this capacitor must be greater than 4.7 µF. A 10-µF ceramic capacitor is recommended for a typical design.
Current limit and thermal protection are included in the regulator. Additionally, if the VO1 voltage exceeds 4.8 V,
then the regulator is switched off and the 5V rails are bootstrapped to the 5-V switcher output, improving the
efficiency of the converter. A glitch-free switchover is accomplished. The VREG5 output voltage does not show a
short “glitch” down to 4.8 V when this bootstrapping action is taken. The switchover impedance from VO1 to
VREG5 is typically 1.3 Ω. Standby current is designed for 30-µA operation allowing the user to leave the
regulator alive while maintaining maximum battery life. The EN5 pin is a high voltage input and can be tied to
VBAT or left open to enable the 5-V regulator. This 5-V regulator must be enabled prior to enable switching
regulators. Pull EN5 to ground to shut off the regulator. Disabling the regulator does not promise shutting down
the switchers once 5 volts is supplied via the bootstrap path. Because switchover occurs, the 5-V switcher MUST
be turned off with the LDO in order to shut down the device. EN5 does NOT function as a master disable.
3.3V, 100 mA, LDO and Switchover (VREG3)
A 3.3-V, 100-mA linear regulator is integrated as a second regulator in the TPS51120. This LDO provides a
handy standby supply for 3.3 V ‘Always On’ voltages in the notebook system. The characteristics of this LDO are
identical to the 5V LDO except for the switchover voltage. Apply 10-µF ceramic capacitor from VREG3 to PGND
in adjacent to the device. If the VO2 voltage exceeds 3.1 V, then this regulator is switched off and the 3.3 V rail
is bootstrapped to the 3.3 V switcher. Note if the VO2 voltage is set higher by external feedback dividers, for
example 5 V, that high voltage is presented at VREG3 after switchover. The EN3 pin is a low voltage input that
can be tied to V5FILT or left open to enable the 3.3-V regulator. This 3.3-V regulator can be turned on or kept
alive independent to the 5-V regulator.
13
TPS51120
www.ti.com
SLUS670A–JULY 2005–REVISED AUGUST 2005
DETAILED DESCRIPTION (continued)
2V, 50 µA Sink/Source Reference (VREF2)
This is a handy reference for generating auxiliary voltages. The tolerance is ±2% over 50-µA load and 0°C to
85°C ambient temperature ranges. The four-state logic (SKIPSEL, TONSEL) takes advantage of this reference
for additional selection modes. This reference is enabled when both EN3 and EN5 become high, shuts down
after both switchers are turned off and VREG5 or VREG3 is shut down. Please refer to Table 4. If this output is
forcibly tied down to ground, both SMPS are turned off without latch. Bypass VREF2 pin to GND by a 1-nF
capacitor.
Low-Side Driver
The low-side gate driver, DRVL, is designed to drive high current low RDS(on) N-channel MOSFET(s). The
maximum drive voltage is 5.5 V which is delivered from VREF5 pin. The instantaneous drive current is supplied
from the output capacitor at the VREF5 pin. The average drive current is equal to the FET’s gate charge at
VGS=5 V times switching frequency. The VREG5 pin voltage may contain high frequency noise due to parasitic
inductance by wiring and pointing current flow into the gate capacitor. The drive capability is represented by its
internal resistance, which are 3.5 Ω for VREG5 to DRVL and 1.5 Ω for DRVL to PGND. Adaptive dead time
control generates delay times between top MOSFET off to bottom MOSFET on, and bottom MOSFET off to top
MOSFET on, preventing the totem-pole switches to shoot through. Top MOSFET off is detected as LL-node
voltage declining below 2 V. Bottom MOSFET off is detected as DRVL voltage become 1.1 V.
High-Side Driver
The high-side gate driver, DRVH, is designed to drive high current, low RDS(on) N-channel MOSFET(s). When
configured as a LL-node referenced floating driver, connect 0.1-µF ceramic capacitor between corresponding
VBST pin and LL pin. A 5-V bias voltage is delivered from VREG5 supply. VBST is internally connected to
VREG5 through a high voltage PN diode. This internal diode provides sufficient gate voltage for ordinary 4.5-V
drive power MOSFETs and helps reducing external component. However, in the case where the gate bias
voltage is critical for driving the top MOSFET, application designer may add an external schottky diode from
VREG5 pin to VBST pin. Note schottky diodes have quite high reverse leakage current at high temperature. The
instantaneous drive current is supplied by the flying capacitor connected between VBST and LL pins. The
average drive current is equal to the gate charge at VGS=5 V times switching frequency. The drive capability is
represented by its internal resistance, which are 3.5-Ω for VBST to DRVH and 1.5Ω for DRVH to LL. The
maximum recommended voltage that can be applied between DRVH pin and LL pin is 5.5 V, DRVH pin to PGND
pin is 34 V.
Soft-Start
The TPS51120 has an internal 3-ms voltage-servo soft start for each channel. When the EN1 or EN2 pin
exceeds 0.9 V, an internal DAC begins ramping up the reference voltage. Smooth control of the output voltage
during start up is maintained. However, if a slower soft-start is required, an external capacitor may be tied from
the EN1 or EN2 pin to GND. In this case, the TPS51120 charges the external capacitor with the integrated 2-µA
current source. The lower of either the EN voltage slew rate or the internal soft start slew rate dominates the
start-up ramp. In addition, if tracking discharge is required, the EN pin can be used to control the output voltage
discharge smoothly. An approximate value for the soft start reference voltage as a function of EN voltage is
VSSREF = (VENX– 0.9)/1.5 < 1 V. At the beginning of soft-start period, the rectifying MOSFET maintains an off
state until the top MOSFET is turned on for at least once. This prevents high negative current to flow back from
the output capacitor in the event of output capacitor pre-charged condition.
Soft-Stop
Discharge mode or ‘Soft Stop’ is always on during Faults or Disable. In this mode, an event that would cause the
switcher to be turned off (EN1 or EN2 low, OVP, UVP, UVLO) causes the output to be discharged through 10-Ω
transistor inside the VO terminal. The external rectifying MOSFET is not turned on for the soft off operation to
avoid a chance to cause negative voltage at the output. Soft-stop time constant is a function of the output
capacitance and the resistance of the discharge transistor. This discharge ensures that, upon restart, the
regulated voltage always starts from zero volts. In case a SMPS is restarted before discharge completion,
soft-stop is terminated and the switching resumes after the reference level comes back to the remaining output
voltage.
14
TPS51120
www.ti.com
SLUS670A–JULY 2005–REVISED AUGUST 2005
DETAILED DESCRIPTION (continued)
Powergood
The TPS51120 has dedicated powergood output for each SMPS, PGOOD1 and PGOOD2. The PGOOD
monitors are open drain 5-mA pull down outputs. These outputs are low on startup and stay low until the switcher
feedback voltages are within a specified range for 256 clocks or approximately 1 ms. If the VFB pin falls outside
the 10% tolerance band, the respective PGOOD pin goes low within microseconds. Then if the VFB pin comes
back within 5% of target (1 V) for greater than 1 ms, then the respective PGOOD pin goes high again. The
PGOOD pin should be typically pulled up through a 100 kΩ or greater value resistor to the V5FILT pin. Both
PGOOD pins go low during fault conditions (Thermal Shutdown, UVLO, UVP, OVP) and Disable.
Current Sensing and Overcurrent Protection
The SMPS has cycle-by-cycle over current limiting. The inductor current is monitored during the rectifying
MOSFET is on and the controller does not allow the next ON cycle while the current level is above the trip
threshold. In order to provide good accuracy and cost effective solution, TPS51120 supports both of external
resistor sensing and MOSFET RDS(on) sensing which are selected by CS terminal connection. For resistor
sensing scheme, an appropriate current sensing resistor should be connected between the source terminal of the
bottom MOSFET and PGND. CS pin is connected to the bottom MOSFET source terminal node. The inductor
current is monitored by the voltage between PGND pin and CS pin. In this scheme, the trip level is fixed value of
80 mV. For RDS(on) sensing scheme, CS terminal is connected to V5FILT through a trip voltage setting resistor
RTRIP. In this scheme, CS terminal sinks 10-µA ITRIP current and the trip level is set to the voltage across the
RTRIP. The trip level should be in the range of 30 mV to 150 mV. This allows designer to select a variety of
MOSFETs for the bottom arm. The inductor current is monitored by the voltage between PGND pin and LL pin so
that LL pin should be connected to the drain terminal of the bottom MOSFET. ITRIP has 4500ppm/°C temperature
slope, with respect to its 25°C value, to compensate the temperature dependency of the RDS(on). In either
scheme, PGND is used as the positive current sensing node so that PGND pin should be connected to the
proper current sensing device, i.e. the sense resistor or the source terminal of the bottom MOSFET. In an
overcurrent condition, since the current to the output capacitor is limited while the load drags more, the output
voltage tends to go down. It ends up with passing into the undervoltage protection and latches off as both DRVH
and DRVL are at low level.
Table 3. Current Sensing Connection
CS
Threshold
Temperature
Coefficient (ppm/°C)
RDS(on) sensing
RSENSE sensing
V5FILT
I
TRIP× RTRIP / RDS(on)
4500
none
Bottom FET source node (=RSENSE (-) node)
80 mV / RSENSE
Overvoltage Protection
For over voltage protection (OVP), the TPS51120 monitors VFB voltage. When the VFB voltage is higher than
115% of the target, the OVP comparator output goes high and the circuit latches both switchers. The offending
channel is latched DRVH low and DRVL high, the other channel is simply latched as DRVH and DRVL at low. Be
aware negative voltage may appear at the output terminal of the offending channel because of LC resonant
configured by the power inductor and the output capacitor. The system designer is responsible to this negative
voltage if any protection is need. The OVP propagation delay is less than 3 µs.
Undervoltage Protection
For under voltage protection (UVP), the TPS51120 monitors VFB voltage. When the VFB voltage is lower than
70% of the target and the UVP comparator output goes high, the internal UVP delay counter begins count. After
the 128 clocks, approximately 0.5 ms, TPS51120 latches off both channels as DRVH and DRVL at low. This
function is enabled after the softstart reference has exceeded the internal 1-V reference operation to ensure
startup. Please refer to Table 5.
15
TPS51120
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SLUS670A–JULY 2005–REVISED AUGUST 2005
DETAILED DESCRIPTION (continued)
5V Supply and UVLO Protection
TPS51120 has two 5-V terminals. VREG5 is the output of 5-V linear regulator. This terminal also serves as input
pin for the gate driver circuits. Internal switchover FET is connected between this pin and VO1. V5FILT is the VCC
supply input for the control circuitry on the chip. Connect with R-C low pass filter from VREG5 to this V5FILT to
eliminate spiky high frequency noise. State definition pins such as SKIPSEL, TONSEL, VFB (fixed output case)
and COMP (for D-CAP mode) or CS resistors that need stable 5V should refer to V5FILT. The part has 5-V
supply under voltage lock out protection (UVLO) to prevent unpredictable operation under insufficient power. The
TPS51120 monitors VREG5 voltage. When the VREG5 voltage is lower than UVLO threshold, the SMPS’s are
shut off. The output discharge or ‘soft stop’ feature is enabled for the channel one and channel two. However,
because the discharge circuit derives its power from the 5-V line, power must be presented long enough to
ensure that discharge is complete during shutdown. Also, during power up, the TPS51120 attempts to discharge
the output capacitor until the UVLO (on) threshold is reached. A 5-V UVLO is non-latch protection and is
automatically resumed up on 5-V recovery.
VIN Line Sag protection (Dynamic UVP)
Since the TPS51120 serves primarily as system power (i.e. used for generating 3.3 V and 5 V) it is very
important that the system not enter UVP if the VIN supply has dropped below 6V. UVP would be caused by the
5-V output dropping due to input line sag. When the VIN pin drops below the 5-V regulator voltage, the 5-V
regulator ‘tracks’ VIN (LDO operation). The UVP threshold is adjusted downward when the VREG5 is below
4.8 V. This ensures that 5-V supply UVLO trips before the latching UVP condition occurs and the system power
can recover normally when VIN recovers. This feature is very useful for transient VIN events such as adapter
insertion
Thermal Shutdown
The TPS51120 employs thermal shutdown for the switchers at 145°C. This is a non-latch protection with
hysteresis of 10°C. Both switching regulators and both internal regulators stop. VREG5 and VREG3 LDOs may
not turn on if the part is preheated above the recovery temperature before starting up. Reduce the temperature to
or below TA = 85°C to resume operation safely.
Table 4. Enable Logic States (VOUT1=5 V, VOUT2=3.3 V)
EN5(1)
Low
EN3
Low
EN1
High or Low
High or Low
High or Low
Low
EN2
High or Low
High or Low
High or Low
Low
VREG5
Off
VREG3
Off
VREF2(2)
SMPS1
Off
SMPS2
Off
Off
Low-to-High
Low
Low
LDO 5 V
Off
Off
Off
Off
Off
Low-to-High
Low-to-High
High
LDO 3.3 V
LDO 3.3 V
SW 3.3 V
LDO 3.3 V
SW 3.3 V
SW 3.3 V
LDO 3.3 V
LDO 3.3 V
Off
Off
Off
Off
Low-to-High
High
LDO 5 V
LDO 5 V
SW 5 V
SW 5 V
SW 5 V
LDO 5 V
Off
On
Off
Off
Low
Low-to-High
Low
On
Off
On
High
High
Low-to-High
High
On
On
Off
High
High
High
On
On
On
High-to-Low
High
High-to-Low
High
High
High
On
On
On
High-to-Low
High-to-Low
High
High-to-Low
High
On
Off
Off
High-to-Low
High
High
Off
Off
Off
High-to-Low
High-to-Low
High
High-to-Low
High-to-Low
Low
SW 5 V
LDO 5 V
Off
On
On
Off
High
Low
Off
Off
Off
Off
High-to-Low
High
Low
LDO 3.3 V
Off
Off
Off
Off
High-to-Low
Low
Low
LDO 5 V
Off
Off
Off
(1) Because of Switch-over, the 5-V switcher MUST be turned off with the LDO in order to shut down the device. EN5 does NOT function as
a master DISABLE.
(2) Forcing VREF2 output to ground disables SMPS1 and SMPS2 without latch.
16
TPS51120
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SLUS670A–JULY 2005–REVISED AUGUST 2005
DETAILED DESCRIPTION (continued)
Table 5. Protection States (VOUT1 = 5 V, VOUT2 = 3.3 V)
DRVH1
DRVL1
DRVH2
DRVL2
PGOOD1
PGOOD2
VREG5
VREG3
VREF2
FOR
RESTART
UVPch1
UVPch2
Low
Low
Low
Low
Low
Low
Low
High
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
High
Low
Low/Low
Low/Low
Low/Low
Low/Low
Low/Low
LDO 5 V LDO 3.3 V
LDO 5 V LDO 3.3 V
LDO 5 V LDO 3.3 V
LDO 5 V LDO 3.3 V
On
On
On
On
Off
Toggle EN1
Toggle EN2
Toggle EN1
Toggle EN2
OVPch1
OVPch1
Thermal SHDN
Off
Off
Lower Package
Temperature
VIN < 5.0
Normal
Low
Normal
Low
Normal
Low
Normal
Low
Low/Normal
Low/Low
SW 5 V
SW 3.3 V
On
On
Raise VIN
VREG
UVLO
LDO but LDO 3.3 V
dropping
Raise VIN, Re-
duce 5V current
OCPch1
OCPch2
EN1 Low
EN2 Low
Limited
Duty
Estended
Duty
Normal
Normal
Low/Normal
Normal/Low
Low/Normal
Normal/Low
Low/Low
LDO 5 V
SW 5 V
LDO 5 V
SW 5 V
LDO 5 V
SW 3.3 V
LDO 3.3 V
SW 3.3 V
LDO 3.3 V
Off
On
On
On
On
Off
Reduce CH1
Current
Normal
Normal
Limited
Duty
Estended
Duty
Reduce CH2
Current
Low
Low
Normal
Normal
Float or tie to
VREG5
Normal
Low
Normal
Low
Low
Low
Float or tie to
VREG5
EN1, EN2, EN3
Low
Low
Low
Float EN3, then
float EN1,2 or
tie to VREG5
EN5, EN1 Low
Low
Low
Low
Low
Low/Low
Off
LDO 3.3 V
Off
Float EN5 or tie
to VBAT, tie
EN1 to VREG5
Loop Compensation and External Parts Selection
Current Mode Operation
A buck converter using TPS51120 current mode operation can be partitioned into three portions, a voltage
divider, an error amplifier and a switching modulator. By linearizing the s witching modulator, we can derive the
transfer function of the whole system. Since current mode scheme directly controls the inductor current, the
modulator can be linearized as shown in Figure 1.
Figure 1. Linearizing the Modulator
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Here, the inductor is located inside the local feedback loop and its inductance does not appear in the small signal
model. As a result, a modulated current source including the power inductor can be modeled as a current source
with its transconductance of 1/RS and the output capacitor represent the modulator portion. This simplified model
is applicable in the frequency space up to approximately a half of the switching frequency. One note is, although
the inductance has no influence to small signal model, it has influence to the large signal model as it limits slew
rate of the current source. This means the buck converter’s load transient response, one of the large signal
behaviors, can be improved by using smaller inductance without affecting the loop stability.
Total open loop transfer function of the whole system is given by Equation 2.
H(s) + H (s) H (s) H (s)
1
2
3
(2)
Assuming RL>>ESR, RO>>RC and CC>>CC2, each transfer function of three block is shown in Equation 3
through Equation 5.
R
2
H (s) +
1
ǒ
1Ǔ
R ) R
2
(3)
O ǒ1 ) s C RCǓ
R
C
H (s) + * Gm
2
ǒ1 ) s C R Ǔ ǒ1 ) s C
R
C2
CǓ
C
O
(4)
(5)
(1 ) s C ESR)
O
RL
H (s) +
3
R
ǒ1 ) s C RLǓ
S
O
There are three poles and two zeros in H(s). Each pole and zero is given by Equation 6 through Equation 10.
1
w
+ ǒC ROǓ
P1
C
(6)
(7)
1
w
+ ǒC RLǓ
P2
O
1
R
w
+ ǒC
CǓ
P3
C2
(8)
1
w
w
+ ǒC RCǓ
Z1
Z2
C
(9)
1
+ ǒC ESRǓ
O
(10)
Usually, each frequency of those poles and zeros is lower than the 0 dB frequency, f0. However, the f0 should be
kept under 1/3 of the switching frequency to avoid effect of switching circuit delay. The f0 is given by next
equation Equation 11.
R
R
Gm
C
S
1.0
Gm
C
S
1
2p
R2
R1 ) R2
1
2p
f +
+
0
C
R
V
C
R
O
OUT
O
(11)
Based on small signal analysis above, the external components can be selected by following manner.
1. Choose the inductor.The inductance value should be determined to give the ripple current of approximately
1/4 to 1/2 of maximum output current.
ǒV
Ǔ
ǒV
Ǔ
* V
V
* V
V
IN(max)
OUT
OUT
IN(max)
OUT OUT
1
2
L +
+
I
f
V
I
f
V
IND(ripple)
IN(max)
OUT(max)
IN(max)
(12)
The inductor also needs to have low DCR to achieve good efficiency, as well as enough room above peak
inductor current before saturation. The peak inductor current can be estimated in Equation 13.
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ǒV
Ǔ
* V
V
OUT
V
IN(max)
OUT
TRIP
1
I
+
)
IND(peak)
R
L f
V
DS(on)
IN(max)
(13)
2. Choose rectifying (bottom) MOSFET. When RDS(on) sensing scheme is selected, the rectifying MOSFET’s
on-resistance is used as this RS so that lower RDS(on) does not always promise better performance. In order
to clearly detect inductor current, minimum RS recommended is to give 15 mV or larger ripple voltage with
the inductor ripple current. This promises smooth transition from CCM to DCM or vice versa. Upper side of
the RDS(on) is of course restricted by the efficiency requirement, and usually this resistance affects efficiency
more at high load conditions. When using external resistor current sensing, there is no restriction for low
RDS(on). However, the current sensing resistance RS itself affects the efficiency.
3. Choose output capacitor(s). If organic semiconductor capacitors (OS-CON) or specialty polymer capacitors
(SP-CAP), are used, the ESR to achieve required ripple value at a stable state or transient load condition
determines the amount of capacitor(s) need, and capacitance is then enough to satisfy stable operation. The
peak-to-peak ripple value can be estimated by ESR times the inductor ripple current for stable state, or ESR
times the load current step for a fast transient load response. In case of ceramic capacitor(s), usually ESR is
small enough to meet ripple requirement. On the other hand, transient undershoot and overshoot driven by
output capacitance becomes the key factor to determine the capacitor(s).
4. Determine f0 and calculate RC using Equation 14. Note that higher RC shows faster transient response in
cost of unstableness. If the transient response is not enough even with high RC value, try increasing the
output capacitance. Recommended f0 is f/4.
C
O
R
v 2p f V
R
S
0
C
OUT
Gm
5. Calculate CC2. The purpose of this capacitance is to cancel the zero caused by ESR of the output capacitor.
If ceramic capacitor are used, there is no need for CC2
(14)
.
1
1
R
w
+ w
p3
+ ǒC
Ǔ
+ ǒC
CǓ
z2
ESR
O
C2
(15)
C
ESR
O
C
+
C2
R
C
(16)
6. Calculate CC. Purpose of CC is to cut DC component to obtain high DC feedback gain. However, as it
causes phase delay, another zero to cancel this effect at f0 frequency is need. This zero, ωz1, is determined
by CC and RC. Recommended ωz1 is 10 times lower to the f0 frequency.
f
10
0
1
f
+
+
z1
2p C R
C
C
(17)
7. In case of adjustable mode, determine the value of R1 and R2. Recommended R2 value is from 10 kΩ to
20 kΩ. Determine R1 using Equation 18.
R + ǒV * 1.0Ǔ R
1
2
OUT
(18)
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D-CAP™ Mode Operation
A buck converter system using D-CAP™ mode can be simplified as shown in Figure 2.
Figure 2. Linearizing the Modulator
The VO voltage is compare with internal reference voltage after divider resistors (Internal resistor mode. For
adjustable mode, the comparison is directly at VFB). The PWM comparator determines the timing to turn on top
MOSFET. The gain and speed of the comparator is high enough to keep the voltage at the beginning of each on
cycle (or the end of off cycle) substantially constant. The DC output voltage may have line regulation due to
ripple amplitude that slightly increases as the input voltage increase.
For the loop stability, the 0-dB frequency, f0, defined below need to be lower than 1/3 of the switching frequency.
f
SW
3
1
f +
v
0
2p ESR C
O
(19)
As f0 is determined solely by the output capacitor’s characteristics, loop stability of D-CAP™ mode is determined
by the capacitor’s chemistry. For example, specialty polymer capacitors (SP-CAP) have Co in the order of
several 100 µF and ESR in range of 10 mΩ. These produce an f0 in the order of 100 kHz or less and the loop is
stable. However, ceramic capacitors have f0 at more than 700 kHz, which is not suitable for this operational
mode.
Although D-CAP™ mode provides many advantages such as ease-of-use, minimum external components
configuration and extremely short response time, due to not employing an error amplifier in the loop, sufficient
amount of feedback signal needs to be provided by external circuit to reduce jitter level. The required signal level
is approximately 15 mV at comparing point, either the internal or external VFB voltages. The output capacitor’s
ESR should meet this requirement.
The external components selection is much simple in D-CAP™ mode.
1. Choose inductor based on frequency and acceptable ripple current.
2. Choose output capacitor(s).Organic semiconductor capacitor(s) or specialty polymer capacitor(s) are
recommended. Determine ESR to meet required ripple voltage above. A quick approximation is shown in
Equation 20.
V
0.015
OUT
I
ESR +
RIPPLE
(20)
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Layout Considerations
Certain points must be considered before starting a layout work using the TPS51120.
•
•
•
Connect RC low-pass filter from VREG5 to V5FILT, 1 µF and 5.1 Ω are recommended. Place the filter
capacitor close to the device, within 12 mm (0.5 inches) if possible.
VREG5 and VREG3 require at least 4.7 µF, VREF2 requires a 1-nF ceramic bypass capacitor which should
be placed close to the device and traces should be no longer than 10 mm.
Connect the overcurrent setting resistors from CSx to V5FILT (NOT VREG5) and close to the device, right
next to the device if possible. The trace from CSx to V5FILT should avoid coupling to high-voltage switching
node.
•
In the case of using adjustable output voltage with an external resistor divider, the discharge path (VOx)
should have a dedicated trace to the output capacitor; separate from the output voltage sensing trace, and
use 1.5 mm or wider trace with no loops. Make the feedback current setting resistor (the resistor between
VFBx to GND) is tied close to the device’s GND. Place on the component side and avoid vias between this
resistor and the device.
•
•
Connections from the drivers to the respective gate of the high-side or the low-side MOSFET should be as
short as possible to reduce stray inductance. Use 0.65 mm (25 mils) or wider trace.
All sensitive analog traces and components such as VOx, COMPx, VFBx, VREF2, GND, ENx, PGOODx,
CSx, V5FILT, TONSEL and SKIPSEL should be placed away from high-voltage switching nodes such as
LLx, DRVLx or DRVHx nodes to avoid coupling. Use internal layer(s) as ground plane(s) and shield feedback
trace from power traces and components.
•
•
Gather ground terminal of VIN capacitor(s), VOUT capacitor(s) and source of low-side MOSFETs as close as
possible. GND (signal ground) and PGNDx (power ground) should be connected strongly together near the
device. PCB trace defined as LLx node, which connects to source of high-side MOSFET, drain of low-side
MOSFET and high-voltage side of the inductor, should be as short and wide as possible.
In order to effectively remove heat from the package, prepare thermal land and solder to the package’s
thermal pad. Three by three or more vias with a 0.33-mm (13mils) diameter connected from the thermal land
to the internal ground plane should be used to help dissipation. Do NOT connect PGNDx to this thermal land
underneath the package.
V5FILT
C31
1 nF
R11
100 kΩ
R21
100 kΩ
GND
8
7
6
5
4
3
2
1
EN_LDO5
P_GOOD2
9
32
SKIPSEL
P_GOOD1
EN5
GND
10 EN3
TONSEL 31
PGOOD1 30
EN1 29
EN_LDO3
VBAT
VBAT
11 PGOOD2
12 EN2
TPS51120RHB
(QFN−32)
EN_2
EN_1
C10
20 µF
C10
20 µF
13 VBST2
14 DRVH2
15 LL2
VBST1 28
DRVH1 27
LL1 26
C11
0.1 µF
Q3
Q1
IRF7821
C21
0.1 µF
IRF7821
L1
4.7 µH
L2
2.2 µH
VO2
3.3V/6A
VO1
5V/6A
+
+
C2A
150 µF
PowerPAD
C2B
150 µF
C1A
150 µF
C1B
150 µF
Q4
IRF7832
Q2
IRF7832
DRVL1
25
DRVL2
16
17
18
19
20
21
22
23
24
VO1_GND
−
VO2_GND
−
PGND1
R22
3.3 kΩ
R50
5.1
PGND2
R12
3.6 kΩ
W
VBAT
C30
NA
C30
10 µF
C51
1 µF
C50
10 µF
UDG−05074
Figure 3. D-CAP™ Mode, Fixed 5-V/6-A, +3.3-V/6-A, RDS(on) Sensing
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SLUS670A–JULY 2005–REVISED AUGUST 2005
C23
180 pF
C13
220 pF
R24
15 kΩ
C22
1 nF
C12
2.2 nF
R14
11 kΩ
R15
26.7 kΩ
R25
16.5 kΩ
R24
33 kΩ
R14
33 kΩ
C31
1 nF
GND
8
7
6
5
4
3
2
1
GND
V5FILT
EN_LDO5
R21
V5FILT
9
32
SKIPSEL
EN5
R11
12 mΩ
EN_LDO3
10 EN3
TONSEL 31
PGOOD1 30
EN1 29
100 kΩ
PowerPad
GND
P_GOOD2
11 PGOOD2
12 EN2
P_GOOD1
VBAT
EN_2
EN_1
TPS51120RHB
(QFN32)
VBAT
VBST2
VBST1 28
DRVH1 27
LL1 26
13
Q3
IRF7821
C21
0.1 µF
Q1
IRF7821
C11
0.1 µF
L2
1.2 µH
L1
2.2 µH
14 DRVH2
15 LL2
VO2
1.5 V/6 A
VO1
+
+
1.8 V/6 A
Q4
20 µF
Q2
IRF7832
IRF7832
DRVL2
16
DRVL1
25
20 µF
C1B
EEFUE0E221R
17
18
19 20
21 22
23
24
C2A
EEFUE0E221R
C2B
EEFUE0E221R
R50
5.1 Ω
VBAT
R10
12 mΩ
R20
12 mΩ
C30
10 µF
VO2_GND
−
−
VO1_GND
C50
10 µF
C51
1 µF
C1A
EEFUE0E221R
PGND2
PGND1
UDG−05077
Figure 4. Current Mode, External 1.8-V/6-A, +1.5-V/6-A, RSENSE Sensing
TYPICAL CHARACTERISTICS
VIN SUPPLY CURRENT
vs
JUNCTION TEMPERATURE
VIN SUPPLY CURRENT
vs
INPUT VOLTAGE
900
800
700
600
900
800
700
600
I = Current Mode
INCAP
I = Current Mode
INCAP
500
400
300
500
400
300
I = D−CAP Mode
INNOCAP
I = D−CAP Mode
INNOCAP
200
100
0
200
100
0
−50
5
10
15
20
25
0
50
100
150
T
J
− Junction Temperature − °C
V
IN
− VIN Input Voltage − V
Figure 5.
Figure 6.
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SLUS670A–JULY 2005–REVISED AUGUST 2005
TYPICAL CHARACTERISTICS (continued)
VIN STANDBY CURRENT
vs
JUNCTION TEMPERATURE
VIN STANDBY CURRENT
vs
INPUT VOLTAGE
140
140
120
100
120
100
80
80
60
40
60
40
20
0
20
0
−50
0
50
100
150
5
10
15
20
25
T
J
− Junction Temperature − °C
V
IN
− VIN Input Voltage − V
Figure 7.
Figure 8.
VIN SHUTDOWN CURRENT
vs
JUNCTION TEMPERATURE
VIN SHUTDOWN CURRENT
vs
INPUT VOLTAGE
20
18
20
18
16
14
16
14
12
10
8
12
10
8
6
4
6
4
2
0
2
0
−50
0
50
100
150
5
10
V
15
20
25
− VIN Input Voltage − V
IN
T
J
− Junction Temperature − °C
Figure 9.
Figure 10.
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SLUS670A–JULY 2005–REVISED AUGUST 2005
TYPICAL CHARACTERISTICS (continued)
NO-LOAD BATTERY CURRENT
CURRENT SENSE CURRENT
vs
JUNCTION TEMPERATURE
vs
INPUT VOLTAGE
16
0.5
0.4
14
12
10
8
0.3
0.2
6
4
0.1
AUTO−SKIP
280 kHz (CH1)
430 kHz (CH2)
0
2
0
−50
0
50
100
150
8
12
V
16
20
24
− VIN Input Voltage − V
T
J
− Junction Temperature − °C
IN
Figure 11.
Figure 12.
SWITCHING FREQUENCY
vs
SWITCHING FREQUENCY
vs
INPUT VOLTAGE
INPUT VOLTAGE
600
500
600
500
CH2
TONSEL = GND
TONSEL = 2 V
CH2
CH1
400
300
200
400
300
200
CH1
100
0
100
0
6
10
V
14
18
24
28
6
10
14
18
24
28
− VIN Input Voltage − V
V
IN
− VIN Input Voltage − V
IN
Figure 13.
Figure 14.
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SLUS670A–JULY 2005–REVISED AUGUST 2005
TYPICAL CHARACTERISTICS (continued)
SWITCHING FREQUENCY
vs
SWITCHING FREQUENCY
vs
INPUT VOLTAGE
INPUT VOLTAGE
400
400
350
300
250
200
150
100
50
TONSEL = FLOAT
TONSEL = 5 V
350
CH2
300
250
200
CH2
CH1
CH1
150
100
50
0
0
6
10
14
18
24
28
6
10
14
18
24
28
V
IN
− VIN Input Voltage − V
V
IN
− VIN Input Voltage − V
Figure 15.
Figure 16.
SWITCHING FREQUENCY
vs
SWITCHING FREQUENCY
vs
OUTPUT CURRENT
OUTPUT CURRENT
600
500
600
500
TONSEL = 2 V
TONSEL = GND
CH2
Auto−skip
CH2−PWM Only
CH2
Auto−skip
CH2−PWM Only
400
300
200
400
300
200
CH1−PWM Only
CH1
Auto−skip
CH1−PWM Only
CH1
Auto−skip
100
0
100
0
0.001
0.01
0.1
1
10
0.001
0.01
0.1
1
10
I
− Output Current − A
OUT
I
− Output Current − A
OUT
Figure 17.
Figure 18.
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SLUS670A–JULY 2005–REVISED AUGUST 2005
TYPICAL CHARACTERISTICS (continued)
SWITCHING FREQUENCY
vs
SWITCHING FREQUENCY
vs
OUTPUT CURRENT
OUTPUT CURRENT
400
400
300
200
100
0
TONSEL = FLOAT
TONSEL = 5 V
CH2−PWM Only
300
CH2−PWM Only
CH1−PWM Only
0.01
CH2 Auto−skip
CH2 Auto−skip
200
CH1−PWM Only
100
CH1 Auto−skip
CH1 Auto−skip
0
0.001
0.01
0.1
1
10
0.001
0.1
1
10
I
− Output Current − A
OUT
I
− Output Current − A
OUT
Figure 19.
Figure 20.
OVP/UVP THRESHOLD VOLTAGE
vs
VREG5 OUTPUT VOLTAGE
vs
JUNCTION TEMPERATURE
OUTPUT CURRENT
150
5.100
5.050
140
130
120
OVP
100
90
80
5.000
4.950
70
60
UVP
50
0
−50
0
50
100
0
20
60
80
100
40
T
J
− Junction Temperature − °C
I
− VREG5 Output Current − mA
VREG5
Figure 21.
Figure 22.
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SLUS670A–JULY 2005–REVISED AUGUST 2005
TYPICAL CHARACTERISTICS (continued)
VREG3 OUTPUT VOLTAGE
vs
VREF2 OUTPUT VOLTAGE
vs
OUTPUT CURRENT
OUTPUT CURRENT
3.340
3.320
3.300
2.020
2.015
2.010
2.005
3.280
3.260
2.000
1.995
1.990
1.985
1.980
3.240
3.220
3.200
0
20
40
60
80
100
−100
−60
20
100
40 60 80
−80
−40 −20
0
I
− VREG3 Output Current − mA
I
− VREF2 Output Current − µA
VREG5
REF2
Figure 23.
Figure 24.
5-V OUTPUT VOLTAGE
vs
OUTPUT CURRENT
3.3-V OUTPUT VOLTAGE vs
OUTPUT CURRENT
3.390
3.360
3.330
3.300
3.270
5.050
5.025
5.000
4.975
4.950
PWM Only
PWM Only
Auto−skip
Auto−skip
0.001
0.01
I
0.1
1
0.001
0.01
0.1
1
10
− 3.3-V Output Current − A
I
− 5-V Output Current − A
OUT2
OUT1
Figure 25.
Figure 26.
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SLUS670A–JULY 2005–REVISED AUGUST 2005
TYPICAL CHARACTERISTICS (continued)
5-V OUTPUT VOLTAGE
vs
3.3-V OUTPUT VOLTAGE
vs
INPUT VOLTAGE
INPUT VOLTAGE
3.32
3.32
5.050
5.025
5.000
3.31
3.33
I
I
= 6 A
= 0 A
I
= 6 A
= 0 A
O
O
3.30
4.975
4.950
I
O
O
3.28
3.27
6
8
10 12 14 16 18 20 22 24 26
6
8
10 12 14 16 18 20 22 24 26
V
IN
− VIN Input Voltage − V
V
IN
− VIN Input Voltage − V
Figure 27.
Figure 28.
5-V EFFICIENCY
vs
OUTPUT CURRENT
3.3-V EFFICIENCY
vs
OUTPUT CURRENT
100
80
100
80
Auto−Skip
Auto−Skip
VIN = 8 V
VIN = 8 V
VIN = 12 V
VIN = 12 V
VIN = 8 V
VIN = 8 V
60
40
60
40
20
VIN = 20 V
VIN = 20 V
VIN = 12 V
VIN = 12 V
20
0
VIN = 20 V
PWM Only
5-V Switcher ON
VIN = 20 V
0.1
PWM Only
1
0
0.001
0.01
0.1
1
10
0.001
0.01
10
I
− 3.3−V Output Current − A
OUT1
I
− 5−V Output Current − A
OUT1
Figure 29.
Figure 30.
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SLUS670A–JULY 2005–REVISED AUGUST 2005
TYPICAL CHARACTERISTICS (continued)
V
OUT2
(100 mV/div)
V
OUT1
(100 mV/div)
I
(5 A/div)
IND
I
(5 A/div)
IND
I
(5 A/div)
I
(5 A/div)
OUT2
OUT1
t − Time − 20 µs/div
t − Time − 20 µs/div
Figure 31. 5-V Load Transient Response
Figure 32. 3.3-V Load Transient Response
EN1 (5 V/div)
EN2 (5 V/div)
VO2 (2 V/div)
VO1 (2 V/div)
PGOOD2 (5 V/div)
PGOOD1 (5 V/div)
t − Time − 1 ms/div
Figure 34. 3.3-V Startup Waveforms
t − Time − 1 ms/div
Figure 33. 5-V Startup Waveforms
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SLUS670A–JULY 2005–REVISED AUGUST 2005
TYPICAL CHARACTERISTICS (continued)
VREG5 (200 mV/div)
VREG3 (200 mV/div)
VO2 (200 mV/div)
VO1 (200 mV/div)
t − Time − 1 ms/div
t − Time − 1 ms/div
Figure 36. 3.3-V Switchover Waveforms
Figure 35. 5-V Switchover Waveforms
EN1 (5 V/div)
VO1 (5 V/div)
EN2 (5 V/div)
VO2 (5 V/div)
PGOOD2 (5 V/div)
DRVL2 (5 V/div)
PGOOD1 (5 V/div)
DRVL1 (5 V/div)
t − Time − 1 ms/div
Figure 38. 3.3-V Soft-Stop Waveforms
t − Time − 1 ms/div
Figure 37. 5-V Soft-Stop Waveforms
30
TPS51120
www.ti.com
SLUS670A–JULY 2005–REVISED AUGUST 2005
TYPICAL CHARACTERISTICS (continued)
GAIN AND PHASE
vs
FREQUENCY
GAIN AND PHASE
vs
FREQUENCY
80
180
80
180
60
135
90
60
40
135
Phase
Phase
40
90
20
0
45
0
20
0
45
0
−20
−45
−20
−45
Gain
−40
−60
−90
−40
−60
−90
Gain
−135
−135
−180
−80
−180
1 M
−80
1 k
10 k
100 k
1 k
10 k
f − Frequency − kHz
Figure 40. 3.3-V Bode Plot (Current Mode)
100 k
1 M
f − Frequency − kHz
Figure 39. 5-V Bode Plot (Current Mode)
31
PACKAGE OPTION ADDENDUM
www.ti.com
13-Sep-2005
PACKAGING INFORMATION
Orderable Device
TPS51120RHBR
TPS51120RHBRG4
TPS51120RHBT
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
QFN
RHB
32
32
32
32
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
QFN
QFN
QFN
RHB
RHB
RHB
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
TPS51120RHBTG4
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
IMPORTANT NOTICE
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