TPS51200MDRCTEP [TI]
灌电流/拉电流 DDR 终端稳压器 | DRC | 10 | -55 to 125;
| 型号： | TPS51200MDRCTEP |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 灌电流/拉电流 DDR 终端稳压器 | DRC | 10 | -55 to 125 双倍数据速率 稳压器 |
| 文件： | 总37页 (文件大小：1288K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TPS51200-EP
ZHCSF57 –JUNE 2016
TPS51200-EP 灌/拉 DDR 终端稳压器
1 特性
2 应用范围
1
•
输入电压：支持 2.5V 和 3.3V 电源轨
VLDOIN 电压范围：1.1V 至 3.5V
•
用于 DDR、DDR2、DDR3、低功耗 DDR3 和
DDR4 的存储器终端稳压器
笔记本、台式机和服务器
电信和数据通信
•
•
•
•
•
•
•
•
•
具有压降补偿功能的灌电流和拉电流终端稳压器
所需最小输出电容为 20μF（通常为 3 × 10μF
MLCC），用于存储器终端 应用 (DDR)
基站
•
•
•
用于监视输出稳压的 PGOOD
EN 输入
液晶 (LCD) 电视和等离子 (PDP) 电视
复印机和打印机
REFIN 输入允许直接或通过电阻分压器灵活进行输
入跟踪
机顶盒
3 说明
•
•
•
•
•
•
•
远程感测 (VOSNS)
TPS51200-EP 器件是一款灌电流和拉电流双倍数据速
率 (DDR) 终端稳压器，专用于空间问题是重要考量因
素的低输入电压、低成本、低噪声系统。
±10mA 缓冲基准 (REFOUT)
内置软启动，欠压锁定 (UVLO) 和过流限制 (OCL)
热关断
符合 DDR 和 DDR2 JEDEC 规范
支持 DDR3、低功耗 DDR3 和 DDR4 VTT 应用
TPS51200-EP 能够保持快速瞬态响应，最低仅需
20μF 输出电容。TPS51200-EP 支持远程感测功能并
且可满足 DDR、DDR2、DDR3、低功耗 DDR3 和
DDR4 VTT 总线的所有电源要求。
带有散热焊盘的 10 引脚超薄小外形尺寸无引线
(VSON) 封装
•
支持国防、航天和医疗 应用
此外，TPS51200-EP 还提供一个开漏 PGOOD 信号
监测输出稳压，提供一个 EN 信号在 S3（挂起至
RA4M）期间针对 DDR 进行 VTT 放电。
–
–
–
–
–
–
–
受控基线
一个组装和测试场所
一个制造场所
支持军用温度范围（-55°C 至 125°C）
延长的产品使用寿命周期
延长的产品变更通知
产品可追溯性
TPS51200-EP 采用带散热焊盘的高效散热型 10 引脚
超薄小外形尺寸无引线 (VSON) 封装，无铅且绿色环
保。其额定工作温度范围为 -55°C 至 +125°C。
器件信息(1)
器件型号
封装
VSON (10)
封装尺寸（标称值）
TPS51200-EP
3.00mm x 3.00mm
(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。
简化的 DDR 应用
1
REFIN
VIN 10
3.3 VIN
VDDQ
TPS51200
VLDOIN
VTT
2
3
4
5
VLDOIN PGOOD
9
8
7
6
PGOOD
VO
GND
EN
PGND
SLP_S3
VTTREF
VOSNS REFOUT
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLUSA48
TPS51200-EP
ZHCSF57 –JUNE 2016
www.ti.com.cn
目录
1
2
3
4
5
6
特性.......................................................................... 1
8
9
Application and Implementation ........................ 14
8.1 Application Information............................................ 14
8.2 Typical VTT DIMM Applications.............................. 14
8.3 System Examples ................................................... 19
Power Supply Recommendations...................... 25
应用范围................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics........................................... 5
6.6 Typical Characteristics.............................................. 7
Detailed Description ............................................ 10
7.1 Overview ................................................................. 10
7.2 Functional Block Diagram ....................................... 10
7.3 Feature Description................................................. 10
7.4 Device Functional Modes........................................ 13
10 Layout................................................................... 25
10.1 Layout Guidelines ................................................. 25
10.2 Layout Example .................................................... 26
10.3 Thermal Design Considerations............................ 26
11 器件和文档支持 ..................................................... 28
11.1 器件支持................................................................ 28
11.2 文档支持 ............................................................... 28
11.3 接收文档更新通知 ................................................. 28
11.4 社区资源................................................................ 28
11.5 商标....................................................................... 28
11.6 静电放电警告......................................................... 28
11.7 Glossary................................................................ 29
12 机械、封装和可订购信息....................................... 29
7
4 修订历史记录
日期
修订版本
注释
2016 年 6 月
*
最初发布。
2
Copyright © 2016, Texas Instruments Incorporated
TPS51200-EP
www.ti.com.cn
ZHCSF57 –JUNE 2016
5 Pin Configuration and Functions
DRC Package
10-Pin VSON With Exposed Thermal Pad
Top View
REFIN
VLDOIN
VO
1
2
3
4
10 VIN
9
8
7
PGOOD
GND
EN
Thermal
Pad
PGND
VOSNS
5
6
REFOUT
Pin Functions
PIN
I/O(1)
DESCRIPTION
NAME
NO.
For DDR VTT application, connect EN to SLP_S3. For any other application, use the EN pin
as the ON/OFF function.
EN
7
I
GND
8
4
9
1
6
G
G
O
I
Signal ground. Connect to negative terminal of the output capacitor.
Power ground output for the LDO.
PGND(2)
PGOOD
REFIN
PGOOD output. Indicates regulation.
Reference input.
REFOUT
O
Reference output. Connect to GND through 0.1-μF ceramic capacitor.
2.5-V or 3.3-V power supply. A ceramic decoupling capacitor with a value between 1-μF and
4.7-μF is required.
VIN
10
I
VLDOIN
VO
2
3
I
Supply voltage for the LDO.
Power output for the LDO.
O
Voltage sense input for the LDO. Connect to positive terminal of the output capacitor or the
load.
VOSNS
5
I
(1) I = Input, O = Output, G = Ground.
(2) Thermal pad connection. See Figure 31 in the Thermal Design Considerations section for additional information.
Copyright © 2016, Texas Instruments Incorporated
3
TPS51200-EP
ZHCSF57 –JUNE 2016
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating junction temperature range (unless otherwise noted)
(1)
MIN
–0.3
–0.3
–0.3
–0.3
–0.3
–55
MAX
3.6
UNIT
REFIN, VIN, VLDOIN, VOSNS
Input voltage(2)
EN
6.5
V
PGND to GND
REFOUT, VO
PGOOD
0.3
3.6
Output voltage(2)
V
6.5
Operating junction temperature, TJ
Storage temperature, Tstg
150
150
°C
°C
–55
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to the network ground terminal unless otherwise noted.
6.2 ESD Ratings
VALUE
±2000
±500
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged device model (CDM), per JEDEC specification JESD22-C101(2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating junction temperature range (unless otherwise noted)
MIN
2.375
–0.1
0.5
NOM
MAX
3.5
UNIT
Supply voltages
Voltage
VIN
V
EN, VLDOIN, VOSNS
REFIN
3.5
1.8
PGOOD, VO
REFOUT
–0.1
–0.1
–0.1
–55
3.5
V
1.8
PGND
0.1
Operating junction temperature, TJ
125
°C
6.4 Thermal Information
TPS51200-EP
THERMAL METRIC(1)
DRC (VSON)
10 PINS
55.6
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
84.6
Junction-to-board thermal resistance
30
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
5.5
ψJB
30.1
RθJC(bot)
10.9
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
4
Copyright © 2016, Texas Instruments Incorporated
TPS51200-EP
www.ti.com.cn
ZHCSF57 –JUNE 2016
6.5 Electrical Characteristics
Over recommended junction temperature range, VVIN = 3.3 V, VVLDOIN = 1.8 V, VREFIN = 0.9 V, VVOSNS = 0.9 V, VEN = VVIN
,
COUT = 3 × 10 μF and circuit shown in (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY CURRENT
IIN
Supply current
TJ = 25 °C, VEN = 3.3 V, no load
0.7
65
1
mA
TJ = 25 °C, VEN = 0 V, VREFIN = 0,
no load
80
IIN(SDN)
Shutdown current
μA
TJ = 25 °C, VEN = 0 V, VREFIN > 0.4 V, no
load
200
400
ILDOIN
Supply current of VLDOIN
TJ = 25 °C, VEN = 3.3 V, no load
TJ = 25 °C, VEN = 0 V, no load
1
50
50
μA
μA
ILDOIN(SDN)
INPUT CURRENT
IREFIN
Shutdown current of VLDOIN
0.1
Input current, REFIN
VEN = 3.3 V
1
μA
VO OUTPUT
1.25
0.9
V
VREFOUT = 1.25 V (DDR1), IO = 0 A
VREFOUT = 0.9 V (DDR2), IO = 0 A
–15
–15
15
15
mV
V
VVOSNS
Output DC voltage, VO
mV
V
0.75
VLDOIN = 1.5 V, VREFOUT = 0.75 V (DDR3),
IO = 0 A
–15
–25
15
25
mV
mV
VVOTOL
IVOSRCL
IVOSNCL
IDSCHRG
Output voltage tolerance to REFOUT
VO source current Limit
–2 A < IVO < 2 A
With reference to REFOUT,
VOSNS = 90% × VREFOUT
3
4.5
5.5
25
A
A
Ω
With reference to REFOUT,
VOSNS = 110% × VREFOUT
VO sink current Limit
Discharge current, VO
3.5
VREFIN = 0 V, VVO = 0.3 V, VEN = 0 V, TJ
25°C
=
18
POWERGOOD COMPARATOR
PGOOD window lower threshold with
respect to REFOUT
–23.5%
17.5%
–20%
–17.5%
23.5%
VTH(PG)
VO PGOOD threshold
PGOOD window upper threshold with
respect to REFOUT
20%
5%
2
PGOOD hysteresis
Start-up rising edge, VOSNS within 15%
of REFOUT
tPGSTUPDLY
VPGOODLOW
tPBADDLY
PGOOD start-up delay
Output low voltage
PGOOD bad delay
ms
V
ISINK = 4 mA
0.4
1
VOSNS is outside of the ±20% PGOOD
window
10
μs
VOSNS = VREFIN (PGOOD high
impedance), VPGOOD = VVIN + 0.2 V
IPGOODLK
Leakage current(1)
μA
REFIN AND REFOUT
VREFIN
REFIN voltage range
0.5
1.8
V
mV
mV
V
VREFINUVLO
VREFINUVHYS
VREFOUT
REFIN undervoltage lockout
REFIN undervoltage lockout hysteresis
REFOUT voltage
REFIN rising
360
390
20
420
REFIN
–10 mA < IREFOUT < 10 mA,
VREFIN = 1.25 V
–15
–15
–15
–15
15
15
15
15
–10 mA < IREFOUT < 10 mA,
VVREFIN = 0.9 V
VREFOUTTOL
REFOUT voltage tolerance to VREFIN
mV
–10 mA < IREFOUT < 10 mA,
VREFIN = 0.75 V
–10 mA < IREFOUT < 10 mA,
VREFIN = 0.6 V
IREFOUTSRCL
IREFOUTSNCL
REFOUT source current limit
REFOUT sink current limit
VREFOUT = 0 V
VREFOUT = 0 V
10
10
40
40
mA
mA
(1) Ensured by design. Not production tested.
Copyright © 2016, Texas Instruments Incorporated
5
TPS51200-EP
ZHCSF57 –JUNE 2016
www.ti.com.cn
Electrical Characteristics (continued)
Over recommended junction temperature range, VVIN = 3.3 V, VVLDOIN = 1.8 V, VREFIN = 0.9 V, VVOSNS = 0.9 V, VEN = VVIN
,
COUT = 3 × 10 μF and circuit shown in (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
2.2
TYP
MAX
UNIT
UVLO AND EN LOGIC THRESHOLD
Wake up, TJ = 25°C
2.3
50
2.375
V
mV
V
VVINUVVIN
UVLO threshold
Hysteresis
Enable
VENIH
High-level input voltage
Low-level input voltage
Hysteresis voltage
1.7
VENIL
Enable
0.3
1
V
VENYST
IENLEAK
Enable
0.5
V
Logic input leakage current
EN, TJ = 25°C
–1
μA
THERMAL SHUTDOWN
TSON
Thermal shutdown threshold(1)
Shutdown temperature
Hysteresis
150
25
°C
100
70
METTOP
50
40
30
20
10
7
5
4
3
2
1
80
85
90
95
100
105
110
115
120
125
130
135
140
145
150
Continuous Junction Temperature, TJ (èC)
D013
(1) Electromigration fail mode = time at temperature with bias.
(2) Silicon operating life design goal is 10 years at 105°C junction temperature (does not include package interconnect
life).
(3) The predicted operating lifetime versus junction temperature is based on reliability modeling and available
qualification data.
Figure 1. Predicted Lifetime Derating Chart for TPS51200-EP
6
Copyright © 2016, Texas Instruments Incorporated
TPS51200-EP
www.ti.com.cn
ZHCSF57 –JUNE 2016
6.6 Typical Characteristics
3 × 10-µF MLCCs (0805) are used on the output.
1.3
1.28
1.26
1.24
1.22
1.2
0.94
0.93
0.92
0.91
0.9
-55°C
-40°C
0°C
25°C
85°C
-55°C
-40°C
0°C
25°C
85°C
0.89
0.88
0.87
1.18
-3
-3
-3
-2
-1
0
1
2
3
-3
-3
-3
-2
-1
0
1
2
3
Output Current (A)
Output Current (A)
D001
D002
VVIN = 3.3 V
Figure 2. Load Regulation
DDR
VVIN = 3.3 V
Figure 3. Load Regulation
DDR2
0.8
0.79
0.78
0.77
0.76
0.75
0.74
0.73
0.72
0.71
0.7
0.67
0.65
0.63
0.61
0.59
0.57
0.55
-55°C
-40°C
0°C
25°C
85°C
-55°C
-40°C
0°C
25°C
85°C
-2
-1
0
1
2
3
-2
-1
0
1
2
3
Output Current (A)
Output Current (A)
D003
D004
VVIN = 3.3 V
Figure 4. Load Regulation
DDR3
VVIN = 3.3 V
LP DDR3 or DDR4
Figure 5. Load Regulation
1.3
1.25
1.2
1
0.95
0.9
1.15
1.1
0.85
0.8
1.05
1
-55°C
-40°C
0°C
25°C
85°C
-55°C
-40°C
0°C
25°C
85°C
0.75
0.7
0.95
0.9
-2
-1
0
1
2
3
-2
-1
0
1
2
3
Output Current (A)
Output Current (A)
D005
D006
VVIN = 2.5 V
Figure 6. Load Regulation
DDR
VVIN = 2.5 V
Figure 7. Load Regulation
DDR2
Copyright © 2016, Texas Instruments Incorporated
7
TPS51200-EP
ZHCSF57 –JUNE 2016
www.ti.com.cn
Typical Characteristics (continued)
3 × 10-µF MLCCs (0805) are used on the output.
0.8
0.75
0.7
-55°C
-40°C
0°C
25°C
85°C
-55°C
-40°C
0°C
25°C
85°C
0.775
0.75
0.725
0.7
0.65
0.6
0.55
0.675
0.65
0.5
-3
-2
-1
0
1
2
3
-3
-2
-1
0
1
2
3
Output Current (A)
Output Current (A)
D007
D008
VVIN = 2.5 V
Figure 8. Load Regulation
DDR3
VVIN = 2.5 V
LP DDR3 or DDR4
Figure 9. Load Regulation
1.255
1.254
1.253
1.252
1.251
1.25
0.905
0.904
0.903
0.902
0.901
0.9
-55°C
-55°C
-40°C
25°C
85°C
-40°C
25°C
85°C
1.249
1.248
1.247
0.899
0.898
0.897
-15
-10
-5
0
5
10
15
-15
-10
-5
0
5
10
15
REFOUT Output Current (mA)
REFOUT Output Current (mA)
D009
D010
DDR
DDR2
Figure 10. REFOUT Load Regulation
Figure 11. REFOUT Load Regulation
0.755
0.605
0.604
0.603
0.602
0.601
0.6
-55°C
-40°C
25°C
85°C
-55°C
0.754
0.753
0.752
0.751
0.75
-40°C
25°C
85°C
0.749
0.748
0.747
0.599
0.598
0.597
-15
-10
-5
0
5
10
15
-15
-10
-5
0
5
10
15
REFOUT Output Current (mA)
REFOUT Output Current (mA)
D011
D012
DDR3
LP DDR3 or DDR4
Figure 12. REFOUT Load Regulation
Figure 13. REFOUT Load Regulation
8
Copyright © 2016, Texas Instruments Incorporated
TPS51200-EP
www.ti.com.cn
ZHCSF57 –JUNE 2016
Typical Characteristics (continued)
3 × 10-µF MLCCs (0805) are used on the output.
1.4
200
150
60
50
1.2
1
40
30
100
50
0.8
0.6
0.4
0.2
0
20
0
10
0
œ50
VOUT (V)
0.6
œ100
œ150
œ10
0.75
0.9
Gain
Phase
œ20
œ30
1.25
œ200
0
0.5
1
1.5
2
2.5
3
3.5
1 k
10 k
100 k
1 M
10 M
Output Current (A)
Frequency (Hz)
DDR2
Figure 14. DROPOUT Voltage vs Output Current
Figure 15. Bode Plot
200
60
50
150
40
30
100
50
20
0
10
0
œ50
œ100
œ150
œ200
œ10
Gain
Phase
œ20
œ30
1 k
10 k
100 k
Frequency (Hz)
1 M
10 M
DDR3
Figure 16. Bode Plot
Copyright © 2016, Texas Instruments Incorporated
9
TPS51200-EP
ZHCSF57 –JUNE 2016
www.ti.com.cn
7 Detailed Description
7.1 Overview
The TPS51200-EP device is a sink and source double data rate (DDR) termination regulator specifically
designed for low-input voltage, low-cost, low-noise systems where space is a key consideration.
The device maintains a fast transient response and only requires a minimum output capacitance of 20 μF. The
device supports a remote sensing function and all power requirements for DDR, DDR2, DDR3, Low-Power
DDR3, and DDR4 VTT bus termination.
7.2 Functional Block Diagram
2
6
VLDOIN
REFIN
1
+
REFOUT
2.3 V
UVLO
+
VIN 10
Gm
DchgREF
DchgVTT
VOSNS
5
3
VO
+
ENVTT
EN
7
8
Gm
4
9
PGND
REFINOK
GND
PGOOD
+
+
Start-up
Delay
Copyright © 2016, Texas Instruments Incorporated
7.3 Feature Description
7.3.1 Sink and Source Regulator (VO Pin)
The TPS51200-EP is a sink and source tracking termination regulator specifically designed for low-input voltage,
low-cost, and low-external component count systems where space is a key application parameter. The device
integrates a high-performance, low-dropout (LDO) linear regulator that is capable of both sourcing and sinking
current. The LDO regulator employs a fast feedback loop so that small ceramic capacitors can be used to
support the fast load transient response. To achieve tight regulation with minimum effect of trace resistance,
connect a remote sensing terminal, VOSNS, to the positive terminal of each output capacitor as a separate trace
from the high-current path from VO.
7.3.2 Reference Input (REFIN Pin)
The output voltage, VO, is regulated to REFOUT. When REFIN is configured for standard DDR termination
applications, REFIN can be set by an external equivalent ratio voltage divider connected to the memory supply
bus (VDDQ). The TPS51200-EP device supports REFIN voltages from 0.5 V to 1.8 V, making it versatile and
ideal for many types of low-power LDO applications.
10
Copyright © 2016, Texas Instruments Incorporated
TPS51200-EP
www.ti.com.cn
ZHCSF57 –JUNE 2016
Feature Description (continued)
7.3.3 Reference Output (REFOUT Pin)
When it is configured for DDR termination applications, REFOUT generates the DDR VTT reference voltage for
the memory application. It is capable of supporting both a sourcing and sinking load of 10 mA. REFOUT
becomes active when REFIN voltage rises to 0.39 V and VIN is above the UVLO threshold. When REFOUT is
less than 0.375 V, it is disabled and subsequently discharges to GND through an internal 10-kΩ MOSFET.
REFOUT is independent of the EN pin state.
7.3.4 Soft-Start Sequencing
A current clamp implements the soft-start function of the VO pin. The current clamp allows the output capacitors
to be charged with low and constant current, providing a linear ramp-up of the output voltage. When VO is
outside of the powergood (PGOOD) window, the current clamp level is one-half of the full overcurrent limit (OCL)
level. When VO rises or falls within the PGOOD window, the current clamp level switches to the full OCL level.
The soft-start function is completely symmetrical and the overcurrent limit works for both directions. The soft-start
function works not only from GND to the REFOUT voltage, but also from VLDOIN to the REFOUT voltage.
7.3.5 Enable Control (EN Pin)
When EN is driven high, the VO regulator begins normal operation. When the device drives EN low, VO
discharges to GND through an internal 18-Ω MOSFET. REFOUT remains on when the device drives EN low.
Ensure that the EN pin voltage remains lower than or equal to VVIN at all times.
7.3.6 Powergood Function (PGOOD Pin)
The TPS51200-EP device provides an open-drain PGOOD output that goes high when the VO output is within
±20% of REFOUT. PGOOD de-asserts within 10 μs after the output exceeds the size of the PGOOD window.
During initial VO start-up, PGOOD asserts high 2 ms (typ) after the VO enters PGOOD window. Because
PGOOD is an open-drain output, a pull-up resistor with a value between 1 kΩ and 100 kΩ, placed between
PGOOD and a stable active supply voltage rail, is required.
7.3.7 Current Protection (VO Pin)
The LDO has a constant overcurrent limit (OCL). The OCL level reduces by one-half when the output voltage is
not within the PGOOD window. This reduction is a non-latch protection.
7.3.8 UVLO Protection (VIN Pin)
For VIN undervoltage lockout (UVLO) protection, the TPS51200-EP monitors VIN voltage. When the VIN voltage
is lower than the UVLO threshold voltage, both the VO and REFOUT regulators are powered off. This shutdown
is a non-latch protection.
7.3.9 Thermal Shutdown
The TPS51200-EP monitors junction temperature. If the device junction temperature exceeds the threshold
value, (typically 150°C), the VO and REFOUT regulators both shut off, discharged by the internal discharge
MOSFETs. This shutdown is a non-latch protection.
7.3.10 Tracking Start-up and Shutdown
The TPS51200-EP also supports tracking start-up and shutdown when the EN pin is tied directly to the system
bus and not used to turn on or turn off the device. During tracking start-up, VO follows REFOUT once REFIN
voltage is greater than 0.39 V. REFIN follows the rise of VDDQ rail through a voltage divider. The typical soft-
start time (tSS) for the VDDQ rail is approximately 3 ms, however it may vary depending on the system
configuration. The soft-start time of the VO output no longer depends on the OCL setting, but it is a function of
the soft-start time of the VDDQ rail. PGOOD is asserted 2 ms after VVO is within ±20% of REFOUT. During
tracking shutdown, the VO pin voltage falls following REFOUT until REFOUT reaches 0.37 V. When REFOUT
falls below 0.37 V, the internal discharge MOSFETs turn on and quickly discharge both REFOUT and VO to
GND. PGOOD is deasserted once VO is beyond the ±20% range of REFOUT. Figure 18 shows the typical timing
diagram for an application that uses tracking start-up and shutdown.
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Feature Description (continued)
3.3VIN
V
VDDQ
= 1.5 V
VLDOIN
REFIN
REFOUT
(VTTREF)
EN
(S3_SLP)
V
t
= 0.75 V
VO
t
SS .
VO
C
x V
O
OUT
=
SS
I
OOCL
PGOOD
2 ms
Figure 17. Typical Timing Diagram for S3 and Pseudo-S5 Support
3.3VIN
EN
VLDOIN
REFIN
REFOUT
(VTTREF)
tSS determined
by the SS time
V
= 0.75 V
VO
of VLDOIN
VO
PGOOD
2 ms
Figure 18. Typical Timing Diagram of Tracking Start-up and Shutdown
12
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7.4 Device Functional Modes
7.4.1 Low-Input Voltage Applications
TPS51200-EP can be used in an application system that offers either a 2.5-V rail or a 3.3-V rail. If only a 5-V rail
is available, consider using the TPS51100 device as an alternative. The TPS51200-EP device has a minimum
input voltage requirement of 2.375 V. If a 2.5-V rail is used, ensure that the absolute minimum voltage (both DC
and transient) at the device pin is be 2.375 V or greater. The voltage tolerance for a 2.5-V rail input is between
–5% and 5% accuracy, or better.
7.4.2 S3 and Pseudo-S5 Support
The TPS51200-EP provides S3 support by an EN function. The EN pin could be connected to an SLP_S3 signal
in the end application. Both REFOUT and VO are on when EN = high (S0 state). REFOUT is maintained while
VO is turned off and discharged via an internal discharge MOSFET when EN = low (S3 state). When EN = low
and the REFIN voltage is less than 0.39 V, TPS51200-EP enters pseudo-S5 state. Both VO and REFOUT
outputs are turned off and discharged to GND through internal MOSFETs when pseudo-S5 support is engaged
(S4 or S5 state). Figure 17 shows a typical start-up and shutdown timing diagram for an application that uses S3
and pseudo-S5 support.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPS51200-EP device is specifically designed to power up the memory termination rail (as shown in
Figure 19). The DDR memory termination structure determines the main characteristics of the VTT rail, which is
to be able to sink and source current while maintaining acceptable VTT tolerance. See Figure 20 for typical
characteristics for a single memory cell.
8.2 Typical VTT DIMM Applications
DDR3 240 Pin Socket
VO
TPS51200
10 mF
10 mF
10 mF
UDG-08022
Figure 19. Typical Application Diagram for DDR3 VTT DIMM Using TPS51200-EP
8.2.1 Design Requirements
Use the information listed in Table 1 as the design parameters.
Table 1. DDR, DDR2, DDR3, and LP DDR3 Termination Technology and Differences
LOW-POWER
DDR3
PARAMETER
DDR
DDR2
DR3
FSB data rates
200, 266, 333 and 400 MHz
400, 533, 677 and 800 MHz
800, 1066, 1330 and 1600 MHz
Same as DDR3
On-die termination for data group. VTT On-die termination for data group. VTT
Motherboard termination to VTT
for all signals
Termination
termination for address, command and
control signals.
termination for address, command and
control signals.
Same as DDR3
Same as DDR3
Not as demanding
Not as demanding
•
Only
34
signals
(address,
•
Only
34
signals
(address,
Termination current Max sink and source transient
demand
command, control) tied to VTT
command, control) tied to VTT
currents of up to 2.6 A to 2.9 A
•
ODT handles data signals
•
ODT handles data signals
Less than 1 A of burst current
2.5-V core and I/O 1.25-V VTT 1.8-V core and I/O 0.9-V VTT
Less than 1 A of burst current
1.5-V core and I/O 0.75-V VTT
1.2-V core and I/O
0.6-V VTT
Voltage level
14
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8.2.2 Detailed Design Procedure
8.2.2.1 Input Voltage Capacitor
Add a ceramic capacitor, with a value between 1-μF and 4.7-μF, placed close to the VIN pin, to stabilize the bias
supply (2.5-V rail or 3.3-V rail) from any parasitic impedance from the supply.
8.2.2.2 VLDO Input Capacitor
Depending on the trace impedance between the VLDOIN bulk power supply to the device, a transient increase of
source current is supplied mostly by the charge from the VLDOIN input capacitor. Use a 10-μF (or greater)
ceramic capacitor to supply this transient charge. Provide more input capacitance as more output capacitance is
used at the VO pin. In general, use one-half of the COUT value for input.
8.2.2.3 Output Capacitor
For stable operation, the total capacitance of the VO output pin must be greater than 20 μF. Attach 3 × 10-μF
ceramic capacitors in parallel to minimize the effect of equivalent series resistance (ESR) and equivalent series
inductance (ESL). If the ESR is greater than 2 mΩ, insert an RC filter between the output and the VOSNS input
to achieve loop stability. The RC filter time constant should be almost the same as or slightly lower than the time
constant of the output capacitor and its ESR.
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8.2.2.4 Output Tolerance Consideration for VTT DIMM Applications
Figure 20 shows the typical characteristics for a single memory cell.
V
V
TT
DDQ
Q1
Q2
25 W
R
S
20 W
Receiver
Ouput
Buffer
(Driver)
V
V
IN
OUT
V
SS
UDG-08023
Figure 20. DDR Physical Signal System Bi-Directional SSTL Signaling
In Figure 20, when Q1 is on and Q2 is off:
•
•
Current flows from VDDQ via the termination resistor to VTT
VTT sinks current
In Figure 20, when Q2 is on and Q1 is off:
•
•
Current flows from VTT via the termination resistor to GND
VTT sources current
Because VTT accuracy has a direct impact on the memory signal integrity, it is imperative to understand the
tolerance requirement on VTT. Equation 1 applies to both DC and AC conditions and is based on JEDEC VTT
specifications for DDR and DDR2 (JEDEC standard: DDR JESD8-9B May 2002; DDR2 JESD8-15A Sept 2003).
VVTTREF – 40 mV < VVTT < VVTTREF + 40 mV
(1)
The specification itself indicates that VTT must keep track of VTTREF for proper signal conditioning.
The TPS51200-EP ensures the regulator output voltage to be as shown in Equation 2, which applies to both DC
and AC conditions.
VVTTREF –25 mV < VVTT < VVTTREF + 25 mV
where
•
–2 A < IVTT < 2 A
(2)
The regulator output voltage is measured at the regulator side, not the load side. The tolerance is applicable to
DDR, DDR2, DDR3, Low Power DDR3, and DDR4 applications (see Table 1 for detailed information). To meet
the stability requirement, a minimum output capacitance of 20 μF is needed. Considering the actual tolerance on
the MLCC capacitors, 3 × 10-μF ceramic capacitors sufficiently meet the VTT accuracy requirement.
16
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The TPS51200-EP device uses transconductance (gM) to drive the LDO. The transconductance and output
current of the device determine the voltage droop between the reference input and the output regulator. The
typical transconductance level is 250 S at 2 A and changes with respect to the load in order to conserve the
quiescent current (that is, the transconductance is very low at no load condition). The (gM) LDO regulator is a
single pole system. Only the output capacitance determines the unity gain bandwidth for the voltage loop, as a
result of the bandwidth nature of the transconductance (see Equation 3).
gM
ƒUGBW
=
2 ´ p ´ COUT
where
•
•
•
ƒUGBW is the unity gain bandwidth
gM is transconductance
COUT is the output capacitance
(3)
Consider these two limitations to this type of regulator that come from the output bulk capacitor requirement. In
order to maintain stability, the zero location contributed by the ESR of the output capacitors must be greater than
the –3-dB point of the current loop. This constraint means that higher ESR capacitors should not be used in the
design. In addition, the impedance characteristics of the ceramic capacitor should be well understood in order to
prevent the gain peaking effect around the transconductance (gM) –3-dB point because of the large ESL, the
output capacitor, and the parasitic inductance of the VO pin voltage trace.
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8.2.3 Application Curves
Figure 21 shows the bode plot simulation for this DDR3 design example of the TPS51200-EP device.
The unity-gain bandwidth is approximately 1 MHz and the phase margin is 52°. When the 0-dB level is crossed,
the gain peaks because of the ESL effect. However, the peaking maintains a level well below 0 dB.
Figure 22 shows the load regulation and Figure 23 shows the transient response for a typical DDR3
configuration. When the regulator is subjected to ±1.5-A load step and release, the output voltage measurement
shows no difference between the DC and AC conditions.
0
80
40
0
œ90
œ180
œ270
œ360
œ40
œ80
Gain
Phase
1
10
100
1000
10 k
100 k
1 M
10 M
100 M
Frequency (Hz)
VVLDOIN = 1.5 V
VIN = 3.3 V
VVO = 0.75 V
ESR = 2.5 mΩ
ESL = 800 pH
IIO = 2 A
3 × 10-μF capacitors
Figure 21. DDR3 Design Example Bode Plot
0.8
-55°C
-40°C
0°C
25°C
85°C
0.79
0.78
0.77
0.76
0.75
0.74
0.73
0.72
0.71
0.7
-3
-2
-1
0
1
2
3
Output Current (A)
D003
VVIN = 3.3 V
Figure 22. Load Regulation
DDR3
Figure 23. Transient Waveform
18
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8.3 System Examples
8.3.1 3.3-VIN, DDR2 Configuration
This design example describes a 3.3-VIN, DDR2 configuration application.
R1
10 kW
TPS51200
1
2
REFIN
VIN 10
3.3 VIN
VVDDQ = 1.8 V
VVLDOIN = VVDDQ = 1.8 V
VVTT = 0.9 V
R2
10 kW
C4
1000 pF
R3
100 kW
C6
4.7 mF
VLDOIN PGOOD
9
PGOOD
C7
10 mF
C8
10 mF
3
4
5
VO
GND
EN
8
7
6
C1
C2
C3
PGND
SLP_S3
VTTREF
10 mF 10 mF 10 mF
VOSNS REFOUT
C5
0.1 mF
UDG-08028
Copyright © 2016, Texas Instruments Incorporated
Figure 24. 3.3-VIN, DDR2 Configuration
Table 2. 3.3-VIN, DDR2 Configuration List of Materials
REFERENCE
DESIGNATOR
DESCRIPTION
Resistor
SPECIFICATION
PART NUMBER
MANUFACTURER
R1, R2
10 kΩ
R3
100 kΩ
C1, C2, C3
C4
10 μF, 6.3 V
1000 pF
GRM21BR70J106KE76L
Murata
C5
Capacitor
0.1 μF
C6
4.7 μF, 6.3 V
10 μF, 6.3 V
GRM21BR60J475KA11L
GRM21BR70J106KE76L
Murata
Murata
C7, C8
Copyright © 2016, Texas Instruments Incorporated
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8.3.2 2.5-VIN, DDR3 Configuration
This design example describes a 2.5-VIN, DDR3 configuration application.
R1
10 kW
TPS51200
1
2
REFIN
VIN 10
2.5 VIN
VVDDQ = 1.5 V
VVLDOIN = VVDDQ = 1.5 V
VVTT = 0.75 V
R2
10 kW
C4
1000 pF
R3
100 kW
C6
4.7 mF
VLDOIN PGOOD
9
PGOOD
C7
10 mF
C8
10 mF
3
4
5
VO
GND
EN
8
7
6
C1
C2
C3
PGND
SLP_S3
VTTREF
10 mF 10 mF 10 mF
VOSNS REFOUT
C5
0.1 mF
UDG-08030
Copyright © 2016, Texas Instruments Incorporated
Figure 25. 2.5-VIN, DDR3 Configuration
Table 3. 2.5-VIN, DDR3 Configuration List of Materials
REFERENCE
DESIGNATOR
DESCRIPTION
Resistor
SPECIFICATION
PART NUMBER
MANUFACTURER
R1, R2
10 kΩ
R3
100 kΩ
C1, C2, C3
C4
10 μF, 6.3 V
1000 pF
GRM21BR70J106KE76L
Murata
C5
Capacitor
0.1 μF
C6
4.7 μF, 6.3 V
10 μF, 6.3 V
GRM21BR60J475KA11L
GRM21BR70J106KE76L
Murata
Murata
C7, C8
20
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8.3.3 3.3-VIN, LP DDR3 or DDR4 Configuration
This design example describes a 3.3-VIN, LP DDR3 or DDR4 configuration application.
R1
10 kW
TPS51200
1
2
REFIN
VIN 10
3.3 VIN
VVDDQ = 1.2 V
VVLDOIN = VVDDQ = 1.2 V
VVTT = 0.6 V
R2
10 kW
C4
1000 pF
R3
100 kW
C6
4.7 mF
VLDOIN PGOOD
9
PGOOD
C7
10 mF
C8
10 mF
3
4
5
VO
GND
EN
8
7
6
C1
C2
C3
PGND
SLP_S3
VTTREF
10 mF 10 mF 10 mF
VOSNS REFOUT
C5
0.1 mF
UDG-08031
Copyright © 2016, Texas Instruments Incorporated
Figure 26. 3.3-VIN, LP DDR3 or DDR4 Configuration
Table 4. 3.3-VIN, LP DDR3 or DDR4 Configuration List of Materials
REFERENCE
DESIGNATOR
DESCRIPTION
Resistor
SPECIFICATION
PART NUMBER
MANUFACTURER
R1, R2
10 kΩ
R3
100 kΩ
C1, C2, C3
C4
10 μF, 6.3 V
1000 pF
GRM21BR70J106KE76L
Murata
C5
Capacitor
0.1 μF
C6
4.7 μF, 6.3 V
10 μF, 6.3 V
GRM21BR60J475KA11L
GRM21BR70J106KE76L
Murata
Murata
C7, C8
Copyright © 2016, Texas Instruments Incorporated
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8.3.4 3.3-VIN, DDR3 Tracking Configuration
This design example describes a 3.3-VIN, DDR3 tracking configuration application.
R1
10 kW
TPS51200
1
2
REFIN
VIN 10
3.3 VIN
VVDDQ = 1.5 V
VVLDOIN = VVDDQ = 1.5 V
VVTT = 0.75 V
R2
10 kW
C4
1000 pF
R3
C6
100 kW 4.7 mF
VLDOIN PGOOD
9
PGOOD
C7
10 mF
C8
10 mF
3
4
5
VO
GND
EN
8
7
6
C1
C2
C3
PGND
10 mF 10 mF 10 mF
VOSNS REFOUT
VTTREF
C5
0.1 mF
UDG-08032
Copyright © 2016, Texas Instruments Incorporated
Figure 27. 3.3-VIN, DDR3 Tracking Configuration
Table 5. 3.3-VIN, DDR3 Tracking Configuration List of Materials
REFERENCE
DESIGNATOR
DESCRIPTION
Resistor
SPECIFICATION
PART NUMBER
MANUFACTURER
R1, R2
10 kΩ
R3
100 kΩ
C1, C2, C3
C4
10 μF, 6.3 V
1000 pF
GRM21BR70J106KE76L
Murata
C5
Capacitor
0.1 μF
C6
4.7 μF, 6.3 V
10 μF, 6.3 V
GRM21BR60J475KA11L
GRM21BR70J106KE76L
Murata
Murata
C7, C8
22
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8.3.5 3.3-VIN, LDO Configuration
This design example describes a 3.3-VIN, LDO configuration application.
R1
10 kW
TPS51200
2.5 V
VVLDOIN = VVLDOREF = 2.5 V
VVLDO = 1.8 V
1
2
REFIN
VIN 10
3.3 VIN
R2
C4
3.86 kW 1000 pF
R3
100 kW
C6
4.7 mF
VLDOIN PGOOD
9
PGOOD
C7
10 mF
C8
10 mF
3
4
5
VO
GND
EN
8
7
6
C1
C2
C3
PGND
ENABLE
REFOUT
10 mF 10 mF 10 mF
VOSNS REFOUT
C5
0.1 mF
UDG-08033
Copyright © 2016, Texas Instruments Incorporated
Figure 28. 3.3-VIN, LDO Configuration
Table 6. 3.3-VIN, LDO Configuration List of Materials
REFERENCE
DESIGNATOR
DESCRIPTION
SPECIFICATION
PART NUMBER
MANUFACTURER
R1
3.86 kΩ
R2
Resistor
10 kΩ
R3
100 kΩ
C1, C2, C3
C4
10 μF, 6.3 V
1000 pF
GRM21BR70J106KE76L
Murata
C5
Capacitor
0.1 μF
C6
4.7 μF, 6.3 V
10 μF, 6.3 V
GRM21BR60J475KA11L
GRM21BR70J106KE76L
Murata
Murata
C7, C8
Copyright © 2016, Texas Instruments Incorporated
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8.3.6 3.3-VIN, DDR3 Configuration with LFP
This design example describes a 3.3-VIN, DDR3 configuration with LFP application.
R1
10 kW
TPS51200
1
2
REFIN
VIN 10
3.3 VIN
VVDDQ = 1.5 V
VVLDOIN = VVDDQ = 1.5 V
VVTT = 0.75 V
R2
10 kW
C4
1000 pF
R3
100 kW
C6
4.7 mF
VLDOIN PGOOD
9
PGOOD
C7
10 mF
C8
10 mF
3
4
5
VO
GND
EN
8
7
6
R4(1)
C1
C2
C3
PGND
SLP_S3
VTTREF
10 mF 10 mF 10 mF
VOSNS REFOUT
C5
0.1 mF
C9(1)
UDG-08034
Copyright © 2016, Texas Instruments Incorporated
Figure 29. 3.3-VIN, DDR3 Configuration with LFP
Table 7. 3.3-VIN, DDR3 Configuration with LFP List of Materials
REFERENCE
DESIGNATOR
DESCRIPTION
SPECIFICATION
PART NUMBER
MANUFACTURER
R1, R2
10 kΩ
R3
Resistor
100 kΩ
R4(1)
C1, C2, C3
C4
10 μF, 6.3 V
1000 pF
GRM21BR70J106KE76L
Murata
C5
0.1 μF
Capacitor
C6
4.7 μF, 6.3 V
10 μF, 6.3 V
GRM21BR60J475KA11L
GRM21BR70J106KE76L
Murata
Murata
C7, C8
C9(1)
(1) Choose values for R4 and C9 to reduce the parasitic effect of the trace (between VO and the output MLCCs) and the output capacitors
(ESR and ESL).
24
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9 Power Supply Recommendations
The TPS51200-EP device is designed to operate from an input bias voltage from 2.375 V to 3.5 V, with LDO
input from 1.1 V to 3.5 V. Refer to Figure 17 and Figure 18 for recommended power-up sequence. Maintain an
EN voltage equal or lower than VVIN at all times. VLDOIN can ramp up earlier than VIN if the sequence in
Figure 17 and Figure 18 cannot be used. The input supplies should be well regulated. VLDOIN decoupling
capacitance
of 2 × 10 µF is recommended, and VIN decoupling capacitance of 1 × 4.7 µF is recommended.
10 Layout
10.1 Layout Guidelines
Consider the following points before starting the TPS51200-EP device layout design.
•
•
•
The input bypass capacitor for VLDOIN should be placed as close as possible to the pin with short and wide
connections.
The output capacitor for VO should be placed close to the pin with short and wide connection in order to
avoid additional ESR and/or ESL trace inductance.
Connect VOSNS to the positive node of each VO output capacitor as a separate trace from the high-current
power line. This configuration is strongly recommended to avoid additional ESR and/or ESL. If sensing the
voltage at the point of the load is required, attach each output capacitor at that point. This layout design
minimizes any additional ESR and/or ESL of ground trace between the GND pin and each output capacitor.
•
•
Consider adding low-pass filter at VOSNS if the ESR of any VO output capacitor is larger than 2 mΩ.
REFIN can be connected separately from VLDOIN. Remember that this sensing potential is the reference
voltage of REFOUT. Avoid any noise-generating lines.
•
•
Tie the negative node of each VO output capacitor to the REFOUT capacitor by avoiding common impedance
to the high current path of the VO source and sink current.
The GND and PGND pins should be connected to the thermal land underneath the die pad with multiple vias
connecting to the internal system ground planes (for better result, use at least two internal ground planes).
Use as many vias as possible to reduce the impedance between PGND or GND and the system ground
plane. Also, place bulk capacitors close to the DIMM load point, route the VOSNS to the DIMM load sense
point.
•
•
In order to effectively remove heat from the package, properly prepare the thermal land. Apply solder directly
to the thermal pad. The wide traces of the component and the side copper connected to the thermal land pad
help to dissipate heat. Connected the numerous vias that are 0.33 mm in diameter from the thermal land to
any internal and solder-side ground plane to increase dissipation.
Consult the TPS51200-EP-EVM User's Guide (SLUU323) for detailed layout recommendations.
Copyright © 2016, Texas Instruments Incorporated
25
TPS51200-EP
ZHCSF57 –JUNE 2016
www.ti.com.cn
10.2 Layout Example
VDDQ Trace
VIN Trace
To
GND
VLDOIN
Plane
GND
PGOOD Trace
EN Trace
VTT Sense Trace,
terminate near the load
VTT
Figure 30. Layout Recommendation
10.3 Thermal Design Considerations
Because the TPS51200-EP is a linear regulator, the VO current flows in both source and sink directions, thereby
dissipating power from the device. When the device is sourcing current, the voltage difference shown in
Equation 4 calculates the power dissipation.
PD _ SRC = (VVLDOIN - VVO ) ´ IO _ SRC
(4)
In this case, if the VLDOIN pin is connected to an alternative power supply lower than the VDDQ voltage, overall
power loss can be reduced. During the sink phase, the device applies the VO voltage across the internal LDO
regulator. Equation 5 calculates the power dissipation, PD_SNK
.
PD _ SNK = VVO ´ ISNK
(5)
Because the device does not sink and source current at the same time and the I/O current may vary rapidly with
time, the actual power dissipation should be the time average of the above dissipations over the thermal
relaxation duration of the system. The current used for the internal current control circuitry from the VIN supply
and the VLDOIN supply are other sources of power consumption. This power can be estimated as 5 mW or less
during normal operating conditions and must be effectively dissipated from the package.
26
Copyright © 2016, Texas Instruments Incorporated
TPS51200-EP
www.ti.com.cn
ZHCSF57 –JUNE 2016
Thermal Design Considerations (continued)
Maximum power dissipation allowed by the package is calculated by Equation 6.
TJ(max) - TA(max)
PPKG
=
qJA
where
•
•
•
TJ(max) is 125°C.
TA(max) is the maximum ambient temperature in the system.
θJA is the thermal resistance from junction to ambient.
(6)
NOTE
Because Equation 6 demonstrates the effects of heat spreading in the ground plane, use it
as a guideline only. Do not use Equation 6 to estimate actual thermal performance in real
application environments.
In an application where the device is mounted on PCB, TI strongly recommends using ψJT and ψJB, as explained
in the section pertaining to estimating junction temperature in the Semiconductor and IC Package Thermal
Metrics application report, SPRA953. Using the thermal metrics ψJT and ψJB, as shown in the Thermal
Information table, estimate the junction temperature with corresponding formulas shown in Equation 7. The older
θJC top parameter specification is listed as well for the convenience of backward compatibility.
TJ = TT + YJT ´ PD
(7)
TJ = TB + YJB ´ PD
where
•
•
•
PD is the power dissipation shown in Equation 4 and Equation 5.
TT is the temperature at the center-top of the IC package.
TB is the PCB temperature measured 1-mm away from the thermal pad package on the PCB surface (see
Figure 32).
(8)
NOTE
Both TT and TB can be measured on actual application boards using a thermo-gun (an
infrared thermometer). For more information about measuring TT and TB, see the
application report Using New Thermal Metrics (SBVA025).
.
TT on top of package
Land Pad
3 mm x 1.9 mm
TB on PCB surface
Exposed Thermal
Die Pad,
2.48 mm x 1.74 mm
1 mm
UDG-08018
Figure 31. Recommended Land Pad Pattern
Figure 32. Package Thermal Measurement
版权 © 2016, Texas Instruments Incorporated
27
TPS51200-EP
ZHCSF57 –JUNE 2016
www.ti.com.cn
11 器件和文档支持
11.1 器件支持
11.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.1.2 开发支持
11.1.2.1 评估模块
评估模块 (EVM) 可与 TPS51200-EP 器件配套使用，协助评估电路初始性能。TPS51200-EPEVM 评估模块及相关
用户指南（文献编号：SLUU323）可在德州仪器 (TI) 网站的产品文件夹下或直接从 TI eStore 获取。
11.1.2.2 Spice 模型
分析模拟电路和系统的性能时，使用
TPS51200-EP 的 SPICE 模型。
SPICE
模型对电路性能进行计算机仿真非常有用。点击此处可获取
11.2 文档支持
11.2.1 相关文档
•
•
•
•
《使用新的热指标》，SBVA025
《半导体和 IC 封装热指标》，SPRA953
《使用 TPS51200-EP EVM 灌/拉电流 DDR 终端稳压器》，SLUU323
有关 TPS51100 器件的更多信息，请参见 ti.com 上的产品文件夹。
11.3 接收文档更新通知
如需接收文档更新通知，请访问 www.ti.com.cn 网站上的器件产品文件夹。点击右上角的提醒我 (Alert me) 注册
后，即可每周定期收到已更改的产品信息。有关更改的详细信息，请查阅已修订文档中包含的修订历史记录。
11.4 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.5 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.6 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
28
版权 © 2016, Texas Instruments Incorporated
TPS51200-EP
www.ti.com.cn
ZHCSF57 –JUNE 2016
11.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 机械、封装和可订购信息
以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对
本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
版权 © 2016, Texas Instruments Incorporated
29
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都遵循在订单确认时所提供的TI 销售条款与条件。
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IMPORTANT NOTICE
邮寄地址： 上海市浦东新区世纪大道1568 号，中建大厦32 楼邮政编码： 200122
Copyright © 2016, 德州仪器半导体技术（上海）有限公司
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS51200MDRCTEP
V62/16610-01XE
ACTIVE
ACTIVE
VSON
VSON
DRC
DRC
10
10
250
250
RoHS & Green
RoHS & Green
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
-55 to 125
-55 to 125
1200M
1200M
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
GENERIC PACKAGE VIEW
DRC 10
3 x 3, 0.5 mm pitch
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4226193/A
www.ti.com
PACKAGE OUTLINE
DRC0010J
VSON - 1 mm max height
SCALE 4.000
PLASTIC SMALL OUTLINE - NO LEAD
3.1
2.9
B
A
PIN 1 INDEX AREA
3.1
2.9
1.0
0.8
C
SEATING PLANE
0.08 C
0.05
0.00
1.65 0.1
2X (0.5)
(0.2) TYP
EXPOSED
THERMAL PAD
4X (0.25)
5
6
2X
2
11
SYMM
2.4 0.1
10
1
8X 0.5
0.30
0.18
10X
SYMM
PIN 1 ID
0.1
C A B
C
(OPTIONAL)
0.05
0.5
0.3
10X
4218878/B 07/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
DRC0010J
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(1.65)
(0.5)
10X (0.6)
1
10
10X (0.24)
11
(2.4)
(3.4)
SYMM
(0.95)
8X (0.5)
6
5
(R0.05) TYP
(
0.2) VIA
TYP
(0.25)
(0.575)
SYMM
(2.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
EXPOSED METAL
EXPOSED METAL
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
SOLDER MASK
DEFINED
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4218878/B 07/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
DRC0010J
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
2X (1.5)
(0.5)
SYMM
EXPOSED METAL
TYP
11
10X (0.6)
1
10
(1.53)
10X (0.24)
2X
(1.06)
SYMM
(0.63)
8X (0.5)
6
5
(R0.05) TYP
4X (0.34)
4X (0.25)
(2.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 11:
80% PRINTED SOLDER COVERAGE BY AREA
SCALE:25X
4218878/B 07/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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