TPS51225BRUKR [TI]
Dual Synchronous, Step-Down Controller with 5-V and 3.3-V LDOs; 双同步，降压型控制器，带有5 - V和3.3 V的LDO
| 型号： | TPS51225BRUKR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Dual Synchronous, Step-Down Controller with 5-V and 3.3-V LDOs |
| 文件： | 总31页 (文件大小：1291K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS51225, TPS51225B, TPS51225C
www.ti.com
SLUSAV0A –JANUARY 2012–REVISED JUNE 2012
Dual Synchronous, Step-Down Controller with 5-V and 3.3-V LDOs
Check for Samples: TPS51225, TPS51225B, TPS51225C
1
FEATURES
APPLICATIONS
2
•
•
Input Voltage Range: 5.5 V to 24 V
•
•
Notebook Computers
Output Voltages: 5 V and 3.3 V (Adjustable
Range ±10%)
Netbook, Tablet Computers
DESCRIPTION
The TPS51225/B/C is
•
•
•
•
Built-in, 100-mA, 5-V and 3.3-V LDOs
Clock Output for Charge-Pump
±1% Reference Accuracy
a
cost-effective, dual-
synchronous buck controller targeted for notebook
system-power supply solutions. It provides 5-V and
3.3-V LDOs and requires few external components.
The 260-kHz VCLK output can be used to drive an
external charge pump, generating gate drive voltage
for the load switches without reducing the main
converter efficiency. The TPS51225/B/C supports
high efficiency, fast transient response and provides a
combined power-good signal. Adaptive on-time, D-
CAP™ control provides convenient and efficient
operation. The device operates with supply input
voltage ranging from 5.5 V to 24 V and supports
Adaptive On-time D-CAP™ Mode Control
Architecture with 300kHz/355kHz Frequency
Setting
•
•
•
•
Auto-skip Light Load Operation (TPS51225/C)
OOA Light Load Operation (TPS51225B)
Internal 0.8-ms Voltage Servo Soft-Start
Low-Side RDS(on) Current Sensing Scheme with
4500 ppm/°C Temperature Coefficient
•
•
Built-in Output Discharge Function
output voltages of 5.0
V
and 3.3 V. The
TPS51225/B/C is available in a 20-pin, 3 mm × 3
mm, QFN package and is specified from –40°C to
85°C.
Separate Enable Input for Switchers
(TPS51225/B/C)
•
•
•
•
•
Dedicated OC Setting Terminals
Power Good Indicator
OVP/UVP/OCP Protection
Non-latch UVLO/OTP Protection
20-Pin, 3 mm × 3 mm, QFN (RUK)
ORDERING INFORMATION(1)
ORDERABLE
DEVICE NUMBER
ENABLE
FUNCTION
OUTPUT
SKIP MODE
ALWAYS ON-LDO
PACKAGE
QUANTITY
SUPPLY
Tape and Reel
Mini reel
TPS51225RUKR
TPS51225RUKT
TPS51225BRUKR
TPS51225BRUKT
TPS51225CRUKR
TPS51225CRUKT
3000
250
EN1/ EN2
EN1/ EN2
EN1/ EN2
Auto-skip
VREG3
PLASTIC Quad
Flat Pack
(20 pin QFN)
Tape and Reel
Mini reel
3000
250
OOA
VREG3
Tape and Reel
Mini reel
3000
250
Auto-skip
VREG3 & VREG5
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
D-CAP, Out-of-Audio are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2012, Texas Instruments Incorporated
TPS51225, TPS51225B, TPS51225C
SLUSAV0A –JANUARY 2012–REVISED JUNE 2012
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
TYPICAL APPLICATION DIAGRAM (TPS51225/TPS51225B)
VIN
5.5 V to 24 V
TPS51225
TPS51225B
VIN
VBST1
DRVH1
VBST2
DRVH2
VOUT
5 V
VOUT
3.3 V
SW1
SW2
DRVL1
VO1
DRVL2
VFB1
CS1
VFB2
CS2
VCLK
EN1
PGOOD
EN2
PGOOD
VOUT
15 V
EN-5V
5 V
EN 3.3 V
VREG5
VREG3
3.3-V Always ON
1 mF
1 mF
UDG-11182
TYPICAL APPLICATION DIAGRAM (TPS51225C)
VIN
5.5 V to 24 V
TPS51225C
VIN
VBST1
DRVH1
VBST2
DRVH2
VOUT
5 V
VOUT
3.3 V
SW1
SW2
DRVL1
VO1
DRVL2
VFB1
CS1
VFB2
CS2
EN 5 V
EN1
PGOOD
EN2
PGOOD
VCLK
VREG5
EN 3.3 V
VOUT
15 V
VREG3
3.3-V Always ON
5 V
Always ON
1 mF
1 mF
UDG-12001
2
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Product Folder Link(s) :TPS51225 TPS51225B TPS51225C
TPS51225, TPS51225B, TPS51225C
www.ti.com
SLUSAV0A –JANUARY 2012–REVISED JUNE 2012
ABSOLUTE MAXIMUM RATINGS(1)
over operating free-air temperature range (unless otherwise noted)
VALUE
UNIT
MIN
–0.3
–0.3
–6.0
–0.3
–0.3
–0.3
–0.3
–6.0
–0.3
–2.5
–0.3
–2.5
–0.3
–0.3
MAX
32
6
VBST1, VBST2
VBST1, VBST2(3)
SW1, SW2
26
26
6
Input voltage(2)
VIN
V
EN1, EN2
VFB1, VFB2
3.6
6
VO1
DRVH1, DRVH2
DRVH1, DRVH2(3)
DRVH1, DRVH2(3) (pulse width < 20 ns)
32
6
6
Output voltage(2)
DRVL1, DRVL2
6
V
DRVL1, DRVL2 (pulse width < 20 ns)
PGOOD, VCLK, VREG5
VREG3, CS1, CS2
6
6
3.6
2
HBM QSS 009-105 (JESD22-A114A)
CDM QSS 009-147 (JESD22-C101B.01)
Electrostatic
discharge
kV
1
Junction temperature, TJ
150
–55
°C
°C
Storage temperature, TST
150
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to the network ground terminal unless otherwise noted
(3) Voltage values are with respect to SW terminals.
THERMAL INFORMATION
TPS51225
TPS51225B
THERMAL METRIC(1)
UNITS
TPS51225C
20-PIN RUK
94.1
θJA
Junction-to-ambient thermal resistance
θJCtop
θJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
58.1
64.3
°C/W
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
31.8
ψJB
58.0
θJCbot
5.9
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
Copyright © 2012, Texas Instruments Incorporated
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TPS51225, TPS51225B, TPS51225C
SLUSAV0A –JANUARY 2012–REVISED JUNE 2012
www.ti.com
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
5.5
TYP MAX UNIT
Supply voltage
Input voltage(1)
VIN
24
30
VBST1, VBST2
VBST1, VBST2(2)
SW1, SW2
–0.1
–0.1
–5.5
–0.1
–0.1
–0.1
–5.5
–0.1
–0.1
–0.1
–0.1
–40
5.5
24
5.5
3.5
5.5
30
V
EN1, EN2
VFB1, VFB2
VO1
DRVH1, DRVH2
DRVH1, DRVH2(2)
5.5
5.5
5.5
3.5
85
Output voltage(1) DRVL1, DRVL2
V
PGOOD, VCLK, VREG5
VREG3, CS1, CS2
Operating free-air temperature, TA
°C
(1) All voltage values are with respect to the network ground terminal unless otherwise noted.
(2) Voltage values are with respect to the SW terminal.
4
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SLUSAV0A –JANUARY 2012–REVISED JUNE 2012
ELECTRICAL CHARACTERISTICS
over operating free-air temperature range, VVIN= 12 V, VVO1= 5 V, VVFB1= VVFB2= 2 V, VEN1= VEN2= 3.3 V (unless otherwise
noted)
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
SUPPLY CURRENT
IVIN1
IVIN2
IVO1
VIN supply current-1
VIN supply current-2
VO1 supply current
TA = 25°C, No load, VVO1=0 V
860
30
μA
μA
μA
TA = 25°C, No load
TA = 25°C, No load, VVFB1= VVFB2=2.05 V
900
TA = 25°C, No load, VVO1= 0 V,
VEN1= VEN2= 0 V
TPS51225
TPS51225B
IVIN(STBY)
IVIN(STBY)
VIN stand-by current
VIN stand-by current
95
μA
μA
TA = 25°C, No load, VVO1=0 V, VEN1=VEN2=0V
(TPS51225C)
180
INTERNAL REFERENCE
TA = 25°C
1.99
1.98
2.00
2.00
2.01
2.02
V
V
VFBx
VFB regulation voltage
VREG5 OUTPUT
TA = 25°C, No load, VVO1= 0 V
4.9
4.85
4.85
100
5.0
5.00
5.00
150
1.8
5.1
5.10
5.10
VVREG5
VREG5 output voltage
VVIN> 7 V , VVO1= 0 V, IVREG5< 100 mA
VVIN > 5.5 V , VVO1= 0 V, IVREG5< 35 mA
VVO1= 0 V, VVREG5= 4.5 V, VVIN= 7 V
TA = 25°C, VVO1= 5 V, IVREG5= 50 mA
V
IVREG5
RV5SW
VREG3 OUTPUT
VREG5 current limit
mA
5-V switch resistance
Ω
TA = 25°C, No load, VVO1= 0 V
3.267
3.217
3.234
3.267
100
3.300
3.300
3.300
3.300
150
3.333
3.383
3.366
3.333
VVIN > 7 V , VVO1= 0 V, IVREG3< 100 mA
5.5 V < VVIN , VVO1= 0 V, IVREG3< 35 mA
VVREG3
VREG3 output voltage
V
0°C ≤ TA ≤ 85°C, VVIN > 5.5 V, VVO1= 0 V, IVREG3< 35 mA
IVREG3
VREG3 current limit
VVO1= 0 V, VVREG3= 3.0 V, VVIN= 7 V
mA
DUTY CYCLE and FREQUENCY CONTROL
fsw1
CH1 frequency(1)
CH2 frequency(1)
Minimum off-time
TA = 25°C, VVIN= 20 V
TA = 25°C, VVIN= 20 V
TA = 25°C
240
280
200
300
355
300
360
430
500
kHz
kHz
ns
fSW2
TOFF(MIN)
MOSFET DRIVERS
Source, (VVBST – VDRVH) = 0.25 V, (VVBST – VSW) = 5 V
Sink, (VDRVH – VSW) = 0.25 V, (VVBST – VSW) = 5 V
Source, (VVREG5 – VDRVL) = 0.25 V, VVREG5 = 5 V
Sink, VDRVL = 0.25 V, VVREG5= 5 V
3.0
1.9
3.0
0.9
12
RDRVH
RDRVL
tD
DRVH resistance
Ω
Ω
DRVL resistance
Dead time
DRVH-off to DRVL-on
ns
DRVL-off to DRVH-on
20
INTERNAL BOOT STRAP SWITCH
RVBST (ON) Boost switch on-resistance
IVBSTLK VBST leakage current
CLOCK OUTPUT
TA = 25°C, IVBST = 10 mA
TA = 25°C
13
Ω
1
µA
RVCLK (PU)
RVCLK (PD)
fCLK
VCLK on-resistance (pull-up)
TA = 25°C
TA = 25°C
TA = 25°C
10
10
Ω
VCLK on-resistance (pull-down)
Clock frequency
260
kHz
(1) Ensured by design. Not production tested.
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TPS51225, TPS51225B, TPS51225C
SLUSAV0A –JANUARY 2012–REVISED JUNE 2012
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ELECTRICAL CHARACTERISTICS
over operating free-air temperature range, VVIN= 12 V, VVO1= 5 V, VVFB1= VVFB2= 2 V, VEN1= VEN2= 3.3 V (unless otherwise
noted)
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
OUTPUT DISCHARGE
TA = 25°C, VVO1 = 0.5 V
VEN1 = VEN2 = 0 V
RDIS1
CH1 discharge resistance
35
Ω
TA = 25°C, VSW2 = 0.5 V
VEN1 = VEN2 = 0 V
RDIS2
RDIS2
CH2 discharge resistance
CH2 discharge resistance
75
70
Ω
Ω
TA = 25°C, VSW2 = 0.5 V, VEN1 = VEN2 = 0 V (TPS51225C)
SOFT START OPERATION
tSS
Soft-start time
From ENx="Hi" and VVREG5 > VUVLO5 to VOUT = 95%
VOUT= 0% to VOUT = 95%, VVREG5 = 5 V
0.91
0.78
ms
ms
tSSRAMP
Soft-start time (ramp-up)
POWER GOOD
Lower (rising edge of PG-in)
Hysteresis
92.5% 95.0% 97.5%
5%
VPGTH
PG threshold
Upper (rising edge of PG-out)
Hysteresis
107.5% 110.0% 112.5%
5%
6.5
1
IPGMAX
IPGLK
PG sink current
PG leak current
PG delay
VPGOOD = 0.5 V
mA
µA
ms
VPGOOD = 5.5 V
tPGDEL
From PG lower threshold (95%=typ) to PG flag high
0.7
CURRENT SENSING
ICS
CS source current
TA = 25°C, VCS= 0.4 V
On the basis of 25°C
9
10
11
μA
ppm/°C
V
TCCS
VCS
VZC
CS current temperature coefficient(1)
CS Current limit setting range
Zero cross detection offset
4500
0.2
–1
2
3
TA = 25°C
1
mV
LOGIC THRESHOLD
VENX(ON)
VENX(OFF)
IEN
EN threshold high-level
SMPS on level
SMPS off level
VENx= 3.3 V
1.6
1
V
V
EN threshold low-level
EN input current
0.3
–1
µA
OUTPUT OVERVOLTAGE PROTECTION
VOVP
OVP trip threshold
112.5% 115.0% 117.5%
0.5
tOVPDLY
OVP propagation delay
TA = 25°C
µs
OUTPUT UNDERVOLTAGE PROTECTION
VUVP
UVP trip Threshold
UVP prop delay
55%
60%
250
65%
tUVPDLY
tUVPENDLY
UVLO
µs
UVP enable delay
From ENx ="Hi", VVREG5 = 5 V
1.35
ms
Wake up
Hysteresis
Wake up
Hysteresis
Wake up
Hysteresis
4.58
0.5
V
V
V
V
V
V
VUVL0VIN
VUVLO5
VUVLO3
VIN UVLO Threshold
4.38
0.4
VREG5 UVLO Threshold
VREG3 UVLO Threshold
3.15
0.15
OVER TEMPERATURE PROTECTION
TOTP
OTP threshold(1)
Shutdown temperature
Hysteresis
155
10
°C
(1) Ensured by design. Not production tested.
6
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Product Folder Link(s) :TPS51225 TPS51225B TPS51225C
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SLUSAV0A –JANUARY 2012–REVISED JUNE 2012
DEVICE INFORMATION
RUK PACKAGE
20 PINS
(TOP VIEW)
20
19
18
17
16
1
2
3
4
5
15
14
13
12
11
CS1
VFB1
DRVL1
VO1
TPS51225
TPS51225B
TPS51225C
VREG3
VFB2
VREG5
VIN
Thermal Pad
CS2
DRVL2
6
7
8
9
10
PIN FUNCTIONS
PIN NO.
TPS51225
TPS51225B
TPS51225C
NAME
I/O
DESCRIPTION
CS1
1
5
O
O
O
O
O
O
I
Sets the channel 1 OCL trip level.
Sets the channel 2OCL trip level.
High-side driver output
High-side driver output
Low-side driver output
Low-side driver output
Channel 1 enable.
CS2
DRVH1
DRVH2
DRVL1
DRVL2
EN1
16
10
15
11
20
6
EN2
I
Channel 2 enable.
PGOOD
SW1
7
O
O
O
I
Power good output flag. Open drain output. Pull up to external rail via a resistor
Switch-node connection.
18
8
SW2
Switch-node connection.
VBST1
VBST2
VCLK
VFB1
VFB2
17
9
Supply input for high-side MOSFET (bootstrap terminal). Connect capacitor from this pin to SW
terminal.
I
19
2
O
I
Clock output for charge pump.
Voltage feedback Input
4
I
Power conversion voltage input. Apply the same voltage as drain voltage of high-side MOSFETs of
channel 1 and channel 2.
VIN
12
I
VO1
14
3
I
Output voltage input, 5-V input for switch-over.
3.3-V LDO output.
VREG3
VREG5
O
O
13
5-V LDO output.
Thermal
pad
—
—
GND terminal, solder to the ground plane
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TPS51225, TPS51225B, TPS51225C
SLUSAV0A –JANUARY 2012–REVISED JUNE 2012
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FUNCTIONAL BLOCK DIAGRAM (TPS51225/B/C)
TPS51225
TPS51225B
TPS51225C
VIN
+
+
155°C/145°C
4.5 V/4.0 V
VO1
+
+
VREG5
+
+
2 V
+
VREG3
VCLK
Osc
EN1
EN2
VBST1
DRVH1
SW1
VDRV VIN VDD VO_OK
EN
VDD VDRV VIN
VBST2
DRVH2
SW2
EN
Switcher
FAULT
Controller
Switcher
Controller
(CH2)
FAULT
REF
(CH1)
DRVL1
VFB1
REF
PGOOD
DCHG
DRVL2
VFB2
PGOOD
DCHG
CS1
PGND GND
GND PGND
CS2
PGOOD
GND
(Thermal Pad)
UDG-12002
8
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SLUSAV0A –JANUARY 2012–REVISED JUNE 2012
SWITCHER CONTROLLER BLOCK DIAGRAM
TPS51225
TPS51225B
TPS51225C
VREF +5%/10%
+
+
+
VREF –40%
UV
Control Logic
+
OV
VREF +15%
VREF –5%/10%
VFB
REF
PWM
+
+
SS Ramp Comp
SKIP
VIN
HS
XCON
OC
+
10 µA
CS
+
LS
NOC
+
One-Shot
Discharge
PGOOD
GND
+
ZC
U
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DETAILED DESCRIPTION
PWM Operations
The main control loop of the switch mode power supply (SMPS) is designed as an adaptive on-time pulse width
modulation (PWM) controller. It supports a proprietary D-CAP™ mode. D-CAP™ mode does not require external
conpensation circuit and is suitable for low external component count configuration when used with appropriate
amount of ESR at the output capacitor(s).
At the beginning of each cycle, the synchronous high-side MOSFET is turned on, or enters the ON state. This
MOSFET is turned off, or enters the ‘OFF state, after the internal, one-shot timer expires. The MOSFET is turned
on again when the feedback point voltage, VVFB, decreased to match the internal 2-V reference. The inductor
current information is also monitored and should be below the overcurrent threshold to initiate this new cycle. By
repeating the operation in this manner, the controller regulates the output voltage. The synchronous low-side
(rectifying) MOSFET is turned on at the beginning of each OFF state to maintain a minimum of conduction loss.
The low-side MOSFET is turned off before the high-side MOSFET turns on at next switching cycle or when
inductor current information detects zero level. This enables seamless transition to the reduced frequency
operation during light-load conditions so that high efficiency is maintained over a broad range of load current.
Adaptive On-Time/ PWM Frequency Control
Bacause the TPS51225/B/C does not have a dedicated oscillator for control loop on board, switching cycle is
controlled by the adaptive on-time circuit. The on-time is controlled to meet the target switching frequency by
feed-forwarding the input and output voltage into the on-time one-shot timer. The target switching frequency is
varied according to the input voltage to achieve higher duty operation for lower input voltage application. The
switching frequency of CH1 (5-V output) is 300 kHz during continuous conduction mode (CCM) operation when
VIN = 20 V. The CH2 (3.3-V output) is 355 kHz during CCM when VIN = 20 V.
Light Load Condition in Auto-Skip Operation (TPS51225/C)
The TPS51225/C automatically reduces switching frequency during light-load conditions to maintain high
efficiency. This reduction of frequency is achieved smoothly and without an increase in output voltage ripple. A
more detailed description of this operation is as follows. As the output current decreases from heavy-load
condition, the inductor current is also reduced and eventually approaches valley zero current, which is the
boundary between continuous conduction mode and discontinuous conduction mode. The rectifying MOSFET is
turned off when this zero inductor current is detected. As the load current further decreases, the converter runs in
discontinuous conduction mode and it takes longer and longer to discharge the output capacitor to the level that
requires the next ON cycle. The ON time is maintained the same as that in the heavy-load condition. In reverse,
when the output current increase from light load to heavy load, the switching frequency increases to the preset
value as the inductor current reaches to the continuous conduction. The transition load point to the light load
operation IOUT(LL) (i.e. the threshold between continuous and discontinuous conduction mode) can be calculated
as shown in Equation 1.
V
- V
´ V
)
OUT OUT
(
1
IN
I
=
´
OUT LL
( )
2´L ´ f
V
IN
SW
where
•
fSW is the PWM switching frequency
(1)
Switching frequency versus output current during light-load conditions is a function of inductance (L), input
voltage (VIN) and output voltage (VOUT), but it decreases almost proportional to the output current from the
IOUT(LL)
.
10
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Light-Load Condition in Out-of-Audio™ Operation (TPS51225B)
Out-of-Audio™ (OOA) light-load mode is a unique control feature that keeps the switching frequency above
acoustic audible frequencies toward a virtual no-load condition. During Out-of-Audio™ operation, the OOA
control circuit monitors the states of both MOSFETs and forces them to transition into the ON state if both of
MOSFETs are off for more than 40 μs. When both high-side and low-side MOSFETs are off for 40 µs during a
light-load condition, the operation mode is changed to FCCM. This mode change initiates the low-side MOSFET
on and pulls down the output voltage. Then, the high-side MOSFET is turned on and stops switching again.
Table 1. SKIP Mode Operation (TPS51225/B/C)
SKIP MODE OPERATION
TPS51225
TPS51225B
TPS51225C
Auto-skip
OOA
Auto-skip
D-CAP™ Mode
From small-signal loop analysis, a buck converter using D-CAP™ mode can be simplified as shown in Figure 1.
TPS51225
TPS51225B
TPS51225C
Switching Modulator
VIN
DRVH
DRVL
R1
R2
L
VFB
VOUT
PWM
Control
Logic
and
+
IOUT
IIND
Divider
IC
+
VREF
ESR
RLOAD
Voltage
Divider
VC
COUT
Output
Capacitor
UDG-12010
Figure 1. Simplifying the Modulator
The output voltage is compared with internal reference voltage after divider resistors, R1 and R2. The PWM
comparator determines the timing to turn onthe high-side MOSFET. The gain and speed of the comparator is
high enough to keep the voltage at the beginning of each ON cycle substantially constant. For the loop stability,
the 0dB frequency, ƒ0, defined in Equation 2 must be lower than 1/4 of the switching frequency.
f
1
SW
f =
£
0
2p´ESR ´C
4
OUT
(2)
As ƒ0 is determined solely by the output capacitor characteristics, the loop stability during D-CAP™ mode is
determined by the capacitor chemistry. For example, specialty polymer capacitors have output capacitance in the
order of several hundred micro-Farads and ESR in range of 10 milli-ohms. These yield an f0 value on the order
of 100 kHz or less and the loop is stable. However, ceramic capacitors have ƒ0 at more than 700 kHz, which is
not suitable for this operational mode.
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Enable and Powergood
VREG3 is an always-on regulator (TPS51225/B), VREG3/VREG5 are always-on regulators (TPS51225C), when
the input voltage is beyond the UVLO threshold it turns ON. VREG5 is turned ON when either EN1 or EN2
enters the ON state. The VCLK signal initiates when EN1 enters the ON state (TPS51225/B/C). Enable states
are shown in Table 2 through Table 3.
Table 2. Enabling/PGOOD State (TPS51225/B)
EN1
OFF
ON
EN2
OFF
OFF
ON
VREG5
OFF
ON
VREG3
ON
CH1 (5Vout)
OFF
CH2 (3.3Vout)
VCLK
OFF
ON
PGOOD
Low
OFF
OFF
ON
ON
ON
Low
OFF
ON
ON
ON
OFF
OFF
ON
Low
ON
ON
ON
ON
ON
High
Table 3. Enabling/PGOOD State (TPS51225C)
EN1
OFF
ON
EN2
OFF
OFF
ON
VREG5
ON
VREG3
ON
CH1 (5Vout)
OFF
CH2 (3.3Vout)
VCLK
OFF
ON
PGOOD
Low
OFF
OFF
ON
ON
ON
ON
Low
OFF
ON
ON
ON
OFF
OFF
ON
Low
ON
ON
ON
ON
ON
High
VIN-UVLO_threshold
VIN
VREG3
EN_threshold
EN1
VREG5-UVLO_threshold
VREG5
95% of VOUT
Soft-Start Time (t
)
SS
5-V VOUT
Soft-Start Time
(t
)
SS(ramp)
EN_threshold
EN2
3.3-V VOUT
PGOOD
95% of Vout
Soft-Start Time (t
)
SS
PGOOD
Delay
tPGDEL
Soft-Start Time
(t
)
SS(ramp)
UDG-12013
Figure 2. TPS51225 and TPS51225B Timing
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VIN-UVLO_threshold
2.4 V
VIN
VREG3
VREG5
EN1
EN_threshold
95% of VOUT
Soft-Start Time (t
)
SS
5-V VOUT
Soft-Start Time
(t
)
SS(ramp)
EN_threshold
EN2
3.3-V VOUT
PGOOD
95% of Vout
Soft-Start Time (t
)
SS
PGOOD
Delay
tPGDEL
Soft-Start Time
(t
)
SS(ramp)
UDG-12015
Figure 3. TPS51225C Timing
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Soft-Start and Discharge
The TPS51225/B/C operates an internal, 0.8-ms, voltage servo soft-start for each channel. When the ENx pin
becomes higher than the enable threshold voltage, an internal DAC begins ramping up the reference voltage to
the PWM comparator. Smooth control of the output voltage is maintained during start-up. When ENx becomes
lower than the lower level of threshold voltage, TPS51225/B/C discharges outputs using internal MOSFETs
through VO1 (CH1) and SW2 (CH2).
VREG5/VREG3 Linear Regulators
There are two sets of 100-mA standby linear regulators which output 5 V and 3.3 V, respectively. The VREG5
pin provides the current for the gate drivers. The VREG3 pin functions as the main power supply for the analog
circuitry of the device. VREG3 is an Always ON LDO and TPS51225C has Always ON VREG5. (see )
Add ceramic capacitors with a value of 1 µF or larger (X5R grade or better) placed close to the VREG5 and
VREG3 pins to stabilize LDOs.
The VREG5 pin switchover function is asserted when three conditions are present:
•
•
•
CH1 internal PGOOD is high
CH1 is not in OCL condition
VO1 voltage is higher than VREG5-1V
In this switchover condition, three things occur:
•
•
•
the internal 5-V, LDO regulator is shut off
the VREG5 output is connected to VO1 by internal switchover MOSFET
VREG3 input pass is changed from VIN to VO1
VCLK for Charge Pump
The 260-kHz VCLK signal can be used in the charge pump circuit. The VCLK signal becomes available when
EN1. The VCLK driver is driven by VO1 voltage. In a design that does not require VCLK output, leave the VCLK
pin open.
Overcurrent Protection
TPS51225/B/C has cycle-by-cycle over current limiting control. The inductor current is monitored during the OFF
state and the controller maintains the OFF state during the inductor current is larger than the overcurrent trip
level. In order to provide both good accuracy and cost effective solution, TPS51225/B/C supports temperature
compensated MOSFET RDS(on) sensing. The CSx pin should be connected to GND through the CS voltage
setting resistor, RCS. The CSx pin sources CS current (ICS) which is 10 µA typically at room temperature, and the
CSx terminal voltage (VCS= RCS × ICS) should be in the range of 0.2 V to 2 V over all operation temperatures.
ꢀThe trip level is set to the OCL trip voltage (VTRIP) as shown in Equation 3.
R
´I
CS CS
V
=
+1mV
TRIP
8
(3)
The inductor current is monitored by the voltage between GND pin and SWx pin so that SWx pin should be
connected to the drain terminal of the low-side MOSFET properly.The CS pin current has a 4500 ppm/°C
temperature slope to compensate the temperature dependency of the RDS(on). GND is used as the positive
current sensing node so that GND should be connected to the source terminal of the low-side MOSFET.
As the comparison is done during the OFF state, VTRIP sets the valley level of the inductor current. Thus, the load
current at the overcurrent threshold, IOCP, can be calculated as shown in Equation 4.
I
V
IN - VOUT ´ V
)
OUT
IND ripple
(
(
VTRIP
VTRIP
)
1
IOCP
=
+
=
+
´
RDS on
2
RDS on
2´L ´ fSW
V
IN
( )
( )
(4)
In an overcurrent condition, the current to the load exceeds the current to the output capacitor thus the output
voltage tends to fall down. Eventually, it ends up with crossing the undervoltage protection threshold and
shutdown both channels.
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Output Overvoltage/Undervoltage Protection
TPS51225/B/C asserts the overvoltage protection (OVP) when VFBx voltage reaches OVP trip threshold level.
When an OVP event is detected, the controller changes the output target voltage to 0 V. This usually turns off
DRVH and forces DRVL to be on. When the inductor current begins to flow through the low-side MOSFET and
reaches the negative OCL, DRVL is turned off and DRVH is turned on. After the on-time expires, DRVH is turned
off and DRVL is turned on again. This action minimizes the output node undershoot due to LC resonance. When
the VFBx reaches 0V, the driver output is latched as DRVH off, DRVL on. The undervoltage protection (UVP)
latch is set when the VFBx voltage remains lower than UVP trip threshold voltage for 250 µs or longer. In this
fault condition, the controller latches DRVH low and DRVL low and discharges the outputs. UVP detection
function is enabled after 1.35 ms of SMPS operation to ensure startup.
Undervoltage Lockout (UVLO) Protection
TPS51225/B/C has undervoltage lock out protection at VIN, VREG5 and VREG3. When each voltage is lower
than their UVLO threshold voltage, both SMPS are shut-off. They are non-latch protections.
Over-Temperature Protection
TPS51225/B/C features an internal temperature monitor. If the temperature exceeds the threshold value
(typically 155°C), TPS51225/B/C is shut off including LDOs. This is non-latch protection.
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External Components Selection
The external components selection is relatively simple for a design using D-CAP™ mode.
Step 1. Determine the Value of R1 and R2
The recommended R2 value is between 10 kΩ and 20 kΩ. Determine R1 using Equation 5.
V
(
- 0.5´ V
- 2.0
)
RIPPLE
OUT
R1=
´R2
2.0
(5)
Step 2. Choose the Inductor
The inductance value should be determined to give the ripple current of approximately 1/3 of maximum output
current. Larger ripple current increases output ripple voltage, improves signal:noise ratio, and helps ensure stable
operation.
V
(
IN
max
(
- V
´ V
)
V
- V
max
)
´ V
)
OUT
OUT
OUT
(
´
IN
OUT
V
IN(max)
)
(
1
3
L =
´
=
I
´ f
V
I
´ f
SW
SW
IN
max
(
OUT
max
( )
IND ripple
(
)
)
(6)
The inductor also needs to have low DCR to achieve good efficiency, as well as enough room above peak
inductor current before saturation. The peak inductor current can be estimated as shown in Equation 7.
V
(
´
- V
´ V
OUT OUT
IN
max
(
)
)
V
1
TRIP
I
=
+
IND peak
(
)
R
L ´ f
V
IN
(
SW
DS on
max
)
( )
(7)
Step 3. Choose Output Capacitor(s)
Organic semiconductor capacitor(s) or specialty polymer capacitor(s) are recommended. Determine ESR to meet
required ripple voltage above. A quick approximation is as shown in Equation 8.
V
OUT ´ 20mV ´(1-D) 20mV ´L ´ fSW
ESR =
=
2V ´I
2V
IND ripple
(
)
where
•
•
D as the duty-cycle factor
the required output ripple voltage slope is approximately 20 mV per tSW (switching period) in terms of VFB
terminal
(8)
V
VOUT
Slope (1)
Jitter
(2)
(1)
Slope (2)
Jitter
20 mV
V
REF
V
+Noise
REF
t
ON
t
OFF
UDG-12012
Figure 4. Ripple Voltage Slope and Jitter Performance
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Layout Considerations
Good layout is essential for stable power supply operation. Follow these guidelines for an efficient PCB layout.
Placement
•
•
Place voltage setting resistors close to the device pins.
Place bypass capacitors for VREG5 and VREG3 close to the device pins.
Routing (Sensitive analog portion)
•
•
Use small copper space for VFBx. There are short and narrow traces to avoid noise coupling.
Connect VFB resistor trace to the positive node of the output capacitor. Routing inner layer away from power
traces is recommended.
•
Use short and wide trace from VFB resistor to vias to GND (internal GND plane).
Routing (Power portion)
•
•
Use wider/shorter traces of DRVL for low-side gate drivers to reduce stray inductance.
Use the parallel traces of SW and DRVH for high-side MOSFET gate drive in a same layer or on adjoin
layers, and keep them away from DRVL.
•
•
Use wider/ shorter traces between the source terminal of the high-side MOSFET and the drain terminal of the
low-side MOSFET
Thermal pad is the GND terminal of this device. Five or more vias with 0.33-mm (13-mils) diameter connected
from the thermal pad to the internal GND plane should be used to have strong GND connection and help heat
dissipation.
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TYPICAL CHARACTERISTICS
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
60
50
40
30
20
10
0
−40 −25 −10
5
20 35 50 65 80 95 110 125
−40 −25 −10
5
20 35 50 65 80 95 110 125
Junction Temperature (°C)
Junction Temperature (°C)
G001
G002
Figure 5. VIN Supply Current 1 vs. Junction Temperature
Figure 6. VIN Supply Current 2 vs. Junction Temperature
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
300
250
200
150
100
50
TPS51225C Only
20 35 50 65 80 95 110 125
0
−40 −25 −10
−40 −25 −10
5
20 35 50 65 80 95 110 125
5
Junction Temperature (°C)
Junction Temperature (°C)
G003
G004
Figure 7. VO1 Supply Current 1 vs. Junction Temperature
Figure 8. VIN Stand-By Current vs. Junction Temperature
20
18
16
14
12
10
8
310
300
290
280
270
260
250
240
230
220
210
6
4
2
0
−40 −25 −10
5
20 35 50 65 80 95 110 125
−40 −25 −10
5
20 35 50 65 80 95 110 125
Junction Temperature (°C)
Junction Temperature (°C)
G005
G006
Figure 9. CS Source Current vs. Junction Temperature
Figure 10. Clock Frequency vs. Junction Temperature
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TYPICAL CHARACTERISTICS (continued)
100
100
90
80
70
60
50
40
30
20
10
0
Auto−Skip
VVOUT = 5 V
Out−of−Audio
VVOUT = 5 V
90
80
70
60
50
40
VVIN = 8 V
VVIN = 12 V
VVIN = 20 V
VVIN = 8 V
VVIN = 12 V
VVIN = 20 V
0.001
0.01
0.1
1
10
0.001
0.01
0.1
1
10
Output Current (A)
Output Current (A)
G007
G008
Figure 11. Efficiency vs. Output Current
Figure 12. Efficiency vs. Output Current
5.15
5.10
5.05
5.00
4.95
4.90
4.85
5.15
5.10
5.05
5.00
4.95
4.90
4.85
Auto−Skip
VVOUT = 5 V
Out−of−Audio
VVOUT = 5 V
VVIN = 8 V
VVIN = 12 V
VVIN = 20 V
VVIN = 8 V
VVIN = 12 V
VVIN = 20 V
0.001
0.01
0.1
1
10
0.001
0.01
0.1
1
10
Output Current (A)
Output Current (A)
G014
G015
Figure 13. Load Regulation
Figure 14. Load Regulation
100
90
80
70
60
50
40
30
20
100
90
80
70
60
50
40
30
20
10
0
Auto−Skip
VVOUT = 3.3 V
Out−of_Audio
VVOUT = 3.3 V
VVIN = 8 V
VVIN = 12 V
VVIN = 20 V
VVIN = 8 V
VVIN = 12 V
VVIN = 20 V
0.001
0.01
0.1
1
10
0.001
0.01
0.1
1
10
Output Current (A)
Output Current (A)
G010
G011
Figure 15. Efficiency vs. Output Current
Figure 16. Efficiency vs. Output Current
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TYPICAL CHARACTERISTICS (continued)
3.43
3.38
3.33
3.28
3.23
3.43
3.38
3.33
3.28
3.23
Auto−skip
VVOUT = 3.3 V
Out−of−Audio
VVOUT = 3.3 V
VVIN = 8 V
VVIN = 12 V
VVIN = 20 V
VVIN = 8 V
VVIN = 12 V
VVIN = 20 V
0.001
0.01
0.1
1
10
0.001
0.01
0.1
1
10
Output Current (A)
Output Current (A)
G012
G013
Figure 17. Load Regulation
Figure 18. Load Regulation
350
300
250
200
150
100
50
350
300
250
200
150
100
50
VVIN = 8 V
VVIN = 12 V
VVIN = 20 V
VVIN = 8 V
VVIN = 12 V
VVIN = 20 V
Auto−Skip
VVOUT = 5 V
Out−of−Audio
VVOUT = 5 V
0
0
0.001
0.01
0.1
1
10
0.001
0.01
0.1
1
10
Output Current (A)
Output Current (A)
G016
G017
Figure 19. Switching Frequency vs. Output Current
Figure 20. Switching Frequency vs. Output Current
450
450
VVIN = 8 V
VVIN = 12 V
VVIN = 20 V
VVIN = 8 V
VVIN = 12 V
VVIN = 20 V
400
350
300
250
200
150
100
50
400
350
300
250
200
150
100
50
Auto−Skip
VVOUT = 3.3 V
Out−of−Audio
VVOUT = 3.3 V
0
0
0.001
0.01
0.1
1
10
0.001
0.01
0.1
1
10
Output Current (A)
Output Current (A)
G018
G019
Figure 21. Switching Frequency vs. Output Current
Figure 22. Switching Frequency vs. Output Current
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TYPICAL CHARACTERISTICS (continued)
V
V
(2 V/div)
V
V
(2 V/div)
(2 V/div)
OUT1
OUT1
OUT2
(2 V/div)
OUT2
PGOOD (5 V/div)
EN1 = EN2 (5 V/div)
PGOOD (5 V/div)
EN1 = EN2 (5 V/div)
Time (10 ms/div)
Time (400 µs/div)
Figure 23. Start-Up
Figure 24. Output Discharge
V
VIN
= 12 V
V
OUT1
(50 mV/div)
I
3A ßà 8 A
OUT
V
VIN
= 12 V
V
OUT1
(50 mV/div)
I
3A ßà 8 A
OUT
V
OUT2
0 A( 50 mV/div)
V
OUT2
0 A ( 50 mV/div)
I
IND1
I
IND1
(5 A/div)
(5 A/div)
SW1 (10 V/div)
SW1 (10 V/div)
Time (100 µs/div)
Time (100 µs/div)
Figure 25. 5-V Load Transient
Figure 26. 3.3-V Load Transient
500
500
VOUT = 5 V
IOUT = 6 A
VOUT = 3.3 V
IOUT = 6 A
450
400
350
300
250
200
150
100
50
450
400
350
300
250
200
150
100
50
0
0
5
10
15
20
25
5
10
15
20
25
Input Voltage (V)
Input Voltage (V)
G000
G000
Figure 27. Switching Frequency vs. Input Voltage
Figure 28. Switching Frequency vs. Input Voltage
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APPLICATION DIAGRAM (TPS51225/TPS51225B/TPS51225C)
VIN
10 µF x 2
U1
10 µF x 2
TPS51225
TPS51225B
12 VIN TPS51225C
0.1 µF
2.2 W
0.1 µF
2.2 W
17 VBST1
16 DRVH1
18 SW1
VBST2
DRVH2 10
SW2
9
L1
L2
Q1
Q3
Q2
VOUT
VOUT
5 V-8A
3.3 V - 8A
8
C1
C2
15 DRVL1
14 VO1
Q4
6.57 kW
DRVL2 11
15.3 kW
10 kW
2
1
VFB1
CS1
VFB2
CS2
4
5
7
6
3
51 kW
47 kW
PGOOD
EN2
PGOOD
19 VCLK
20 EN1
0.1 µF
0.1 µF
EN 3.3 V
EN 5V
VREG
(3.3-V LDO)
10 kW
Charge-pump
Output
VREG3
VREG5
(5-V LDO)
13 VREG5
D1
1 µF
1 µF
0.1 µF
0.1 µF
UDG-12008
GND
Table 4. Key External Components (APPLICATION DIAGRAM (TPS51225/TPS51225B/TPS51225C))
REFERENCE
DESIGNATOR
FUNCTION
MANUFACTURER
PART NUMBER
L1
L2
Output Inductor (5-VOUT
)
Toko
FDVE1040-3R3M
FDVE1040-2R2M
6TPE330MIL x 2
4TPE470MIL
FDMC7692
Output Inductor (3.3-VOUT
Output Capacitor (5-VOUT
Output Capacitor (3.3-VOUT
High-side MOSFET (5-VOUT
High-side MOSFET (3.3-VOUT
Low-side MOSFET (5-VOUT
Low-side MOSFET (3.3-VOUT
)
Toko
C1
C2
Q1
Q2
Q3
Q4
)
SANYO
SANYO
Fairchild
Fairchild
Fairchild
Fairchild
)
)
)
FDMC7692
)
FDMC7672
)
FDMC7672
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Changes from Original (January 2012) to Revision A
Page
•
Deleted references to obsolete option TPS51225A throughout document .......................................................................... 1
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Product Folder Link(s) :TPS51225 TPS51225B TPS51225C
PACKAGE OPTION ADDENDUM
www.ti.com
19-May-2012
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
TPS51225BRUKR
TPS51225BRUKT
TPS51225CRUKR
TPS51225CRUKT
TPS51225RUKR
TPS51225RUKT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
QFN
QFN
QFN
QFN
QFN
QFN
RUK
RUK
RUK
RUK
RUK
RUK
20
20
20
20
20
20
3000
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
3000
250
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
3000
250
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
19-May-2012
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
19-May-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS51225BRUKR
TPS51225BRUKT
TPS51225CRUKR
TPS51225CRUKT
TPS51225RUKR
TPS51225RUKT
QFN
QFN
QFN
QFN
QFN
QFN
RUK
RUK
RUK
RUK
RUK
RUK
20
20
20
20
20
20
3000
250
330.0
180.0
330.0
180.0
330.0
180.0
12.4
12.4
12.4
12.4
12.4
12.4
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
1.1
1.1
1.1
1.1
1.1
1.1
8.0
8.0
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
12.0
12.0
Q2
Q2
Q2
Q2
Q2
Q2
3000
250
3000
250
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
19-May-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS51225BRUKR
TPS51225BRUKT
TPS51225CRUKR
TPS51225CRUKT
TPS51225RUKR
TPS51225RUKT
QFN
QFN
QFN
QFN
QFN
QFN
RUK
RUK
RUK
RUK
RUK
RUK
20
20
20
20
20
20
3000
250
346.0
210.0
346.0
210.0
346.0
210.0
346.0
185.0
346.0
185.0
346.0
185.0
29.0
35.0
29.0
35.0
29.0
35.0
3000
250
3000
250
Pack Materials-Page 2
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