TPS51518_17 [TI]
Single-Phase, D-CAP and D-CAP2 Controller with 2-Bit Flexible VID Control;
| 型号： | TPS51518_17 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Single-Phase, D-CAP and D-CAP2 Controller with 2-Bit Flexible VID Control |
| 文件： | 总34页 (文件大小：4067K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS51518
www.ti.com
SLUSAO8 –DECEMBER 2011
Single-Phase, D-CAP™ and D-CAP2™ Controller with 2-Bit Flexible VID Control
Check for Samples: TPS51518
1
FEATURES
APPLICATIONS
2
•
Differential Voltage Feedback
•
•
•
Notebook Computers
•
•
•
DC Compensation for Accurate Regulation
Wide Input Voltage Range: 3 V to 28 V
GFX Supplies
System Agent for Intel Chief River Platform
Flexible, 2-Bit VID Supports Output Voltage
from 0.5 V to 2.0 V
DESCRIPTION
The TPS51518 is
a
single phase, D-CAP™/
•
Adaptive On-Time Modulation with Selectable
Control Architecture
D-CAP2™ synchronous buck controller with 2-bit VID
inputs which can select up to four independent
externally programmable output voltage levels where
full external programmability in the voltage level, step
setting and voltage transition slew rate is desired. It is
used for GFX applications where multiple voltage
levels are desired.
–
D-CAP™ Mode at 350 kHz for Fast
Transient Response
–
D-CAP2™ Mode at 350 kHz for
Ultra-Low/Low ESR Output Capacitor
•
•
4700 ppm/°C, Low-Side RDS(on) Current Sensing
The TPS51518 supports all POS/SPCAP and/or all
ceramic MLCC output capacitor options in
applications where remote sense is a requirement.
Tight DC load regulation is achieved through external
programmable integrator capacitor.
Programmable Soft-Start Time and Output
Voltage Transition Time
•
•
•
•
•
•
Built-In Output Discharge
Power Good Output
Integrated Boost Switch
The TPS51518 provides full protection suite,
including OVP, OCL, 5-V UVLO and thermal
shutdown. It supports the conversion voltage up to
28 V, and output voltages adjustable from 0.5 V to
2 V.
Built-In OVP/UVP/OCP
Thermal Shutdown (Non-latched)
3 mm × 3 mm, 20-Pin, QFN (RUK) Package
The TPS51518 is available in the 3 mm × 3 mm,
QFN, 0.4-mm pitch package and is specified
from –10°C to 105°C.
GSNS
VSNS
GSNS
SLEW
TRIP
GND
MODE
V5IN
V5IN
VIN
V3
V2
V1
V0
DRVL
DRVH
SW
VSNS
TPS51518
VOUT
BST
VREF PGOOD VID0
VID1 EN
PGOOD
VID0
VID1 EN
UDG-11217
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
D-CAP, D-CAP2 are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011, Texas Instruments Incorporated
TPS51518
SLUSAO8 –DECEMBER 2011
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION(1)(2)
ORDERABLE DEVICE
NUMBER
MINIMUM
QUANTITY
TA
PACKAGE
PINS
OUTPUT SUPPLY
TPS51518RUKR
TPS51518RUKT
20
20
Tape and reel
Mini reel
3000
250
PLASTIC QUAD FLAT PACK
(QFN)
–10℃ to 105℃
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the TI
website at www.ti.com.
(2) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package
ABSOLUTE MAXIMUM RATINGS(1)
MIN
–0.3
–0.3
–5
MAX
36.0
6.0
30
UNIT
BST
BST(3)
SW
EN, TRIP, MODE, VID1, VID0
–0.3
–0.3
–0.3
–0.35
–0.3
–5
5.5
5.3
3.6
0.35
0.3
36
Input voltage range(2)
V
5VIN
SLEW, VSNS
GSNS
GND
DRVH
DRVH(3)
–0.3
–0.3
–2.0
–0.3
–0.3
–40
6.0
6.0
6.0
6.0
3.6
125
150
Output voltage range(2)
DRVL
V
transient < 20 ns
PGOOD
VREF, V0, V1, V2, V3
Junction temperature, TJ
Storage temperature, TSTG
°C
°C
–55
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to the network ground terminal unless otherwise noted.
(3) Voltage values are with respect to the SW terminal.
2
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SLUSAO8 –DECEMBER 2011
RECOMMENDED OPERATING CONDITIONS(1)(2)
VALUE
MIN
4.50
MAX
5.25
UNIT
Supply voltage
V5IN
V
BST
BST(1)
–0.1
–0.1
–3
33.5
5.5
28
SW
SW(2)
–4.5
–0.1
–0.1
–0.3
–0.1
–3.0
–4.5
–0.1
–0.1
–1.5
–0.1
–0.1
–10
28.0
5.5
3.5
0.3
0.1
33.5
33.5
5.5
5.5
5.5
5.5
3.5
105
Input voltage range
V
EN, TRIP, MODE, VID1, VID0
SLEW, VSNS
GSNS
GND
DRVH
DRVH(2)
DRVH(1)
Output voltage range
V
DRVL
transient < 20 ns
PGOOD
VREF, V0, V1, V2, V3
Operating free-air temperature, TA
°C
(1) Voltage values are with respect to the SW terminal.
(2) This voltage should be applied for less than 30% of the repetitive period.
THERMAL INFORMATION
TPS51518
THERMAL METRIC(1)
UNITS
RUK (20) PINS
θJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
94.1
58.1
64.3
31.8
58.0
5.9
θJCtop
θJB
°C/W
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ψJB
θJCbot
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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ELECTRICAL CHARACTERISTICS
over operating free-air temperature range, VV5IN= 5 V, VMODE= 5 V, VEN= 3.3 V (unless otherwise noted)
PARAMETER
TEST CONDITION
MIN
TYP
MAX UNIT
SUPPLY CURRENT
IV5IN
V5IN supply current
TA = 25°C, No load, VEN = 5 V, VMODE = 5 V
TA = 25°C, No load, VEN = 0 V
560
1
μA
μA
IV5SDN
V5IN shutdown current
VREF OUTPUT
VVREF
Output voltage
IVREF = 30 µA, w/r/t GSNS
2.000
1.0
V
0.8%
0 µA ≦ IVREF < 30 µA, 0°C ≦ TA < 85°C
0 µA ≦ IVREF < 300 µA, –10°C ≦ TA < 105°C
VVREF-GSNS = 1.7 V
–0.8%
–1%
0.4
VVREFTOL
Output voltage tolerance
1%
IVREFOCL
Current limit
mA
OUTPUT VOLTAGE
VSLEWCLP SLEW clamp voltage
gM
VREFIN = 1 V
0.92
1.08
1
V
Error amplifier transconductance
VSNS input current
VREFIN = 1 V
60
12
µS
μA
mA
IVSNS
VVSNS = 1.0 V
–1
IVSNSDIS
VSNS discharge current
VEN = 0 V, VVSNS = 0.5 V, VMODE = 0 V
SMPS FREQUENCY
fSW
Switching frequency
VIN = 12 V, VVSNS = 1.0 V, VMODE = 0 V
DRVH rising to falling
350
40
kHz
ns
tON(min)
tOFF(min)
DRIVERS
Minimum on-time
Minimum off-time
DRVH falling to rising
320
Source, IDRVH = 50 mA
Sink, IDRVH = 50 mA
Source, IDRVL = 50 mA
Sink, IDRVL = 50 mA
1.7
0.8
1.1
0.6
RDH
RDL
High-side driver resistance
Low-side driver resistance
Ω
Ω
INTERNAL BOOT STRAP SW
VFBST
IBST
Forward voltage
VV5IN-BST, TA = 25°C, IF = 10 mA
0.1
0.2
V
BST leakage current
TA = 25°C, VBST = 33 V, VSW = 28 V
0.01
1.50
μA
LOGIC THRESHOLD AND TIMING
VVIDx(LL)
VVIDx(LH)
VVIDx(HYST)
IVIDx(LLK)
VEN(LL)
VID1/VID0 low-level voltage
VID1/VID0 high-level voltage
VID1/VID0 hysteresis voltage
VID1/VID0 input leakage current
EN low-level voltage
0.3
V
V
0.9
–1
0.4
0
V
1
μA
V
0.5
VEN(LH)
EN high-level voltage
1.5
–1
V
VEN(HYST)
IEN(LLK)
EN hysteresis voltage
0.25
V
EN input leakage current
1
nA
SOFT START/SLEW RATE
ISS
Soft-start current
Soft-start current source
10
50
μA
μA
ISLEW
Slew control current
4
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ELECTRICAL CHARACTERISTICS (continued)
over operating free-air temperature range, VV5IN= 5 V, VMODE= 5 V, VEN= 3.3 V (unless otherwise noted)
PARAMETER
PGOOD COMPARATOR
TEST CONDITION
MIN
TYP
MAX UNIT
PGOOD in from higher
108%
92%
116%
84%
6.0
PGOOD in from lower
PGOOD out to higher
PGOOD out to lower
VPGOOD = 0.5 V
VPGTH
PGOOD threshold
IPG
PGOOD sink current
PGOOD delay time
mA
ms
μs
Delay for PGOOD in
1
tPGDLY
Delay for PGOOD out
PGOOD comparator wake up delay
0.2
tPGCMPSS
IPGLK
PGOOD start-up delay time
PGOOD leakage current
1.5
ms
–1
0
1
μA
CURRENT DETECTION
ITRIP
TRIP source current
TA = 25°C, VTRIP = 0.4 V
9
10
11
μA
ppm/°C
V
TRIP source current temperature
coefficient(1)
TCITRIP
VTRIP
4700
VTRIP voltage range
0.2
360
190
20
3
390
210
30
VTRIP = 3.0 V
VTRIP = 1.6 V
VTRIP = 0.2 V
VTRIP = 3.0 V
VTRIP = 1.6 V
VTRIP = 0.2 V
375
200
25
VOCL
Current limit threshold
mV
–390
–212
–30
–375
–200
–25
0
–360
–188
–20
VOCLN
Negative current limit threshold
Zero cross detection offset
mV
mV
VZC
PROTECTIONS
Wake-up
4.3
3.8
4.4
4.0
4.6
4.2
VUVLO
V5IN UVLO threshold voltage
V
Shutdown
VOVP
OVP threshold voltage
OVP propagation delay
UVP threshold voltage
UVP delay
OVP detect voltage
With 100-mV overdrive
UVP detect voltage
118% 120% 122%
300
tOVPDLY
VUVP
tUVPDLY
tUVPENDLY
ns
66%
68%
1
70%
ms
ms
UVP enable delay
1.4
THERMAL SHUTDOWN
Shutdown temperature
Hysteresis
140
10
TSDN
Thermal shutdown threshold(1)
°C
(1) Ensured by design. Not production tested.
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DEVICE INFORMATION
20
19
18
17
16
1
2
3
4
5
15
14
13
12
11
GSNS
V3
V5IN
DRVL
DRVH
SW
TPS51518
V2
V1
Thermal Pad
V0
BST
6
7
8
9
10
PIN DESCRIPTIONS
PIN
I/O
DESCRIPTION
No.
NAME
I
Supply input for high-side MOSFET driver (bootstrap terminal). Connect a capacitor from this pin to the SW
pin. Internally connected to V5IN via the bootstrap MOSFET switch.
11
BST
13
14
10
17
DRVH
DRVL
EN
O
O
I
High-side MOSFET gate driver output.
Synchronous low-side MOSFET gate driver output.
Enable input for the device. Support 3.3-V logic
GND
I
Combined AGND and PGND point. The positive on-resistance current sensing input.
Voltage sense return tied directly to GND sense point of the load. Tie to GND with a 10-Ω resistor to close
feedback if die sensing is used. Short to GND if remote sense is not used.
1
GSNS
I
16
7
MODE
I
See Table 2.
PGOOD
O
PGOOD output. Connect pull-up resistor.
Program the startup using 10 µA and voltage transition time using 50 µA from an external capacitor via
current source.
19
12
18
SLEW
SW
I
I/O High-side MOSFET gate driver return. The RDS(on) current sensing input (–).
Connect resistor to GND to set OCL at VTRIP/8. Output 10 µA current at room temperature, TC
=
TRIP
I
4700ppm/°C.
5
4
V0
I
I
I
I
I
Voltage set-point programming resistor input, corresponding to 00
Voltage set-point programming resistor input, corresponding to 01
Voltage set-point programming resistor input, corresponding to 10
Voltage set-point programming resistor input, corresponding to 11
5-V power supply input for internal circuits and MOSFET gate drivers
V1
3
V2
2
V3
15
V5IN
Logic input for set-point voltage selector. Use in conjunction with VID1 pin to select among four set-point
reference voltages. Support 1-V and 3.3-V logic.
8
VID0
I
Logic input for set-point voltage selector. Use in conjunction with VID0 pin to select among four set-point
reference voltages. Support 1-V and 3.3-V logic.
9
6
VID1
I
O
I
VREF
VSNS
2 V, 300-µA voltage reference. Bypass to GND with a 1-µF ceramic capacitor.
Voltage sense return tied directly to the load voltage sense point. Tie to VOUT with a 10-Ω resistor to close
feedback if die sensing is used.
20
Thermal Pad
Connect directly to system GND plane with multiple vias.
6
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SLUSAO8 –DECEMBER 2011
FUNCTIONAL BLOCK DIAGRAM
V0
00
V1
01
V2
10
V3
11
VID0
VID1
VREF
GSNS
EN
Reference
UV
VREFIN – 32%
+
PGOOD
VREFIN +8/16%
+
Delay
Soft-Start
OV
+
+
VREFIN + 20%
VREFIN – 8/16%
SLEW
VSNS
Control Logic
+
PWM
+
VREFIN
·
On/Off Time
Minimum On /Off
SKIP/FCCM
OCL/OVP/UVP
Disharge
Control Mode
On-Time
Selection
·
·
·
·
MODE
BST
Discharge
VBG
Phase
Compensation
DH
10 mA
SW
8 R
OC
+
XCON
tON
One-
Shot
R
V5
+
TRIP
7 R
DRVL
NOC
+
5-V UVLO
+
R
+
ZC
V5OK
4.4 V/4.0 V
GND
TPS51518
UDG-11203
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TYPICAL CHARACTERISTICS
100
90
100
90
80
70
80
VIN = 8 V
VIN = 12 V
VIN = 20 V
VIN = 8 V
VIN = 12 V
VIN = 20 V
60
50
Mode = 5 V
VVID_00 = 1.20 V
Mode = 5 V
VVID_10 = 0.80 V
70
0.1
1
10
Output Current (A)
100
0.1
1
10
Output Current (A)
G004
G009
Figure 1. GFX Efficiency
Figure 2. SA Efficiency
1.000
0.900
0.800
0.700
0.600
0.500
0.400
1.200
1.000
0.800
0.600
0.400
0.200
VVID_00 = 1.20 V
VVID_01 = 1.05 V
VVID_10 = 0.90 V
VVID_11 = 0.60 V
VVID_00 = 0.900 V
VVID_01 = 0.725 V
VVID_10 = 0.800 V
VVID_11 = 0.675 V
Mode = 5 V
VIN = 12 V
Mode = 5 V
VIN = 12 V
0
5
10
15
20
25
0
1
2
3
4
5
6
Output Current (A)
Output Current (A)
G016
G013
Figure 3. GFX Load Regulation
Figure 4. SA Load Regulation
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
1.00
0.90
0.80
0.70
0.60
0.50
0.40
VVID_00 = 1.20 V
VVID_00 = 0.900 V
VVID_01 = 1.05 V
VVID_10 = 0.9 V
VVID_11 = 0.6 V
VVID_01 = 0.725 V
VVID_10 = 0.800 V
VVID_11 = 0.675 V
IOUT = 20 A
6
IOUT = 6 A
6
4
8
10
12
14
16
18
20
4
8
10
12
14
16
18
20
Input Voltage (V)
Input Voltage (V)
G007
G011
Figure 5. GFX Line Regulation
Figure 6. SA Line Regulation
8
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TYPICAL CHARACTERISTICS (continued)
600
500
400
300
200
100
0
600
MODE = 5 V
VOUT = 1.2 V
L = 0.45 µH
MODE = 5 V
VOUT = 0.8 V
L = 1.5 µH
500
400
300
200
100
0
VIN = 8 V
VIN = 12 V
VIN = 20 V
VIN = 8 V
VIN = 12 V
VIN = 20 V
0
2
4
6
8
10
12
14
16
18
20
0
1
2
3
4
5
6
Output Current (A)
Output Current (A)
G006
G010
Figure 7. GFX Frequency vs. Load Current
Figure 8. SA Frequency vs. Load Current
80
60
450
80
450
400
350
300
250
200
150
100
50
VIN = 12 V
IOUT = 25 A
MODE = 5 V
VIN = 12 V
IOUT = 6 A
MODE = 5 V
400
350
300
250
200
150
100
50
60
40
VVID_00 = 1.2 V
VVID_10 = 0.8 V
40
20
20
0
0
−20
−40
−20
−40
−60
0
0
Gain
Phase
Gain
Phase
−50
−50
−60
100
−100
1000000
−100
1000000
1000
10000
100000
100
1000
10000
100000
Frequency (Hz)
Frequency (Hz)
G001
G008
Figure 9. GFX Bode Plot
Figure 10. SA Bode Plot
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TYPICAL CHARACTERISTICS
Figure 11. Load Transient
Figure 12. Load Transient
Figure 13. Startup
Figure 14. Shutdown
Figure 15. Steady-State Ripple, ILOAD = 0.1 A
Figure 16. Steady-State Ripple, ILOAD = 1 A
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TYPICAL CHARACTERISTICS (continued)
Figure 17. Steady-State Ripple, ILOAD = 10 A
Figure 18. Steady-State Ripple, ILOAD = 30 A
Figure 19. VID transition, ILOAD = 0 A
Figure 20. VID transition, ILOAD = 6 A
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Switch Mode Power Supply Control
The TPS51518 is a high performance, single-synchronous step-down controller with differential voltage feedback.
It realizes accurate regulation at the specific load point over wide load range.
The TPS51518 supports two control architectures, D-CAP™ mode and D-CAP2™ mode. Both control modes do
not require complex external compensation networks and are suitable for designs with small external
components counts. The D-CAP™ mode provides fast transient response with appropriate amount of equivalent
series resistance (ESR) on the output capacitors. The D-CAP2™ mode is dedicated for a configuration with very
low ESR output capacitors such as multi-layer ceramic capacitors (MLCC). For the both modes, an adaptive
on-time control scheme is used to achieve pseudo-constant frequency. The TPS51518 adjusts the on-time (tON
)
to be inversely proportional to the input voltage (VIN) and proportional to the SMPS output voltage (VOUT). The
switching frequency remains nearly constant over the variation of input voltage at the steady-state condition.
Control modes are selected by the MODE pin described in Table 2.
VREF, V0, V1, V2, V3 and Output Voltage
The device provides a 2.0-V, accurate voltage reference from the VREF pin. This output has a 300-µA current
sourcing capability to drive V0, V1, V2 and V3 input voltages through a voltage divider circuit as shown in
Figure 21. If higher overall system accuracy is required, the sum of total resistance (R1+R2+R3+R4+R5) from
VREF to GND should be designed to be more than 67 kΩ. A MLCC capacitor with a value of 0.1-µF or larger
should be attached close to the VREF pin.
The device also provides 2-bit VID flexible output voltage control. Up to four voltage levels can be programmed
externally by a voltage divider circuit. V0 corresponds to VID 00, V1 coresponds to VID 01, V2 coresponds to
VID 10 and V3 coresponds to VID 11. It is not necessary to match the voltage set point (VSET1, VSET2, VSET3 or
VSET4) to any particular V0, V1, V2 or V3 input. Assignment of the input voltage is entirely dependent on the user
requirement, which makes the device very easy and flexible to use.
The device can also be configured to provide 1-bit VID flexible output voltage operation. Up to two voltage levels
can be programmed externally by a voltage divider circuit. Normally, if 1-bit VID operation is desired, the VID0
pin is generally used (the VID1 pin should be grounded if not used).
In the applications where fewer than four input voltage levels are needed, the remaining input voltage pins
cannot be left floating. Connection from the unused pins to GND is required for proper operation.
.
Table 1. VID Settings
VID1
VID0
V0
V1
V2
V3
0
0
1
1
0
1
0
1
VSET1, VSET2, VSET3, VSET4
VSET1, VSET2, VSET3, VSET4
VSET1, VSET2, VSET3, VSET4
VSET1, VSET2, VSET3, VSET4
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VREF 2 V
R1
TPS51518
V3
V2
V1
V0
VSET1
11
10
01
00
R2
R3
R4
R5
VSET2
VSET3
VSET4
VID0 VID1
UDG-11207
Figure 21. Setting the Output Voltage
Soft-Start and Power Good
Prior to asserting EN high, the power stage conversion voltage and V5IN voltage should be ready. When EN is
asserted high, TPS51518 provides soft start to suppress in-rush current during start-up. The soft start action is
achieved by an internal SLEW current of 10 µA (typ) sourcing into a small external MLCC capacitor connected
from SLEW pin to GND.
Use Equation 1 to determine the soft-start timing.
V
OUT
t
= C
´
SS
SLEW
I
SLEW
where
•
•
•
CSLEW is the soft start capacitance
VOUT is the output voltage
ISLEW is the internal 10-µA current source
(1)
The TPS51518 has a powergood open-drain output that indicates the Vout voltage is within the target range. The
target voltage window and transition delay times of the PGOOD comparator are ±8% (typ) and 1-ms delaly for
assertion from low to high, and ±16% (typ) and 0.2-µs delay for de-assertion from high to low during operation.
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SLEW and VID Function
In addition to providing soft start function, SLEW is also used to program the VID transition time. TPS51518
supports 2-bit VID and 1-bit VID operations. VID0 and VID1 works with 1.05-V logic level signals with capability
of supporting up to 3.3-V logic high.
V0 V1 V2 V3
VID0
00
01
10
11
VID1
I1(1)
+
gM
I2(2)
VSNS
SLEW
UDG-11206
(1) I1: Enable during VID transitioning, 50 µA.
(2) I2: Soft start, 10 µA.
Figure 22. VID Configuration
During VID transition:
•
SLEW current is increased to 50 µA. Based on the VID transition time of the system, the amount of the SLEW
capacitance can be calculated to meet such requirement. The minimum SLEW capacitance can be supported
by the device is 2.7 nF.
dt
C
= I
´
SLEW
SLEW _ VID
dV
where
•
ISLEW is 50 µA, dv is the voltage change during VID transition
•
dt is the required transition time
(2)
•
•
FCCM (forced continuous conduction mode) operation is used regardless of the load level. In the meantime,
the overcurrent level is temporality increased to 125% times the normal OCL level to prevent false OC trip
during fast SLEW up transition. Power good, UVP and OVP functions are all blanked as well. All normal
functions are resumed 16 internal clock cycles (64 µs) after VID transition is completed.
Additional SLEW CLAMP is implemented. If severe output short occurs (either to GND or to some other high
voltage rails in the system), SLEW is engaged into SLEW CLAMP, approximately 50 mV above or below the
output voltage reference point. After 32 internal clockcycles, the CLAMP is engaged, UVP and OVP functions
are activated to disable the controller at fault.
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MODE Pin Configuration
The TPS51518 reads the MODE pin voltage when the EN signal is raised high and stores the status in a
register.Table 2 shows the MODE connection, corresponding control topology.
Table 2. Mode States
MODE PIN CONNECTION
GND
CONTROL TOPOLOGY
D-CAP
CURRENT SENSE
fSW (KHz)
RDS(on)
350
5-V Supply
D-CAP2
D-CAP™ Mode
Figure 23 shows a simplified model of D-CAP™ mode architecture in the TPS51518.
VIN
SLEW
19
C1
VSNS
DH
gM= 60 mS
20
13
VOUT
-
Lx
+
PWM
+
V0
Control
Logic
and
5
6
VSNS
RLOAD
ESR
Driver
VREF
R1
DL
+
COUT
2.0 V
14
R2
UDG-11264
Figure 23. D-CAP™ Mode Application
The transconductance (gM) amplifier and SLEW capacitor (C1) forms an integrator. The ripple voltage generated
by ESR of the output capacitor is inversed and averaged by the integrator. The small AC component is
superimposed onto otherwise DC information and forms a reference input at the PWM comparator. As long as
the integrator time constant is much larger than the inverse of the loop crossover frequency, the AC component
is negligible. The VSNS voltage is directly compared to the SLEW voltage at the PWM comparator. The PWM
comparator creates a set signal to turn on the high side MOSFET each cycle.
The PWM comparator creates a set signal to turn on the high-side MOSFET each cycle. The D-CAP™ mode
offers flexibility on output inductance and capacitance selections with ease-of-use without complex feedback loop
calculation and external components. However, it does require sufficient amount of ESR that represents inductor
current information for stable operation and good jitter performance. Organic semiconductor capacitor(s) or
specialty polymer capacitor(s) are recommended.
The requirement for loop stability is simple and is described in Equation 3. The 0-dB frequency, f0, is
recommended to be lower than 1/3 of the switching frequency to secure proper phase margin. The integrator
time constant should be long enough compared to f0, for example one decade low, as described in Equation 4.
f
1
SW
f =
£
0
2p´ESR ´C
3
OUT
where
•
ESR is the effective series resistance of the output capacitor
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•
•
COUT is the capacitance of the output capacitor
fSW is the switching frequency
(3)
g
f
M
0
£
2p´ C1 10
where
•
gM is transconductance of the error amplifier (typically 60 µS)
(4)
Jitter is another attribute caused by signal-to-noise ratio of the feedback signal. One of the major factors that
determine jitter performance in D-CAP™ mode is the down-slope angle of the VSNS ripple voltage. Figure 24
shows, in the same noise condition, that jitter is improved by making the slope angle larger.
Slope (1)
Jitter
V
VSNS
(2)
(1)
Slope (2)
Jitter
20 mV
V
, V , V , V
V1 V2 V3
V0
V
, V , V , V +Noise
V1 V2 V3
V0
t
ON
t
OFF
Time
UDG-11263
Figure 24. Ripple Voltage Slope and Jitter Performance
For a good jitter performance, use the recommended down slope of approximately 20 mV per switching period as
shown in Figure 24 and Equation 5.
V
´ESR
OUT
³ 20mV
f
´L
SW
X
where
•
VOUT is the SMPS output voltage
LX is the inductance
•
(5)
D-CAP2™ Mode
Figure 25 shows a simplified model of D-CAP2™ mode architecture in the TPS51518.
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VIN
CC1
VSNS
SW
DH
RC1
20
12
13
CC2
RC2
SLEW
LX
C1
Control
Logic
and
G
VOUT
19
–
–
PWM
Comparator
Driver
DL
+
V0
+
ESR
RLOAD
14
5
4
3
2
COUT
V1
V2
V3
VREF
R1
6
+
2.0 V
R2
TPS51518
UDG-11262
Figure 25. Simplified D-CAP2 Mode Architecture
When TPS51518 operates in D-CAP2 mode, it uses an internal phase compensation network (RC1, RC2, CC1 and
CC2 and G) to work with very low ESR output capacitors such as multi-layer ceramic capacitors (MLCC). The role
of such network is to sense and scale the ripple component of the inductor current information and then use it in
conjunction with the voltage feedback to achieve loop stability of the converter.
The switching frequency used for D-CAP2 mode is 350 kHz and it is generally recommended to have a unity
gain crossover (f0) of 1/4 or 1/3 of the switching frequency, which is approximately 90 kHz to 120 kHz for the
purpose of this application.
Given the range of the recommended unity gain frequency, the power stage design is flexible, as long as
Equation 6 is true.
1
1
£
´ f
0
10
2´ p´ L
´ C
OUT
OUT
(6)
When TPS51518 is configured in D-CAP2 mode, the overall loop response is dominated by the internal phase
compensation network. The compensation network is designed to have two identical zeros at 5.2 kHz in the
frequency domain, which serves the purpose of splitting the L-C double pole into one low frequency pole (same
as the L-C double pole frequency) and one high-frequency pole (greater than the unity gain crossover
frequency).
Light-Load Operation
In auto-skip mode, the TPS51518 SMPS control logic automatically reduces its switching frequency to improve
light-load efficiency. To achieve this intelligence, a zero cross detection comparator is used to prevent negative
inductor current by turning off the low-side MOSFET. Equation 7 shows the boundary load condition of this skip
mode and continuous conduction operation.
V
- V
OUT ) V
´
(
1
IN
OUT
I
=
´
LOAD(LL)
2´L
V
f
SW
X
IN
(7)
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Out-of-Bound Operation
When the output voltage rises to 8% above the target value, the out-of-bound operation starts. During the
out-of-bound condition, the controller operates in forced PWM-only mode. Turning on the low-side MOSFET
beyond the zero inductor current quickly discharges the output capacitor. During this operation, the
cycle-by-cycle negative overcurrent limit is also valid. Once the output voltage returns to within regulation range,
the controller resumes to auto-skip mode.
Current Sensing
In order to provide both cost effective solution and good accuracy, TPS51518 supports MOSFET RDS(on) sensing.
For RDS(on) sensing scheme, TRIP pin should be connected to GND through the trip voltage setting resistor,
RTRIP. In this scheme, TRIP terminal sources 10µA of ITRIP current (at TA = 25°C) and the trip level is set to 1/8 of
the voltage across the RTRIP. The inductor current is monitored by the voltage between the GND pin and the SW
pin so that the SW pin is connected to the drain terminal of the low-side MOSFET. ITRIP has a 4700ppm/°C
temperature slope to compensate the temperature dependency of the RDS(on). GND is used as the positive
current sensing node so that GND should be connected to the sense resistor or the source terminal of the
low-side MOSFET.
Overcurrent Protection
TPS51518 has cycle-by-cycle overcurrent limiting protection. The inductor current is monitored during the
off-state and the controller maintains the off-state when the inductor current is larger than the overcurrent trip
level. The overcurrent trip level, VOCTRIP, is determined by Equation 8.
I
æ
ç
è
ö
÷
ø
TRIP
VOCTRIP = RTRIP
´
8
(8)
Because the comparison is made during the off-state, VOCTRIP sets the valley level of the inductor current. The
load current OCL level, IOCL, can be calculated by considering the inductor ripple current.
Overcurrent limiting using RDS(on) sensing is shown in Equation 9.
æ
ç
ö
÷
æ
ç
ö
÷
I
VOCTRIP
VOCTRIP
V
IN - VOUT
VOUT
1
2
IND(ripple)
IOCL
=
+
=
+
´
´
ç
è
÷
ø
ç
è
÷
ø
RDS on
2
RDS on
LX
fSW ´ V
IN
( )
( )
where
•
IIND(ripple) is inductor ripple current
(9)
In an overcurrent condition, the current to the load exceeds the current to the output capacitor, thus the output
voltage tends to fall down. Eventually, it crosses the undervoltage protection threshold and shuts down.
Overvoltage and Undervoltage Protection
The TPS51518 sets the overvoltage protection (OVP) when VSNS voltage reaches a level 20% (typ) higher than
the target voltage. When an OV event is detected, the controller changes the output target voltage to 0 V. This
usually turns off DRVH and forces DRVL to be on. When the inductor current begins to flow through the low-side
MOSFET and reaches the negative OCL, DRVL is turned off and DRVH is turned on, for a minimum on-time.
After the minimum on-time expires, DRVH is turned off and DRVL is turned on again. This action minimizes the
output node undershoot due to LC resonance. When the VSNS reaches 0 V, the driver output is latched as
DRVH off, DRVL on.
The undervoltage protection (UVP) latch is set when the VSNS voltage remains lower than 68% (typ) of the
REFIN voltage for 1 ms or longer. In this fault condition, the controller latches DRVH low and DRVL low and
discharges the VOUT. UVP detection function is enabled after 1.2 ms of SMPS operation to ensure startup.
To release the OVP and UVP latches, toggle EN or adjust the V5IN voltage down and up beyond the
undervoltage lockout threshold.
V5IN Undervoltage Lockout Protection
TPS51518 has a 5-V supply undervoltage lockout protection (UVLO) threshold. When the V5IN voltage is lower
than UVLO threshold voltage, typically 4.0 V, VOUT is shut off. This is a non-latch protection.
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Thermal Shutdown
TPS51518 includes an internal temperature monitor. If the temperature exceeds the threshold value, 140°C (typ),
VOUT is shut off. The state of VOUT is open at thermal shutdown. This is a non-latch protection and the operation
is restarted with soft-start sequence when the device temperature is reduced by 10°C (typ).
Layout Considerations
Certain issues must be considered before designing a layout using the TPS51518.
VREF
TPS51518
6
V3
5
VIN
V2
4
0.1 µF
V1
V5
3
Controller
15
VOUT
#1
V0
2.2 µF
2
1
#2
GSNS
VSNS
GSNS
DL
14
#3
VSNS
20
PwrPad GND
17
SLEW
10 nF
TRIP
MODE
19
18
16
UDG-11261
Figure 26. DC/DC Converter Ground System
•
VIN capacitor(s), VOUT capacitor(s) and MOSFETs are the power components and should be placed on one
side of the PCB (solder side). Other small signal components should be placed on another side (component
side). At least one inner plane should be inserted, connected to ground, in order to shield and isolate the
small signal traces from noisy power lines.
•
•
All sensitive analog traces and components such as VSNS, SLEW, MODE, V0, V1, V2, V3, VREF and TRIP
should be placed away from high-voltage switching nodes such as SW, DH, DL or BST to avoid coupling.
Use internal layer(s) as ground plane(s) and shield feedback trace from power traces and components.
The DC/DC converter has several high-current loops. The area of these loops should be minimized in order to
suppress generating switching noise.
–
–
–
Loop #1. The most important loop to minimize the area of is the path from the VIN capacitor(s) through the
high and low-side MOSFETs, and back to the capacitor(s) through ground. Connect the negative node of
the VIN capacitor(s) and the source of the low-side MOSFET at ground as close as possible. (Refer to loop
#1 of Figure 26)
Loop #2. The second important loop is the path from the low-side MOSFET through inductor and VOUT
capacitor(s), and back to source of the low-side MOSFET through ground. Connect source of the low-side
MOSFET and negative node of VOUT capacitor(s) at ground as close as possible. (Refer to loop #2 of
Figure 26)
Loop #3. The third important loop is of gate driving system for the low-side MOSFET. To turn on the
low-side MOSFET, high current flows from V5 capacitor through gate driver and the low-side MOSFET,
and back to negative node of the capacitor through ground. To turn off the low-side MOSFET, high current
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flows from gate of the low-side MOSFET through the gate driver and PGND, and back to source of the
low-side MOSFET through ground. Connect negative node of V5 capacitor, source of the low-side
MOSFET and PGND at ground as close as possible. (Refer to loop #3 of Figure 26)
•
VSNS can be connected directly to the output voltage sense point at the load device or the bulk capacitor at
the converter side. For additional noise filtering, insert a 10-Ω, 1-nF, R-C filter between the sense point and
the VSNS pin. Connect GSNS to ground return point at the load device or the general ground plane/layer.
VSNS and GSNS can be used for the purpose of remote sensing across the load device, however, care must
be taken to minimize the routing trace to prevent excess noise injection to the sense lines.
•
•
Connect the overcurrent setting resistors from TRIP pin to ground and make the connections as close as
possible to the device. The trace from TRIP pin to resistor and from resistor to ground should avoid coupling
to a high-voltage switching node.
Connections from gate drivers to the respective gate of the high-side or the low-side MOSFET should be as
short as possible to reduce stray inductance. Use 0.65 mm (25 mils) or wider trace and via(s) of at least 0.5
mm (20 mils) diameter along this trace.
•
•
The PCB trace defined as SW node, which connects to the source of the switching MOSFET, the drain of the
rectifying MOSFET and the high-voltage side of the inductor, should be as short and wide as possible.
In order to effectively remove heat from the package, prepare the thermal land and solder to the package
thermal pad. Wide trace of the component-side copper, connected to this thermal land, helps to dissipate
heat.ꢀNumerous vias with a 0.3-mm diameter connected from the thermal land to the internal/solder-side
groundꢀplane(s) should be used to help dissipation.
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DESIGN EXAMPLES
This section describes three different applications for the TPS51518 controller. Design 1 is a 2-Bit VID ICC(max)
=
25 A, D-CAP2™, 350-kHz application. Design 2 is a 2-Bit VID ICC(max) = 2 5A, D-CAP™, 350-kHz application.
Design 3 is a 2-Bit VID ICC(max) D-CAP2™, 350-kHz for Intel Chief River System Agent application (SV
processor).
Design 1: 2-Bit VID ICC(max) = 25 A, D-CAP2™, 350-kHz Application
GSNS
0 W
4.7 nF
47.5 kW
2.2 mF
VSNS SLEW
GSNS
TRIP
GND
MODE
V5IN
V5IN
VIN
100 kW
V3
V2
V1
V0
DRVL
DRVH
SW
VSNS
50 kW
25 kW
25 kW
Q1
4.7 W
0 W
LOUT
TPS51518
VOUT
0.1 mF
COUT_BULK + COUT_MLCC
VREF
PGOOD VID0
VID1 EN BST
Q2
133 kW
0.1mF
100 kW
PGOOD
VID0
VID1 EN
UDG-11266
Figure 27. Application Circuit for Design 1
Table 3. VID Table for Design 1
OUTPUT VOLTAGE
(V)
VID1
VID0
0
0
1
1
0
1
0
1
1.2
1.05
0.9
0.6
Table 4. List of Materials for Design 1
REFERENCE
DESIGNATOR
PART
NUMBER
QTY
SPECIFICATION
MANUFACTURER
CIN (not shown)
4
3
10 µF, 25 V
Taiyo Yuden
Sanyo
TMK325BJ106MM
2TPE330M9
COUT_BULK
COUT_MLCC
LOUT
330 µF, 2.5 V, 9 mΩ
22 µF, 6.3 V
10
1
Murata
GRM21BB30J226ME38
ETQP4LR45XFC
CSD17302Q5A
0.45 µH, 17 A, 1.1 mΩ
30 V, 7.3 mΩ
Panasonic
Q1
1
Texas Instruments
Texas Instruments
Q2
2
30 V, 3.3 mΩ
CSD17306Q5A
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Design 2: 2-Bit VID ICC(max) = 25 A, D-CAP™, 350-kHz, Application Circuit
GSNS
0 W
4.7 nF
17.8 kW
2.2 mF
VSNS SLEW
GSNS
TRIP
GND
MODE
V5IN
V5IN
VIN
100 kW
V3
V2
V1
V0
DRVL
DRVH
SW
VSNS
50 kW
25 kW
25 kW
Q1
4.7 W
0 W
LOUT
TPS51518
VOUT
0.1 mF
COUT_BULK
VREF
PGOOD VID0
VID1 EN BST
Q2 × 2
133 kW
0.1mF
100 kW
PGOOD
VID0
VID1 EN
UDG-11267
Figure 28. Application Circuit for Design 2
Table 5. VID Table for Design 2
OUTPUT VOLTAGE
(V)
VID1
VID0
0
0
1
1
0
1
0
1
1.2
1.05
0.9
0.6
Table 6. List of Materials for Design 2
REFERENCE
DESIGNATOR
PART
NUMBER
QTY
SPECIFICATION
MANUFACTURER
CIN (not shown)
COUT_BULK
LOUT
4
3
1
1
2
10 µF, 25 V
Taiyo Yuden
Sanyo
TMK325BJ106MM
2TPE330M9
330 µF, 2.5 V, 9 mΩ
0.45 µH, 17 A, 1.1 mΩ
30 V, 7.3 mΩ
Panasonic
ETQP4LR45XFC
CSD17302Q5A
CSD17306Q5A
Q1
Texas Instruments
Texas Instruments
Q2
30 V, 3.3 mΩ
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Design 3: 2-Bit VID, ICC(max) = 6 A, D-CAP2™ 350-kHz for Intel Chief River System Agent Application (SV
Processor)
GSNS
0 W
4.7 nF
47.5 kW
2.2 mF
VSNS SLEW
GSNS
TRIP
GND
MODE
V5IN
V5IN
VIN
100 kW
V3
V1
V2
V0
DRVL
DRVH
SW
VSNS
7.41 kW
11.1 kW
Q1
4.7 W
0W
LOUT
TPS51518
VOUT
14.7 kW
162 kW
0.1 mF
COUT_BULK + COUT_MLCC
VREF
PGOOD VID0
VID1 EN BST
Q2
0.1mF
100 kW
PGOOD
VID0
VID1 EN
UDG-11268
Figure 29. Application Circuit for Design 3
Table 7. VID Table for Design 3
OUTPUT VOLTAGE
VID1
VID0
(V)
0
0
1
1
0
1
0
1
0.9
0.8
0.725
0.675
Table 8. List of Materials for Design 3
REFERENCE
DESIGNATOR
PART
NUMBER
QTY
SPECIFICATION
MANUFACTURER
CIN (not shown)
2
1
1
1
1
1
10 µF, 25 V
Taiyo Yuden
Sanyo
TMK325BJ106MM
COUT_BULK
COUT_MLCC
LOUT
220 µF, 2.5 V, 9 mΩ
22 µF, 6.3 V
2TPE330M9
Murata
GRM21BB30J226ME38
ETQP4LR45XFC
CSD17302Q5A
CSD17306Q5A
1.5 µH, 10 A, 9.7 mΩ
30 V, 7.3 mΩ
Panasonic
Q1
Texas Instruments
Texas Instruments
Q2
30 V, 3.3 mΩ
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DESIGN PROCEDURE
The simplified design procedure is done for a system agent rail for IMVP7 Intel platform application using the
TPS51518 controller.
Step One: Determine the specifications.
The system agent rail requirements provide the following key parameters:
•
•
•
•
•
•
V00 = 0.90 V
V01 = 0.725 V
V10 = 0.80 V
V11 = 0.675 V
ICC(max) = 6 A
IDYN(max) = 2 A
Step Two: Determine system parameters.
The input voltage range and operating frequency are of primary interest.
In this example:
•
•
9 V ≤ VIN ≤ 20 V
fSW = 350 kHz
Step Three: Determine inductor value and choose Inductor.
Smaller values of inductor have better transient performance but higher ripple and lower efficiency. Higher values
have the opposite characteristics. It is common practice to limit the ripple current to 25% to 50% of the maximum
current. In this example, use 25%:
IP-P = 6 A × 0.25 = 1.5 A
At fSW = 350 kHz with a 20-V input and a 0.80-V output:
æ
ö
÷
IN ø
V
æ
ç
è
ö
÷
ø
0.8V
10
V
- V
´
ç
OUT
(
)
20V - 0.8V ´
( )
IN
f
´ V
350kHz ´ 20V
V ´ dT
è SW
L =
=
=
I
I
1.5A
P-P
P-P
(10)
For this application, a 1.5-µH, 9.7-mΩ inductor from TDK with part number SPM6530T-1R5M100 is used.
Step Four: Set the output voltages.
Set the output voltage levels. for V0, V1, V2 and V3 pins ).
•
•
•
•
VID 00, V0 = VSET1 = 0.9 V
VID 10, V2 = VSET2 = 0.8 V
VID 01, V1 = VSET3 = 0.725 V
VID 11, V3 = VSET4 = 0.675 V
Follow the TPS51518 Design Tool_1.0.xls (in the VID_Config section) to determine the resistor values:
•
•
•
•
•
•
VREF = 2 V
R1 = 162 kΩ
R2 = 14.7 kΩ
R3 = 11.1 kΩ
R4 = 7.41 kΩ
R5 = 100 kΩ
24
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TPS51518
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SLUSAO8 –DECEMBER 2011
VREF 2 V
R1
TPS51518
VSET1
V3
V2
R2
R3
R4
R5
VSET2
VSET3
V1
V0
VSET4
VID0
VID1
UDG-11272
Figure 30. Setting the Output Voltage
Step Five: Calculate SLEW capacitance.
SLEW can be used to program the soft-start time and voltage transition timing. During soft-start operation, the
current source used to program the SLEW rate is 10 µA (nominal). During VID transition, the current source is
switched to a higher current of 50 µA.
In this design example, the requirement is to complete VID_00 to VID_11 transition within 20 µs, calculate the
SLEW capacitance based on Equation 11.
dt
20ms
C
= I ´
= 50 mA ´
= 4.7nF
SLEW
dV
0.9V - 0.675V
(11)
For VOUT = 0.9 V, the soft start timing based on CSLEW is 423 µs.
The slower slew rate is desired to minimize large inductor current perturbation during startup and voltage
transition, thus reducing the possibility of acoustic noise.
Step Six
TPS51518 uses a low-side on-resistance (RDS(on) ) sensing scheme. The TRIP pin sources 10 µA of current and
the trip level is set to 1/8 of the voltage across the TRIP resistor (RTRIP ). The overcurrent trip level is determined
by RTRIP × (ITRIP /8). Because the comparison is done during the off state, the trip voltage sets the valley current.
The load current can be calculated by considering the inductor ripple current.
æ
ö
æ
ö
V
(
- V
V
(
OUT
)
)
IN
OUT
8´ I
-
´
´R
DS on
ç
÷
÷
ø
ç
÷
OCL
( )
ç
÷
ç
2´Lx
f
(
´ V
)
SW IN
(
)
è
ø
è
R
=
TRIP
I
TRIP
-
where
•
•
•
•
•
•
VIN is the input voltage
VOUT is the output voltage
fSW is the switching frequency (350 kHz)
RDS(on) is the low-side FET on resistance
ITRIP is the trip current, 10 µA (nominal)
Lx is the output inductance
(12)
25
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Step Seven: Determine the output capacitance.
D-CAP™ Mode
Organic semiconductor capacitor(s) or specialty polymer capacitor(s) are recommended. Determine the ESR
value to meet small signal stability and recommended ripple voltage. A quick reference is shown in Equation 13
and Equation 14.
f
1
SW
f =
£
0
2p´ESR ´C
3
OUT
(13)
g ´ESR
f
0
M
£
2´ p´ C1 10
where
•
gM is the 60 µS
C1 is the SLEW capacitance
´ESR
•
(14)
(15)
V
OUT
³ 20mV
f
´Lx
SW
D-CAP2™ Mode
The switching frequency for D-CAP2™ mode is 350 kHz and it is generally recommend to have a unity gain
crossover (f0) of 1/4 or 1/3 of the switching frequency, which is approximately 90 kHz to 120kHz for the purpose
of this application.
f
f
SW
SW
f =
= 90kHz or f =
= 120kHz
0
0
3
4
(16)
Given the range of the recommended unity gain frequency, the power stage design is flexible, as long as the LC
double pole frequency is less than 10% of f0.
1
1
f
=
£
´ f = 9kHz Û 12kHz
0
LC
10
2p L
´ C
OUT
OUT
(17)
As long as the LC double pole frequency is designed to be less than 1/10 of f0, the internal compensation
network provides sufficient phase boost at the unity gain crossover frequency in order for the converter to be
stable with enough margin (> 60°).
When the ESR frequency of the output bulk capacitor is in the vicinity of the unity gain crossover frequency of
the loop, additional phase boost is achieved. This applies to POSCAP and/or SPCAP output capacitors.
When the ESR frequency of the output capacitor is beyond the unity gain crossover frequency of the loop, no
additional phase boost is achieved. This applies to low/ultra low ESR output capacitors, such as MLCCs.
Equation 18 and Equation 19 can be used to estimate the amount of capacitance needed for a given dynamic
load step/release. Note that there are other factors that may impact the amount of output capacitance for a
specific design, such as ripple and stability. Equation 18 and Equation 19 are used only to estimate the transient
requirement, the result should be used in conjuction with other factors of the design to determine the necessary
output capacitance for the application.
æ
ö
2
)
V
´ t
SW
OUT
L ´ DI
(
´
+ t
MIN(off)
ç
ç
è
÷
÷
ø
LOAD(max)
V
IN(min)
C
=
OUT(min_under)
æ
ö
æ
ö
´ t
÷
V
- V
IN(min)
OUT
ç
ç
è
÷
÷
ø
2´ DV
´
- t
´ V
OUT
ç
ç
è
LOAD(insert)
SW
MIN(off)
÷
V
IN(min)
ø
(18)
(19)
2
)
LOUT ´ DI
(
LOAD(max)
COUT(min_over)
=
2´ DVLOAD(release) ´ VOUT
Equation 18 and Equation 19 calculate the minimum COUT for meeting the transient requirement, which is 72.9
µF assuming ±3% voltage allowance for load step and release.
26
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Step Eight: Select decoupling and peripheral components.
For the TPS51518, peripheral capacitors use the following minimum values of ceramic capacitance. X5R or
better temperature coefficient is recommended. Tighter tolerances and higher voltage ratings are always
appropriate.
•
•
•
•
V5IN decoupling ≥2.2 µF, ≥ 10 V
VREF decoupling 0.22 µF to 1 µF, ≥ 4 V
Bootstrap capacitors ≥ 0.1 µF, ≥ 10 V
Pull-up resistors on PGOOD, 100 kΩ
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PACKAGE OPTION ADDENDUM
www.ti.com
23-Aug-2012
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
TPS51518RUKR
TPS51518RUKT
ACTIVE
ACTIVE
WQFN
WQFN
RUK
RUK
20
20
3000
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
22-Aug-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS51518RUKR
TPS51518RUKT
WQFN
WQFN
RUK
RUK
20
20
3000
250
330.0
180.0
12.4
12.4
3.3
3.3
3.3
3.3
1.1
1.1
8.0
8.0
12.0
12.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
22-Aug-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS51518RUKR
TPS51518RUKT
WQFN
WQFN
RUK
RUK
20
20
3000
250
367.0
210.0
367.0
185.0
35.0
35.0
Pack Materials-Page 2
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