TPS5300DAPG4 [TI]
3.3A SWITCHING CONTROLLER, 500kHz SWITCHING FREQ-MAX, PDSO32, GREEN, PLASTIC, HTSSOP-32;
| 型号： | TPS5300DAPG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 3.3A SWITCHING CONTROLLER, 500kHz SWITCHING FREQ-MAX, PDSO32, GREEN, PLASTIC, HTSSOP-32 开关 光电二极管 |
| 文件： | 总24页 (文件大小：573K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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8,1 mm x 11 mm
SLVS334A − DECEMBER 2000 − REVISED SEPTEMBER 2001
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technology. The TPS5300 provides
a
precise,
FEATURES
programmable supply voltage to a mobile processor or
other processor power applications. A ripple regulator
provides the core voltage, while two linear regulator
drivers regulate external NPN power transistors for the
I/O and CLK voltages. A 5-bit voltage identification
(VID) DAC allows programming for the ripple regulator
voltage to values between 0.925 V to 1.275 V in 25-mV
steps and 1.3 V to 2 V in 50-mV steps. Other voltage
ranges and steps can be easily set. The fast transient
response time and active voltage DROOP positioning
reduce the number of output capacitors required to
keep the output voltage within tight dynamic voltage
regulation limits. The power saving mode (PSM) allows
the user to select a single operating ramp or allows the
controller to automatically switch to lower frequencies
at low loads. The high-gain current sense differential
amplifier allows the use of small-value sense resistors
that minimize conduction losses.
D
D
D
Power Stage Input Voltage Range of 3 V to
28 V
Single-Chip Dynamic Output Voltage
Transition Solution
Hysteretic Controller Provides Fast Transient
Response Time and Reduced Output
Capacitance
D
D
Two Linear Regulator Controllers Regulating
Clock and I/O Voltages
Internal 2-A (Typ) Gate Drivers With Bootstrap
Diode For Increased Efficiency
D
5-Bit Dynamic VID
D
Active Droop Compensation Enables Tight
Dynamic Regulation for Reduced Output
Capacitance
D
VGATE Terminal Provides Power-Good Signal
for All Three Outputs
D
Enable External Terminal (ENABLE_EXT)
D
32-Pin TSSOP PowerPAD Enhances Thermal
Performance
V = 12 V
I
D
1% Reference Voltage Accuracy
APPLICATIONS
D
D
Intel Mobile CPUs With SpeedStep
Technology
AMD Mobile CPUs With PowerNow!
Technology
D
DSP Processors
D
Other One, Two, or Three Output
Point-of-Load Applications
DESCRIPTION
The TPS5300 is a hysteretic synchronous-buck
controller, with two on-chip linear regulator controllers,
incorporating dynamic output voltage positioning
Output Voltage Transient Load Response
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Speed Step is a trademark of Intel Corp.
PowerNow is a trademark of Advanced Micro Devices Inc.
PowerPAD is a trademark of Texas Instruments.
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Copyright 2001, Texas Instruments Incorporated
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ꢛ ꢟ ꢜ ꢛꢔ ꢕꢩ ꢗꢖ ꢚ ꢢꢢ ꢠꢚ ꢘ ꢚ ꢙ ꢟ ꢛ ꢟ ꢘ ꢜ ꢤ
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1
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ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢅ
SLVS334A − DECEMBER 2000 − REVISED SEPTEMBER 2001
description (continued)
The TPS5300 includes high-side and low-side gate drivers rated at 2 A typical, that enable efficient operation
at higher frequencies and drive larger or multiple power MOSFETs (such as 50-A output current applications).
An adaptive dead-time circuit minimizes dead-time losses while preventing cross-conduction of high-side and
low-side switches. All three outputs power up together as they track the same user programmable slowstart
voltage. The enable external (ENABLE_EXT) terminal allows the TPS5300 to activate external switching
controllers for additional system power requirements.
The TPS5300 features V
undervoltage lockout, output overvoltage protection, output undervoltage
CC
protection, and user-programmable overcurrent protection, and is packaged in a small 32-pin TSSOP
PowerPAD package.
pin assignments
TSSOP PACKAGE
(TOP VIEW)
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
DRV_CLK
VSENSE_CLK
DT_SET
ANAGND
VSENSE_CORE
SLOWST
VREFB
DRV_IO
VSENSE_IO
VBIAS
ENABLE_EXT
RAMP
VID0
VID1
VID2
VID3
VID4
2
3
4
5
6
7
8
VHYST
OCP
DROOP
THERMAL
PAD
9
10
11
12
13
14
15
16
IOUT
PSM/LATCH
IS−
VR_ON
BOOT
TG
IS+
VGATE
DRVGND
PH
V
CC
BG
2
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ꢀꢁ ꢂ ꢃꢄ ꢅꢅ
SLVS334A − DECEMBER 2000 − REVISED SEPTEMBER 2001
†
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
CC
Input voltage, V : VBIAS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
I
VR_ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V
VID0, VID1, VID2, VID3, VID4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V
PSM/LATCH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V
IS−, IS+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V
RAMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 V
VSENSE_CORE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V
VSENSE_IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V
VSENSE_CLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V
All other input terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
BOOT to DRVGND voltage (high-side driver on) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 V
BOOT to PH voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
BOOT to TG voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
PH to DRVGND voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −1 V to 35 V
ANAGND to DRVGND voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 V
Output voltage, V : VGATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V
O
ENABLE_EXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V
Continuous power dissipation, P : Without PowerPad soldered, T = 25°C, T = 125°C . . . . . . . . . . . . . . . . 1.2 W
D
A
J
With PowerPad soldered, T = 25°C, T = 125°C . . . . . . . . . . . . . . . . . . 6.25 W
C
J
Operating junction temperature, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 125°C
J
Storage temperature, T
Lead temperature, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
(soldering, 10 seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C
stg
(lead)
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
DISSIPATION RATING TABLE
‡
PWP
T
A
< 25°C
Derating Factor
0.0358 W/°C
T
A
= 70°C
T = 85°C
A
PowerPAD mounted
PowerPAD unmounted
3.58 W
1.78 W
1.96 W
0.98 W
1.43 W
0.71 W
0.0178 W/°C
JUNCTION-CASE THERMAL RESISTANCE TABLE
Junction-case thermal resistance 0.72 °C/W
‡
Test Board Conditions:
1. Thickness: 0.062”
2. 3” x 3” (for packages < 27 mm long)
3. 4” x 4” (for packages > 27 mm long)
4. 2 oz. Copper traces located on the top of the board (0,071 mm thick )
5. Copper areas located on the top and bottom of the PCB for soldering
6. Power and ground planes, 1 oz. Copper (0,036 mm thick)
7. Thermal vias, 0,33 mm diameter, 1,5 mm pitch
8. Thermal isolation of power plane
For more information, refer to TI technical brief SLMA002.
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functional schematic
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SLVS334A − DECEMBER 2000 − REVISED SEPTEMBER 2001
recommended operating conditions, 0 < T < 125°C (unless otherwise noted)
J
MIN NOM
MAX
28
6
UNIT
Supply voltage, V
batt
3
3
12.5
3.3
5
V
V
V
Linear regulator supply voltage, V
I(IO+CLK)
Supply voltage range, V , VBIAS
CC
4.5
6
dc and ac electrical characteristics over recommended operating free-air temperature range,
0 < T < 125°C, V = 3 V − 28 V (unless otherwise noted)
J
IN
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Reference/Voltage Identification
V
V
High-level input voltage, D0−D4
Low-level input voltage, D0−D4
Current source pullup to V
CC
2.25
V
V
IH(VID)
1
IL(VID)
Cumulative Reference (see Note 1)
0.925 V ≤ V
ref(core)
≤ 2 V,
−1.5%
−1%
1.5%
1%
Hysteresis window = 30 mV (see Note 2)
V
Initial accuracy ripple regulator
Output voltage, VREFB
(CUM_ACCRR)
0.925 V ≤ V ≤ 2 V, T = 25°C
ref(core)
Hysteresis window = 30 mV
J
Buffered Reference
V
I
= 50 µA (see Note 2)
−2.5%
2.5%
250
O(VREFB)
Hysteretic Comparator (core)
Propagation delay time from (AC)
(VREFB)
20-mV overdrive, pulse
0.925 V ≤ V ≤ 2 V (see Note 2)
t
VSENSE_CORE to TG or BG
(excluding deadtime)
220
220
ns
ns
PHL(HC)
ref
Ramp circuit from 0 into 26 mV ramp
(see Note 2)
t
PHL(HC_ramp)
Overcurrent Protection (core)
Trip point, OCP
Normal operation
235
111
300
400
365
V
mV
(OCP)
During dynamic VID change
Overvoltage Protection (core, IO, CLK)
Trip point, OVP
Undervoltage Protection (IO, CLK)
Trip point, UVP
Bias UVLO (Resets fault latch)
V
Upper threshold
Lower threshold
115
75
119 %V
(OVP)
ref
V
%V
(UVP)
ref
V
V
V
Start threshold
Stop threshold
Hysteresis
4.46
V
V
IT(start_UVLO)
IT(stop_UVLO)
hys
3.3
500
20
mV
VR_ON connected to GND and V above
I
UVLO start threshold
VBIAS quiescent current, I
(ving1)
µA
VR_ON UVLO (Resets fault latch)
V
V
V
Start threshold
Stop threshold
Hysteresis
2.5
V
V
IT(start_VR_ON)
IT(stop_VR_ON)
hys
1.3
475
mV
NOTES: 1. Cumulative reference accuracy is the combined accuracy of the reference voltage and the input offset voltage of the hysteretic
comparator. Cumulative accuracy equals to the average of the low-level and high-level thresholds of the hysteretic comparator.
2. Ensured by design, not production tested.
5
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ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢅ
SLVS334A − DECEMBER 2000 − REVISED SEPTEMBER 2001
electrical characteristics over recommended operating free-air temperature range, 0 < T < 125°C,
J
V
= 3 V − 28 V (unless otherwise noted) (continued)
IN
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Slowstart
V
= 0.5 V,
(SS)
I
Charge current (I
(chg)
= (I
(REFB)
/5)
I
I
= 65 µA VREFB = 1.35 V,
(VREFB)
= 1.35 V,
10.4
13
3
15.6
µA
(chg)
(VREFB)
= (I
/5)
(chg)
V
(SS)
Design for V
I
Discharge current
mA
(dischg)
= 4.5 V
IN(min)
VGATE (CORE, IO, CLK) (PWRGD of three outputs with open drain output)
Undervoltage trip point
V
V
(VSENSE_CORE, VSENSE_IO, and
VSENSE_CLK)
V
and V
above UVLO thresholds
85
90
95 %Vref
(VGATE)
IN (drv)
Output saturation voltage
I
O
= 2.5 mA
0.5
0.75
V
V
O(VGATE)
Enable EXT (SHUTDOWN of IC with open-drain output. Use pullup resistor to 5 V or 3.3 V)
Output saturation voltage = 2.5 mA
DROOP Compensation
Maximum output CMR
V
I
O
0.5
0.75
O(EN_EXT)
200
200
mV
ns
15-mV to 150-mV swing,
0.925 V ≤ V ≤ 2 V, V
(see Note 2)
t
Propagation delay
= 5 V
500
PHL(HC)
ref
CC
Current Sensing
G
Gain
See Note 2
25
26
V/V
mV
(CS)
V
(IS+)
− V = 1 mV,
(IS−)
V
Output systematic offset
O(SO)
1 mV input (see Note 2)
V
V
Output random offset
See Note 2
15
mV
V
O(RO)
Maximum output voltage swing
1.75
OM
V
= 0.925 V – 2 V, V
to (V
(IS−) (IS−)
= 5 V (see Note 2)
is pulsed
+ 50 mV),
(IS−)
from V
(IS+)
Response time (measured from 50% of
t
500
2.3
ns
(VDSRESP)
(V
(IS+)
− V ) to 50% of V
(IS−) (IOUT)
V
CC
PSM/LATCH Power Saving Mode (PSM Comparator)
V
V
V
V
V
V
V
V
PSM comparator start threshold
PSM comparator stop threshold
Hysteresis
2.1
V
V
(startINH)
(stopINH)
hys(INH)
(PSMth1)
(PSMth2)
(PSMth3)
(PSMth4)
hys(PSM)
1.8
90
30
100
120
mV
150
90
OCP voltage trip points for PSM
Hysteresis
mV
mV
kΩ
OCP↑
60
10
10
PH to CT, PSM = GND,
R
R
R
8
16
1
12
24
(tPSM1)
(tPSM2)
(tPSM3)
V
= 150 mV (see Note 3)
(OCP)
PH to CT, PSM = GND,
= 85 mV (see Note 3)
20
PSM ramp timing resistance
V
(OCP)
PH to CT, PSM = GND,
= 15 mV (see Note 3)
MΩ
V
(OCP)
NOTES: 2. Ensured by design, not production tested.
3. The VBIAS voltage is required to be a quiet bias supply for the TPS5300 control logic. External noisy loads should use VCC instead
of the VBIAS voltage.
6
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SLVS334A − DECEMBER 2000 − REVISED SEPTEMBER 2001
electrical characteristics over recommended operating free-air temperature range, 0 < T < 125°C,
J
V
= 3 V − 28 V (see test circuits) (unless otherwise noted) (continued)
IN
PARAMETER
PSM/LATCH Fault Latch Disable
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Disable latch threshold
PSM enabled
V
VBIAS + 0.7
V
(No_Latch/PSM)
Disable latch threshold
PSM disabled
V
V
ANAGND − 0.7
VBIAS
V
V
(No_Latch)
Enable latch threshold
ANAGND
(Latch_enabled)
Thermal Shutdown
Over temperature trip
point
T
See Note 2
See Note 2
155
25
°C
°C
(OTP)
(hyst)
T
Hysteresis
Dynamic VID Change (No current limit)
Voltage change timing
V
= 5 V,
V
= 1.35 V,
CC
(ref1)
SRC SNK
Ι
14
µA
∆tSRC/SNK
current
Output Drivers (see Note 4)
DT_SET = 0.925 V
/V
Duty cycle < 2%, tpw < 100 µs,
I
I
V
– V = 4.5 V,
1.2
1.2
2
A
A
O(src_TG)
(BOOT)
− V
(PH)
V
(TG)
= 0.5 V (src)
(PH)
Duty cycle < 2%, tpw < 100 µs,
V
– V
= 4.5 V,
= 4 V (sink)
3.3
O(sink_TG)
(BOOT)
− V
(PH)
Peak output current (see
Notes 2 and 4)
V
(TG)
(PH)
Duty cycle < 2%, tpw < 100 µs,
= 4.5 V, V = 0.5 V (src)
I
I
1.4
1.3
2
A
A
O(src_BG)
V
CC
(BG)
Duty cycle < 2%, tpw < 100 µs,
3.3
O(sink_BG)
V
V
V
V
V
= 4.5 V, V = 4 V (src)
(BG)
CC
r
r
r
r
– V
= 4.5 V, V
= 4 V
2.5
1.5
2.5
1.5
Ω
Ω
Ω
Ω
o(src_TG)
o(sink_TG)
o(src_BG)
o(sink_BG)
(BOOT)
(BOOT)
(PH)
(PH)
(TG)
= 0.5 V
– V
= 4.5 V, V
(TG)
Output resistance (see
Note 4)
= 4.5 V, V
= 4 V
CC
CC
(BG)
(BG)
= 4.5 V, V
= 0.5 V
TG fall time (AC) (see
Note 5)
t
t
t
t
f(TG)
r(TG)
f(BG)
r(BG)
C = 3.3 nF, V
= 4.5 V,
l
(BOOT)
10
10
ns
ns
V
(PH)
= GND
TG rise time (AC) (see
Note 5)
BG fall time (AC) (see
Note 5)
C = 3.3 nF, V
l CC
= 4.5 V
BG rise time (AC) (see
Note 5)
High-Side Driver Quiescent Current
VR_ON grounded, or V
CC
(BOOT)
PH grounded (see Note 2)
below UVLO
Highdrive (TG)
quiescent current
I
threshold; V
= 5 V,
2
µA
Q(highdrq1)
NOTES: 2. Ensured by design, not production tested.
4. The pulldown (sink) circuit of the high-side driver is a MOSFET transistor referenced to DRVGND. The driver circuits are bipolar
and MOSFET transistors in parallel. The peak output current rating is the combined current rating from the bipolar and MOSFET
transistors. The output resistance is the r
saturation voltage of the bipolar transistor.
of the MOSFET transistor when the voltage on the driver output is less than the
ds(on)
5. Rise and fall times are measured from 10% to 90% of pulsed values.
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SLVS334A − DECEMBER 2000 − REVISED SEPTEMBER 2001
electrical characteristics over recommended operating free-air temperature range, 0 < T < 125°C,
J
V
= 3 V − 28 V (see test circuits) (unless otherwise noted) (continued)
IN
PARAMETER
Adaptive Deadtime Circuit
TEST CONDITIONS
MIN
2.4
3
TYP
MAX
UNIT
V
V
V
V
TG − PH High-level input voltage
TG − PH Low-level input voltage
BG High-level input voltage
BG Low-level input voltage
V
V
V
V
= 0.925 V – 2 V (see Note 2)
= 0.925 V – 2 V (see Note 2)
= 0.925 V – 2 V (see Note 2)
= 0.925 V – 2 V (see Note 2)
V
V
V
V
IH(TG)
IL(TG)
IH(BG)
IL(BG)
(IS−)
(IS−)
(IS−)
(IS−)
1.33
1.7
50
CBG = 9 nF, 10% threshold on BG,
t
Driver nonoverlap time (AC)
ns
(NUL)
V
CC
= 5 V (see Note 2)
Linear Regulator OUTPUT DRIVERs (IO, CLK) (see Note 4)
V
CC
= 5 V,
I
VSENSE_IO = 0.9 × V
134
mA
O(src_LDODR_IO)
O(sink_LDODR_IO)
(REF_IO)
(see Note 2)
Peak output current linear regula-
tor driver IO
V
CC
= 5 V,
I
VSENSE_IO = 1.1 × V
14
µA
(REF_IO)
(see Note 2)
Initial accuracy IO condition:
closed loop; linear regulator
V
V
V
= 5 V, V = 1.5 V, I = 134 mA
−1.7%
1.7%
(CUM_ACC_IO)
CC
ref
O
5.5 V ≥ V
3 V ≤ V (IO) ≤ 6 V, (see Note 2)
≥ 4.5 V,
CC
VIN line regulation IO
5
mV
mA
(CC_Line_Reg_IO)
IN
V
= 5 V,
CC
I
VSENSE_IO = 0.9 × V
(see Note 2)
10
O(src_LDODR_CLK)
O(sink_LDODR_CLK)
O(REF_IO)
Peak output current regulator, driv-
er CLK
V
CC
= 5 V,
I
VSENSE_IO = 1.1 × V
14
µA
O(REF_IO)
(see Note 2)
Initial accuracy CLK condition:
closed loop
V
V
V
= 5 V, V = 2.5 V, I = 10 mA
−1.55%
1.55%
(CUM_ACCCLK)
CC
ref
O
5.5 V ≥ V
3 V ≤ V (CLK) ≤ 6 V, (see Note 2)
≥ 4.5 V,
CC
Line regulation CLK
5
mV
CC(LineReg_CLK)
IN
NOTES: 2. Ensured by design, not production tested.
4. The pulldown (sink) circuit of the high-side driver is a MOSFET transistor referenced to DRVGND. The driver circuits are bipolar
and MOSFET transistors in parallel. The peak output current rating is the combined current rating from the bipolar and MOSFET
transistors. The output resistance is the r
saturation voltage of the bipolar transistor.
of the MOSFET transistor when the voltage on the driver output is less than the
ds(on)
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SLVS334A − DECEMBER 2000 − REVISED SEPTEMBER 2001
Terminal Functions
TERMINAL
NAME
ANAGND
I/O
DESCRIPTION
NO.
4
Analog ground
BG
17
21
O
I
Bottom gate drive. BG is an output drive to the low-side synchronous rectifier FET.
BOOT
Bootstrap. Connect a 1-µF low-ESR ceramic capacitor to PH to generate a floating drive for the high-side
FET driver.
DROOP
10
1
I
Active voltage droop position voltage. DROOP is a voltage input used to set the amount of output-voltage,
set-point droop as a function of load current. The amount of droop compensation is set with a resistor divider
between IOUT and ANAGND. A voltage divider from V to VSENSE_CORE sets the no-load offset.
O
DRV_CLK
O
CLK voltage regulator. DRV_CLK drives an external NPN bipolar power transistor for regulating CLK
voltage to VREF_CLK.
DRVGND
DRV_IO
DT_SET
16
32
3
Drive ground. Ground for FET drivers. Connect to FET PWRGND
O
I
Drives an external NPN bipolar power transistor for regulating IO voltage to VREF_IO.
DT_SET sets the transition time for speed step output voltage positioning. Attach a capacitor from DT_SET
to ground to program time.
ENABLE_EXT
29
O
Open drain output. ENABLE_EXT enables the external converters when the internal enable signal is high
(good), and disables when there is a fault with any regulator (OVP, UVP, OCPrr), VR_ON UVLO is low, or the
VBIAS UVLO is low. Can be connected to the enable terminal of an external linear regulator or switching
controller. A pullup resistor is required to set the desired voltage rail.
IS−
IS+
13
14
I
I
Current sense negative Kelvin connection. Connect to the node between the current sense resistor and the
output capacitors. Keep the PCB trace short and route trace next to the IS+ trace to help reduce loop
inductance noise pickup and cancel common mode noise through mutual coupling.
Current sense positive Kelvin connection. Connect to the node between the output inductor and the current
sense resistor. Keep the PCB trace short and route trace next to the IS-trace to help reduce loop inductance
noise and cancel common mode noise through mutual coupling.
IOUT
11
9
O
I
Current sense differential amplifier output. The voltage on IOUT equals
25 x (V
I(+)
− V ) = 25 x (R x I ).
I(−) (sense) L
OCP
Overcurrent protection. Current limit trip point is set with a resistor divider between IOUT and ANAGND. The
typical OCP trip point should be set at 1.30 × I . The OCP voltage also sets the PSM automatic trip points.
(max)
PH
19
12
I/O Phase voltage node. PH is used for bootstrap low reference. PH connects to the junction of the high-side and
low-side FET’s.
PSM/LATCH
I
PSM. Power saving mode boosts efficiency at low-load current by automatically decreasing the switching
frequency toward the natural converter operating frequency. A logic low (<1.8) disables PSM, maintaining
the higher switching frequency range set by ramp components. See Figure 1.
LATCH. Allows disabling fault latch. Recommend enabling fault latch protection
RAMP
28
6
I/O Sets a ramp on the feedback signal to increase the switching frequency. Add a resistor from PH to RAMP and
connect RAMP to VSENSE_CORE for a dc-coupled ramp. Add a capacitor from RAMP to VSENSE_CORE
to set an ac-coupled ramp.
SLOWST
I
Slowstart (softstart). A capacitor from SLOWST to GND sets the slowstart time for the ripple regulator and
the two linear regulators. The three converters will ramp up together while tracking the output voltage. A
current equal to I
/5 charges the capacitor.
(VREFB)
TG
20
30
18
15
O
I
Top gate drive. TG is an output drive to the high-side power switching FET’s. It is also used in the
anticross-conduction circuit to eliminate shoot-through current.
VBIAS
Analog VBIAS. It is recommended that at least a 1-µF capacitor be connected to ANAGND. Supply from V
through RC filter
CC
V
CC
Supply voltage. V
is the supply voltage for the FET drivers. Add an external resistor/capacitor filter from
VCC to VBIAS. It is recommended that a 1-µF capacitor be connected to the DRVGND terminal.
CC
VGATE
O
Logical and output of the combined core, IO, and CLK powergood. VGATE outputs a logic high when all
(core, IO, CLK) output voltages are within 7% of the reference voltage. An open drain output allows setting to
desired voltage level through a pullup resistor.
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SLVS334A − DECEMBER 2000 − REVISED SEPTEMBER 2001
Terminal Functions (Continued)
TERMINAL
NAME
VHYST
I/O
DESCRIPTION
NO.
8
I
Ripple regulator hysteresis set terminal. The hysteresis is set with a resistor divider from VREFB to ANGND.
The hysteresis voltage window will be the voltage between VREFB and VHYST.
VID0
VID1
VID2
VID3
VID4
VREFB
27
26
25
24
23
7
I
I
Voltage identification inputs 0, 1, 2, 3, and 4. These terminals are digital inputs that set the output voltage of
the converter. The code pattern for setting the output voltage is located in the terminal functions table. These
terminals are internally pulled up to VBIAS.
I
I
I
O
I
Buffered ripple regulator reference voltage from VID network
VR_ON
22
Enables the drive signals to the MOSFET drivers. The comparator input can be used to monitor voltage,
such as the linear regulators’ input supply using a resistor divider.
VSENSE_CLK
2
5
I
I
CLK feedback voltage sense. Connect to CLK linear regulator output voltage to regulate.
VSENSE_CORE
Feedback voltage sense input for the core. Connect to ripple regulator output voltage to sense and regulate
output voltage. It is recommended that an RC low-pass filter be connected at this pin to filter high-frequency
noise.
VSENSE_IO
31
I
I/O feedback voltage sense. Connect to I/O linear regulator output voltage to regulate.
detailed description
reference/voltage identification
The reference /voltage programming (VP) section consists of a temperature-compensated, bandgap reference
and a 5-bit voltage selection network. The five VID pins are inputs to the VID selection network and are TTL
compatible inputs that are internally pulled up to V
with pullup resistors. The internal reference voltage can
CC
be programmed from 0.925 V to 2 V with the VID pins. The VID codes are listed in Table 1. The output voltage
of the VP network, V , is within 1.5% of the nominal setting. The 1.5% tolerance is over the full VP range
ref
of 0.925 V to 2 V, and includes a junction temperature range of 0°C to 125°C, and a V
range of 4.5 V to 5.5 V.
CC
The output of the reference/VP network is indirectly brought out through a buffer to the VREFB pin. The voltage
on this pin will be within 5 mV of V . It is not recommended to drive loads with VREFB, other than setting the
ref
hysteresis of the hysteretic comparator, because the current drawn from VREFB sets the charging current for
the slowstart capacitor. Refer to the slowstart section for additional information.
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SLVS334A − DECEMBER 2000 − REVISED SEPTEMBER 2001
detailed description (continued)
Table 1. Voltage Programming Code
VID PINS
0 = GROUND, 1 = FLOATING, OR PULLUP TO 5 V
V
ref
VID4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VID3
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
VID2
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
VID1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
VID0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
(Vdc)
No CPU − Off
0.925
0.950
0.975
1.000
1.025
1.050
1.075
1.100
1.125
1.150
1.175
1.200
1.225
1.250
1.275
No CPU − Off
1.300
1.350
1.400
1.450
1.500
1.550
1.600
1.650
1.700
1.750
1.800
1.850
1.900
1.950
2.000
NOTE: If the VID bits are set to 11111 or 01111, then the high-side and low-side driver outputs
will be set low.
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SLVS334A − DECEMBER 2000 − REVISED SEPTEMBER 2001
detailed description (continued)
dynamic VID change
Dynamic VID change controls the rate of change of the programmed VID to allow transitioning within 100 µs,
while controlling the dv/dt to avoid large input surge currents. VID could change with any input voltage, output
voltage, or output current. A new change is ignored until the current transition is finished. Program the transition
by adding a capacitor from DT_SET to ANAGND.
I
Dt
REF
14 µA Dt
* V
Dt
C
+
+
DT_SET
DV
V
REF2
REF1
hysteretic comparator
The hysteretic comparator regulates the output voltage of the synchronous-buck converter. The hysteresis is
set by two external resistors and is centered around VREFB. The two external resistors form a resistor divider
from VREFB to ANAGND, and the divided down voltage connects to the VHYST terminal. The hysteresis of the
comparator will be equal to twice the voltage that is across the VREFB and VHYST pins. The maximum
hysteresis setting is 60 mV.
ramp generator
The ramp generator circuit is partially composed of the PSM circuit. An external resistor from PH to
VSENSE_CORE superimposes a ramp (proportional to V and V ) onto the feedback voltage. This allows
I
O
increasing the operating frequency, and reduces frequency dependance on the output filter values. A capacitor
can be used to provide ac-coupling. Also, connecting a resistor from V to VSENSE_CORE allows feed forward
I
to counteract any dc offsets due to the ramp generator or propagation delays limiting duty cycle.
power saving mode/latch
The power saving mode circuit reduces the operating frequency of the ripple regulator during light load. This
helps boost the efficiency during light loads by reducing the switching losses. Care should be taken to not allow
rms current losses to exceed the switching losses. A 2-bit binary weighted resistor ramp circuit allows setting
four operating frequencies.
The PSM/LATCH terminal allows disabling of the fault latch (see Table 2). This allows the user to troubleshoot
or implement an external protection circuit.
Table 2. PSM Program Modes
Pin Voltage
< (ANAGND − 0.3 V)
ANAGND to 1.8 V
2.3 V to VBIAS
Function
1
2
3
4
Disable PSM and disable fault latch
Disable PSM and enable fault latch
Enable PSM and enable fault latch
Enable PSM and disable fault latch
> (VBIAS + 0.3 V)
active voltage DROOP positioning
The droop compensation network reduces the load transient overshoot/undershoot on V , relative to V
.
O
ref
V
is programmed to a voltage greater than V in the Application Information drawing by an external
O(max)
ref
resistor divider from V to the VSENSE_CORE pin to reduce the undershoot on V
during a low to high load
O
OUT
transient. The overshoot during a high-to-low load transient is reduced by subtracting the voltage that is on the
DROOP pin from V . The voltage on the IOUT pin is divided down with an external resistor divider, and
ref
connected to the DROOP pin. Thus, under loaded conditions, V is regulated to V
− V
. The
O
O(max)
(DROOP)
continuous sensing of the inductor current allows a fast regulating voltage adjustment allowing higher transient
repetition rates.
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SLVS334A − DECEMBER 2000 − REVISED SEPTEMBER 2001
detailed description (continued)
low-side driver
The low-side driver is designed to drive low r
2-A source and 3.3-A sink. The supply to the low-side driver is internally connected to V
, N-channel MOSFETs. The current of the driver is typically
ds(on)
.
CC
high-side driver
The high-side driver is designed to drive low r
N-channel MOSFETs. The current of the driver is typically
ds(on)
2-A source and 3.3-A sink. The high-side driver is configured as a floating bootstrap driver. The internal
bootstrap diode, connected between the DRV and BOOT pins, is a Schottky diode for improved drive efficiency.
The maximum voltage that can be applied between the BOOT pin and ground is 35 V.
deadtime control
The deadtime control prevents shoot-through current from flowing through the main power FET’s during the
switching transitions by actively controlling the turnon times of the MOSFET drivers. The high-side driver is not
allowed to turn on until the gate drive voltage to the low-side FET is below 1.7 V. The low-side driver is not
allowed to turn on until the gate drive voltage from the high-side FET to PH is below 1.3 V.
current sensing
Current sensing is achieved by sensing the voltage across a current-sense resistor placed in series between
the output inductor and the output capacitors. The sensing network consists of a high bandwidth differential
amplifier with a gain of 25x to allow using sense resistors with values as low as 1 mΩ. Sensing occurs at all times
to allow having real-time information for quick response during an active voltage droop positioning transition.
The voltage on the IOUT pin equals 25 times the sensed voltage.
VR_ON
The VR_ON terminal is a TTL compatible digital pin that is used to enable the controller. When VR_ON is low,
the output drivers are low, the linear regulator drivers are off, and the slowstart capacitor is discharged. When
VR_ON goes high, the short across the slowstart capacitor is released and normal converter operation begins.
When the system logic supply is connected to the VR_ON pin, the VR_ON pin can control power sequencing
by locking out controller operation until the system logic supply exceeds the input threshold voltage of the
VR_ON circuit. Thus, V
and the system logic supply (either 5 V or 3.3 V) must be above UVLO thresholds
CC
before the controller is allowed to start up. Likewise, a microprocessor or other external logic can also control
the sequencing through VR_ON.
V
undervoltage lockout
BIAS
The VBIAS undervoltage-lockout circuit disables the controller, while VBIAS is below the 4.46-V start threshold
during power up. The controller is disabled when VBIAS goes below 3.3 V. While the controller is disabled, the
output drivers will be low and the slowstart capacitor will be shorted. When VBIAS exceeds the start threshold,
the short across the slowstart capacitor is released and normal converter operation begins.
IO linear regulator driver
The IO linear regulator driver circuit drives a high power NPN external power transistor, allowing external power
dissipation. The IO voltage is ramped up with the slowstart with the other two converters. Under voltage
protection protects against hard shorts or extreme loading. The VSENSE_IO voltage is monitored by the VGATE
(powergood) circuit. A fault or shutdown on any converter will shut down the linear regulator.
CLK linear regulator driver
The CLK linear regulator driver circuit drives a lower power NPN external power transistor, allowing external
power dissipation. The CLK voltage is ramped up with the slowstart with the other two converters. Under voltage
protection protects against hard shorts or extreme loading. The VSENSE_CLK voltage is monitored by the
VGATE (powergood) circuit. A fault or shutdown on any converter will shut down the linear regulator.
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SLVS334A − DECEMBER 2000 − REVISED SEPTEMBER 2001
detailed description (continued)
slowstart
The slowstart circuit controls the rate at which V
powers up. A capacitor is connected between the SLOWST
OUT
and ANAGND pins and is charged by an internal current source. The value of the current source is proportional
to the reference voltage, so that the charging rate of C is proportional to the reference voltage. By
(SLOWST)
making the charging current proportional to V , the power up time for V will be independent of V . Thus,
ref
O
ref
C
can remain the same value for all VP settings. The slowstart charging current is determined by the
(SLOWST)
following equation:
I(VREFB)
5
I
+
(amps)
SLOWSTART
where, I
is the current flowing out of the VREFB terminal. It is recommended that no additional loads be
(VREFB)
connected to VREFB, other than the resistor divider for setting the hysteresis voltage. Thus, these resistor
values will determine the slowstart charging current. The maximum current that can be sourced by the VREFB
circuit is 500 µA. The equation for setting the slowstart time is:
t
= 5 × C
× R
(seconds)
SLOWSTART
(SLOWSTART)
(VREFB)
where, R
is the total external resistance from VREFB to ANAGND.
(VREFB)
VGATE
The VGATE circuit monitors for an undervoltage condition on V
, V
, and
O(VSENSE_CORE)
O(VSENSE_IO)
V
. If any V is 7% below its reference voltage, or if any UVLO (V , VR_ON) threshold is not
O(VSENSE_CLK)
O cc
reached, then the VGATE pin is pulled low. The VGATE terminal is an open drain output.
overvoltage protection
The overvoltage protection circuit monitors V
, V
, and V
for an
O(VSENSE_CORE) O(VSENSE_IO)
O(VSENSE_CLK)
overvoltage condition. If any V is 15% above its reference voltage, then a fault latch is set, then both the ripple
O
regulator output drivers and the linear regulator drivers are turned off. The latch will remain set until VBIAS goes
below the undervoltage lockout value or until VR_ON is pulled low.
overcurrent protection
The overcurrent protection circuit monitors the current through the current sense resistor. The overcurrent
threshold is adjustable with an external resistor divider between IOUT and ANAGND terminals, with the divider
voltage connected to the OCP terminal. If the voltage on the OCP terminal exceeds 200 mV, then a fault latch
is set and the output drivers (ripple regulator and linear regulators) are turned off. The latch remains set until
VBIAS goes below the undervoltage lockout value or until VR_ON is pulled low.
thermal shutdown
Thermal shutdown disables the controller if the junction temperature exceeds the 165°C thermal shutdown trip
point. The hysteresis is 10°C.
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SLVS334A − DECEMBER 2000 − REVISED SEPTEMBER 2001
APPLICATION INFORMATION
Figure 1 is a standard application schematic. The circuit can be divided into the power-stage section and the
control-circuit section. The power stage that includes the power FETs (Q1−Q3), input capacitor (C2), output filter
(L1 and C3), and the current sense resistor (R1) must be tailored to the input/output requirements of the
application. The design documentation and test results for different mobile CPU power supplies covering core
current from 13 A and up to 40 A is available from the factory upon request or can be found in applications notes.
The control circuit is basically the same for all applications with minor tweaking of specific values.
The main waveforms are shown in Figure 2 through Figure 5. These waveforms include the following:
D
D
The output ripple and Vds voltage of the low-side FET in the whole input voltage range (see Figure 2).
The dynamic output voltage change between the performance and battery modes of operation (see
Figure 3).
D
D
The transient response characteristics on the load current step up and down transitions (see Figure 4).
The typical start-up waveforms for core, clock and I/O voltages (see Figure 5).
The waveforms confirm the excellent dynamic characteristics of the hysteretic controller. The modification, that
includes an additional ramp signal superimposed to the input VSENSE_CORE internally and externally by
circuits R17, R22, C13, and C10 makes the switching frequency independent of the output filter characteristics.
It also decreases the comparator delay times by increasing efficiency overdrive. This approach is shown in
Figure 6.
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SLVS334A − DECEMBER 2000 − REVISED SEPTEMBER 2001
APPLICATION INFORMATION
NOTES: A. Contact factory or see application notes for documentation and test results of different mobile core regulator applications at the
output current up to 40 A.
B. R21 allows VID code voltage adjustment.
Figure 1. Standard Application Circuit
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SLVS334A − DECEMBER 2000 − REVISED SEPTEMBER 2001
APPLICATION INFORMATION
I
= 24 A
I
= 24 A
O
I
O
I
V = 22 V
V = 6 V
(a)
NOTE: Channel 1 = drain source voltage (10 V/div), Channel 2 = output voltage ripple (50 nV/div)
(b)
Figure 2. Output Voltage Ripple and Low-Side FET Drain-Source Voltage
I
= 10 A
O
V = 4.5 V
I
NOTE: Channel 1 = input voltage ripple, Channel 2 = output voltage, Channel 3 = VGATE signal, Channel 4 = input current.
Figure 3. Dynamic VID-Code Change Waveforms From 1.35 V to 1.6 V and Back
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SLVS334A − DECEMBER 2000 − REVISED SEPTEMBER 2001
APPLICATION INFORMATION
V = 12 V
I
V = 12 V
I
NOTE: The load current (M3) has 10-A step with a slew rate
of 30 A/µs. Channel 3 = drain source of low-side FET,
and channel 4 = input current.
NOTE: From bottom to top: V
IO, V
OUT
core, V CLK,
OUT
OUT
and the voltage of the slow-start capacitor.
Figure 5. Start-Up Waveforms at 12 V Input
Voltage and 10-A Load Current on the
Switching Regulator
Figure 4. Output Voltage Transient Response
(Channel 2)
(V − V ) − Hysteresis Window
HI
(V
LO
− V
Because of Delays
) − Overshoot
MIN
MAX
V
HC
V
MAX
V
HI
V
REF
V
LO
V
MIN
V
Signal With
Superimposed Ramp
Output Ripple
(SENSE_CORE)
t
Figure 6. Hysteretic Comparator Input Waveforms
18
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ꢀꢁ ꢂ ꢃꢄ ꢅꢅ
SLVS334A − DECEMBER 2000 − REVISED SEPTEMBER 2001
APPLICATION INFORMATION
switching cycle and frequency calculation
The switching cycle calculation is shown below.
V Cadd Hyst Radd
V
V
I
V * V
I
I
T +
) Tdel1
) Tdel2
s
V
(V * V
V
O
I
O)
O
I
O
where, V = input voltage, V = output voltage, Cadd = C10 and Radd = R22 + R17 in Figure 1, Hyst is the
I
O
hysteresis window, Tdel1 and Tdel2 are the comparator and drive circuit delays when the high-side and low-side
FETs turn on correspondingly. The switching frequency variation for the different input and output voltages is
shown in Figure 7. In this case the parameters of equation above are the following: Radd = 49.9 kΩ,
Cadd = 1060 pF, Tdel1 = 240 ns, Tdel2 = 250 ns, Hyst = 0.5% of V . The lower-switching frequency at higher
O
input voltages helps to keep low switching losses during the input voltage range.
1000
900
800
V
= 2 V
700
600
500
400
300
200
100
0
O
V
O
= 1.65 V
V
= 1.3 V
O
4
5
6
7
8
9
10
11
12 13
V − Input Voltage − V
I
Figure 7. Theoretical (Solid) and Measured (Points) Switching Frequency
output voltage
The output voltage with a dc decoupling capacitor (C13) is defined below:
R1
R2
ǒ1 )
Ǔ
V
+ V
O
ref
where, R1 = R13 and R2 = R16 (see Figure 1)
additional literature
An Analytical Comparison of Alternative Control Techniques for Powering Next-Generation Microprocessors,
SEM−1400 TI/Unitrode Power Supply Design Seminar, Topic 1.
19
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PACKAGE OPTION ADDENDUM
www.ti.com
30-Jul-2011
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
TPS5300DAP
ACTIVE
ACTIVE
HTSSOP
HTSSOP
DAP
DAP
32
32
46
46
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
TPS5300DAPG4
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
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Addendum-Page 1
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