TPS53126
更新时间：2024-09-18 07:47:05
品牌：TI
描述：DUAL SYNCHRONOUS STEP-DOWN CONTROLLER FOR LOW VOLTAGE POWER RAILS
概述
数据手册
替代型号TPS53126 概述
DUAL SYNCHRONOUS STEP-DOWN CONTROLLER FOR LOW VOLTAGE POWER RAILS 双路同步降压控制器，适用于低压电源轨
TPS53126 数据手册
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www.ti.com ........................................................................................................................................................................................................ SLUS909–MAY 2009
DUAL SYNCHRONOUS STEP-DOWN CONTROLLER FOR LOW VOLTAGE POWER RAILS
1
FEATURES
APPLICATIONS
•
Point-of-Load Regulation in Low Power
Systems for Wide Range of Applications
2
•
D-CAP2™ Mode Control
–
–
Fast Transient Response
–
–
–
–
–
Digital TV Power Supply
Networking Home Terminal
Digital Set Top Box (STB)
DVD Player/Recorder
No External Parts Required For Loop
Compensation
–
Compatible with Ceramic Output
Capacitors
Gaming Consoles and Other
•
•
•
•
•
•
High Initial Reference Accuracy (±1%)
Low Output Ripple
DESCRIPTION
Wide Input Voltage Range: 4.5 V to 24 V
Output Voltage Range: 0.76 V to 5.5 V
Low-Side RDS(on) Loss-Less Current Sensing
The TPS53126 is
a
dual, adaptive on-time,
D-CAP2™ mode synchronous Buck controller. The
TPS53126 enables system designers to complete the
suite of various end equipment's power bus
Adaptive Gate Drivers with Integrated Boost
Diode
regulators with
a
cost effective, low external
component count, and low standby current solution.
The main control loop for the TPS53126 uses the
D-CAP2™ mode control which provides a very fast
transient response with no external components. The
TPS53126 also has a proprietary circuit that enables
the device to adapt to both low equivalent series
resistance (ESR) output capacitors, such as
POSCAP or SP-CAP, and ultra-low ESR ceramic
capacitors. The device provides convenient and
efficient operation with input voltages from 4.5 V to 24
V and output voltages from 0.76 V to 5.5 V.
•
•
•
Internal 1.2 ms Voltage-Servo Soft Start
Pre-Biased Soft Start
Selectable Switching Frequency: 350 kHz / 700
kHz
•
•
•
Cycle-by-Cycle Over-Current Limiting Control
30 mV to 300 mV OCP Threshold Voltage
Thermally Compensated OCP by 4000 ppm/C°
at ITRIP
The TPS53126 is available in 4mm x 4mm 24 pin
QFN (RGE) or 24 pin TSSOP (PW) packages and is
specified from –40°C to 85°C ambient temperature
range.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
D-CAP2 is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009, Texas Instruments Incorporated
TPS53126
SLUS909–MAY 2009........................................................................................................................................................................................................ www.ti.com
QFN APPLICATION DIAGRAM
Input Voltage
4.5V to 24V
C9
10mF
SGND
R5
10kW
R2
10kW
R4
3.52kW
R1
13kW
PGND
6
5
4
3
2
1
7
8
9
EN2
EN1 24
Q3
FDS8878
Q1
FDS8878
C2
0.1mF
C5
0.1mF
VBST2
DRVH2
VBST1 23
DRVH1 22
SW1 21
C3
10mF
C6
10mF
L2
SPM6530T
1.5mH
L1
SPM6530T
1.5mH
PowerPAD
TPS53126
RGE
(QFN)
10 SW2
VO2
1.05V/4A
VO1
1.8V/4A
C1
22mF ´ 4
Q4
FDS8690
Q2
FDS8690
11 DRVL2
12 PGND2
DRVL1 20
PGND1 19
C4
22mF ´ 4
13
14
15
16
17
18
R6
3.3kW
C7
4.7mF
R3
4.7kW
C8
1mF
PGND
PGND
PGND
SGND
2
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Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): TPS53126
TPS53126
www.ti.com ........................................................................................................................................................................................................ SLUS909–MAY 2009
TSSOP APPLICATION DIAGRAM
Q1
FDS8878
C3
10mF
C2
0.1mF
L1
SPM6530T
1.5mH
1
2
DRVH1
VBST1
SW1 24
VO1
1.8V/4A
C1
22mF ´ 4
Q2
FDS8690
DRVL1 23
3
4
EN1
VO1
PGND1 22
TRIP1 21
R1
13kW
R3
3.3kW
PGND
R2
10kW
Input Voltage
4.5V to 24V
5
6
7
8
9
VFB1
GND
VIN 20
VREG5 19
V5FILT 18
TEST2 17
TRIP2 16
C7
4.7mF
C9
10mF
TPS53126
PW
(TSSOP)
TEST1
VFB2
VO2
R5
10kW
C8
1mF
PGND
SGND
R6
4.3kW
R4
3.52kW
SGND
10 EN2
PGND2 15
DRVL2 14
SW2 13
Q4
FDS8690
PGND
11 VBST2
12 DRVH2
C4
22mF ´ 4
VO2
1.05V/4A
L2
SPM6530T
1.5mH
C6
10mF
C5
0.1mF
Q3
FDS8878
ORDERING INFORMATION(1)(2)
ORDERING PART
TA
PACKAGE
PINS
OUTPUT SUPPLY
ECO PLAN
NUMBER
Plastic Quad
Flat Pack (QFN)
TPS53126RGET
TPS53126RGER
TPS53126PWR
TPS53126PW
Tape-and-Reel
Tape-and-Reel
Tape-and-Reel
Tube
Green
(RoHS and no Sb/Br)
–40°C to 85°C
24
TSSOP
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) All packaging options have Cu NIPDAU lead/ball finish.
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ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
(1)
VALUE
–0.3 to 26
–0.3 to 32
–0.3 to 6
–0.3 to 6
–2 to 26
UNIT
VIN, EN1, EN2
VBST1, VBST2
Input voltage range
Output voltage range
VBST1, VBST2 (wrt SWx)
V5FILT, VFB1, VFB2, TRIP1, TRIP2, VO1, VO2, TEST1, TEST2
SW1, SW2
V
DRVH1, DRVH2
–1 to 32
DRVH1, DRVH2 (wrt SWx)
DRVL1, DRVL2, VREG5
PGND1, PGND2
–0.3 to 6
–0.3 to 6
–0.3 to 0.3
–40 to 85
–55 to 150
–40 to 150
V
TA
Operating ambient temperature range
Storage temperature range
°C
°C
°C
TSTG
TJ
Junction temperature range
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions are not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
DISSIPATION RATING TABLE (2 OZ. TRACE AND COPPER PAD WITH SOLDER)
TA < 25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
TA = 85°C
POWER RATING
PACKAGE
24 pin QFN
2.33 W
23.3 mW/°C
7.8 mW/°C
0.93 W
0.31 W
24 pin TSSOP
0.778 W
RECOMMENDED OPERATING CONDITIONS
MIN
4.5
MAX UNIT
VIN
Supply input voltage range
V5FILT
24
5.5
30
V
4.5
VBST1, VBST2
–0.1
–0.1
–0.1
–0.1
–0.1
–1.8
–0.1
–0.1
–0.1
–0.1
–40
VBST1, VBST2 (wrt SWx)
5.5
5.5
0.3
24
VFB1, VFB2, VO1, VO2, TEST1, TEST2
Input voltage range
Output voltage range
V
TRIP1, TRIP2
EN1, EN2
SW1, SW2
24
DRVH1, DRVH2
VBST1, VBST2 (wrt SWx)
DRVL1, DRVL2, VREG5
PGND1, PGND2
30
5.5
5.5
0.1
85
V
TA
TJ
Operating free-air temperature
Operating junction temperature
°C
°C
–40
125
ELECTRICAL CHARACTERISTICS
over recommended free-air temperature range, VIN = 12 V (Unless otherwise noted)
PARAMETER
SUPPLY CURRENT
CONDITIONS
MIN
TYP
MAX
UNIT
VIN current, TA = 25°C, VREG5 tied to V5FLT, EN1 =
EN2 = 5V, VFB1 = VFB2 = 0.8V, SW1 = SW2 = 0.5V
IIN
VIN supply current
450
30
800
60
µA
µA
VIN current, TA = 25°C, No load, EN1 = EN2 = 0 V,
VREG5 = ON
IVINSDN
VIN shutdown current
4
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ELECTRICAL CHARACTERISTICS (continued)
over recommended free-air temperature range, VIN = 12 V (Unless otherwise noted)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
VFB VOLTAGE and DISCHARGE RESISTANCE
Bandgap initial regulation
VBG
TA = 25°C
-1.0%
1.0%
accuracy
TA = 25°C, TEST2 = 0 V, SWinj = OFF
TA = –40°C to 85°C, TEST2 = 0 V, SWinj = OFF(1)
TA = 25°C, TEST2 = V5FILT, SWinj = OFF
TA = –40°C to 85°C, TEST2 = V5FILT, SWinj = OFF(1)
VFBx = 0.8 V, TA = 25°C
755
752
748
745
765
758
775
778
768
771
±0.1
80
VVFBTHLx
VFBx threshold voltage
mV
mV
VVFBTHHx
VFBx threshold voltage
IVFB
VFB input current
–0.01
40
µA
RDischg
VO discharge resistance
ENx = 0 V, VOx = 0.5 V, TA = 25°C
Ω
VREG5 OUTPUT
TA = 25°C, 5.5 V < VIN < 24 V,
0 < IVREG5 < 10 mA
VVREG5
VREG5 output voltage
4.8
5.0
5.2
V
VLN5
Line regulation
Load regulation
Output current
5.5 V < VIN < 24 V, IVREG5 = 10 mA
1 mA < IVREG5 < 10 mA
20
40
mV
mV
mA
VLD5
IVREG5
VIN = 5.5 V, VVREG5 = 4 V, TA = 25°C
170
OUTPUT: N-CHANNEL MOSFET GATE DRIVERS
Source, IDRVHx = –100 mA
Sink, IDRVHx = 100 mA
Source, IDRVLx = –100 mA
Sink, IDRVLx = 100 mA
5.5
2.5
4
11
5
RDRVH
RDRVL
TD
DRVH resistance
DRVL resistance
Dead time
Ω
Ω
8
2
4
DRVHx-low to DRVLx-on
DRVLx-low to DRVHx-on
20
20
50
40
80
80
ns
INTERNAL BOOST DIODE
VFBST
Forward voltage
VVREG5-VBSTx, IF = 10 mA, TA = 25°C
VBSTx = 29 V, SWx = 24 V, TA = 25°C
0.7
0.8
0.1
0.9
1
V
IVBSTLK
VBST leakage current
µA
ON-TIME TIMER CONTROL
TON1L
TON2L
TOFF1L
TOFF2L
TON1H
TON2H
CH1 on time
SW1 = 12 V, VO1 = 1.8 V, TEST2 = 0 V
490
390
285
285
165
140
ns
ns
ns
ns
ns
ns
CH2 on time
SW2 = 12 V, VO2 = 1.8 V, TEST2 = 0 V
CH1 min off time
CH2 min off time
CH1 on time
SW1 = 0.7 V, TA = 25°C, VFB1 = 0.7 V, TEST2 = 0 V
SW2 = 0.7 V, TA = 25°C, VFB2 = 0.7 V, TEST2 = 0 V
SW1 = 12 V, VO1 = 1.8 V, TEST2 = V5FILT
SW2 = 12 V, VO2 = 1.8 V, TEST2 = V5FILT
CH2 on time
SW1 = 0.7 V, TA = 25°C, VFB1 = 0.7 V, TEST2 =
V5FILT
TOFF1H
TOFF2H
SOFT START
CH1 min off time
216
216
ns
ns
SW2 = 0.7 V, TA = 25°C, VFB2 = 0.7 V, TEST2 =
V5FILT
CH2 min off time
Tss
Internal SS time
Internal soft start VFBx = 0.735 V
0.85
1.2
1.4
ms
V
UVLO
Wake up
3.7
0.2
4.0
0.3
4.3
0.4
VUV5VFILT V5FILT UVLO threshold
Hysteresis
LOGIC THRESHOLD
VENH
VENL
ENx H-level input voltage
ENx L-level input voltage
EN
EN
2.0
8.5
V
V
0.3
CURRENT SENSE
ITRIP
TRIP source current
VTRIPx = 0.1 V, TA = 25°C
10
11.5
µA
(1) Ensured by design. Not production tested.
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ELECTRICAL CHARACTERISTICS (continued)
over recommended free-air temperature range, VIN = 12 V (Unless otherwise noted)
PARAMETER
CONDITIONS
On the basis of 25°C(2)
MIN
TYP
MAX
UNIT
TCITRIP
ITRIP temperature coefficient
4000
ppm/°C
(VTRIPx-GND-VPGNDx-SWx) voltage,
VTRIPx-GND = 60 mV, TA = 25°C
–15
–20
30
0
15
20
VOCLoff
OCP compensation offset
mV
mV
(VTRIPx-GND-VPGNDx-SWx) voltage,
VTRIPx-GND = 60 mV
Current limit threshold setting
range
VRtrip
VTRIPx-GND voltage
300
OUTPUT UNDERVOLTAGE AND OVERVOLTAGE PROTECTION
VOVP
Output OVP trip threshold
Output OVP prop delay time
OVP detect
110% 115% 120%
1.5
TOVPDEL
µs
UVP detect
65%
70%
10%
30
75%
VUVP
Output UVP trip threshold
Output UVP delay time
Hysteresis (recovery < 20 µs)
TUVPDEL
TUVPEN
THERMAL SHUTDOWN
17
40
µs
Output UVP enable delay time UVP enable delay
1.2
2
2.5
ms
Shutdown temperature(3)
Hysteresis(3)
150
20
TSDN
Thermal shutdown threshold
°C
(2) Ensured by design. Not production tested.
(3) Ensured by design. Not production tested.
DEVICE INFORMATION
PIN FUNCTIONS
PIN
I/O
DESCRIPTION
QFN
24
TSSOP
24
NAME
Supply input for high-side NFET driver (Boost Terminal). Bypass to SWx with a
high-quality 0.1µF ceramic capacitor. An external schottky diode can be added if forward
drop is critical to drive the high-side FET.
VBST1,
VBST2
23, 8
2, 11
I
EN1, EN2
VO1, VO2
24, 7
1, 6
3, 10
4, 9
I
I
Channel 1 and channel 2 high level enable pins.
Output voltage inputs for on-time adjustment and output discharge. Connect directly to the
output voltage.
VFB1,
VFB2
2, 5
3
5, 8
6
I
I
D-CAP2 feedback inputs. Connect to output voltage with resistor divider.
GND
Signal ground pin. Connect to PGND1, PGND2 and system ground at a single point.
DRVH1,
DRVH2
High-side MOSFET gate driver outputs. SWx referenced drivers switch between SWx
(OFF) and VBSTx (ON).
22, 9
21, 10
20, 11
1, 12
24, 13
23, 14
O
SW1, SW2
I/O Switch node connections for both the high-side drivers and the current comparators.
DRVL1,
DRVL2
Low-side MOSFET gate driver outputs. PGND referenced drivers switch between PGNDx
(OFF) and VREG5 (ON).
O
PGND1,
PGND2
Power ground connections for both the low-side drivers and the current comparators.
Connect PGND1, PGND2 and GND strongly together near the IC.
19, 12
22, 15
I/O
TRIP1,
TRIP2
Over current trip point programming pin. Connect to GND with a resistor to GND to set
threshold for low-side RDS(on) current limit.
18, 13
17
21, 16
20
I
VIN
I
I
Supply Input for 5V linear regulator.
5V supply input for the entire control circuit except the MOSFET drivers. Bypass to GND
with a minimum 1.0µF, high-quality ceramic capacitor. V5FILT is connected to VREG5 via
an internal 10Ω resistor.
V5FILT
15
16
18
19
Output of 5V linear regulator and supply for MOSFET drivers. Bypass to GND with a
minimum 4.7µF high-quality ceramic capacitor. VREG5 is connected to V5FILT via an
internal 10Ω resistor.
VREG5
O
6
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TPS53126
www.ti.com ........................................................................................................................................................................................................ SLUS909–MAY 2009
PIN FUNCTIONS (continued)
PIN
I/O
DESCRIPTION
QFN
24
TSSOP
24
NAME
TEST1
TEST2
4
7
O
I
Test interface pin, not used during application. Connect directly to GND.
Frequency select pin. Connect to GND for 350kHz switching. Connect to V5FILT for
700kHz switching.
14
17
QFN (RGE) Package
(Top View)
TSSOP (PW) Package
(Top View)
1
24
23
22
21
20
19
18
17
16
15
14
13
DRVH1
VBST1
EN1
SW1
2
DRVL1
PGND1
TRIP1
VIN
3
4
VO1
1
2
3
4
5
6
18
VO1
VFB1
GND
TRIP1
VIN
5
VFB1
GND
6
VREG5
V5FILT
TEST2
TRIP2
PGND2
DRVL2
SW2
17
16
15
14
13
7
TEST1
VFB2
VO2
VREG5
V5FILT
TEST2
TRIP2
8
TEST1
VFB2
VO2
9
10
11
12
EN2
VBST2
DRVH2
FUNCTIONAL BLOCK DIAGRAM
VREG5
4V/3.7V
TSD
V5FILT
VO1
VO2
VBST1
VBST2
Ref
Fault
Sdn
BGR
Ref
DRVH1
DRVH2
SW2
Switcher Controller
Switcher Controller
SW1
Fault
Sdn
DRVL1
PGND1
DRVL2
PGND2
EN/SS Control
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–30%
UV
V5FILT
GND
OV
15%
Ref
ERR
SSx
COMP
V5OK
VFBx
VREG5
GND
Control Logic
TRIPx
VBSTx
DRVHx
SWx
OCP
LL
1 Shot
PGNDx
XCON
VREG5
DRVLx
PGNDx
LLx
VOx
On/Off Time
VOx
Minimun On/Off
OVP/UVP,
Discharge
Control
Fault
Sdn
ENx
PGNDx
8
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DETAILED DESCRIPTION
PWM OPERATION
The main control loop of the TPS53126 is an adaptive on-time pulse width modulation (PWM) controller that
supports a proprietary D-CAP2 mode control. D-CAP2 Mode control combines constant on-time control with an
internal compensation circuit for pseudo-fixed frequency and low external component count configuration with
both low ESR and ceramic output capacitors. It is stable even with virtually no ripple at the output.
At the beginning of each cycle, the high-side MOSFET is turned on. This MOSFET is turned off after internal one
shot timer expires. This one shot timer is set by the converter input voltage ,VIN, and the output voltage ,VO, to
maintain a pseudo-fixed frequency over the input voltage range, hence it is called adaptive on-time control. The
one-shot timer is reset and the high-side MOSFET is turned on again when the feedback voltage falls below the
reference voltage. An internal ramp is added to the reference voltage to simulate output ripple, eliminating the
need for ESR induced output ripple from D-CAP mode control.
DRIVERS
Each SMPS of the TPS53126 contains 2 high-current resistive MOSFET drivers. The Low-side driver is a ground
referenced, VREG5 powered driver designed to drive the gate of a high-current, low RDS(on) N-channel MOSFET
whose source is connected to PGND. The High-side Driver is a floating SW referenced VBST powered driver
designed to drive the gate of a high-current, low RDS(on) N-channel MOSFET. To maintain the BST voltage during
the high-side driver ON time, a capacitor is placed from SW to VBST. Each driver draws average current equal to
Gate Charge (Qg AT Vgs = 5V) times Switching Frequency (fsw).
To prevent cross-conduction, there is a narrow dead-time when both high-side and low-side drivers are OFF
between each driver transition. During this time the inductor current is carried by one of the MOSFETs body
diodes.
PWM FREQUENCY AND ADAPTIVE ON-TIME CONTROL
The TPS53126 uses an adaptive on-time control scheme and does not have a dedicated on board oscillator. The
TPS53126 runs with pseudo-constant frequency by using the input voltage and output voltage to set the on-time
one-shot timer. The on-time is inversely proportional to the input voltage and proportional to the output voltage,
therefore, when the duty ratio is VOUT/VIN, the frequency is constant.
5 VOLT REGULATOR
The TPS53126 has an internal 5V Low-Dropout (LDO) Regulator to provide a regulated voltage for all four
drivers and the ICs internal logic. A capacitor from VREG5 to GND is required to stabilize the internal regular. An
internal 10Ω resistor from VREG5 filters the regulator output to the IC’s analog and logic input voltage, V5FILT.
An additional capacitor is required from V5FILT to GND to filter switching noise from VREG5.
SOFT START
The TPS53126 has an internal, 1.2ms, voltage servo soft-start for each channel. When the ENx pin becomes
high, an internal DAC begins ramping up the reference voltage to the PWM comparator. Smooth control of the
output voltage is maintained during start up. As the TPS53126 shares one DAC with both channels, if ENx pin is
set to high while another channel is starting up, soft start is postponed until another channel soft start has
completed. If both of EN1 and EN2 are set high at a same time, both channels start up at same time.
PRE-BIAS SUPPORT
The TPS53126 supports pre-bias start-up without sinking current from the output capacitor. When enabled, the
low-side driver is held off until the soft-start commands a voltage higher than the pre-bias level (internal soft-start
becomes greater than feedback voltage [VFB]), then the TPS53126 slowly activates synchronous rectification by
limiting the first DRVL pulses with a narrow on-time. This limited on-time is then incremented on a cycle-by-cycle
basis until it coincides with the full 1-D off-time. This scheme prevents the initial sinking of current from the
pre-bias output, and ensure that the output voltage (VOUT) starts and ramps up smoothly into regulation and the
control loop is given time to transition from pre-biased start-up to normal mode operation.
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SWITCHING FREQUENCY SELECTION
The TPS53126 allows the user to select from 2 different switching frequencies by connecting the TEST2 pin to
either GND or V5FILT. Connect TEST2 to GND for a switching frequency (fsw) of 350KHz. Connect TEST2 to
V5FILT for a switching frequency of 700KHz.
OUTPUT DISCHARGE CONTROL
The TPS53126 discharges the outputs when ENx is low, or when the controller is turned off by the protection
functions (OVP, UVP, UVLO, and thermal shutdown). The device discharges an output using an internal 40-Ω
MOSFET which is connected to VOx and PGNDx. The external low-side MOSFET is not turned on during the
output discharge operation to avoid the possibility of causing negative voltage at the output. This discharge
ensures that, on start, the regulated voltage always initializes from zero volts.
OVERCURRENT LIMIT
The TPS53126 has a cycle-by-cycle over current limit feature. The over current limits the inductor valley current
by monitoring the voltage drop across the low-side MOSFET RDS(on) during the low-side driver on-time. If the
inductor current is larger than the over current limit (OCL), the TPS53126 delays the start of the next switching
cycle until the sensed inductor current falls below the OCL current. MOSFET RDS(on) current sensing is used to
provide an accuracy and cost effective solution without external devices. To program the OCL, the TRIPx pin
should be connected to GND through a trip voltage setting resistor, according to the following equations.
(VIN - Vo)
VO
Vtrip = IOCL ´ RDS(on)
-
´
2 ´ L1 ´ ¦sw
V
IN
(1)
Vtrip(mV)
Rtrip(kW) =
Itrip(mA)
(2)
The trip voltage should be between 30mV to 300mV over all operational temperature, including the 4000ppm/°C
temperature slope compensation for the temperature dependency of the RDS(on). If the load current exceeds the
over-current limit, the voltage will begin to drop. If the over-current conditions continues the output voltage will fall
below the under voltage protection threshold and the TPS53126 will shut down.
OVER/UNDER VOLTAGE PROTECTION
The TPS53126 monitors the output voltage via the feedback voltage to detect over and under voltage. When the
feedback voltage becomes higher than 115% of the reference voltage, the TPS53126 turns off the high-side
MOSFET driver, turns on the low-side MOSFET driver and latches off.
When the feedback voltage becomes lower than 70% of the reference voltage, the TPS53126 begins an internal
UVP delay counter. After 30µs, the TPS53126 turns off both top and bottom MOSFET drivers and latches off.
The UVP function is enabled approximately 2.0ms after power-on to prevent detecting UVP during soft-start.
Both OVP and UVP latch conditions are reset when V5FILT triggers UVLO or the ENx pin goes low.
UVLO PROTECTION
The TPS53126 has under voltage lock out protection (UVLO) that monitors the voltage of V5FILT pin. When the
V5FILT voltage is lower than UVLO threshold voltage, the device is shut off. During shut-off, VREG5 and all
output drivers are OFF and output discharge is ON. The UVLO is non-latch protection.
THERMAL SHUTDOWN
The TPS53126 includes an over temperature protection shut-down feature. If the TPS53126 die temperature
exceeds the OTP threshold (typically 150°C), both the high-side and low-side drivers are shut off, the output
voltage discharge function is enabled and then the device is shut off until the die temperature drops. Thermal
shutdown is a non-latch protection.
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TYPICAL CHARACTERISTICS
VIN SUPPLY CURRENT
vs
JUNCTION TEMPERATURE
VIN SHUTDOWN CURRENT
vs
JUNCTION TEMPERATURE
60
50
40
30
20
10
0
800
700
600
500
400
300
200
100
0
−50
0
50
100
150
−50
0
50
100
150
T − Junction Temperature − °C
J
T − Junction Temperature − °C
J
G001
G002
Figure 1.
Figure 2.
TRIP SOURCE CURRENT
vs
JUNCTION TEMPERATURE
VREG5 VOLTAGE
vs
JUNCTION TEMPERATURE
20
15
10
5
5.07
5.06
5.05
5.04
5.03
5.02
5.01
5.00
0
−50
0
50
100
150
−50
0
50
100
150
T − Junction Temperature − °C
J
T − Junction Temperature − °C
J
G003
G004
Figure 3.
Figure 4.
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TYPICAL CHARACTERISTICS (continued)
VREG5 VOLTAGE
vs
INPUT VOLTAGE
VFB1 VOLTAGE (CH1 = 1.8 V, IO = 4 A)
vs
JUNCTION TEMPERATURE
5.5
5.3
5.1
4.9
4.7
4.5
0.800
0.795
0.790
0.785
0.780
0.775
0.770
0.765
0.760
0.755
0.750
I
= 4A
OUT
VO1 = 1.8V
TEST2 = GND
0
5
10
15
20
25
−50
0
50
100
150
V
IN
− Input Voltage − V
T − Junction Temperature − °C
J
G005
G006
Figure 5.
Figure 6.
VFB2 VOLTAGE (CH2 = 1.05 V, IO = 4 A)
VFB1 VOLTAGE (CH1 = 1.8 V, IO = 4 A)
vs
vs
JUNCTION TEMPERATURE
JUNCTION TEMPERATURE
0.800
0.795
0.790
0.785
0.780
0.775
0.770
0.765
0.760
0.755
0.750
0.800
0.795
0.790
0.785
0.780
0.775
0.770
0.765
0.760
0.755
0.750
I
= 4A
I
= 4A
OUT
OUT
VO2 = 1.05V
VO1 = 1.8V
TEST2 = GND
TEST2 = V5FILT
−50
0
50
100
150
−50
0
50
100
150
T − Junction Temperature − °C
J
T − Junction Temperature − °C
J
G007
G008
Figure 7.
Figure 8.
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TYPICAL CHARACTERISTICS (continued)
VFB2 VOLTAGE (CH2 = 1.05 V, IO = 4 A)
VFB1 VOLTAGE (CH1 = 1.8 V)
vs
vs
JUNCTION TEMPERATURE
INPUT VOLTAGE
0.800
0.795
0.790
0.785
0.780
0.775
0.770
0.765
0.760
0.755
0.750
0.800
0.795
0.790
0.785
0.780
0.775
0.770
0.765
0.760
0.755
0.750
I
= 4A
VO1 = 1.8V
OUT
VO2 = 1.05V
TEST2 = GND
TEST2 = V5FILT
−50
0
50
100
150
0
5
10
15
20
25
T − Junction Temperature − °C
J
V
IN
− Input Voltage − V
G009
G010
Figure 9.
Figure 10.
VFB2 VOLTAGE (CH2 = 1.05 V)
VFB1 VOLTAGE (CH1 = 1.8 V)
vs
vs
INPUT VOLTAGE
INPUT VOLTAGE
0.800
0.795
0.790
0.785
0.780
0.775
0.770
0.765
0.760
0.755
0.750
0.800
0.795
0.790
0.785
0.780
0.775
0.770
0.765
0.760
0.755
0.750
VO2 = 1.05V
VO1 = 1.8V
TEST2 = GND
TEST2 = V5FILT
0
5
10
15
20
25
0
5
10
15
20
25
V
IN
− Input Voltage − V
V
IN
− Input Voltage − V
G011
G012
Figure 11.
Figure 12.
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TYPICAL CHARACTERISTICS (continued)
VFB2 VOLTAGE (CH2 = 1.05 V)
vs
INPUT VOLTAGE
0.800
VO2 = 1.05V
0.795
0.790
0.785
0.780
0.775
TEST2 = V5FILT
0.770
0.765
0.760
0.755
0.750
0
5
10
15
20
25
V
IN
− Input Voltage − V
G013
Figure 13.
TYPICAL APPLICATION PERFORMANCE
SWITCHING FREQUENCY (IO1 = 3A)
SWITCHING FREQUENCY (IO2 = 3A)
vs
vs
INPUT VOLTAGE (CH1)
INPUT VOLTAGE (CH2)
800
700
600
500
400
300
200
100
0
800
700
600
500
400
300
200
100
0
TEST2 = V5FILT
TEST2 = V5FILT
TEST2 = GND
TEST2 = GND
I
= 3A
I
= 3A
OUT
OUT
VO1 = 1.8V
VO2 = 1.05V
0
5
10
15
20
25
0
5
10
15
20
25
V
IN
− Input Voltage − V
V
IN
− Input Voltage − V
G014
G015
Figure 14.
Figure 15.
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TYPICAL APPLICATION PERFORMANCE (continued)
OUTPUT VOLTAGE (VIN = 12V)
vs
OUTPUT VOLTAGE (VIN = 12V)
vs
OUTPUT CURRENT (CH1)
OUTPUT CURRENT (CH2)
1.85
1.84
1.83
1.82
1.81
1.80
1.79
1.78
1.77
1.76
1.75
1.10
1.09
1.08
1.07
1.06
1.05
1.04
1.03
1.02
1.01
1.00
TEST2 = V5FILT
TEST2 = GND
TEST2 = V5FILT
TEST2 = GND
VIN = 12V
VO1 = 1.8V
VIN = 12V
VO2 = 1.05V
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
I
− Output Current − A
I
− Output Current − A
OUT
OUT
G016
G017
Figure 16.
Figure 17.
VO1 (50mV/div)
VO1 (50mV/div)
TEST2 = V5FILT
700kHz Selection
TEST2 = GND
350kHz Selection
Iout1 (2A/div)
Iout1 (2A/div)
t − time − 100µs/div
C
OUT
= 22µF × 2
t − time − 100µs/div
C
OUT
= 22µF × 4
G019
G018
Figure 18. 1.8V LOAD TRANSIENT RESPONSE
(CH1,TEST2 = GND)
Figure 19. 1.8V LOAD TRANSIENT RESPONSE
(CH1,TEST2 = V5FILT)
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TYPICAL APPLICATION PERFORMANCE (continued)
VO2 (50mV/div)
VO2 (50mV/div)
TEST2 = GND
350kHz Selection
TEST2 = V5FILT
700kHz Selection
Iout2 (2A/div)
Iout2 (2A/div)
t − time − 100µs/div
C
OUT
= 22µF × 4
t − time − 100µs/div
C
OUT
= 22µF × 2
G020
G021
Figure 20. 1.05V LOAD TRANSIENT RESPONSE
(CH2,TEST2 = V5FILT)
Figure 21. 1.05V LOAD TRANSIENT RESPONSE
(CH2,TEST2 = V5FILT)
EN2 (5V/div)
EN1 (10V/div)
VO2 (0.2V/div)
VO1 (0.5V/div)
TEST2 = GND
350kHz Selection
TEST2 = V5FILT
700kHz Selection
G022
G023
Figure 22. 1.8V START-UP WAVEFORMS
Figure 23. 1.05V START-UP WAVEFORMS
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TYPICAL APPLICATION PERFORMANCE (continued)
1.8V EFFICIENCY (VIN = 12V)
vs
OUTPUT CURRENT (CH1)
1.05V EFFICIENCY (VIN = 12V)
vs
OUTPUT CURRENT (CH2)
100
80
60
40
20
0
100
80
60
40
20
0
TEST2 = GND
350kHz Selection
TEST2 = V5FILT
700kHz Selection
VIN = 12V
VO1 = 1.8V
VIN = 12V
VO2 = 1.05V
0
1
2
3
4
0
1
2
3
4
I
− Output Current − A
I
− Output Current − A
OUT
OUT
G024
G025
Figure 24.
Figure 25.
1.8V OUTPUT VOLTAGE (IO = 3A)
1.05V OUTPUT VOLTAGE (IO = 3A)
vs
vs
INPUT VOLTAGE
INPUT VOLTAGE
1.90
1.88
1.86
1.84
1.82
1.80
1.78
1.76
1.74
1.72
1.70
1.15
1.13
1.11
1.09
1.07
1.05
1.03
1.01
0.99
0.97
0.95
TEST2 = V5FILT
TEST2 = GND
TEST2 = V5FILT
TEST2 = GND
I
= 3A
I
= 3A
OUT
OUT
VO1 = 1.8V
VO2 = 1.05V
0
5
10
15
20
25
0
5
10
15
20
25
V
IN
− Input Voltage − V
V
IN
− Input Voltage − V
G026
G027
Figure 26.
Figure 27.
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TYPICAL APPLICATION PERFORMANCE (continued)
VO1 (20mV/div)
VO2 (20mV/div)
TEST2 = GND
350kHz Selection
TEST2 = V5FILT
700kHz Selection
VO1 = 1.8V
VO2 = 1.05V
G028
G029
Figure 28. 1.8V OUTPUT RIPPLE VOLTAGE
Figure 29. 1.05V OUTPUT RIPPLE VOLTAGE
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APPLICATION INFORMATION
Input Voltage
4.5V to 24V
C9
10mF
SGND
R5
10kW
R2
10kW
R4
3.52kW
R1
13kW
PGND
6
5
4
3
2
1
7
8
9
EN2
EN1 24
Q3
FDS8878
Q1
FDS8878
C2
0.1mF
C5
0.1mF
VBST2
DRVH2
VBST1 23
DRVH1 22
SW1 21
C3
10mF
C6
10mF
L2
SPM6530T
1.5mH
L1
SPM6530T
1.5mH
PowerPAD
TPS53126
RGE
(QFN)
10 SW2
VO2
1.05V/4A
VO1
1.8V/4A
C1
22mF ´ 4
Q4
FDS8690
Q2
FDS8690
11 DRVL2
12 PGND2
DRVL1 20
PGND1 19
C4
22mF ´ 4
13
14
15
16
17
18
R6
3.3kW
C7
4.7mF
R3
4.7kW
PGND
PGND
C8
1mF
PGND
SGND
Figure 30. Typical Application Circuit at 350kHz Switching Frequency Selection (TEST2 Pin = GND)
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Input Voltage
4.5V to 24V
C9
10mF
SGND
R5
10kW
R2
10kW
R4
3.52kW
R1
13kW
PGND
6
5
4
3
2
1
7
8
9
EN2
EN1 24
Q3
FDS8878
Q1
FDS8878
C2
0.1mF
C5
0.1mF
VBST2
DRVH2
VBST1 23
DRVH1 22
SW1 21
C3
10mF
C6
10mF
L2
SPM6530T
1.5mH
L1
SPM6530T
1.5mH
PowerPAD
TPS53126
RGE
(QFN)
10 SW2
VO2
1.05V/4A
VO1
1.8V/4A
C1
22mF ´ 4
Q4
FDS8690
Q2
FDS8690
11 DRVL2
12 PGND2
DRVL1 20
PGND1 19
C4
22mF ´ 4
13
14
15
16
17
18
R6
3.3kW
C7
4.7mF
R3
4.7kW
PGND
PGND
C8
1mF
PGND
SGND
Figure 31. Typical Application Circuit at 700 kHz Switching frequency Selection (TEST2 Pin = V5FILT)
Component Selection:
1. Choose inductor.
The inductance value is selected to provide approximately 30% peak to peak ripple current at maximum load.
Larger ripple current increases output ripple voltage, improve S/N ratio and contribute to stable operation.
Equation 3 can be used to calculate L1.
V
- Vo1
3 ´
V
- Vo1
(
)
(
Io1 ´ ¦sw
)
´
IN(max)
IN(max)
Vo1
Vo1
L1 =
´
=
IL1(ripple) ´ ƒsw
V
V
IN(max)
IN(max)
(3)
The inductors current ratings needs to support both the RMS (thermal) current and the Peak (saturation)
current. The RMS and peak inductor current can be estimated as follows:
V
- Vo1
Vo1
IN(max)
IL1(ripple)
IL1(peak)
IL1(RMS)
=
´
L1 ´ ¦sw
V
IN(max)
(4)
Vtrip
=
+ IL1(ripple)
RDS(on)
(5)
(6)
2
)
=
Io12 + 1
I
(
L1(ripple)
12
Note: The calculation above shall serve as a general reference. To further improve transient response, the
output inductance could be reduced further. This needs to be considered along with the selection of the
output capacitor.
2. Choose output capacitor.
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The capacitor value and ESR determines the amount of output voltage ripple and load transient response.
Recommend to use ceramic output capacitor.
DIload2 ´ L1
C1 =
2 ´ Vo1 ´ DVos
(7)
ΔIload2 ´ L1
C1 =
2 ´ K ´ DVus
(8)
Where:
Tmin(off)
Ton1
Ton1
æ
ö
K = (V - Vo1) -
´ Vo1 ´
IN
ç
÷
Ton1 + Tmin(off)
è
ø
(9)
IL1(ripple)
1
C1 =
´
8 Vo1(ripple)
¦sw
(10)
Select the capacitance value greater than the largest value calculated from Equation 7, Equation 8 and
Equation 10. The capacitance for C1 should be greater than 66 µF.
Where:
ΔVos = the allowable amount of overshoot voltage in load transition
ΔVus = the allowable amount of undershoot voltage in load transition
Tmin(off) = Min-off time
3. Choose input capacitor.
The TPS53126 requires an input decoupling capacitor and a bulk capacitor is needed depending on the
application. A minimum 10-µF high-quality ceramic capacitor is recommended for the input capacitor. The
capacitor voltage rating needs to be greater than the maximum input voltage.
4. Choose bootstrap capacitor.
The TPS53126 requires a bootstrap capacitor from SWx to VBSTx to provide the floating supply for the
high-side drivers. A minimum 0.1-µF high-quality ceramic capacitor is recommended. The voltage rating
should be greater than 6 V.
5. Choose VREG5 and V5FILT capacitors.
The TPS53126 requires both the VREG5 regulator and V5FILT input are bypassed. A minimum 4.7-µF
high-quality ceramic capacitor must be connected between the VREG5 and GND for proper operation. A
minimum 1.0-µF high-quality ceramic capacitor must be connected between the V5FILT and GND for proper
operation. Both of these capacitors’ voltage ratings should be greater than 6 V.
6. Choose output voltage divide resistors.
The output voltage is set with a resistor divider from output voltage node to the VFBx pin. It is recommended
to use 1% tolerance or better resisters. Select R2 between 10 kΩ and 100 kΩ and use Equation 11 and
Equation 12 to calculate R1.
æ
ç
ç
ç
ç
è
ö
÷
Vo1
÷
R1 =
-1 ´R2
(TEST2=GND)
VFB1
÷
÷
ø
(ripple)
0.765 +
2
(11)
(12)
æ
ö
ç
÷
Vo1
R1 = ç
-1÷ ´R2
(TEST2 = V5FILT)
VFB1
(ripple)
ç
ç
è
÷
÷
ø
0.758 +
2
Where:
VFB1(ripple) = Ripple Voltage at VFB1
7. Choose resister setting for over current limit.
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æ
ö
÷
ø
(V - Vo)
VO
IN
Vtrip
=
I
+
´
´ RDS(on)
ç OCL
2 ´ L1 ´ ¦sw
V
IN
è
(13)
(14)
Vtrip(mV)
Rtrip(kW) =
Itrip(mA)
Where:
RDS(on) = Low Side FET on-resistance
Itrip = TRIP pin source current （= 10 µA）
IOCL = Over current limit
LAYOUT SUGGESTIONS
•
Keep the input switching current loop as small as possible.
•
Place the input capacitor (C3,C6) close to the top switching FET. The output current loop should also
be kept as small as possible.
•
Keep the SW node as physically small and short as possible as to minimize parasitic capacitance and
inductance and to minimize radiated emissions Kelvin connections should be brought from the
output to the feedback pin (FBx) of the device.
•
•
•
Keep analog and non-switching components away from switching components
Make a single point connection from the signal ground to power ground
Do not allow switching current to flow under the device
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PACKAGE OPTION ADDENDUM
www.ti.com
4-Jun-2009
PACKAGING INFORMATION
Orderable Device
TPS53126PW
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
TSSOP
PW
24
24
24
24
60 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TPS53126PWR
TPS53126RGER
TPS53126RGET
TSSOP
VQFN
VQFN
PW
RGE
RGE
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
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information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
2-Jun-2009
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) W1 (mm)
(mm) (mm) Quadrant
TPS53126PWR
TPS53126RGER
TPS53126RGET
TSSOP
VQFN
VQFN
PW
RGE
RGE
24
24
24
2000
3000
250
330.0
330.0
180.0
16.4
12.4
12.4
6.95
4.3
8.3
4.3
4.3
1.6
1.5
1.5
8.0
8.0
8.0
16.0
12.0
12.0
Q1
Q2
Q2
4.3
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
2-Jun-2009
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS53126PWR
TPS53126RGER
TPS53126RGET
TSSOP
VQFN
VQFN
PW
RGE
RGE
24
24
24
2000
3000
250
346.0
346.0
190.5
346.0
346.0
212.7
33.0
29.0
31.8
Pack Materials-Page 2
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
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TPS53126 替代型号
| 型号 | 制造商 | 描述 | 替代类型 | 文档 |
| TPS53124 | TI | Dual Synchronous Step-Down Controller For Low-Voltage Power Rails | 功能相似 |
|
| TPS53125 | TI | DUAL SYNCHRONOUS STEP-DOWN CONTROLLER FOR LOW VOLTAGE POWER RAILS | 功能相似 |
|
| TPS53127 | TI | DUAL SYNCHRONOUS STEP-DOWN CONTROLLER FOR LOW VOLTAGE POWER RAILS | 功能相似 |
|
TPS53126 相关器件
| 型号 | 制造商 | 描述 | 价格 | 文档 |
| TPS53126PW | TI | DUAL SYNCHRONOUS STEP-DOWN CONTROLLER FOR LOW VOLTAGE POWER RAILS | 获取价格 |
|
| TPS53126PWR | TI | DUAL SYNCHRONOUS STEP-DOWN CONTROLLER FOR LOW VOLTAGE POWER RAILS | 获取价格 |
|
| TPS53126RGER | TI | DUAL SYNCHRONOUS STEP-DOWN CONTROLLER FOR LOW VOLTAGE POWER RAILS | 获取价格 |
|
| TPS53126RGET | TI | DUAL SYNCHRONOUS STEP-DOWN CONTROLLER FOR LOW VOLTAGE POWER RAILS | 获取价格 |
|
| TPS53127 | TI | DUAL SYNCHRONOUS STEP-DOWN CONTROLLER FOR LOW VOLTAGE POWER RAILS | 获取价格 |
|
| TPS53127PW | TI | DUAL SYNCHRONOUS STEP-DOWN CONTROLLER FOR LOW VOLTAGE POWER RAILS | 获取价格 |
|
| TPS53127PWR | TI | DUAL SYNCHRONOUS STEP-DOWN CONTROLLER FOR LOW VOLTAGE POWER RAILS | 获取价格 |
|
| TPS53127RGER | TI | DUAL SYNCHRONOUS STEP-DOWN CONTROLLER FOR LOW VOLTAGE POWER RAILS | 获取价格 |
|
| TPS53127RGET | TI | DUAL SYNCHRONOUS STEP-DOWN CONTROLLER FOR LOW VOLTAGE POWER RAILS | 获取价格 |
|
| TPS53127_1 | TI | DUAL SYNCHRONOUS STEP-DOWN CONTROLLER FOR LOW VOLTAGE POWER RAILS | 获取价格 |
|
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