TPS53515RVET_技术文档

TPS53515

www.ti.com.cn

ZHCSBL7 –AUGUST 2013

高性能 12A 单通道同步降压转换器

1

特性

应用范围

2

•

宽转换输入电压范围：

1.5V 至 22V

•

服务器和云计算负载点 (POL)

I/O 电源

打印机

电信类

•

宽 VDD 输入电压：4.5V 至 25V

输出电压范围：0.6V 至 5.5V

带有 12A 持续输出电流的集成型功率金属氧化物半

导体场效应晶体管 (MOSFET)

说明

•

支持所有陶瓷输出电容器

TPS53515 是一款具有自适应接通时间 D-CAP3 模式

控制的小尺寸、单通道降压转换器。此器件为空间有

限的电源系统提供易于使用且低外部组件数量。

基准电压 600mV（耐受幅度 ±0.5%）

内置 5V 低压降稳压器 (LDO)

D-CAP3™ 100ns 负载阶跃响应模式

自动跳跃 Eco-mode™ 用于轻负载有效性

这个器件特有高性能集成 MOSFET，精准 0.5% 0.6V

基准和集成的升压开关。竞争优势包括极低外部组件

数量、快速负载瞬态响应、自动跳跃模式运行、内部软

启动控制，并且无需补偿。

针对严格输出纹波和电压要求的连续传导模式

(FCCM)

•

具有八个可选择频率设置的自适应接通时间控制架

构

转换输入电压范围介于 1.5V 至 22V 之间。 VDD 输入

电压的范围介于 4.5V 至 25V 之间。输出电压范围为

0.6V 至 5.5V。TPS53515 采用 28 引脚 QFN 封装，

额定温度范围介于 -40°C 至 +85°C 之间。

•

热关断

预充电启动功能

内置输出放电

开漏电源正常输出

集成升压开关

内置保护：过压、欠压、过流

3.5mm × 4.5mm 28 引脚四方扁平无引线 (QFN)

封装

PGOOD

V_IN

23

22

21

20

19

18

17

16

15

24 VO

PGND 14

PGND 13

PGND 12

PGND 11

PGND 10

25 TRIP

26 DNC

27 GND1

28 GND2

TPS53515

1

2

3

4

5

6

7

8

9

V_OUT

Thermal Pad

VREG

EN

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2

D-CAP3, Eco-mode are trademarks of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

English Data Sheet: SLUSBN5

TPS53515

ZHCSBL7 –AUGUST 2013

www.ti.com.cn

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

VALUE

MIN

UNIT

MAX

7.7

30

32

36

6

EN

–0.3

–3

DC

SW

Transient < 10 nS

–5

VBST

–0.3

Input voltage range⁽²⁾

VBST⁽³⁾

V

VBST when transient < 10 nS

VDD

38

28

30

6

–0.3

–40

VIN

VO, FB, MODE, RF

PGOOD

7.7

6

Output voltage range

Temperature

VREG, TRIP

Junction, T_J

Storage, T_stg

150

°C

–55

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods my affect device reliability.

(2) All voltages are with respect to network ground terminal.

(3) Voltage values are with respect to the SW terminal.

THERMAL INFORMATION

TPS53515

THERMAL METRIC⁽¹⁾

RVE

28 PINS

37.5

UNITS

θ_JA

Junction-to-ambient thermal resistance⁽²⁾

Junction-to-case (top) thermal resistance⁽³⁾

Junction-to-board thermal resistance⁽⁴⁾

Junction-to-top characterization parameter⁽⁵⁾

Junction-to-board characterization parameter⁽⁶⁾

Junction-to-case (bottom) thermal resistance⁽⁷⁾

θ_JCtop

θ_JB

34.1

18.1

°C/W

ψ_JT

1.8

ψ_JB

18.1

θ_JCbot

2.2

(1) 有关传统和全新热度量的更多信息，请参阅 IC 封装热度量应用报告（文献号：ZHCA543）。

(2) 在 JESD51-2a 描述的环境中，按照 JESD51-7 的规定，在一个 JEDEC 标准高 K 电路板上进行仿真，从而获得自然对流条件下的结至环

境热阻抗。

(3) 通过在封装顶部模拟一个冷板测试来获得结至芯片外壳（顶部）的热阻。不存在特定的 JEDEC 标准测试，但可在 ANSI SEMI 标准 G30-

88 中找到内容接近的说明。

(4) 按照 JESD51-8 中的说明，通过在配有用于控制 PCB 温度的环形冷板夹具的环境中进行仿真，以获得结至电路板的热阻。

(5) 结至顶部的特征参数，( ψ_JT)，估算真实系统中器件的结温，并使用 JESD51-2a（第 6 章和第 7 章）中描述的程序从仿真数据中提取出该

参数以便获得 θ_JA

(6) 结至电路板的特征参数，(ψ_JB)，估算真实系统中器件的结温，并使用 JESD51-2a（第 6 章和第7 章）中描述的程序从仿真数据中提取出该

参数以便获得 θ_JA

。

(7) 通过在外露（电源）焊盘上进行冷板测试仿真来获得结至芯片外壳（底部）热阻。不存在特定的 JEDEC 标准测试，但可在 ANSI SEMI

标准 G30-88 中找到了内容接近的说明。

间距

2

TPS53515

www.ti.com.cn

ZHCSBL7 –AUGUST 2013

RECOMMENDED OPERATING CONDITIONS

over operating free-air temperature range (unless otherwise noted)

MIN

–0.1

–3

MAX

7

UNIT

EN

SW

27

28

5.5

25

18

5.5

7

VBST

VBST⁽¹⁾

–0.1

4.5

Input voltage range

V

VDD

VIN

1.5

VO, FB, MODE, RF

PGOOD

–0.1

–40

Output voltage range

T_A

V

VREG, TRIP

5.5

85

Operating free-air temperature

°C

(1) Voltage values are with respect to the SW pin.

ELECTRICAL CHARACTERISTICS

over operating free-air temperature range, VREG = 5 V, EN = 5 V (unless otherwise noted)

PARAMETER

SUPPLY CURRENT

TEST CONDITIONS

MIN

TYP

MAX

UNIT

T_A= 25°C, No load

Power conversion enabled (no switching)

I_VDD

VDD bias current

1350

850

1850

µA

T_A= 25°C, No load

Power conversion disabled

I_VDDSTBY

I_VIN(leak)

VDD standby current

VIN leakage current

1150

0.5

µA

V_EN= 0 V

VREF OUTPUT

V_VREF

Reference voltage

FB w/r/t GND, T_A= 25°C

597

–0.7%

–1%

600

603

1.0%

1%

mV

FB w/r/t GND, T_J= 0°C to 85°C

FB w/r/t GND, T_J= –40°C to 85°C

V_VREFTOLReference voltage tolerance

OUTPUT VOLTAGE

I_FB

FB input current

V_FB= 600 mV

50

12

100

15

nA

I_VODIS

VO discharge current

V_VO= 0.5 V, Power Conversion Disabled

10

mA

SMPS FREQUENCY

V_IN= 12 V, V_VO= 3.3 V, R_DR< 0.041

V_IN= 12 V, V_VO= 3.3 V, R_DR= 0.096

V_IN= 12 V, V_VO= 3.3 V, R_DR= 0.16

V_IN= 12 V, V_VO= 3.3 V, R_DR= 0.229

V_IN= 12 V, V_VO= 3.3 V, R_DR= 0.297

V_IN= 12 V, V_VO= 3.3 V, R_DR= 0.375

V_IN= 12 V, V_VO= 3.3 V, R_DR= 0.461

V_IN= 12 V, V_VO= 3.3 V, R_DR> 0.557

T_A= 25°C⁽²⁾

250

300

400

500

600

750

850

1000

60

f_SW

VO switching frequency⁽¹⁾

kHz

t_ON(min)

Minimum on-time

Minimum off-time

ns

t_OFF(min)

T_A= 25°C

175

240

310

INTERNAL BOOTSTRAP SW

V_F

Forward Voltage

V_VREG–VBST, T_A= 25°C, I_F= 10 mA

T_A= 25°C, V_VBST= 33 V, V_SW= 28 V

0.15

0.01

0.25

1.5

V

I_VBST

VBST leakage current

µA

(1) Resistor divider ratio (R_DR) is described in Equation 1.

(2) Specified by design. Not production tested.

3

TPS53515

ZHCSBL7 –AUGUST 2013

www.ti.com.cn

ELECTRICAL CHARACTERISTICS (continued)

over operating free-air temperature range, VREG = 5 V, EN = 5 V (unless otherwise noted)

PARAMETER

LOGIC THRESHOLD

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V_ENH

EN enable threshold voltage

EN disable threshold voltage

EN hysteresis voltage

1.3

1.1

1.4

1.2

0.22

0

1.5

1.3

V

V_ENL

V_ENHYST

V_ENLEAK

V

EN input leakage current

–1

1

µA

SOFT START

t_SS

Soft-start time⁽³⁾

1

ms

PGOOD COMPARATOR

PGOOD in from higher

104%

89%

113%

80%

4

108%

92%

116%

84%

6

111%

96%

PGOOD in from lower

PGOOD out to higher

PGOOD out to lower

V_PGTH

VDDQ PGOOD threshold

120%

87%

I_PG

PGOOD sink current

PGOOD delay time

V_PGOOD= 0.5 V

mA

Delay tolerance for PGOOD going in

Delay for PGOOD coming out

V_PGOOD= 5 V

–20%

20%

1

t_PGDLY

I_PGLK

2

0

µs

PGOOD leakage current

–1

µA

CURRENT DETECTION

R_TRIPTRIP pin resistance range

20

10.1

7.2

70

13.9

11.0

–8.5

–6

kΩ

R_TRIP= 52.3 kΩ

R_TRIP= 38 kΩ

R_TRIP= 52.3 kΩ

R_TRIP= 38 kΩ

12.0

9.1

I_OCL

Current limit threshold, valley

A

–15.3

–12

–11.9

–9

Negative current limit threshold,

valley

I_OCLN

V_ZC

A

Zero cross detection offset

0

mV

PROTECTIONS

Wake-up

3.25

3.05

4.2

3.34

3.12

4.3

3.41

3.19

4.4

VREG undervoltage-lockout

(UVLO) threshold voltage

V_VREGUVLO

V

Shutdown

Wake-up (default)

Shutdown

V_VDDUVLOVDD UVLO threshold voltage

4

4.03

120%

4.16

124%

V_OVP

Overvoltage-protection (OVP)

threshold voltage

OVP detect voltage

116%

t_OVPDLY

V_UVP

OVP propagation delay

With 100-mV overdrive

UVP detect voltage

300

ns

Undervoltage-protection (UVP)

threshold voltage

64%

68%

71%

t_UVPDLY

UVP delay

UVP filter delay

1

ms

°C

THERMAL SHUTDOWN

Shutdown temperature

Hysteresis

140

40

T_SDN

Thermal shutdown threshold⁽⁴⁾

LDO VOLTAGE

V_REG

LDO output voltage

V_IN= 12 V, I_LOAD= 10 mA

V_IN= 4.5 V, I_LOAD= 30 mA, T_A= 25°C

V_IN= 12 V, T_A= 25°C

4.65

170

5

5.45

365

V

V_DOVREG

I_LDOMAX

LDO low droop drop-out voltage

LDO over-current limit

mV

mA

200

INTERNAL MOSFETS

R_DS(on)HHigh-side MOSFET on-resistance

R_DS(on)LLow-side MOSFET on-resistance

13.8

5.9

18

8

mΩ

(3) t_SS= 4 ms typical for the special trimming option.

(4) Specified by design. Not production tested.

4

TPS53515

www.ti.com.cn

ZHCSBL7 –AUGUST 2013

DEVICE INFORMATION

QFN

28-PIN

(TOP VIEW)

28

27

26

25

24

1

2

3

4

5

6

7

8

9

23

22

21

20

19

18

17

16

15

RF

PGOOD

EN

FB

GND

MODE

VREG

VDD

NC

VBST

NC

TPS53515

SW

VIN

SW

VIN

Thermal Pad

SW

VIN

10

11

12

13

14

PIN DESCRIPTIONS

I/O⁽¹⁾DESCRIPTION

NAME

EN

NO.

3

I

The enable pin turns on the DC-DC switching converter.

FB

23

V_OUTfeedback input. Connect this pin to a resistor divider between the VOUT pin and GND.

This pin is the ground of internal analog circuitry and driver circuitry. Connect GND to the PGND plane

with a short trace (For example, connect this pin to the thermal pad with a single trace and connect the

thermal pad to PGND pins and PGND plane).

GND

22

G

GND1

GND2

27

28

G

Connect this pin to ground. GND1 is the input of unused internal circuitry and must connect to ground.

Connect this pin to ground. GND2 is the input of unused internal circuitry and must connect to ground.

The MODE pin sets the forced continuous-conduction mode (FCCM) or Skip-mode operation. It also

selects the ramp coefficient of D-CAP3 mode.

MODE

21

I

5

NC

—

O

Not connected. These pins are floating internally.

18

26

10

11

12

13

14

DNC

Do not connect. This pin is the output of unused internal circuitry and must be floating.

PGND

G

These ground pins are connected to the return of the internal low-side MOSFET.

Open-drain power-good status signal which provides startup delay after the FB voltage falls within the

specified limits. After the FB voltage moves outside the specified limits, PGOOD goes low within 2 µs.

PGOOD

RF

2

1

O

I

RF is the SW-frequency configuration pin. Connect this pin to a resistor divider between VREG and

GND to program different SW frequency settings.

6

7

8

9

SW

B

SW is the output switching terminal of the power converter. Connect this pin to the output inductor.

(1) I = Input, O = Output, B = Bidirectional, P = Supply, G = Ground

5

TPS53515

ZHCSBL7 –AUGUST 2013

www.ti.com.cn

PIN DESCRIPTIONS (continued)

I/O⁽¹⁾DESCRIPTION

NAME

NO.

TRIP is the OCL detection threshold setting pin. I_TRIP= 10 µA at room temp, 3000 ppm/°C current is

I/O sourced and sets the OCL trip voltage. See the Current Sense and Overcurrent Protection section for

detailed OCP setting.

TRIP

25

VBST is the supply rail for the high-side gate driver (boost terminal). Connect the bootstrap capacitor

from this pin to the SW node. Internally connected to VREG via bootstrap PMOS switch.

VBST

VDD

4

P

19

15

16

17

20

24

P

Power-supply input pin for controller. Input of the VREG LDO. The input range is from 4.5 to 25 V.

VIN is the conversion power-supply input pins.

VIN

VREG

VO

O

I

VREG is the 5-V LDO output. This voltage supplies the internal circuitry and gate driver.

VOUT voltage input to the controller.

6

TPS53515

www.ti.com.cn

ZHCSBL7 –AUGUST 2013

BLOCK DIAGRAM

PGOOD

+

0.6 V + 8/16%

0.6 V ± 32%

+

UV

+

Delay

VREG

OV

0.6 V ± 8/16%

0.6 V+20%

Internal Ramp

Control Logic

RF

0.6 V

SS

UVP / OVP

Logic

+

PWM

OCP

VBST

VIN

VFB

10 µA

GND

+

1 SHOT

TRIP

LL

SW

XCON

+

ZC

Control

Logic

PGND

VO

SW

xꢀ On/Off time

xꢀ Minimum On/Off

xꢀ Light load

xꢀ OVP/UVP

xꢀ FCCM/SKIP

xꢀ Soft-Start

FCCM / SKIP

RC time Constant

MODE

Fault

Shut Down

LDO

VREG

VDD

+

VREGOK

3.34 V /

3.12 V

+

EN

VDDOK

THOK

Enable

4.3 V /

4.03 V

1.4 V / 1.2 V

+

140°C /

100°C

GND

GND1

GND2

NC

TPS53515

7

TPS53515

ZHCSBL7 –AUGUST 2013

www.ti.com.cn

APPLICATION CIRCUIT DIAGRAM

R1

6.65 Nꢀ

PGOOD

R2

C3

C4

2 kꢀꢀ

1 µF

Thermal

Pad

V_IN

C_IN

R6

150 Nꢀ

C_IN

2.2 nF

23

22

21

20

19

18

17

16

15

3 × 22 µF

24 VO

PGND 14

PGND 13

PGND 12

PGND 11

PGND 10

25 TRIP

26 DNC

27 GND1

28 GND2

R8

34.8 Nꢀ

TPS53515

1

2

3

4

5

6

7

8

9

PIMB065T±1R0MS-63

V_OUT

R4

249 Nꢀ

R10

100 Nꢀ

1 µH

R7

C2

R3

3 ꢀ

Thermal Pad

0 ꢀꢀ 0.1 µF

C_OUT

4 × 10 µF

6 × 22 µF

R5

105 Nꢀ

VREG

EN

C1

470 pF

Figure 1. Typical Application Circuit Diagram

8

TPS53515

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ZHCSBL7 –AUGUST 2013

TYPICAL CHARACTERISTICS

100

90

100

90

80

f_SW= 500 KHz, V_IN= 12 V, V_DD= 5 V

T_A= 25°C, L _OUT= 1 ꢀH, Mode = Auto-skip

f_SW= 500 KHz, V_IN= 12 V, V_DD= 5 V

T_A= 25°C, L _OUT= 1 ꢀH, Mode = FCCM

70

60

Vout = 0.6 V

V_OUT= 0.6 V

Vout = 1 V

V_OUT= 1 V

V_Oo_Uu_Tt = 1.5 V

Vout = 0.6 V

V_OUT= 0.6 V

Vout = 1 V

V_OUT= 1 V

V_Oo_Uu_Tt = 1.5 V

Vout = 1.2 V

OUT

V

out

OUT

= 1.8 V

V

= 2.5 V

V

out

OUT

= 1.8 V

V

= 2.5 V

out

OUT

out

OUT

V

= 3.3 V

V

= 5 V

V

= 3.3 V

V

= 5 V

Vout = 3.3 V

V_Oo_Uu_Tt = 5 V

Vout = 3.3 V

V_Oo_Uu_Tt = 5 V

OUT

60

0

2

4

6

8

10

12

0

2

4

6

8

10

12

Output Current (A)

C003

C004

Figure 2. Efficiency vs. Output Current

Figure 3. Efficiency vs. Output Current

100

90

100

90

80

70

60

50

80

70

f_SW= 1 MHz, V_IN= 12 V, V_DD= 5 V

T_A= 25°C, L _OUT= 1 ꢀH, Mode = Auto-Skip

f_SW= 1 MHz, V_IN= 12 V, V_DD= 5 V

T_A= 25°C, L _OUT= 1 ꢀH, Mode = FCCM

out

V_OUT= 0.6 V

Vout

1

out

V_OUT= 0.6 V

Vout

1

V_OUT= 1 V

60

V

= 1.2 V

V

= 1.5 V

= 2.5 V

= 5 V

V

= 1.2 V

out

V

= 1.5 V

= 2.5 V

= 5 V

out

V_Oo_Uu_Tt 1.5

OUT

V

= 1.8 V

= 3.3 V

V

= 1.8 V

= 3.3 V

V

V_Oo_Uu_Tt = 1.8 V

V_Oo_Uu_Tt = 2.5 V

V_Oo_Uu_Tt = 1.8 V

V_Oo_Uu_Tt = 2.5 V

V

V^Oo^Uu^Tt = 3.3 V

V^Oo^Uu^Tt = 5 V

V^Oo^Uu^Tt = 3.3 V

V^Oo^Uu^Tt = 5 V

50

0

2

4

6

8

10

12

2

4

6

8

10

12

Output Current (A)

C005

C006

Figure 4. Efficiency vs. Output Current

Figure 5. Efficiency vs. Output Current

1.3

1.25

1.2

1.3

1.25

1.2

f_SW= 500 KHz

V_DD= 5 V

V_OUT= 1.2 V

T_A= 25°C

L_OUT= 1 ꢀH

f_SW= 1 MHz

V_DD= 5 V

V_OUT= 1.2 V

T_A= 25°C

L_OUT= 1 ꢀH

Mode = Auto-skip

1.15

1.1

V_II_NN==55VV

IN = 12 V

V_IN= 12 V

IN = 12 V

V_IN= 12 V

VIN = 18 V

V_IN= 18 V

VIN = 18 V

V_IN= 18 V

10 12

1.1

0

2

4

6

8

10

12

2

4

6

8

Output Current (A)

C007

C008

Figure 6. Output Voltage vs. Output Current

Figure 7. Output Voltage vs. Output Current

9

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ZHCSBL7 –AUGUST 2013

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TYPICAL CHARACTERISTICS (continued)

1.3

1.25

1.2

1.3

f_SW= 500 KHz

V_DD= 5 V

T_A= 25°C

f_SW= 1 MHz

V_DD= 5 V

T_A= 25°C

L_OUT= 1 ꢀH

Mode = FCCM

V_OUT= 1.2 V

L_OUT= 1 ꢀH

Mode = FCCM

V_OUT= 1.2 V

1.25

1.2

1.15

1.1

1.15

1.1

V_II_NN==55VV

IN = 12 V

V_IN= 12 V

IN = 12 V

V_IN= 12 V

VIN = 18 V

V_IN= 18 V

VIN = 18 V

V_IN= 18 V

0

2

4

6

8

10

12

0

2

4

6

8

10

12

Output Current (A)

C009

C010

Figure 8. Output Voltage vs. Output Current

Figure 9. Output Voltage vs. Output Current

1200

1000

800

600

550

500

450

400

f_SW= 500 kHz

V_DD= 5 V

V_OUT= 1.2 V

T_A= 25°C

L_OUT= 1 ꢀH

Mode = FCCM

V_IN= 12 V, V_DD= 5 V, T_A= 25°C

L_OUT= 1 ꢀH, Mode = FCCM, V_OUT= 1.2 V

Fsw = 250 KHz

f_SW= 250 KHz

Ff_Ss_Ww==55000KKHHzz

Ff_Ss_Ww==11MMHHzz

600

V_II_NN==55VV

400

IN = 12 V

V_IN= 12 V

VIN = 18 V

V_IN= 18 V

200

1

2

3

4

5

6

7

8

9

10 11 12

1

2

3

4

5

6

7

8

9

10 11 12

Output Current (A)

C011

C012

Figure 10. Switching Frequency vs. Output Current

Figure 11. Switching Frequency vs. Output Current

100

85

70

55

40

25

100

85

70

55

40

25

V_IN= V_DD= 18 V

V_OUT= 1.2 V

f_SW= 1 MHz

L_OUT= 1 µH

V_IN= V_DD= 18 V

V_OUT= 5 V

f_SW= 1 MHz

L_OUT= 1 µH

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16

Output Current (A)

C001

C002

Figure 12. Safe Operating Area, V_OUT= 1.2 V

Figure 13. Safe Operating Area, V_OUT= 5 V

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TYPICAL CHARACTERISTICS (continued)

VIN = 12 V

VOUT = 1.2 V

Fsw = 1 MHz

VOUT = 1.2 V

Fsw = 1 MHz

Mode = Auto-skip

IOUT = 0 A

Mode = FCCM

IOUT = 0 A

Figure 14. Auto-Skip Steady-State Operation

Figure 15. FCCM Steady-State Operation

VIN = 12 V

VOUT = 1.2 V

Fsw = 1 MHz

VOUT = 1.2 V

Fsw = 1 MHz

Mode = Auto-skip

IOUT = 0.1 A

Mode = FCCM

IOUT = 0.1 A

Figure 16. Auto-Skip Steady-State Operation

Figure 17. FCCM Steady-State Operation

VIN = 12 V

VOUT = 1.2 V

Fsw = 1 MHz

VOUT = 1.2 V

Fsw = 1 MHz

Mode = Auto-skip

IOUT = 6 A

Mode = FCCM

IOUT = 6 A

Figure 18. Auto-Skip Steady-State Operation

Figure 19. FCCM Steady-State Operation

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TYPICAL CHARACTERISTICS (continued)

VIN = 12 V

VOUT = 1.2 V

Fsw = 1 MHz

VOUT = 1.2 V

Fsw = 1 MHz

Mode = Auto-skip

Idyn = 0 A to 6 A

Mode = FCCM

Idyn = 0 A to 6 A

Figure 20. Auto-Skip Mode Load Transient

Figure 21.

VIN = 12 V

VOUT = 1.2 V

Fsw = 1 MHz

VOUT = 1.2 V

Fsw = 1 MHz

Mode = Auto-skip

IOUT = 0 A

Mode = FCCM

IOUT = 0 A

Figure 22. Start-Up

Figure 23. Start-Up

VIN = 12 V

VOUT = 1.2 V

Fsw = 1 MHz

VOUT = 1.2 V

Fsw = 1 MHz

Mode = Auto-skip

IOUT = 6 A

Mode = FCCM

IOUT = 6 A

Figure 24. Start-Up

Figure 25. Start-Up

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TYPICAL CHARACTERISTICS (continued)

VIN = 12 V

VOUT = 1.2 V

Fsw = 1 MHz

VOUT = 1.2 V

Fsw = 1 MHz

Mode = Auto-skip

IOUT = 0 A

Mode = FCCM

IOUT = 0 A

Figure 26. Shut-Down Operation

Figure 27. Shut-Down Operation

VIN = 12 V

VOUT = 1.2 V

Fsw = 1 MHz

VOUT = 1.2 V

Fsw = 1 MHz

Mode = Auto-skip

IOUT = 6 A

Mode = FCCM

IOUT = 6 A

Figure 28. Shut-Down Operation

Figure 29. Shut-Down Operation

VIN = 12 V

VOUT = 1.2 V

Fsw = 500 KHz

Mode = Auto-skip

IOUT = 0 A

VIN = 12 V

VOUT = 1.2 V

Fsw = 1 MHz

Mode = Auto-skip

IOUT = 0 A

Pre-bias = 0.6 V

Figure 30. Pre-Bias Operation

Figure 31. Overvoltage Protection

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TYPICAL CHARACTERISTICS (continued)

VIN = 12 V

VOUT = 1.2 V

Fsw = 500 MHz

Mode = FCCM

Figure 32. Overcurrent Protection

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APPLICATION INFORMATION

General Description

The TPS53515 is a high-efficiency, single-channel, synchronous-buck converter. The device suits low-output

voltage point-of-load applications with 12-A or lower output current in computing and similar digital consumer

applications. The TPS53515 features proprietary D-CAP3 mode control combined with adaptive on-time

architecture. This combination builds modern low-duty-ratio and ultra-fast load-step-response DC-DC converters

in an ideal fashion. The output voltage ranges from 0.6 V to 5.5 V. The conversion input voltage ranges from 1.5

V to 22 V and the VDD input voltage ranges from 4.5 V to 25 V. The D-CAP3 mode uses emulated current

information to control the modulation. An advantage of this control scheme is that it does not require a phase-

compensation network outside which makes the device easy-to-use and also allows low-external component

count. Adaptive on-time control tracks the preset switching frequency over a wide range of input and output

voltage while increasing switching frequency as needed during load-step transient.

Frequency Selection

TPS53515 allows users to select the switching frequency by using the RF pin. Table 1 lists the divider ratio and

some example resistor values for the switching frequency selection. The 1% tolerance resistors with a typical

temperature coefficient of ±100 ppm/ºC are recommended. If the design requires a tighter noise margin for more

reliable SW-frequency detection, use higher performance resistors.

Table 1. Switching Frequency Selection

SWITCHING

FREQUENCY

(f_SW) (kHz)

RESISTOR

EXAMPLE RF FREQUENCY COMBINATIONS

DIVIDER RATIO⁽¹⁾

R_{RF_H}(kΩ)

R_{RF_L}(kΩ)

(R_DR

)

1000

850

750

600

500

400

300

250

> 0.557

0.461

0.375

0.297

0.229

0.16

1

300

154

120

105

71.5

47.5

27

180

200

249

240

249

255

270

0.096

< 0.041

11.5

(1) Resistor divider ratio (R_DR) is described in Equation 1.

space

R_DR

R_{RF _L}

=

R

(

+ R_{RF _H}

)

RF _L

where

•

R_{RF_L}is the low-side resistance of the RF pin resistor divider

R_{RF_H}is the high-side resistance of the RF pin resistor divider

(1)

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D-CAP3 Control and Mode Selection

R_R

SW

To comparator

C_R

V_OUT

Figure 33. Internal RAMP Generation Circuit

The TPS53515 uses D-CAP3 mode control to achieve fast load transient while maintaining the ease-of-use

feature. An internal RAMP is generated and fed to the VFB pin to reduce jitter and maintain stability. The

amplitude of the ramp is determined by the R-C time-constant as shown in Figure 33. At different switching

frequencies, (f_SW) the R-C time-constant varies to maintain relatively constant RAMP amplitude.

Select a MODE pin configuration as shown in Table 2 to double the R-C time-constant option. The MODE pin

also selects Skip-mode or FCCM-mode operation.

D-CAP3 Mode

From small-signal loop analysis, a buck converter using the D-CAP3 mode control architecture can be simplified

as shown in Figure 34.

VO

SW

C_C1

R_C1

V_IN

C_C2

R_C2

Sample

and Hold

DRVH

PWM

Comparator

Lx

R_FBH

Control

Logic

and

G

+

V_RAMP

V_OUT

FB

DRVL

Driver

R_CO

+

V_REF

R_LOAD

C_OUT

R_FBL

Figure 34. D-CAP3 Mode

The D-CAP3 control architecture in TPS53515 includes an internal ripple generation network enabling the use of

very low-ESR output capacitors such as multi-layer ceramic capacitors (MLCC). No external current sensing

networks or compensators are required with D-CAP3 control architecture in order to simplify the power supply

design. The role of the internal ripple generation network is to emulate the ripple component of the inductor

current information and then combine it with the voltage feedback signal. The 0-dB frequency of the D-CAP3

architecture can be approximated as shown in Equation 2.

R

´ C ´ 0.6´ 0.67 + D

C1

(

)

C1

f =

0

2p´ G´L ´ C

´ V

OUT

X

OUT

where

•

G is gain of the amplifier which amplifies the ripple current information generated by the network

D is the duty ratio

(2)

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The typical G value is 0.25. The R_C1C_C1time constant value varies according to the selected switching frequency

as shown in Table 2

In order to secure enough phase margin, consider that f₀should be lower than 1/3 of the switching frequency, but

is also higher than 5 times the f_C2as shown in Equation 3.

f

SW

5´ f £ f £

C2

0

3

where

•

f_C2is determined by the internal network of R_C2and C_C2(2.7 kHz typ)

(3)

This example describes a DC-DC converter with an input voltage range of 12-V and an output voltage of 1.2-V. If

the switching frequency is 500 kHz and the inductor is given as 1 uH, then C_OUTshould be larger than 80 μF,

and also be smaller than 1.7 mF based on the design requirements. The characteristics of the capacitors should

be also taken into considerations. For MLCC, use X5R or better dielectric and take into account derating of the

capacitance by both DC bias and AC bias. When derating by DC bias and AC bias are 80% and 50%,

respectively, the effective derating is 40% because 0.8 × 0.5 = 0.4. The capacitance of specialty polymer

capacitors may change depending on the operating frequency. Consult capacitor manufacturers for specific

characteristics.

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Sample and Hold Circuitry

S3

S1

R1

S2

S1

S2

CSP

Sampled_CSP

C1

C2

Buffer 1

Buffer 2

Figure 35. Sample and Hold Circuitry

The sample and hold circuitry is the difference between D-CAP3 and D-CAP2. The sample and hold circuitry,

which is a advance control scheme to boost output voltage accuracy higher on the TPS53515, is one of features

of the TPS53515. The sample and hold circuitry generates a new DC voltage of CSN instead of the voltage

which is produced by R_C2and C_C2which allows for tight output-voltage accuracy and makes the TPS53515 more

competitive.

CSP

CSN

CSP

CSN

CSN_NEW

(sample at valley of CSP)

CSN_NEW

(sample at valley of CSP)

Figure 36. Continuous Conduction Mode (CCM)

With Sample and Hold Circuitry

Figure 37. Dicontinuous Conduction Mode (DCM)

With Sample and Hold Circuitry

CSP

CSN

CSP

CSN

Figure 38. Continuous Conduction Mode (CCM)

Without Sample and Hold Circuitry

Figure 39. Dicontinuous Conduction Mode (DCM)

Without Sample and Hold Circuitry

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1.25

1.23

1.21

1.19

1.17

1.15

1.23

1.21

V_IN= 12 V

V_DD= 5 V

V_IN= 12 V

V_DD= 5 V

1.19

1.17

1.15

V_OUT= 1.2 V

f_SW= 500 kHz

T_A= 25°C

L_OUT= 1 ꢀH

Mode = FCCM

V_OUT= 1.2 V

f_SW= 500 kHz

T_A= 25°C

L_OUT= 1 ꢀH

Mode = Auto-skip

D-CAP3

D-CAP2

D-CAP3

D-CAP2

1

2

3

4

5

6

7

8

9

10 11 12

1

2

3

4

5

6

7

8

9

10 11 12

Output Current (A)

C013

C014

Figure 40. Output Voltage vs Output Current

Figure 41. Output Voltage vs Output Current

Table 2. Mode Selection and Internal RAMP RC Time Constant

SWITCHING

FREQUENCIES

f_SW(kHz)

MODE

ACTION

R_MODE

(kΩ)

R-C TIME

CONSTANT (µs)

SELECTION

60

50

250

and

300

400

600

850

250

400

600

850

250

400

600

850

250

400

600

850

250

400

600

850

500

750

0

40

30

and 1000

Skip Mode

Pull down to GND

120

100

80

and

300

500

750

150

20

150

0

60

and 1000

60

and

300

500

750

50

40

30

and 1000

Connect to

PGOOD

FCCM⁽¹⁾

120

100

80

and

300

500

750

60

and 1000

120

100

80

and

300

500

750

FCCM

Connect to VREG

60

and 1000

(1) Device goes into Forced CCM (FCCM) after PGOOD becomes high.

Auto-Skip Eco-mode™ Light Load Operation

While the MODE pin is pulled to GND directly or via 150-kΩ resistor, the TPS53515 automatically reduces the

switching frequency at light-load conditions to maintain high efficiency. This section describes the operation in

detail.

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As the output current decreases from heavy load condition, the inductor current also decreases until the rippled

valley of the inductor current touches zero level. Zero level is the boundary between the continuous-conduction

and discontinuous-conduction modes. The synchronous MOSFET turns off when this zero inductor current is

detected. As the load current decreases further, the converter runs into discontinuous-conduction mode (DCM).

The on-time is maintained to a level approximately the same as during continuous-conduction mode operation so

that discharging the output capacitor with a smaller load current to the level of the reference voltage requires

more time. The transition point to the light-load operation I_O(LL)(for example: the threshold between continuous-

and discontinuous-conduction mode) is calculated as shown in Equation 4.

V

- V

´ V

(

)

OUT OUT

V

IN

1

IN

I

=

´

OUT LL

( )

2´L ´ f

SW

where

•

f_SWis the PWM switching frequency

(4)

Using only ceramic capacitors is recommended for Auto-skip mode.

Adaptive Zero-Crossing

The TPS53515 uses an adaptive zero-crossing circuit to perform optimization of the zero inductor-current

detection during skip-mode operation. This function allows ideal low-side MOSFET turn-off timing. The function

also compensates the inherent offset voltage of the Z-C comparator and delay time of the Z-C detection circuit.

Adaptive zero-crossing prevents SW-node swing-up caused by too-late detection and minimizes diode

conduction period caused by too-early detection. As a result, the device delivers better light-load efficiency.

Forced Continuous-Conduction Mode

When the MODE pin is tied to the PGOOD pin through a resistor, the controller operates in continuous

conduction mode (CCM) during light-load conditions. During CCM, the switching frequency maintained to an

amost constant level over the entire load range which is suitable for applications requiring tight control of the

switching frequency at the cost of lower efficiency.

Power-Good

The TPS53515 has power-good output that indicates high when switcher output is within the target. The power-

good function is activated after the soft-start operation is complete. If the output voltage becomes within ±8% of

the target value, internal comparators detect the power-good state and the power-good signal becomes high

after a 1-ms internal delay. If the output voltage goes outside of ±16% of the target value, the power-good signal

becomes low after a 2-μs internal delay. The power-good output is an open-drain output and must be pulled-up

externally.

Current Sense and Overcurrent Protection

The TPS53515 has cycle-by-cycle overcurrent limiting control. The inductor current is monitored during the OFF

state and the controller maintains the OFF state during the period that the inductor current is larger than the

overcurrent trip level. In order to provide good accuracy and a cost-effective solution, the TPS53515 supports

temperature compensated MOSFET R_DS(on)sensing. Connect the TRIP pin to GND through the trip-voltage

setting resistor, R_TRIP. The TRIP terminal sources I_TRIPcurrent, which is 10 μA typically at room temperature, and

the trip level is set to the OCL trip voltage V_TRIPas shown in Equation 5.

V_TRIP= R_TRIP´I_TRIP

where

•

V_TRIPis in mV

R_TRIPis in kΩ

I_TRIPis in µA

(5)

The inductor current is monitored by the voltage between the GND pin and SW pin so that the SW pin is properly

connected to the drain terminal of the low-side MOSFET. I_TRIPhas a 3000-ppm/°C temperature slope to

compensate the temperature dependency of R_DS(on). The GND pin acts as the positive current-sensing node.

Connect the GND pin to the proper current sensing device, (for example, the source terminal of the low-side

MOSFET.)

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Because the comparison occurs during the OFF state, V_TRIPsets the valley level of the inductor current. Thus,

the load current at the overcurrent threshold, I_OCP, is calculated as shown in Equation 6.

I

V

- V

´ V

(

)

OUT OUT

V

IN

V

TRIP

1

IND(ripple)

IN

TRIP

I

=

+

=

+

´

OCP

2

2´L ´ f

8´R

DS(on)

SW

(

)

(

)

DS(on)

where

•

R_DS(on)is the on-resistance of the low-side MOSFET

R_TRIPis in kΩ

(6)

In an overcurrent condition, the current to the load exceeds the current to the output capacitor thus the output

voltage tends to decrease. Eventually, the output voltage crosses the undervoltage-protection threshold and

shuts down.

A special trimming option uses hiccup mode as the overcurrent protection (OCP).

Overvoltage and Undervoltage Protection

The TPS53515 monitors a resistor-divided feedback voltage to detect overvoltage and undervoltage. When the

feedback voltage becomes lower than 68% of the target voltage, the UVP comparator output goes high and an

internal UVP delay counter begins counting. After 1 ms, the TPS53515 latches OFF both high-side and low-side

MOSFETs drivers. The UVP function enables after soft-start is complete.

When the feedback voltage becomes higher than 120% of the target voltage, the OVP comparator output goes

high and the circuit latches OFF the high-side MOSFET driver and turns on the low-side MOSFET until reaching

a negative current limit. Upon reaching the negative current limit, the low-side FET is turned off and the high-side

FET is turned on again for a minimum on-time. The TPS53515 operates in this cycle until the output voltage is

pulled down under the UVP threshold voltage for 1 ms. After the 1-ms UVP delay time, the high-side FET is

latched off and low-side FET is latched on. The fault is cleared with a reset of VDD or by re-toggling EN pin.

Out-Of-Bounds Operation (OOB)

The TPS53515 has an out-of-bounds (OOB) overvoltage protection that protects the output load at a much lower

overvoltage threshold of 8% above the target voltage. OOB protection does not trigger an overvoltage fault, so

the device is not latched off after an OOB event. OOB protection operates as an early no-fault overvoltage-

protection mechanism. During the OOB operation, the controller operates in forced PWM mode only by turning

on the low-side FET. Turning on the low-side FET beyond the zero inductor current quickly discharges the output

capacitor thus causing the output voltage to fall quickly towards the setpoint. During the operation, the cycle-by-

cycle negative current limit is also activated to ensure the safe operation of the internal FETs.

UVLO Protection

The TPS53515 monitors the voltage on the VDD pin. If the VDD pin voltage is lower than the UVLO off-threshold

voltage, the switch mode power supply shuts off. If the VDD voltage increases beyond the UVLO on-threshold

voltage, the controller turns back on. UVLO is a non-latch protection.

Thermal Shutdown

The TPS53515 monitors internal temperature. If the temperature exceeds the threshold value (typically 140°C),

TPS53515 shuts off. When the temperature falls approximately 40°C below the threshold value, the device turns

on. Thermal shutdown is a non-latch protection.

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External Parts Selection

The external components selection is a simple process using D-CAP3™ Mode. Select the external components

using the following steps

1. CHOOSE THE SW FREQUENCY

The SW frequency is configured by the resistor divider on the RF pin. Select one of eight SW frequencies

from 250 kHz to 1 MHz. Refer Table 1 for the relationship between the SW frequency and resistor-divider

configuration.

2. CHOOSE THE OPERATION MODE

Select the operation mode using Table 2.

3. CHOOSE THE INDUCTOR

Determine the inductance value to set the ripple current at approximately ¼ to ½ of the maximum output

current. Larger ripple current increases output ripple voltage, improves S/N ratio, and helps stable operation.

V

(

IN

max

(

- V

´ V

V

- V

max

´ V

OUT

)

OUT

(

IN

OUT

)

(

)

1

3

L =

´

=

´

I

´ f

V

I

´ f

V

IN(max)

SW

IN

max

(

OUT

SW

IND ripple

(

max

)

(

)

(7)

The inductor requires a low DCR to achieve good efficiency. The inductor also requires enough room above

peak inductor current before saturation. The peak inductor current is estimated using Equation 8.

V

(

IN

max

(

- V

´ V

OUT

)

V

1

TRIP

I

=

+

´

IND peak

(

)

8´R

L ´ f

V

IN

SW

DS on

max

( )

(

(8)

4. CHOOSE THE OUTPUT CAPACITOR

The output capacitor selection is determined by output ripple and transient requirement. When operating in

CCM, the output ripple has two components as shown in Equation 9. Equation 10 and Equation 11 define

these components.

V

= V

+ V

RIPPLE

RIPPLE(C) RIPPLE(ESR)

(9)

I_{L ripple}

(

)

V_{RIPPLE C}

=

( )

8´ C_OUT´ f_SW

V_{RIPPLE ESR}= I_{L ripple}´ESR

(10)

(11)

(

)

(

)

5. DETERMINE THE VALUE OF R1 AND R2

The output voltage is programmed by the voltage-divider resistors, R1 and R2, shown in Figure 1. R1 is

connected between the VFB pin and the output, and R2 is connected between the VFB pin and GND. The

recommended R2 value is from 1 kΩ to 20 kΩ. Determine R1 using Equation 12.

V_OUT- 0.6

R1=

´R2

0.6

(12)

LAYOUT CONSIDERATIONS

Before beginning a design using the TPS53515, consider the following:

•

Place the power components (including input and output capacitors, the inductor, and the TPS53515) on the

solder side of the PCB. In order to shield and isolate the small signal traces from noisy power lines, insert and

connect at least one inner plane to ground.

•

All sensitive analog traces and components such as VFB, PGOOD, TRIP, MODE, and RF must be placed

away from high-voltage switching nodes such as SW and VBST to avoid coupling. Use internal layers as

ground planes and shield the feedback trace from power traces and components.

•

Pin 22 (GND pin) must be connected directly to the thermal pad. Connect the thermal pad to the PGND pins

and then to the GND plane.

Place the VIN decoupling capacitors as close to the VIN and PGND pins as possible to minimize the input

AC-current loop.

•

Place the feedback resistor near the IC to minimize the VFB trace distance.

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TPS53515

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•

Place the frequency-setting resistor (RF), OCP-setting resistor (R_TRIP) and mode-setting resistor (R_MODE

close to the device. Use the common GND via to connect the resistors to the GND plane if applicable.

Place the VDD and VREG decoupling capacitors as close to the device as possible. Provide GND vias for

each decoupling capacitor and ensure the loop is as small as possible.

The PCB trace is defined as switch node, which connects the SW pins and high-voltage side of the inductor.

The switch node should be as short and wide as possible.

Use separated vias or trace to connect SW node to the snubber, bootstrap capacitor, and ripple-injection

resistor. Do not combine these connections.

Place one more small capacitor (2.2 nF- 0402 size) between the VIN and PGND pins. This capacitor must be

placed as close to the IC as possible.

TI recommends placing a snubber between the SW shape and GND shape for effective ringing reduction.

The value of snubber design starts at 3 Ω + 470 pF.

)

Consider R,C,Cc network (Ripple injection network) component placement and place the AC coupling

capacitor, Cc, close to the device, and R and C close to the power stage.

See Figure 42 for the layout recommendation.

VIN Shape

To inner GND plane

C_IN

HF cap.

Cc

2

3

2

1

2

0

1

9

1

8

1

7

1

6

1

5

To VOUT Shape

VO

TRIP

PGND

DNC

GND Shape

GND1

GND2

C_OUT

1

2

3

4

5

6

7

8

9

VOUT Shape

SW Shape

L_OUT

To VREG Pin

Cap.

Res.

Trace on bottom layer

Trace of top layer

RCC On Bottom layer

Trace of bottom layer

Trace on inner layer

Figure 42. Layout Recommendation

23

PACKAGE OUTLINE

RVE0028A

VQFN - 1 mm max height

S

C

A

L

E

3

.

3

0

PLASTIC QUAD FLATPACK - NO LEAD

3.6

3.4

B

A

PIN 1 INDEX AREA

4.6

4.4

1.0

0.8

C

SEATING PLANE

0.08 C

0.05

0.00

2.1 0.1

2X 1.6

(0.2) TYP

14

EXPOSED

THERMAL PAD

10

24X 0.4

9

15

2X

29

SYMM

3.2

3.1 0.1

23

1

0.25

28X

0.15

28

24

0.1

C A B

PIN 1 ID

(OPTIONAL)

SYMM

28X

0.05

0.5

0.3

4219151/A 07/2022

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT

RVE0028A

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(2.1)

SYMM

28

24

28X (0.6)

28X (0.2)

23

1

(1.3) TYP

SYMM

24X (0.4)

29

(4.3)

(3.1)

(R0.05)

TYP

9

15

(

0.2) TYP

VIA

10

14

(3.3)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:18X

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

SOLDER MASK

OPENING

METAL

EXPOSED

METAL

EXPOSED

METAL

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4219151/A 07/2022

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

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EXAMPLE STENCIL DESIGN

RVE0028A

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

4X (0.94)

(0.57) TYP

28

24

28X (0.6)

1

23

28X (0.2)

24X (0.4)

(0.775)

TYP

29

SYMM

(4.3)

(R0.05) TYP

4X (1.35)

9

15

METAL

TYP

10

14

SYMM

(3.3)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD 29

78% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

SCALE:20X

4219151/A 07/2022

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

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型号：	TPS53515RVET
厂家：	TEXAS INSTRUMENTS
描述：	1.5V 至 18V、12A 同步 SWIFT™ 降压转换器 \| RVE \| 28 \| -40 to 85 输入元件开关转换器
文件：	总31页 (文件大小：35297K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TPS53515RVET [TI]

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