TPS54010PWPRG4_技术文档

Typical Size

6,4 mm X 9,7 mm

TPS54010

www.ti.com

SLVS509A–MAY 2004–REVISED AUGUST 2004

2.2 – 4 -V, 14-A OUTPUT SYNCHRONOUS BUCK PWM SWITCHER

WITH INTEGRATED FETs (SWIFT™)

FEATURES

DESCRIPTION

•

Separate Low-Voltage Power Bus

As a member of the SWIFT™ family of dc/dc regu-

lators, the TPS54010 low-input voltage, high-output

current synchronous buck PWM converter integrates

all required active components. Included on the

substrate with the listed features are a true, high-

performance, voltage error amplifier that enables

maximum performance under transient conditions

and flexibility in choosing the output filter L and C

components; an undervoltage-lockout circuit to pre-

vent start-up until the VIN input voltage reaches 3 V;

an internally and externally set slowstart circuit to limit

in-rush currents; and a power-good output useful for

processor/logic reset, fault signaling, and supply se-

quencing.

•

8-mΩ MOSFET Switches for High Efficiency at

14-A Continuous Output

•

Adjustable Output Voltage Down to 0.9 V

Externally Compensated With 1% Internal

Reference Accuracy

•

Fast Transient Response

Wide PWM Frequency: Adjustable 280 kHz to

700 kHz

•

Load Protected by Peak Current Limit and

Thermal Shutdown

Integrated Solution Reduces Board Area and

Total Cost

The TPS54010 is available in a thermally enhanced

28-pin TSSOP (PWP) PowerPAD™ package, which

eliminates bulky heatsinks.

APPLICATIONS

•

Low-Voltage, High-Density Systems With

Power Distributed at 2.5 V, 3.3 V Available

•

Point of Load Regulation for High-

Performance DSPs, FPGAs, ASICs, and

Microprocessors

•

Broadband, Networking, and Optical

Communications Infrastructure

SIMPLIFIED SCHEMATIC

EFFICIENCY

vs

2.5 V or 3.3 V

0.68 mH

Input1

OUTPUT CURRENT

Output

PVIN

PH

100

TPS54010

350 mF

0.047 mF

0.1 mF

200 mF

BOOT

PGND

95

90

85

3.3 V

Input2

1 mF

VIN

120 pF

4.64 kW

COMP

10 kW

80

75

70

VBIAS

VSENSE

3300 pF

AGND

422 W

1 mF

65

60

VIN = 3.3 V,

PVIN = 2.5 V,

14.7 kW

1500 pF

V

= 1.5 V,

Compensation

Network

O

55

50

f = 700 kHz

s

0

2

4

6

8

10

12

14 16

I

− Output Current − A

O

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

SWIFT, PowerPAD are trademarks of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

TPS54010

www.ti.com

SLVS509A–MAY 2004–REVISED AUGUST 2004

These devices have limited built-in ESD protection. The leads should be shorted together or the device

placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

ORDERING INFORMATION

T_A

-40°C to 85°C

OUTPUT VOLTAGE

PACKAGE

Plastic HTSSOP (PWP)⁽¹⁾

PART NUMBER

Adjustible down to 0.9 V

TPS54010PWP

(1) The PWP package is also available taped and reeled. Add an R suffix to the device type (i.e., TPS54010PWPR). See the application

section of the data sheet for PowerPAD drawing and layout information.

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted)

(1)

TPS54010

–0.3 to 7

–0.3 to 6

–0.3 to 4

–0.3 to 4.5

–0.3 to 10

–0.3 to 7

–0.6 to 6

UNIT

SS/ENA, SYNC

RT

V_I

Input voltage range

VSENSE

V

PVIN, VIN

BOOT

VBIAS, COMP, PWRGD

PH

V_O

Output voltage range

Source current

V

PH

Internally limited

COMP, VBIAS

PH

6

25

mA

A

I_S

Sink current

COMP

6

mA

SS/ENA, PWRGD

AGND to PGND

10

Voltage differential

±0.3

V

T_J

Operating junction temperature range

Storage temperature range

–40 to 125

–65 to 150

300

°C

kV

V

T_stg

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds

Human body model (HBM)

CDM

1.5

Electrostatic Discharge (ESD) ratings

750

(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating

conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

RECOMMENDED OPERATING CONDITIONS

MIN

3

NOM

MAX

4

UNIT

V

V_I

Input voltage, VIN

Power Input voltage, PVIN

Operating junction temperature

2.2

–40

4

V

T_J

125

°C

DISSIPATION RATINGS⁽¹⁾⁽²⁾

THERMAL IMPEDANCE

JUNCTION-TO-AMBIENT

T_A= 25°C

POWER RATING

T_A= 70°C

POWER RATING

T_A= 85°C

POWER RATING

PACKAGE

28-Pin PWP with solder

14.4°C/W

6.94 W⁽³⁾

3.81 W

2.77 W

28-Pin PWP without solder

27.9°C/W

3.58 W

1.97 W

1.43 W

(1) For more information on the PWP package, refer to TI technical brief, literature number SLMA002.

(2) Test board conditions:

a. 3 inch x 3 inch, 4 layers, thickness: 0.062 inch

b. 1.5-oz. copper traces located on the top of the PCB

c. 1.5-oz. copper ground plane on the bottom of the PCB

d. 0.5-oz. copper ground planes on the 2 internal layers

e. 12 thermal vias (see Recommended Land Pattern in applications section of this data sheet)

(3) Maximum power dissipation may be limited by over current protection.

2

TPS54010

www.ti.com

SLVS509A–MAY 2004–REVISED AUGUST 2004

ELECTRICAL CHARACTERISTICS

T_J= -40°C to 125°C, VIN = 3 V to 4 V, PVIN = 2.2 V to 4 V (unless otherwise noted)

PARAMETER

SUPPLY VOLTAGE, VIN

V_IInput voltage, VIN

TEST CONDITIONS

MIN

TYP

MAX UNIT

3

4

V

Supply voltage range, PVIN

Output = 1.8 V

2.2

f_s= 350 kHz, RT open, PH pin open, PVIN = 2.5 V,

SYNC = 0 V

6.3

8.3

10

13

mA

VIN

f_s= 550 kHz, RT open, PH pin open, SYNC ≥ 2.5 V,

PVIN = 2.5 V

SHUTDOWN, SS/ENA = 0 V, PVIN = 2.5 V

1

6

1.4

8

mA

I_Q

Quiescent current

f_s= 350 kHz, RT open, PH pin open, PVIN = 3.3 V,

SYNC = 0 V

PVIN

f_s= 550 kHz, RT open, PH pin open, SYNC ≥ 2.5 V,

PVIN = 2.5 V, VIN = 3.3 V

6

9

mA

µA

SHUTDOWN, SS/ENA = 0 V, VIN = 3.3 V

<140

UNDERVOLTAGE LOCKOUT (VIN)

Start threshold voltage, UVLO

Stop threshold voltage, UVLO

Hysteresis voltage, UVLO

2.95

2.8

3

V

2.7

0.11

2.5

V

Rising and falling edge deglitch, UVLO⁽¹⁾

µs

BIAS VOLTAGE

Output voltage, VBIAS

I_(VBIAS)= 0

2.7

2.8

2.9

V

Output current, VBIAS⁽²⁾

100

µA

CUMULATIVE REFERENCE

V_ref

REGULATION

Line regulation⁽¹⁾⁽³⁾

Load regulation⁽¹⁾⁽³⁾

Accuracy

0.882

0.891

0.900

V

I_L= 7 A, f_s= 350 kHz, T_J= 85°C

0.05

%/V

%/A

I_L= 0 A to 14 A, f_s= 350 kHz, T_J= 85°C

PVIN = 2.5 V, VIN = 3.3 V

0.013

OSCILLATOR

RT open⁽¹⁾, SYNC ≤ 0.8 V

280

440

252

460

663

2.5

350

550

280

500

700

420

660

308

540

762

Internally set—free running frequency

kHz

RT open⁽¹⁾, SYNC ≥ 2.5 V

RT = 180 kΩ (1% resistor to AGND)⁽¹⁾

RT = 100 kΩ (1% resistor to AGND)

RT = 68 kΩ (1% resistor to AGND)⁽¹⁾

Externally set—free running frequency range

High-level threshold voltage, SYNC

Low-level threshold voltage, SYNC

Pulse duration, SYNC⁽¹⁾

V

0.8

50

ns

kHz

V

Frequency range, SYNC

300

700

Ramp valley⁽¹⁾

0.75

1

Ramp amplitude (peak-to-peak)⁽¹⁾

Minimum controllable on time⁽¹⁾

Maximum duty cycle⁽¹⁾

V

200

ns

90%

(1) Specified by design

(2) Static resistive loads only

(3) Specified by the circuit used in Figure 12

3

TPS54010

www.ti.com

SLVS509A–MAY 2004–REVISED AUGUST 2004

ELECTRICAL CHARACTERISTICS (continued)

T_J= -40°C to 125°C, VIN = 3 V to 4 V, PVIN = 2.2 V to 4 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

ERROR AMPLIFIER

Error amplifier open-loop voltage gain

Error amplifier unity gain bandwidth

1 kΩ COMP to AGND⁽⁴⁾

90

3

110

5

dB

Parallel 10 kΩ, 160 pF COMP to AGND⁽⁴⁾

Powered by internal LDO⁽⁴⁾

VSENSE = V_ref

MHz

Error amplifier common mode input voltage

range

0

VBIAS

250

V

Input bias current, VSENSE

60

nA

Output voltage slew rate (symmetric), COMP

1

1.4

V/µs

PWM COMPARATOR

PWM comparator propagation delay time, PWM

comparator input to PH pin (excluding

deadtime)

10-mV overdrive⁽⁴⁾

70

85

ns

SLOW-START/ENABLE

Enable threshold voltage, SS/ENA

Enable hysteresis voltage, SS/ENA⁽⁴⁾

Falling edge deglitch, SS/ENA⁽⁴⁾

Internal slow-start time

0.82

1.2

0.03

2.5

1.4

V

µs

ms

µA

mA

2.6

2

3.35

5

4.1

8

Charge current, SS/ENA

SS/ENA = 0 V

Discharge current, SS/ENA

SS/ENA = 0.2 V, VIN = 2.7 V, PVIN = 2.5 V

1.3

2.3

4

POWER GOOD

Power-good threshold voltage

Power-good hysteresis voltage⁽⁴⁾

Power-good falling edge deglitch⁽⁴⁾

Output saturation voltage, PWRGD

Leakage current, PWRGD

VSENSE falling

93

3

%V_ref

µs

35

I_(sink)= 2.5 mA

0.18

0.3

1

V

VIN = 3.3 V, PVIN = 2.5 V

µA

CURRENT LIMIT

Current limit

VIN = 3.3 V, PVIN = 2.5 V ⁽⁴⁾, Output shorted

14.5

135

21

100

200

A

Current limit leading edge blanking time⁽⁴⁾

Current limit total response time⁽⁴⁾

ns

THERMAL SHUTDOWN

Thermal shutdown trip point⁽⁴⁾

Thermal shutdown hysteresis⁽⁴⁾

165

10

°C

OUTPUT POWER MOSFETS

VIN = 3 V, PVIN = 2.5 V

VIN = 3.6 V, PVIN = 2.5 V

8

21

18

r_DS(on)Power MOSFET switches

mΩ

(4) Specified by design

4

TPS54010

www.ti.com

SLVS509A–MAY 2004–REVISED AUGUST 2004

DEVICE INFORMATION

PWP PACKAGE

(TOP VIEW)

1

28

27

26

25

24

23

22

21

20

19

18

17

16

15

AGND

VSENSE

COMP

PWRGD

BOOT

PH

RT

SYNC

SS/ENA

VBIAS

VIN

PVIN

PGND

2

3

4

5

6

7

PH

THERMAL

PAD

8

9

10

11

12

13

14

TERMINAL FUNCTIONS

PIN NAME

PIN NUMBER DESCRIPTION

Analog ground. Return for compensation network/output divider, slow-start capacitor, VBIAS capacitor, and

RT resistor. If using the PowerPAD, connect it to AGND. See the Application Information section for

details.

AGND

1

Bootstrap output. 0.022-µF to 0.1-µF low-ESR capacitor connected from BOOT to PH generates floating

drive for the high-side FET driver.

BOOT

COMP

5

3

Error amplifier output. Connect frequency compensation network from COMP to VSENSE

Power ground. High current return for the low-side driver and power MOSFET. Connect PGND with large

copper areas to the input and output supply returns, and negative terminals of the input and output

capacitors. A single point connection to AGND is recommended.

15, 16, 17, 18,

19

PGND

PH

6-14

Phase output. Junction of the internal high-side and low-side power MOSFETs, and output inductor.

Input supply for the power MOSFET switches and internal bias regulator. Bypass the PVIN pins to the

PGND pins close to device package with a high-quality, low-ESR 10-µF ceramic capacitor.

PVIN

20, 21, 22, 23

Power-good open-drain output. High when VSENSE > 90% V_ref, otherwise PWRGD is low. Note that

output is low when SS/ENA is low or the internal shutdown signal is active.

PWRGD

RT

4

28

26

Frequency setting resistor input. Connect a resistor from RT to AGND to set the switching frequency, f_s.

Slow-start/enable input/output. Dual function pin which provides logic input to enable/disable device

operation and capacitor input to externally set the start-up time.

SS/ENA

Synchronization input. Dual function pin which provides logic input to synchronize to an external oscillator

or pin select between two internally set switching frequencies. When used to synchronize to an external

signal, a resistor must be connected to the RT pin.

SYNC

VBIAS

27

25

Internal bias regulator output. Supplies regulated voltage to internal circuitry. Bypass VBIAS pin to AGND

pin with a high-quality, low-ESR 0.1-µF to 1.0-µF ceramic capacitor.

Input supply for the internal control circuits. Bypass the VIN pin to the PGND pins close to device package

with a high-quality, low-ESR 1-µF ceramic capacitor.

VIN

24

2

VSENSE

Error amplifier inverting input. Connect to output voltage compensation network/output divider.

5

TPS54010

www.ti.com

SLVS509A–MAY 2004–REVISED AUGUST 2004

FUNCTIONAL BLOCK DIAGRAM

VBIAS

AGND

VIN

REG

VBIAS

3.0 − 4.0 V

2.2 − 4.0 V

Enable

Comparator

SS/ENA

Falling

Edge

Deglitch

SHUTDOWN

PVIN

ILIM

Comparator

1.2 V

Thermal

Shutdown

150°C

Hysteresis: 0.03 V

Leading

Edge

2.5 µs

Blanking

VIN UVLO

Comparator

Falling

and

100 ns

VIN

BOOT

Rising

Edge

2.95 V

Deglitch

Hysteresis: 0.11 V

8 mΩ

2.5 µs

SS_DIS

SHUTDOWN

L

OUT

V

O

PH

Internal/External

Slow-start

(Internal Slow-start Time = 3.35 ms

+

−

C

O

Adaptive Dead-Time

and

Control Logic

R

S

Q

Error

Amplifier

PWM

Comparator

Reference

VIN

VREF = 0.891 V

8 mΩ

OSC

PGND

Power-Good

Comparator

PWRGD

VSENSE

Falling

Edge

0.90 V

ref

Deglitch

TPS54010

Hysteresis: 0.03 Vref

SHUTDOWN

35 µs

VSENSE

COMP

RT SYNC

6

TPS54010

www.ti.com

SLVS509A–MAY 2004–REVISED AUGUST 2004

TYPICAL CHARACTERISTICS

DRAIN-SOURCE ON-STATE

RESISTANCE

INTERNALLY SET OSCILLATOR

FREQUENCY

RESISTANCE

vs

JUNCTION TEMPERATURE

12

10

8

12

750

VIN = 3.3 V,

VIN = 3.6 V,

PVIN = 2.5 V,

10

I

= 9 A

I

= 9 A

O

650

SYNC ≥ 2.5 V

8

6

4

2

0

550

6

450

4

2

0

SYNC ≤ 0.8 V

350

250

−40

0

25

85

125

−40 −20

0

20 40 60 80 100

100 125

0

20 40 60 80

T

J

− Junction Temperature − °C

T

J

− Junction Temperature − °C

T

J

− Junction Temperature − °C

Figure 1.

Figure 2.

Figure 3.

EXTERNALLY SET OSCILLATOR

FREQUENCY

VOLTAGE REFERENCE

vs

JUNCTION TEMPERATURE

DEVICE POWER DISSIPATION

vs

JUNCTION TEMPERATURE

OUTPUT CURRENT

0.895

0.893

0.891

0.889

8

800

700

600

V

= 1.5 V,

O

V = PVIN = 3.3 V,

7

6

5

4

3

2

I

T

J

= 125°C

RT = 68 kΩ

RT = 100 kΩ

RT = 180 kΩ

500

400

300

200

0.887

0.885

1

0

−40

0

25

85

125

−40

0

25

85

125

0

5

10

15

20

T

J

− Junction Temperature − °C

T

J

− Junction Temperature − °C

I

− Output Current − A

O

Figure 4.

Figure 5.

Figure 6.

REFERENCE VOLTAGE

vs

INTERNAL SLOWS-START TIME

vs

JUNCTION TEMPERATURE

ERROR AMPLIFIER

OPEN-LOOP RESPONSE

INPUT VOLTAGE

0

3.80

0.895

0.893

0.891

0.889

140

R

C

T

= 10 kΩ,

= 160 pF,

= 25°C

L

VIN = 3.3 V,

PVIN = 2.5 V

−20

120

100

80

L

3.65

3.50

−40

−60

−80

A

Phase

Gain

3.35

−100

−120

−140

−160

−180

−200

60

3.20

3.05

40

20

0.887

0.885

0

2.90

2.75

−20

1

10 100 1 k 10 k 100 k 1 M 10 M

−40

0

25

85

125

3

3.1

3.2

3.3

3.4

3.5

3.6

f − Frequency − Hz

T

J

− Junction Temperature − °C

V − Input Voltage − V

I

Figure 7.

Figure 8.

Figure 9.

7

TPS54010

www.ti.com

SLVS509A–MAY 2004–REVISED AUGUST 2004

APPLICATION INFORMATION

PCB LAYOUT

ANALOG GROUND TRACE

FREQUENCY SET RESISTOR

AGND

RT

SYNC

SS/ENA

VBIAS

VIN

INPUT

BYPASS

CAPACITOR

SLOW-START

CAPACITOR

VSENSE

COMP

COMPENSATION

NETWORK

BIAS CAPACITOR

PWRGD

BOOT

CAPACITOR

EXPOSED

POWERPAD

AREA

PH

PVIN

VOUT

PH

PVIN

PH

PGND

OUTPUT INDUCTOR

OUTPUT

PGND

FILTER

CAPACITOR

INPUT

BULK

BYPASS

CAPACITOR FILTER

TOPSIDE GROUND AREA

VIA to GROUND PLANE

Figure 10. TPS54010 Layout

The PVIN pins are connected together on the printed-

circuit board (PCB) and bypassed with a low ESR

ceramic bypass capacitor. Care should be taken to

minimize the loop area formed by the bypass capaci-

tor connections, the PVIN pins, and the TPS54010

ground pins. The minimum recommended bypass

capacitance is a 10-µF ceramic capacitor with a X5R

or X7R dielectric. The optimum placement is as close

as possible to the PVIN pins, the AGND, and PGND

pins. See Figure 10 for an example of a board layout.

If the VIN is connected to a separate source supply, it

is bypassed with its own capacitor. There is an area

of ground on the top layer of the PCB, directly under

the IC, with an exposed area for connection to the

PowerPAD. Use vias to connect this ground area to

any internal ground planes. Use additional vias at the

ground side of the input and output filter capacitors.

The AGND and PGND pins are tied to the PCB

ground by connecting them to the ground area under

the device as shown in Figure 10. Use a separate

wide trace for the analog ground signal path. This

analog ground is used for the voltage set point

divider, timing resistor RT, slow-start capacitor, and

bias capacitor grounds. The PH pins are tied together

and routed to the output inductor. Because the PH

connection is the switching node, an inductor is

located close to the PH pins, and the area of the PCB

conductor is minimized to prevent excessive capaci-

tive coupling. Connect the boot capacitor between the

phase node and the BOOT pin as shown in Fig-

ure 10. Keep the boot capacitor close to the IC, and

minimize the conductor trace lengths. Connect the

output filter capacitor(s) between the VOUT trace and

PGND. It is important to keep the loop formed by the

PH pins, Lout, Cout, and PGND as small as is

practical. Place the compensation components from

the VOUT trace to the VSENSE and COMP pins. Do

not place these components too close to the PH

trace. Due to the size of the IC package and the

device pinout, they must be routed close, but main-

8

TPS54010

www.ti.com

SLVS509A–MAY 2004–REVISED AUGUST 2004

tain as much separation as possible while keeping

the layout compact. Connect the bias capacitor from

the VBIAS pin to analog ground using the isolated

analog ground trace. If a slow-start capacitor or RT

resistor is used, or if the SYNC pin is used to select

350-kHz operating frequency, connect them to this

trace.

ted to the largest area available. Additional areas on

the top or bottom layers also help dissipate heat, and

any area available must be used when 6-A or greater

operation is desired. Connection from the exposed

area of the PowerPAD to the analog ground plane

layer must be made using 0.013-inch diameter vias to

avoid solder wicking through the vias.

For operation at full rated load current, the analog

Eight vias must be in the PowerPAD area with four

additional vias located under the device package. The

size of the vias under the package, but not in the

exposed thermal pad area, can be increased to

0.018. Additional vias beyond the twelve rec-

ommended that enhance thermal performance must

be included in areas not under the device package.

ground

plane

must

provide

an

adequate

heat-dissipating area. A 3-inch by 3-inch plane of

1-ounce copper is recommended, though not manda-

tory, depending on ambient temperature and airflow.

Most applications have larger areas of internal ground

plane available, and the PowerPAD must be connec-

Minimum Recommended Thermal Vias: 8 x 0.013 Diameter Inside

PowerPAD Area 4 x 0.018 Diameter Under Device as Shown.

Additional 0.018 Diameter Vias May Be Used if Top Side Analog Ground

Area Is Extended.

Ø0.0130

8 PL

4 PL Ø0.0180

Connect Pin 1 to Analog Ground Plane

in This Area for Optimum Performance

0.0150

0.06

0.0339

0.0650

0.0500

0.3820 0.3478

0.2090

0.0256

0.0500

0.0650

0.0339

Minimum Recommended Exposed

Copper Area for PowerPAD. 5mm

Stencils May Require 10 Percent

0.1700

Larger Area

0.1340

0.0630

Minimum Recommended Top

Side Analog Ground Area

0.0400

Figure 11. Recommended Land Pattern for 28-Pin PWP PowerPAD

9

TPS54010

www.ti.com

SLVS509A–MAY 2004–REVISED AUGUST 2004

µF

kΩ

µF

kΩ

µF

kΩ

µ

µF

kΩ

Figure 12. Application Circuit, 2.5 V to 1.5 V

Figure 12 shows the schematic for typical

a

TPS54010 application. The TPS54010 can provide

up to 14-A output current at a nominal output voltage

of 1.5 V. Nominal input voltages are 2.5 V for PVIN

and 3.3 V for VIN. For proper thermal performance,

the exposed PowerPAD underneath the device must

be soldered down to the printed-circuit board.

DESIGN PARAMETERS

To begin the design process, a few parameters must

be decided. The designer needs to know:

•

Input voltage range

Output voltage

Input ripple voltage

Output ripple voltage

Output current rating

Operating frequency

DESIGN PROCEDURE

The following design procedure can be used to select

component values for the TPS54010. Alternately, the

SWIFT Designer Software may be used to generate a

complete design. The SWIFT Designer Software uses

an iterative design procedure and accesses a com-

prehensive database of components when generating

a design. This section presents a simplified dis-

cussion of the design process.

For this design example, use the following as the

input parameters:

DESIGN PARAMETER

Input voltage (VIN)

EXAMPLE VALUE

3.3 V

Input voltage range (PVIN)

Output voltage

2.2 to 3.5 V

1.5 V

Input ripple voltage

Output ripple voltage

Output current rating

Operating frequency

300 mV

50 mV

14 A

700 kHz

10

TPS54010

www.ti.com

SLVS509A–MAY 2004–REVISED AUGUST 2004

SWITCHING FREQUENCY

capacitors, TDK C3225X5R1C106M are each rated

for 16 V, and the ripple current capacity is greater

than 3 A at the operating frequency of 700 kHz. Total

ripple current handling is in excess of 10.4 A. It is

important that the maximum ratings for voltage and

current are not exceeded under any circumstance.

The switching frequency can be set to either one of

two internally programmed frequencies or set to a

externally programmed frequency. With the RT pin

open, setting the SYNC pin at or above 2.5 V selects

550-kHz operation, whereas grounding or leaving the

SYNC pin open selects 350-kHz operation. For this

design, the switching frequency is externally pro-

grammed using the RT pin. By connecting a resistor

(R4) from RT to AGND, any frequency in the range of

250 to 700 kHz can be set. Use Equation 1 to

determine the proper value of RT.

OUTPUT FILTER COMPONENTS

Two components need to be selected for the output

filter, L1 and C2. Because the TPS54010 is an

externally compensated device, a wide range of filter

component types and values can be supported.

500 kHz

ƒs(kHz)

R4(kW) +

100 kW

Inductor Selection

(1)

To calculate the minimum value of the output induc-

tor, use Equation 4

In this example circuit, R4 is calculated to be 71.5 kΩ

and the switching frequency is set at 700 kHz.

ǒ_{Vin(MAX) OUT}Ǔ

V

* V

OUT

INPUT CAPACITORS

L

+

MIN

V

K

I

F

sw

The TPS54010 requires an input de-coupling capaci-

tor and, depending on the application, a bulk input

capacitor. The minimum value for the de-coupling

capacitor, C9, is 10 µF. A high-quality ceramic type

X5R or X7R is recommended. The voltage rating

should be greater than the maximum input voltage.

Additionally, some bulk capacitance may be needed,

especially if the TPS54010 circuit is not located within

about 2 inches from the input voltage source. The

value for this capacitor is not critical but it also should

be rated to handle the maximum input voltage includ-

ing ripple voltage, and should filter the output so that

input ripple voltage is acceptable.

IN(MAX)

IND

OUT

(4)

K_INDis a coefficient that represents the amount of

inductor ripple current relative to the maximum output

current. For designs using low ESR output capacitors

such as ceramics, use K_IND= 0.3. When using higher

ESR output capacitors, K_IND= 0.2 yields better

results.

For this design example, use K_IND= 0.2 to keep the

inductor ripple current small. The minimum inductor

value is calculated to be 0.44 µH.

For the output filter inductor, it is important that the

RMS current and saturation current ratings not be

exceeded. The RMS inductor current can be found

from Equation 5:

This input ripple voltage can be approximated by

Equation 2:

I

0.25

2

OUT(MAX)

₎ǒ_IOUT(MAX)

_MAXǓ

DV

+

ESR

ȡ

ȣ

ȧ

ǒ_Vin(MAX)

IN(MAX)

Ǔ

sw

* V

PVIN

OUT

F

OUT

C

ƒ

sw

1

12

I

+

I²

)

V

OUT

BULK

Ǹ

ȧ

Ȣ

L(RMS)

OUT(MAX)

V

L

^0.8Ȥ

(2)

Where I_OUT(MAX)is the maximum load current.

(5)

The TPS54010 requires an input de-coupling capaci-

tor and, depending on the application, a bulk input

capacitor. ƒ_swis the switching frequency, C_(BULK)is

the bulk capacitor value and ESR_MAXis the maximum

series resistance of the bulk capacitor.

and the peak inductor current can be found from

Equation 6

ǒ_{Vin(MAX) OUT}Ǔ

V

* V

OUT

1.6 V

I

+ I

)

L(PK)

OUT(MAX)

L

F

sw

IN(MAX)

OUT

The maximum RMS ripple current also needs to be

checked. For worst-case conditions, this can be

approximated by Equation 3:

(6)

For this design, the RMS inductor current is 15.4 A,

and the peak inductor current is 15.1 A. For this

design, a Vishay IHLP2525CZ-01 style output induc-

tor is specified. The largest value greater than 0.44

µH that meets these current requirements is 0.68 µH.

Increasing the inductor value decreases the ripple

I

OUT(MAX)

I

+

CIN

2

(3)

In this case, the input ripple voltage would be 155 mV

and the RMS ripple current would be 7 A. The

maximum voltage across the input capacitors would

be Vin max plus delta Vin/2. The chosen bulk

capacitor, a Sanyo POSCAP 6TPD330M is rated for

6.3 V and 4.4 A of ripple current; two bypass

11

TPS54010

www.ti.com

SLVS509A–MAY 2004–REVISED AUGUST 2004

current and the corresponding output ripple voltage.

The inductor value can be decreased if more margin

in the RMS current is required. In general, inductor

values for use with the TPS54010 falls in the range of

0.47 to 2.2 µH.

specified in the initial design parameters. The output

ripple voltage is the inductor ripple current times the

ESR of the output filter; therefore, the maximum

specified ESR as listed in the capacitor data sheet is

given by Equation 9 :

ȡ_V

_0.8ȣ

ȧ

L

F

sw

OUT

^IN(MAX)ǒ_V

_OUTǓ

Capacitor Requirements

ESR

+ N

DV

ȧ

Ȣ

MAX

C

P*P(MAX)

V

* V

IN(MAX)

The important design factors for the output capacitor

are dc voltage rating, ripple current rating, and

equivalent series resistance (ESR). The dc voltage

and ripple current ratings cannot be exceeded. The

ESR is important because along with the inductor

current it determines the amount of output ripple

voltage. The actual value of the output capacitor is

not critical, but some practical limits do exist. Con-

sider the relationship between the desired

closed-loop crossover frequency of the design and

LC corner frequency of the output filter. In general, it

is desirable to keep the closed-loop crossover fre-

quency at less than 1/5 of the switching frequency.

With high switching frequencies such as the 500 kHz

frequency of this design, internal circuit limitations of

the TPS54010 limit the practical maximum crossover

frequency to about 70 kHz. To allow for adequate

phase gain in the compensation network, the LC

corner frequency should be about one decade or so

below the closed-loop crossover frequency. This

limits the minimum capacitor value for the output filter

OUT

Ȥ

(9)

and the maximum ESR required is 22.2 mΩ. A

capacitor that meets these requirements is a Cornell

Dubilier Special Polymer (SP) ESRD101M06 rated at

6.3 V with a maximum ESR of 0.015 Ω and a ripple

current rating of 2 A. An additional small 0.1-µF

ceramic bypass capacitor C13 is a also used.

Other capacitor types work well with the TPS54010,

depending on the needs of the application.

Compensation Components

The external compensation used with the TPS54010

allows for a wide range of output filter configurations.

A large range of capacitor values and types of

dielectric are supported. The design example uses

Type-3 compensation consisting of R1, R3, R5, C6,

C7, and C8. Additionally, R2 along with R1 forms a

voltage divider network that sets the output voltage.

These component reference designators are the

same as those used in the SWIFT Designer

Software. There are a number of different ways to

design a compensation network. This procedure

outlines a relatively simple procedure that produces

good results with most output filter combinations. Use

the SWIFT Designer Software for designs with un-

usually high closed-loop crossover frequencies, low

value, low ESR output capacitors such as ceramics

or if you are unsure about the design procedure.

to:

2

1

K

ǒ Ǔ

2p ƒ

C

+

OUT(MIN)

L

CO

OUT

(7)

Where K is the frequency multiplier for the spread

between f_LCand f_CO. K should be between 5 and 15,

typically 10 for one decade difference. For a desired

crossover of 100-kHz and a 0.68-µH inductor, the

minimum value for the output capacitor is 93 µF using

a minimum K factor of 5. Increasing the K factor

would require using a larger capacitance as 100 kHz

is approaching the maximum practical closed-loop

crossover frequency for this device. The selected

output capacitor must be rated for a voltage greater

than the desired output voltage plus one half the

ripple voltage. Any de-rating amount must also be

included. The maximum RMS ripple current in the

output capacitors is given by Equation 8:

When designing compensation networks for the

TPS54010, a number of factors need to be con-

sidered. The gain of the compensated error amplifier

should not be limited by the open-loop amplifier gain

characteristics and should not produce excessive

gain at the switching frequency. Also, the closed-loop

crossover frequency should be set less than one-fifth

of the switching frequency, and the phase margin at

crossover must be greater than 45 degrees. The

general procedure outlined here produces results

consistent with these requirements without going into

great detail about the theory of loop compensation.

ȡ_VOUT

ȣ

Ǔ

ǒ_VPVIN(MAX)

* V

ȧ

Ȣ

^OUTȧ

1

12

I

+

COUT(RMS)

Ǹ

V

L

F

sw

PVIN(MAX)

OUT

Ȥ

First, calculate the output filter LC corner frequency

using Equation 10:

(8)

1

The calculated RMS ripple current is 780 mA in the

output capacitors.

ƒ

+

LC

2p ǸL

C

OUT OUT

For the design example, f_LC= 19.3 kHz.

(10)

The maximum ESR of the output capacitor is deter-

mined by the amount of allowable output ripple as

12

TPS54010

www.ti.com

SLVS509A–MAY 2004–REVISED AUGUST 2004

1

The closed-loop crossover frequency should be

chosen to be greater than f_LCand less than one-fifth

of the switching frequency. Also, the crossover fre-

quency should not exceed 150 kHz, as the error

amplifier may not provide the desired gain. For this

design, a crossover frequency of 100 kHz was

chosen. This value is chosen for comparatively wide

loop bandwidth while still allowing for adequate phase

boost to insure stability.

C8 +

2pR1 ƒ

LC

(20)

The first pole, f_P1is located to coincide with output

filter ESR zero frequency. This frequency is given by:

1

ƒ

+

ESR0

2pR

C

ESR OUT

(21)

where R_ESRis the equivalent series resistance of the

output capacitor.

Next, calculate the R2 resistor value for the output

voltage of 1.5 V using Equation 11:

In this case, the ESR zero frequency is 88.4 kHz, and

R5 can be calculated from:

R1 0.891

R2 +

V

* 0.891

1

OUT

(11)

R5 +

2pC8 ƒ

ESR

(22)

For any TPS54010 design, start with an R1 value of

10 kΩ. R2 is 14.7 kΩ.

The final pole is placed at a frequency above the

closed-loop crossover frequency high enough to not

cause the phase to decrease too much at the

crossover frequency while still providing enough at-

tenuation so that there is little or no gain at the

switching frequency. The f_P2pole location for this

circuit is set to 3.5 times the closed-loop crossover

frequency and the last compensation component

value C7 can be derived:

Now, the values for the compensation components

that set the poles and zeros of the compensation

network can be calculated. Assuming that R1 >> than

R5 and C6 >> C7, the pole and zero locations are

given by Equation 12 through Equation 18:

1

ƒ

+

Z1

Z2

P1

P2

2pR3C6

(12)

(13)

(14)

(15)

1

2pR1C8

C7 +

7pR3 ƒ

CO

(23)

1

2pR5C8

Note that capacitors are only available in a limited

range of standard values, so the nearest standard

value has been chosen for each capacitor. The

measured closed-loop response for this design is

shown in Figure 5.

1

2pR3C7

Additionally, there is a pole at the origin, which has

unity gain at a frequency:

1

ƒ

+

BIAS AND BOOTSTRAP CAPACITORS

INT

2pR1C6

(16)

Every TPS54010 design requires a bootstrap capaci-

tor, C3, and a bias capacitor, C4. The bootstrap

capacitor must be a 0.1 µF. The bootstrap capacitor

is located between the PH pins and BOOT. The bias

capacitor is connected between the VBIAS pin and

AGND. The value should be 1.0 µF. Both capacitors

should be high-quality ceramic types with X7R or

X5R grade dielectric for temperature stability. They

should be placed as close to the device connection

pins as possible.

This pole is used to set the overall gain of the

compensated error amplifier and determines the

closed-loop crossover frequency. Because R1 is

given as 1 kΩ and the crossover frequency is

selected as 100 kHz, the desired f_INTcan be calcu-

lated from Equation 17:

ƒ

CO

ƒ

+

INT

V

2

IN(MAX)

(17)

And the value for C6 is given by Equation 18:

POWER GOOD

1

C6 +

The TPS54010 is provided with a power-good output

pin PWRGD. This output is an open-drain output and

is intended to be pulled up to a 3.3-V or 5-V logic

supply. A 10-kΩ pullup works well in this application.

2pR1 ƒ

INT

(18)

The first zero, f_Z1is located at one-half the output

filter LC corner frequency; so, R3 can be calculated

from:

1

R3 +

pC6 ƒ

LC

(19)

The second zero, f_Z2is located at the output filter LC

corner frequency; so, C8 can be calculated from:

13

TPS54010

www.ti.com

SLVS509A–MAY 2004–REVISED AUGUST 2004

SNUBBER CIRCUIT

large degree on parasitic effects, it is best to choose

these component values based on actual measure-

ments of any design layout. See literature number

SLVP100 for more detailed information on snubber

design.

R10 and C11 of the application schematic comprise a

snubber circuit. The snubber is included to reduce

overshoot and ringing on the phase node when the

internal high-side FET turns on. Because the fre-

quency and amplitude of the ringing depends to a

kΩ

µ

71.5 kΩ

µF

kΩ

µ

µF

Ω

10 kΩ

14.7 kΩ

The following part numbers are used for test purposes:

C1 = T520D337M0O4ASE015 (Kemet)

C2 = TDK C3225X5R0J107M ceramic 6.3 V X5R

L1 = IHLP2525CZ−01 0.68 µH (Vishay Dale)

Figure 13. 1.5-V Power Supply With Ceramic Output Capacitors

Figure 13 shows an application where all ceramic

capacitors, including the main output filter capacitor,

are used. The compensation network components

were calculated using SWIFT Designer Software. See

Figure 22 through Figure 30 for loop response,

performance graphs, and switching waveforms for

this circuit.

14

TPS54010

www.ti.com

SLVS509A–MAY 2004–REVISED AUGUST 2004

µF

kΩ

µF

µ

µF

10 kΩ

µF

20 kΩ

10 kΩ

49.9 Ω

10 kΩ

2 kΩ

10 kΩ

µF

14.7 kΩ

Figure 14. 1.5-V Power Supply With Remote Sense

With an output current of 14 A, if the load is located

far from the dc/dc converter circuit, it may be ben-

eficial to include a remote sense capability. Figure 14

is an example of a power supply incorporating active

differential remote sensing. As the TPS54010 only

has a positive VSENSE input, this circuit compen-

sates for voltage drops in both the output voltage rail

and the return (GND). The difference amplifier of U2

forces the output of the TPS54010 to generate an

output voltage that maintains a constant 1.5-V differ-

ence

between

+1.5V_REMOTE_SENSE

and

-1.5V_REMOTE_SENSE.

15

TPS54010

www.ti.com

SLVS509A–MAY 2004–REVISED AUGUST 2004

3.6 V

100 nF

330 µF

10 µF

C17

1 µF

100 nF

0.047 µF

1 µF

10 kΩ

0.68 µH

0.047 µF

100 µF

0.1 µF

2.4 kΩ

422 Ω

10 kΩ

14.7 kΩ

Figure 15. 2.5 V to 1.5 V Power Supply with Charge Pump

If a suitable 3-V to 4-V source is not available for the VIN supply, a charge pump may be used to boost the PVIN

voltage. In this circuit, the charge pump is used to boost a 2.5-V source to a nominal 3.6 V.

16

TPS54010

www.ti.com

SLVS509A–MAY 2004–REVISED AUGUST 2004

PERFORMANCE GRAPHS

The performance data for Figure 16 through Figure 24 are for the circuit in Figure 12. Conditions are PVIN = 2.5

V, VIN = 3.3 V, V_O= 1.5 V, f_s= 700 kHz, and I_O= 7 A, T_A= 25°C, unless otherwise specified.

MEASURED LOOP RESPONSE

LOAD REGULATION

vs

OUTPUT CURRENT

LINE REGULATION

vs

INPUT VOLTAGE

vs

FREQUENCY

0.3

0.25

0.2

60

40

180

0.5

0.4

0.3

0.2

0.1

Phase

120

I

= 0A

O

3.3 V

0.15

0.1

20

0

60

2.5 V

Gain

0.05

0

= 7A

0

-0.05

-0.1

-0.15

-0.2

-0.25

-0.3

2.2 V

-0.1

I

= 14A

O

-20

-40

-60

-120

-180

-0.2

-0.3

-0.4

-0.5

4.0 V

100

1 k

10 k

100 k

1 M

0

2

4

6

8

10 12 14 16

2.5

3.5

2

3

4

I

- Output - A

f - Frequency - Hz

O

PVIN - V

Figure 16.

Figure 17.

Figure 18.

EFFICIENCY

vs

OUTPUT CURRENT

INPUT RIPPLE VOLTAGE

OUTPUT VOLTAGE RIPPLE

100

95

90

85

80

75

70

65

60

55

50

V

= 20 mV/div (ac coupled)

O(RIPPLE)

PVIN(RIPPLE) = 100 mV/div (ac coupled)

2.2 V

3.3 V

2.5 V

4.0 V

I

= 14 A

V(PH ) = 1 V/div

I

= 14 A

V(PH) = 1 V/div

O

0

2

4

6

8

10 12 14 16

Time = 500 nsec/div

I

- Output - A

O

Figure 19.

Figure 20.

Figure 21.

START-UP WAVEFORM

OUTPUT VOLTAGE RELATIVE

TO ENABLE

START-UP WAVEFORM

OUTPUT VOLTAGE RELATIVE

TO VIN

LOAD TRANSIENT RESPONSE

VIN = 1 V/div

V

= 1 V/div

(SS/ENA)

V

= 50 mV/div (ac coupled)

O

I

= 5 A/div

O

V

= 1 V/div

O

V

= 1 V/div

O

Time = 10 msec/div

Time = 200 msec/div

Time = 10 msec/div

Figure 22.

Figure 23.

Figure 24.

17

TPS54010

www.ti.com

SLVS509A–MAY 2004–REVISED AUGUST 2004

PERFORMANCE GRAPHS

The performance data for Figure 25 through Figure 34 are for the circuit in Figure 13. Conditions are PVIN = 2.5

V, VIN = 3.3 V, V_O= 1.5 V, f_s= 700 kHz, and I_O= 7 A, T_A= 25°C, unless otherwise specified.

FREE-AIR TEMPERATURE

vs

MAXIMUM OUTPUT CURRENT

MEASURED LOOP RESPONSE

LOAD REGULATION

vs

OUTPUT CURRENT

vs

FREQUENCY

60

40

180

125

115

105

95

0.5

0.4

0.3

0.2

0.1

V

= 1.5 V,

O

Phase

PVIN = V = 3.3 V,

I

120

T

J

= 125°C

3.3 V

20

0

60

85

2.5 V

Gain

75

0

65

2.2 V

-0.1

55

-20

-60

-0.2

-0.3

-0.4

-0.5

4.0 V

45

Safe Operating Area

-40

-60

-120

-180

35

25

15

100

1 k

10 k

100 k

1 M

0

2

4

6

8

10 12 14 16

- Output Current - A

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15

f - Frequency - Hz

I

O

I

− Output Current − A

O

Note: Figure 25 applies to the application circuit

(Figure 13) installed on a 3 inch x 3 inch x 0.062 inch

four-layer PCB.

Figure 25.

Figure 26.

Figure 27.

LINE REGULATION

EFFICIENCY

vs

OUTPUT CURRENT

vs

PVIN

INPUT RIPPLE VOLTAGE

0.3

100

95

90

85

80

75

70

65

60

55

50

PVIN(RIPPLE) = 100 mV/div (ac coupled)

2.2 V

0.25

0.2

0.15

0.1

3.3 V

I

= 0A

O

2.5 V

0.05

0

= 7A

4.0 V

-0.05

-0.1

-0.15

-0.2

-0.25

-0.3

I

= 14A

O

I

= 14 A

V

= 1 V/div

O

(PH)

2.5

3.5

0

2

4

6

8

10 12 14 16

2

3

4

Time = 500 nsec/div

PVIN - V

I

- Output Current - A

O

Figure 28.

Figure 29.

Figure 30.

18

TPS54010

www.ti.com

SLVS509A–MAY 2004–REVISED AUGUST 2004

PERFORMANCE GRAPHS (continued)

START-UP WAVEFORM

OUTPUT VOLTAGE RELATIVE

TO ENABLE

OUTPUT VOLTAGE RIPPLE

LOAD TRANSIENT RESPONSE

V

= 1 V/div

V

= 100 mV/div (ac coupled)

(SS/ENA)

O

V

= 10 mV/div (ac coupled)

O(RIPPLE)

I

= 5 A/div

O

V

= 1 V/div

O

I

= 14 A

V

= 1 V/div

O

(PH )

Time = 500 nsec/div

Time = 200 msec/div

Time = 10 msec/div

Figure 31.

Figure 32.

Figure 33.

START-UP WAVEFORM

OUTPUT VOLTAGE RELATIVE

TO ENABLE

VIN = 1 V/div

V

= 1 V/div

O

Time = 10 msec/div

Figure 34.

NOTE:

DETAILED DESCRIPTION

If the PVIN input is controlled via a fast bus switch, it

results in a hard-start condition and may damage the

load (i.e., whatever is connected to the regulated

output of the TPS54010). If a power-good signal is

not available from the 2.5-V power supply, one can

be generated using a comparator and hold the

SS/ENA pin low until the 2.5-V bus power is good. An

example of this is shown in Figure 35. This circuit can

also be used to prevent the TPS54010 output from

following the PVIN input while the PVIN power supply

is ramping up.

OPERATING WITH SEPARATE PVIN

The TPS54010 is designed to operate with the power

stage (high-side and low-side MOSFETs) and the

PVIN input connected to a separate power source

from VIN. The primary intended application has VIN

connected to a 3.3-V bus and PVIN connected to a

2.5-V bus. The TPS54010 cannot be damaged by

any sequencing of these voltages. However, the

UVLO (see detailed description section) is referenced

to the VIN input. Some conditions may cause unde-

sirable operation.

If PVIN is absent when the VIN input is high, the

slow-start is released, and the PWM circuit goes to

maximum duty factor. When the PVIN input ramps

up, the output of the TPS54010 follows the PVIN

input until enough voltage is present to regulate to the

proper output value.

19

TPS54010

www.ti.com

SLVS509A–MAY 2004–REVISED AUGUST 2004

the UVLO comparator, and a 2.5-ms rising and falling

edge deglitch circuit reduce the likelihood of shutting

the device down due to noise on VIN. UVLO is with

respect to VIN and not PVIN, see the Application

Information section.

100 kΩ

VIN

10 kΩ

PVIN

VBIAS

+

−

SS/ENA

1/2 LM293

10 kΩ

27.4 kΩ

SLOW-START/ENABLE (SS/ENA)

The slow-start/enable pin provides two functions.

First, the pin acts as an enable (shutdown) control by

keeping the device turned off until the voltage ex-

ceeds the start threshold voltage of approximately

1.2 V. When SS/ENA exceeds the enable threshold,

device start-up begins. The reference voltage fed to

the error amplifier is linearly ramped up from 0 V to

0.891 V in 3.35 ms. Similarly, the converter output

voltage reaches regulation in approximately 3.35 ms.

Voltage hysteresis and a 2.5-ms falling edge deglitch

circuit reduce the likelihood of triggering the enable

due to noise.

Figure 35. Undervoltage Lockout Circuit for PVIN

Using Open-Collector or Open-Drain Comparator

PVIN and VIN can be tied together for 3.3-V bus

operation.

MAXIMUM OUTPUT VOLTAGE

The maximum attainable output voltage is limited by

the minimum voltage at the PVIN pin. Nominal

maximum duty cycle is limited to 90% in the

TPS54010; so, maximum output voltage is:

V

PVIN

0.9

The second function of the SS/ENA pin provides an

external means of extending the slow-start time with

a low-value capacitor connected between SS/ENA

and AGND.

O(max)

(min)

(24)

Care must be taken while operating when nominal

conditions cause duty cycles near 90%. Load transi-

ents can require momentary increases in duty cycle.

If the required duty cycle exceeds 90%, the output

may fall out of regulation.

Adding a capacitor to the SS/ENA pin has two effects

on start-up. First, a delay occurs between release of

the SS/ENA pin and start-up of the output. The delay

is proportional to the slow-start capacitor value and

lasts until the SS/ENA pin reaches the enable

threshold. The start-up delay is approximately:

GROUNDING AND PowerPAD LAYOUT

The TPS54010 has two internal grounds (analog and

power). Inside the TPS54010, the analog ground ties

to all of the noise-sensitive signals, whereas the

power ground ties to the noisier power signals. The

PowerPAD must be tied directly to AGND. Noise

injected between the two grounds can degrade the

performance of the TPS54010, particularly at higher

output currents. However, ground noise on an analog

ground plane can also cause problems with some of

the control and bias signals. For these reasons,

separate analog and power ground planes are rec-

ommended. These two planes must tie together

directly at the IC to reduce noise between the two

grounds. The only components that must tie directly

to the power ground plane are the input capacitor, the

output capacitor, the input voltage decoupling capaci-

tor, and the PGND pins of the TPS54010.

1.2 V

t

+ C

d

(SS)

5 mA

(25)

Second, as the output becomes active, a brief

ramp-up at the internal slow-start rate may be ob-

served before the externally set slow-start rate takes

control and the output rises at a rate proportional to

the slow-start capacitor. The slow-start time set by

the capacitor is approximately:

0.7 V

t

+ C

(SS)

5 mA

(26)

The actual slow-start time is likely to be less than the

above approximation due to the brief ramp-up at the

internal rate.

VBIAS REGULATOR (VBIAS)

UNDERVOLTAGE LOCKOUT (UVLO)

The VBIAS regulator provides internal analog and

digital blocks with a stable supply voltage over

variations in junction temperature and input voltage. A

high-quality, low-ESR, ceramic bypass capacitor is

required on the VBIAS pin. X7R or X5R grade

dielectrics are recommended because their values

are more stable over temperature. The bypass ca-

pacitor must be placed close to the VBIAS pin and

returned to AGND.

The TPS54010 incorporates an undervoltage-lockout

circuit to keep the device disabled when the input

voltage (VIN) is insufficient. During power up, internal

circuits are held inactive until VIN exceeds the

nominal UVLO threshold voltage of 2.95 V. Once the

UVLO start threshold is reached, device start-up

begins. The device operates until VIN falls below the

nominal UVLO stop threshold of 2.8 V. Hysteresis in

20

TPS54010

www.ti.com

SLVS509A–MAY 2004–REVISED AUGUST 2004

External loading on VBIAS is allowed, with the

caution that internal circuits require a minimum

VBIAS of 2.7 V, and external loads on VBIAS with ac

or digital-switching noise may degrade performance.

The VBIAS pin may be useful as a reference voltage

for external circuits. VBIAS is derived from the VIN

pin; see the functional block diagram of this data

sheet.

During this period, the PWM ramp discharges rapidly

to its valley voltage. When the ramp begins to charge

back up, the low-side FET turns off and high-side

FET turns on. As the PWM ramp voltage exceeds the

error amplifier output voltage, the PWM comparator

resets the latch, thus turning off the high-side FET

and turning on the low-side FET. The low-side FET

remains on until the next oscillator pulse discharges

the PWM ramp. During transient conditions, the error

amplifier output could be below the PWM ramp valley

voltage or above the PWM peak voltage. If the error

amplifier is high, the PWM latch is never reset, and

the high-side FET remains on until the oscillator pulse

signals the control logic to turn the high-side FET off

and the low-side FET on. The device operates at its

maximum duty cycle until the output voltage rises to

the regulation set-point, setting VSENSE to approxi-

mately the same voltage as VREF. If the error

amplifier output is low, the PWM latch is continually

reset and the high-side FET does not turn on. The

low-side FET remains on until the VSENSE voltage

VOLTAGE REFERENCE

The voltage reference system produces a precise V_ref

signal by scaling the output of a temperature stable

bandgap circuit. During manufacture, the bandgap

and scaling circuits are trimmed to produce 0.891 V

at the output of the error amplifier, with the amplifier

connected as a voltage follower. The trim procedure

adds to the high-precision regulation of the

TPS54010, because it cancels offset errors in the

scale and error amplifier circuits.

OSCILLATOR AND PWM RAMP

decreases to

a

range that allows the PWM

comparator to change states. The TPS54010 is

capable of sinking current continuously until the

output reaches the regulation set-point.

The oscillator frequency is set to an internally fixed

value of 350 kHz. The oscillator frequency can be

externally adjusted from 280 to 700 kHz by con-

necting a resistor between the RT pin to ground. The

switching frequency is approximated by the following

equation, where R is the resistance from RT to

AGND:

If the current limit comparator trips for longer than

100 ns, the PWM latch resets before the PWM ramp

exceeds the error amplifier output. The high-side FET

turns off and low-side FET turns on to decrease the

energy in the output inductor and consequently the

output current. This process is repeated each cycle in

which the current limit comparator is tripped.

100 kW

Switching Frequency +

500 [kHz]

R

(27)

ERROR AMPLIFIER

DEAD-TIME CONTROL AND MOSFET

DRIVERS

The high-performance, wide bandwidth, voltage error

amplifier sets the TPS54010 apart from most dc/dc

converters. The user is given the flexibility to use a

wide range of output L and C filter components to suit

the particular application needs. Type-2 or Type-3

compensation can be employed using external com-

pensation components.

Adaptive dead-time control prevents shoot-through

current from flowing in both N-channel power

MOSFETs during the switching transitions by actively

controlling the turn-on times of the MOSFET drivers.

The high-side driver does not turn on until the voltage

at the gate of the low-side FET is below 2 V. While

the low-side driver does not turn on until the voltage

at the gate of the high-side MOSFET is below 2 V.

PWM CONTROL

Signals from the error amplifier output, oscillator, and

current limit circuit are processed by the PWM control

logic. Referring to the internal block diagram, the

control logic includes the PWM comparator, OR gate,

PWM latch, and portions of the adaptive dead-time

and control-logic block. During steady-state operation

below the current limit threshold, the PWM

comparator output and oscillator pulse train alter-

nately reset and set the PWM latch. Once the PWM

latch is set, the low-side FET remains on for a

minimum duration set by the oscillator pulse width.

The high-side and low-side drivers are designed with

300-mA source and sink capability to quickly drive the

power MOSFETs gates. The low-side driver is sup-

plied from VIN, whereas the high-side driver is

supplied from the BOOT pin. A bootstrap circuit uses

an external BOOT capacitor and an internal 2.5-Ω

bootstrap switch connected between the VIN and

BOOT pins. The integrated bootstrap switch improves

drive efficiency and reduces external component

count.

21

TPS54010

www.ti.com

SLVS509A–MAY 2004–REVISED AUGUST 2004

OVERCURRENT PROTECTION

Thermal shutdown provides protection when an over-

load condition is sustained for several milliseconds.

With a persistent fault condition, the device cycles

continuously; starting up by control of the slow-start

circuit, heating up due to the fault condition, and then

shutting down on reaching the thermal shutdown trip

point. This sequence repeats until the fault condition

is removed.

The cycle-by-cycle current limiting is achieved by

sensing the current flowing through the high-side

MOSFET and comparing this signal to a preset

overcurrent threshold. The high-side MOSFET is

turned off within 200 ns of reaching the current limit

threshold. A 100-ns leading-edge blanking circuit

prevents current limit false tripping. Current limit

detection occurs only when current flows from VIN to

PH when sourcing current to the output filter. Load

protection during current sink operation is provided by

thermal shutdown.

POWER-GOOD (PWRGD)

The power-good circuit monitors for undervoltage

conditions on VSENSE. If the voltage on VSENSE is

10% below the reference voltage, the open-drain

PWRGD output is pulled low. PWRGD is also pulled

low if VIN is less than the UVLO threshold or SS/ENA

is low. When VIN, UVLO threshold, SS/ENA, enable

THERMAL SHUTDOWN

The device uses the thermal shutdown to turn off the

power MOSFETs and disable the controller if the

junction temperature exceeds 150°C. The device is

released from shutdown automatically when the junc-

tion temperature decreases to 10°C below the ther-

mal shutdown trip point, and starts up under control

of the slow-start circuit.

threshold, and VSENSE

> 90% of Vref, the

open-drain output of the PWRGD pin is high. A

hysteresis voltage equal to 3% of V_refand a 35-µs

falling-edge deglitch circuit prevent tripping of the

power-good comparator due to high-frequency noise.

22

THERMAL PAD MECHANICAL DATA

www.ti.com

PWP (R-PDSO-G28)

THERMAL INFORMATION

This PowerPAD™ package incorporates an exposed thermal pad that is designed to be attached directly to an

external heatsink. When the thermal pad is soldered directly to the printed circuit board (PCB), the PCB can be

used as a heatsink. In addition, through the use of thermal vias, the thermal pad can be attached directly to a

ground plane or special heatsink structure designed into the PCB. This design optimizes the heat transfer from

the integrated circuit (IC).

For additional information on the PowerPAD package and how to take advantage of its heat dissipating abilities,

refer to Technical Brief, PowerPAD Thermally Enhanced Package, Texas Instruments Literature No. SLMA002

and Application Brief, PowerPAD Made Easy, Texas Instruments Literature No. SLMA004. Both documents are

available at www.ti.com.

The exposed thermal pad dimensions for this package are shown in the following illustration.

28

15

Exposed Thermal Pad

2,35

1,60

1

14

6,46

5,35

Top View

NOTE: All linear dimensions are in millimeters

PPTD032

Exposed Thermal Pad Dimensions

PowerPAD is a trademark of Texas Instruments

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,

enhancements, improvements, and other changes to its products and services at any time and to discontinue

any product or service without notice. Customers should obtain the latest relevant information before placing

orders and should verify that such information is current and complete. All products are sold subject to TI’s terms

and conditions of sale supplied at the time of order acknowledgment.

TI warrants performance of its hardware products to the specifications applicable at the time of sale in

accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI

deems necessary to support this warranty. Except where mandated by government requirements, testing of all

parameters of each product is not necessarily performed.

TI assumes no liability for applications assistance or customer product design. Customers are responsible for

their products and applications using TI components. To minimize the risks associated with customer products

and applications, customers should provide adequate design and operating safeguards.

TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,

copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process

in which TI products or services are used. Information published by TI regarding third-party products or services

does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.

Use of such information may require a license from a third party under the patents or other intellectual property

of the third party, or a license from TI under the patents or other intellectual property of TI.

Reproduction of information in TI data books or data sheets is permissible only if reproduction is without

alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction

of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for

such altered documentation.

Resale of TI products or services with statements different from or beyond the parameters stated by TI for that

product or service voids all express and any implied warranties for the associated TI product or service and

is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.

Following are URLs where you can obtain information on other Texas Instruments products and application

solutions:

Products

Applications

Audio

Amplifiers

amplifier.ti.com

www.ti.com/audio

Data Converters

dataconverter.ti.com

Automotive

www.ti.com/automotive

DSP

dsp.ti.com

Broadband

Digital Control

Military

www.ti.com/broadband

www.ti.com/digitalcontrol

www.ti.com/military

Interface

Logic

interface.ti.com

logic.ti.com

Power Mgmt

Microcontrollers

power.ti.com

Optical Networking

Security

www.ti.com/opticalnetwork

www.ti.com/security

www.ti.com/telephony

www.ti.com/video

microcontroller.ti.com

Telephony

Video & Imaging

Wireless

www.ti.com/wireless

Mailing Address:

Texas Instruments

Post Office Box 655303 Dallas, Texas 75265


型号：	TPS54010PWPRG4
厂家：	TEXAS INSTRUMENTS
描述：	输入电压为 3V 至 4V 的 14A 同步降压转换器 \| PWP \| 28 \| -40 to 85 开关光电二极管转换器
文件：	总25页 (文件大小：688K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TPS54010PWPRG4 [TI]

相关型号：

TPS5401DGQ

TPS5401DGQR

TPS5401DGQT

TPS5401EVM-708

TPS5402

TPS54020

TPS54020RUWR

TPS54020RUWT

TPS54020_13

TPS5402DR

TPS5403

TPS5403DR