TPS5405 [TI]

6.5-V TO 28-V INPUT VOLTAGE, 5-V FIXED OUTPUT, 2-A OUTPUT CURRENT, NON-SYNCHRONOUS STEP-DOWN REGULATOR WITH INTEGRATED MOSFET; 6.5 V至28 V的输入电压，5 -V固定输出， 2 -A的输出电流，集成MOSFET的非同步降压稳压器


型号：	TPS5405
厂家：	TEXAS INSTRUMENTS
描述：	6.5-V TO 28-V INPUT VOLTAGE, 5-V FIXED OUTPUT, 2-A OUTPUT CURRENT, NON-SYNCHRONOUS STEP-DOWN REGULATOR WITH INTEGRATED MOSFET 6.5 V至28 V的输入电压，5 -V固定输出， 2 -A的输出电流，集成MOSFET的非同步降压稳压器稳压器输出元件输入元件
文件：	总18页 (文件大小：719K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TPS5405

www.ti.com

SLVSBF7A –MAY 2012–REVISED JUNE 2012

6.5-V TO 28-V INPUT VOLTAGE, 5-V FIXED OUTPUT, 2-A OUTPUT CURRENT,

NON-SYNCHRONOUS STEP-DOWN REGULATOR WITH INTEGRATED MOSFET

Check for Samples: TPS5405

FEATURES

•

Fixed 5-V Output

APPLICATIONS

6.5-V to 28-V Wide Input Voltage Range

•

9-V, 12-V and 24-V Distributed Power Systems

Up to 2-A Maximum Continuous Output

Loading Current

Consumer Applications Such as Home

Appliances, Set-Top Boxes, CPE Equipment,

LCD Displays, Peripherals, and Battery

Chargers

•

Pulse Skipping Mode to Achieve High Light

Load Efficiency

•

Industrial and Car Entertainment Power

Supplies

•

Over 80% Efficiency at 10-mA Loading

Adjustable 50-kHz to 1.1-MHz Switching

Frequency Set by an External Resistor

(Leave pin ROSC floating. Set frequency to

120 kHz and ground connection to 70 kHz)

•

Peak Current-Mode Control

Cycle-by-Cycle Over Current Protection

Switching Node Anti-Ringing to Ease EMI

Issue

•

External Soft Start

Available in SOIC8 Package

DESCRIPTION

The TPS5405 is a monolithic non-synchronous buck regulator with wide operating input voltage range from 6.5 V

to 28 V. Current mode control with internal slope compensation is implemented to reduce component count.

TPS5405 also features a light load pulse skipping mode, which allows for a power loss reduction from the input

power supply to the system at light loading.

The switching frequency of the converters can be set from 50 kHz to 1.1 MHz with an external resistor.

Frequency spread spectrum operation is introduced for EMI reduction.

LX anti-ringing is added to address high frequency EMI issues.

A cycle-by-cycle current limit with frequency fold back protects the IC at over loading condition.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

TPS5405

SLVSBF7A –MAY 2012–REVISED JUNE 2012

www.ti.com

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

TYPICAL APPLICATION

Cboot

Vout

Cout

BOOT

VIN

Cin

Vin

GND

TPS5405

ROSC

COMP

Rosc

VSENSE

Css

FUNCTIONAL BLOCK DIAGRAM

VIN

165°C

Thermal

Shutdown

Logic

Shutdown

Boot

Charge

VSENSE

Boot

UVLO

Minimum Clamp

BOOT

9A/V

Current

Sense

2.1V

PWM

Comparator

PWM

Latch

Gate

Drive

Logic

2µA

0.8V

Voltage

Reference

Slope

Compensation

Shutdown

Discharge

Logic

Frequency

Shift

Oscillator

VSENSE

GND

COMP

Maximum

Clamp

ROSC

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SLVSBF7A –MAY 2012–REVISED JUNE 2012

PCB LAYOUT

VOUT

GROUND

1 BOOT

LX 8

2 VIN

GND 7

VIN

ROSC

COMP 6

VSENSE 5

ORDERING INFORMATION⁽¹⁾

T_A

PACKAGE⁽²⁾

ORDERABLE PART NUMBER

TOP-SIDE MARKING

–40°C to 85°C

8-pin SOIC (D)

TPS5405DR

TPS5405

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

web site at www.ti.com.

(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.

PIN OUT

D PACKAGE

(TOP VIEW)

BOOT

VIN

GND

ROSC

COMP

VSENSE

TERMINAL FUNCTIONS

NAME

BOOT

NO.

DESCRIPTION

A 0.1-µF bootstrap capacitor is required between BOOT and LX.

Input supply voltage, 6.5 V to 28 V

VIN

Switching frequency program pin. Connect a resistor to this pin to set the switching frequency. Connect the

pin to ground for a default 70-kHz switching frequency. Leave the pin open for 120-kHz switching

frequency.

ROSC

Soft start pin. An external capacitor connected to this pin sets the output rise time.

Output voltage feedback pin

VSENSE

Error amplifier output and input to the PWM comparator. Connect frequency compensation components to

this pin.

COMP

GND

Ground

Switching node to external inductor

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(1)

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted)

Voltage range at VIN, LX

Voltage range at LX (maximum withstand voltage transient < 20 ns)

Voltage from BOOT to LX

Voltage at VSENSE

–0.3 to 30

–5 to 30

–0.3 to 7

–0.3 to 3

–0.3 to 0.3

–40 to 125

–55 to 150

Voltage at SS

Voltage at ROSC

Voltage at COMP

Voltage at GND

T_J

Operating junction temperature range

Storage temperature range

°C

T_STG

(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating

conditions" is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.

RECOMMENDED OPERATING CONDITIONS

over operating free-air temperature range (unless otherwise noted)

MIN

6.5

NOM

MAX

UNIT

VIN

T_A

Input operating voltage

Ambient temperature

–40

°C

THERMAL INFORMATION

TPS5405

THERMAL METRIC⁽¹⁾

UNITS

8 PINS

116.7

62.4

θ_JA

Junction-to-ambient thermal resistance⁽²⁾

Junction-to-case (top) thermal resistance⁽³⁾

Junction-to-board thermal resistance⁽⁴⁾

θ_JCtop

θ_JB

57.0

°C/W

ψ_JT

Junction-to-top characterization parameter⁽⁵⁾

Junction-to-board characterization parameter⁽⁶⁾

Junction-to-case (bottom) thermal resistance⁽⁷⁾

14.5

ψ_JB

56.5

θ_JCbot

N/A

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as

specified in JESD51-7, in an environment described in JESD51-2a.

(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-

standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB

temperature, as described in JESD51-8.

(5) The junction-to-top characterization parameter, ψ_JT, estimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtaining θ_JA, using a procedure described in JESD51-2a (sections 6 and 7).

(6) The junction-to-board characterization parameter, ψ_JB, estimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtaining θ_JA, using a procedure described in JESD51-2a (sections 6 and 7).

(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific

JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

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SLVSBF7A –MAY 2012–REVISED JUNE 2012

ELECTRICAL CHARACTERISTICS

T_A= -40°C to 125°C, V_IN= 12 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

INPUT SUPPLY

V_IN

Input Voltage range

VIN1 and VIN2

6.5

Non switching quiescent power supply

current

VFB1 = VFB2 = 900 mV,

LOW_P = high

IDD_{Q_nsw}

100

µA

Rising V_IN

Hysteresis

3.5

UVLO

V_INunder voltage lockout

200

FEEDBACK AND ERROR AMPLIFIER

V_SENSE

Regulated output voltage

V_IN= 12 V

4.85

5.15

-2 µA < I_COMP< 2 µA,

V_COMP= 1 V

G_{m_EA}

Error amplifier trans-conductance

µs

I_gm

Error amplifier source/sink current

V_COMP= 1 V, 100 mV overdrive

V_IN= 12 V

±7

µA

G_{m_SRC}

COMP voltage to inductor current Gm

A/V

PFM MODE AND SOFT-START

Pulse skipping mode switch current

threshold

I_th

300

µA

I_SS

Charge current

OSCILLATOR

f_{SW_BK}

Switching frequency range

Programmable frequency

Set by external resistor ROSC

ROSC = GND

1100

kHz

120

300

f_SW

ROSC = OPEN

ROSC = 85.5 kΩ

Frequency spread spectrum in

percentage of f_SW

f_jitter

V_IN= 12 V

±6

Jittering swing frequency in percentage

of f_SW

f_swing

1/512

t_{min_on}

Minimum on time

V_IN= 12 V, T_A= 25°C

V_IN= 12 V

200

D_max

Maximum duty ratio

CURRENT LIMIT

I_LIMIT

Peak inductor current limit

V_IN= 12 V

2.5

120

165

MOSFET ON-RESISTANCE

R_{dson_HS}

On resistance of high side FET

V_IN= 12 V

240

mΩ

°C

THERMAL SHUTDOWN

T_TRIP

Thermal protection trip point

Rising temperature

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TYPICAL CHARACTERISTICS

T_A= 25°C, V_IN= 12 V, f_SW= 120 kHz (unless otherwise noted)

Figure 1. Efficiency

V_IN= 12 V, V_OUT= 5 V

Figure 2. Efficiency

V_IN= 12 V, V_OUT= 5 V

Figure 3. Load Regulation

V_IN= 12 V, V_OUT= 5 V

Figure 4. Line Regulation

V_OUT= 5 V

Figure 5. Startup

1-A Preset Loading

Figure 6. Steady State

I_O= 1 A

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TYPICAL CHARACTERISTICS (continued)

T_A= 25°C, V_IN= 12 V, f_SW= 120 kHz (unless otherwise noted)

Figure 7. Steady State

I_O= 20 mA

Figure 8. Load Transient

I_O= 0.1 A to 1 A

Figure 9. Short Circuit Protection

Figure 10. Short Circuit Recovery

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OVERVIEW

The TPS5405 is a 28-V, 2-A, step-down (buck) converter with an integrated high-side N-channel MOSFET. To

improve performance during line and load transients, the device implements a constant frequency, current mode

control which reduces output capacitance and simplifies external frequency compensation design.

The TPS5405’s switching frequency is adjustable with an external resistor or fixed by connecting the frequency

program pin to GND or leaving it unconnected.

The TPS5405 starts switching at V_INequal to 3.5 V. The operating current is 100 μA typically when not switching

and under no load. When the device is disabled, the supply current is 1 μA typically.

The integrated 120-mΩ high-side MOSFET allows for high efficiency power supply designs with continuous

output currents up to 2 A.

The TPS5405 reduces the external component count by integrating the boot recharge diode. The bias voltage for

the integrated high-side MOSFET is supplied by an external capacitor on the BOOT to PH pins. The boot

capacitor voltage is monitored by an UVLO circuit and will turn the high-side MOSFET off when the voltage falls

below a preset threshold of 2.1 V typically.

By adding an external capacitor, the slow start time of the TPS5405 can be adjustable which enables flexible

output filter selection. To improve the efficiency at light load conditions, the TPS5405 enters a special pulse

skipping mode when the peak inductor current drops below 300 mA typically. The frequency foldback reduces

the switching frequency during startup and over current conditions to help control the inductor current. The

thermal shut down gives the additional protection under fault conditions.

DETAILED DESCRIPTION

Adjustable Frequency PWM Control

The TPS5405 uses an external resistor to adjust the switching frequency. Connecting the ROSC pin to ground

fixes the switching frequency at 70 kHz, leaving it open gives 120-kHz switching frequency.

Figure 11. ROSC vs Switching Frequency

-1.167

R_OSC(kW) = 21.82× f_SW

(1)

For operation at 300 kHz, an 85.5-kΩ resistor is required.

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SLVSBF7A –MAY 2012–REVISED JUNE 2012

Pulse Skipping Mode

The TPS5405 is designed to operate in pulse skipping mode at light load currents to boost light load efficiency.

When the peak inductor current is lower than 300 mA typically, the COMP pin voltage falls to 0.5 V typically and

the device enters pulse skipping mode. When the device is in pulse skipping mode, the COMP pin voltage is

clamped at 0.5 V internally which prevents the high side integrated MOSFET from switching. The peak inductor

current must rise above 300 mA for the COMP pin voltage to rise above 0.5 V and exit pulse skipping mode.

Since the integrated current comparator catches the peak inductor current only, the average load current

entering pulse skipping mode varies with the applications and external output filters.

Voltage Reference (V_SENSE

)

The voltage reference system produces a ±2% initial accuracy voltage reference (±4% over temperature) by

scaling the output of a temperature stable bandgap circuit. The typical voltage reference is designed at 0.8 V.

Bootstrap Voltage (BOOT)

The TPS5405 has an integrated boot regulator and requires a 0.1-µF ceramic capacitor between the BOOT and

LX pins to provide the gate drive voltage for the high-side MOSFET. A ceramic capacitor with an X7R or X5R

grade dielectric is recommended because of the stable characteristics over temperature and voltage. To improve

drop out, the TPS5405 is designed to operate at 100% duty cycle as long as the BOOT to LX pin voltage is

greater than 2.1 V typically.

Programmable Slow Start Using SS Pin

It is recommended to program the slow start time externally because no slow start time is implemented internally.

The TPS5405 effectively uses the lower voltage of the internal voltage reference or the SS pin voltage as the

power supply’s reference voltage fed into the error amplifier and will regulate the output accordingly. A capacitor

(C_SS) on the SS pin to ground implements a slow start time. The TPS5405 has an internal pull-up current source

of 2 μA that charges the external slow start capacitor. The equation for the slow start time (10% to 90%) is

shown in Equation 2. The internal V_refis 0.8 V and the I_SScurrent is 2 μA.

C_ss(nF)´ V_ref(V)

t_ss(ms) =

I_ss(mA)

(2)

The slow start time should be set between 1 ms to 10 ms to ensure good start-up behavior. The slow start

capacitor should be no more than 27 nF.

If during normal operation, the input voltage drops below the VIN UVLO threshold, or a thermal shutdown event

occurs, the TPS5405 stops switching.

Error Amplifier

The TPS5405 has a transconductance amplifier for the error amplifier. The error amplifier compares the

VSENSE voltage to the internal effective voltage reference presented at the input of the error amplifier. The

transconductance of the error amplifier is 92 μA/V during normal operation. Frequency compensation

components are connected between the COMP pin and ground.

Slope Compensation

To prevent the sub-harmonic oscillations when operating the device at duty cycles greater than 50%, the

TPS5405 adds a built-in slope compensation which is a compensating ramp to the switch current signal.

Overcurrent Protection and Frequency Shift

The TPS5405 implements current mode control that uses the COMP pin voltage to turn off the high-side

MOSFET on a cycle by cycle basis. Every cycle the switch current and the COMP pin voltage are compared;

when the peak inductor current intersects the COMP pin voltage, the high-side switch is turned off. During

overcurrent conditions that pull the output voltage low, the error amplifier responds by driving the COMP pin high,

causing the switch current to increase. The COMP pin has a maximum clamp internally, which limits the output

current.

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The TPS5405 provides robust protection during short circuits. There is potential for overcurrent runaway in the

output inductor during a short circuit at the output. The TPS5405 solves this issue by increasing the off time

during short circuit conditions by lowering the switching frequency. The switching frequency is divided by 8, 4, 2,

and 1 as the voltage ramps from 0 V to 5V on the VSENSE pin. The relationship between the switching

frequency and the VSENSE pin voltage is shown in Table 1.

Table 1. Switching Frequency Conditions

SWITCHING FREQUENCY

VSENSE PIN VOLTAGE

_SENSE≥ 3.75 V

f_SW

f_SW/2

f_SW/4

f_SW/8

3.75 V > V_SENSE≥ 2.5 V

2.5 V > V_SENSE≥ 1.25 V

1.25 V > V_SENSE

Spread Spectrum

In order to reduce EMI, TPS5405 introduces frequency spread spectrum. The jittering span is ±6% of the

switching frequency with 1/512 swing frequency.

Switching Node Anti-Ringing

When the non-synchronous buck converter operates in DCM mode, the filter inductor and the parasitic

capacitance in the switching node (LX) form an LC resonant circuit; due to its high Q factor, lengthy high

frequency oscillation can be observed in the switching node. This ringing could cause radiated EMI issues in

some systems. TPS5405 adds an anti-ringing circuit to prevent the ringing from happening, when the inductor

current crosses zero and LX starts to climb up, an internal MOSFET between LX and VSENSE is turned on,

providing a damping path for the resonant circuit so as to eliminate the ringing.

Overvoltage Transient Protection

The TPS5405 incorporates an overvoltage transient protection (OVTP) circuit to minimize output voltage

overshoot when recovering from output fault conditions or strong unload transients. The OVTP circuit includes an

overvoltage comparator to compare the VSENSE pin voltage and internal thresholds. When the VSENSE pin

voltage goes above 109% × V_ref, the high-side MOSFET will be forced off. When the VSENSE pin voltage falls

below 107% × V_ref, the high-side MOSFET will be enabled again.

Inductor Selection

The higher operating frequency allows the use of smaller inductor and capacitor values. A higher frequency

generally results in lower efficiency because of switching loss and MOSFET gate charge losses. In addition to

this basic trade-off, the effect of the inductor value on ripple current and low current operation must also be

considered. The ripple current depends on the inductor value. The inductor ripple current (i_L) decreases with

higher inductance or higher frequency and increases with higher input voltage (V_IN). Accepting larger values of i_L

allows the use of low inductances, but results in higher output voltage ripple and greater core losses.

To calculate the value of the output inductor, use Equation 3. LIR is a coefficient that represents inductor peak-

to-peak ripple to DC load current. It is recommended to set LIR to 0.1 ~ 0.3 for most applications.

Actual core loss of the inductor is independent of core size for a fixed inductor value, but it is very dependent on

the inductance value selected. As inductance increases, core losses go down. Unfortunately, increased

inductance requires more turns of wire and therefore copper losses will increase. Ferrite designs have very low

core loss and are preferred for high switching frequencies, so design goals can concentrate on copper loss and

preventing saturation. Ferrite core material saturates hard, which means that inductance collapses abruptly when

the peak design current is exceeded. It results in an abrupt increase in inductor ripple current and consequent

output voltage ripple. Do not allow the core to saturate. It is important that the RMS current and saturation

current ratings are not exceeding the inductor specification. The RMS and peak inductor current can be

calculated from Equation 5 and Equation 6.

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V_IN- V_OUT

V_OUT

L =

I_O×LIR

_IN- V_OUT

_IN× fsw

(3)

(4)

V_OUT

Di_L=

I_O

V_IN× fsw

_OUT×(V

- V_OUT)

INmax

(

)

×L × fsw

i_LRMS

I_O²+

INmax

(5)

(6)

Di_L

I_Lpeak= I_O²×

For this design example, use LIR = 0.3 and the inductor is calculated to be 5.40 µH with V_IN= 12 V. Choose

4.7 µH value for the standard inductor and the peak to peak inductor ripple is about 34% of 1-A DC load current.

Output Capacitor Selection

There are two primary considerations for selecting the value of the output capacitor. The output capacitors are

selected to meet load transient and output ripple’s requirements.

Equation 7 gives the minimum output capacitance to meet the transient specification. For this example,

L = 4.7 µH, ΔI_OUT= 1 A – 0.0 A = 1 A and ΔV_OUT= 500 mV (10% of regulated 5 V). Using these numbers gives a

minimum capacitance of 1 µF. A standard 22-µF ceramic is chosen in the design.

DI_OUT²×L

Co >

2× V_OUT× DV_OUT

(7)

The selection of C_Ois driven by the effective series resistance (ESR). Equation 8 calculates the minimum output

capacitance needed to meet the output voltage ripple specification. Where f_SWis the switching frequency, ΔV_OUT

is the maximum allowable output voltage ripple, and Δi_Lis the inductor ripple current. In this case, the maximum

output voltage ripple is 50 mV (1% of regulated 5 V). From Equation 4, the output current ripple is 1 A. From

Equation 8, the minimum output capacitance meeting the output voltage ripple requirement is 2.5 µF with 3-mΩ

ESR resistance.

Co >

DV_OUT

8 × fsw

- ESR

Di_L

(8)

After considering both requirements, for this example, one 22-µF, 6.3-V X7R ceramic capacitor with 3-mΩ ESR

should be used.

Input Capacitor Selection

A minimum 10-µF X7R/X5R ceramic input capacitor is recommended to be added between VIN and GND. These

capacitors should be connected as close as physically possible to the input pins of the converters as they handle

the RMS ripple current shown in Equation 9. For this example, I_OUT= 1 A, V_OUT= 5 V, minimum V_INmin= 9.6 V,

from Equation 9, the input capacitors must support a ripple current of 1-A RMS.

- V_OUT

(

)

V_OUT

INmin

= I_OUT

INRMS

INmin

(9)

The input capacitance value determines the input ripple voltage of the regulator. The input voltage ripple can be

calculated using Equation 10. Using the design example values, I_OUTmax= 1 A, C_IN= 10 µF, f_SW= 300 kHz, yields

an input voltage ripple of 83 mV.

I_OUTmax×0.25

C_IN× f_SW

(10)

To prevent large voltage transients, a low ESR capacitor sized for the maximum RMS current must be used.

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Bootstrap Capacitor Selection

An external bootstrap capacitor connected to the BST pins supplies the gate drive voltages for the topside

MOSFETs. The capacitor between BST pin and LX pin is charged though internal diode from V7V when the LX

pin is low. When a high side MOSFET is to be turned on, the driver places the bootstrap voltage across the gate-

source of the desired MOSFET. This enhances the top MOSFET switch and turns it on. The switch node voltage,

LX, rises to VIN and the BST pin follows. With the internal high side MOSFET on, the bootstrap voltage is above

the input supply: V_BST= V_IN+ V7V. The selection on bootstrap capacitance is related with internal high side

power MOSFET gate capacitance. A 0.047-μF ceramic capacitor is recommended between the BST pin and LX

pin for proper operation. It is recommended to use a ceramic capacitor with X5R or better grade dielectric. The

capacitor should have 10-V or higher voltage rating.

Thermal Shutdown

The device implements an internal thermal shutdown to protect itself if the junction temperature exceeds 165°C.

The thermal shutdown forces the device to stop switching when the junction temperature exceeds the thermal

trip threshold. Once the die temperature decreases below 165°C, the device reinitiates the power up sequence.

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PACKAGE OPTION ADDENDUM

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2-Jul-2012

PACKAGING INFORMATION

Status ⁽¹⁾

Eco Plan ⁽²⁾

MSL Peak Temp ⁽³⁾

Samples

Orderable Device

Package Type Package

Drawing

Pins

Package Qty

Lead/

Ball Finish

(Requires Login)

TPS5405DR

ACTIVE

SOIC

3000

Green (RoHS

& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

⁽³⁾MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

2-Jul-2012

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TPS5405DR

SOIC

3000

330.0

12.4

6.4

5.2

2.1

8.0

12.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

2-Jul-2012

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SOIC

SPQ

Length (mm) Width (mm) Height (mm)

340.5 338.1 20.6

TPS5405DR

3000

Pack Materials-Page 2

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TPS5405 [TI]

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