TPS54061QDRBRQ1 [TI]
汽车类、4.7V 至 60V、200mA 同步降压直流/直流转换器 | DRB | 8 | -40 to 150;
| 型号： | TPS54061QDRBRQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 汽车类、4.7V 至 60V、200mA 同步降压直流/直流转换器 | DRB | 8 | -40 to 150 开关 光电二极管 转换器 |
| 文件： | 总36页 (文件大小：2043K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS54061-Q1
www.ti.com.cn
ZHCSAY7 –MARCH 2013
具有低 IQ的宽输入，60V，200mA 同步降压直流至直流 (DC-DC) 转换器
查询样品: TPS54061-Q1
1
特性
说明
•
•
符合汽车应用要求
TPS54061-Q1 器件是一款 60V，200mA，同步降压
dc-dc 转换器，此转换器具有高侧和低侧 MOSFET。
电流模式控制提供简单的外部补偿和灵活的组件选择。
非开关电源电流为 90µA。 使能引脚的使用将关断电流
减少至 1.4µA。
具有符合 AEC-Q100 的下列结果：
–
–
–
器件温度 1 级：-40°C 至 125°C 的环境运行温
度范围
器件人体模型 (HBM) 静电放电 (ESD) 分类等级
H2
为了增加轻负载效率，当电感器电流达到零值时，低侧
器件充电器件模型 (CDM) ESD 分类等级 C3B
MOSFET 仿真一个二极管。
•
集成型高侧和低侧金属氧化物半导体场效应晶体管
(MOSFET)
内部欠压闭锁设置值为 4.5V，但是在使能引脚上使用
2 个电阻器能够增加此设置值。 内部缓启动时间控制
输出电压启动斜升。
•
•
•
•
•
•
•
•
针对轻负载效率的二极管仿真
峰值电流模式控制
90µA 运行静态电流
可调开关频率范围可实现效率和外部组件尺寸的优化。
频率折返和热关断功能负责在过载情况下保护器件。
1.4µA 关断电源电流
50KHz 至 1.1MHz 可调节开关频率
同步至外部时钟
TPS54061-Q1 通过集成 MOSFET，引导再充电二极
管，以及将集成电路 (IC) 封装尺寸大大减小为小型
3mm x 3mm 散热增强型超薄小外形尺寸无引线
(VSON) 封装来实现小型设计。
0.8V±1% 电压基准
与陶瓷输出电容器或者低成本铝制电解电容器一起
工作时保持稳定
•
逐周期电流限制、过热、过压保护 (OVP) 和频率折
返保护
效率
100
•
•
带散热垫的 3mm x 3mm 封装
-40°C 至 150°C 运行结温
VIN = 12 V
90
80
70
60
50
40
30
应用范围
•
•
低功耗待机或偏置电压电源
高压线性稳压器的高效替代产品
简化的电路原理图
VOUT = 5 V, fSW = 50 kHz
20
VIN
VOUT = 5 V, fSW = 400 kHz
10
VOUT = 3.3 V, fSW = 400 kHz
0
VOUT
0.001
0.010
0.100
Load Current (A)
COMP
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2013, Texas Instruments Incorporated
English Data Sheet: SLVSBM7
TPS54061-Q1
ZHCSAY7 –MARCH 2013
www.ti.com.cn
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Table 1. ORDERING INFORMATION(1)
TJ
PACKAGE
PART NUMBER
–40°C to 150°C
VSON-8 DRB
TPS54061QDRBRQ1
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
PIN CONFIGURATION
VSON-8 PACKAGE
(BOTTOM VIEW)
8
7
1
2
PH
GND
BOOT
VIN
Thermal
Pad (9)
See appended
Mechanical
Data for
6
5
3
4
COMP
EN
VSENSE
size and shape
RT/CLK
PIN FUNCTIONS
PIN
NAME
DESCRIPTION
NUMBER
The device requires a bootstrap capacitorbetween BOOT and PH. If the voltage on this capacitor is below the
minimum required by the output device, the output switches off until refreshing of the capacitor is complete.
BOOT
COMP
EN
1
Error amplifier output and input to the output switch current comparator. Connect frequency compensation
components to this pin.
6
3
Enable pin with internal pullup current source. Pull below 1.18 V to disable. Float to enable. Adjust the input
undervoltage lockout with two resistors, see the Enable and Adjusting Undervoltage Lockout section.
GND
PH
7
8
Ground
The source of the internal high-side power MOSFET and drain of the internal low-side MOSFET
Resistor timing and external clock. An internal amplifier holds this pin at a fixed voltage when using an external
resistor to ground to set the switching frequency. Pulling the pin above the PLL upper threshold causes a mode
change, and the pin becomes a synchronization input. The change disables the internal amplifier, and the pin
becomes a high-impedance clock input to the internal PLL. Stoppage of the clocking edges re-enables the
internal amplifier, and the mode returns to a resistor frequency programming.
RT/CLK
4
VIN
2
5
9
Input supply voltage, 4.7 V to 60 V
VSENSE
Thermal pad
Inverting input of the transconductance (gm) error amplifier
Connect the GND pin electrically to the exposed pad on the printed circuit board for proper operation.
2
Copyright © 2013, Texas Instruments Incorporated
TPS54061-Q1
www.ti.com.cn
ZHCSAY7 –MARCH 2013
FUNCTIONAL BLOCK DIAGRAM
EN
VIN
Thermal
Shutdown
UVLO
Enable
Comparator
Shutdown
Shutdown
Logic
Enable
Threshold
Boot
Charge
Regulator
OV
VSENSE
Boot
UVLO
Current
Sense
Minimum
Clamp
ERROR
AMPLIFIER
PWM
Comparator
BOOT
Deadtime
Control Logic
Shutdown
Reference DAC
With
Slope
Compensation
Slow Start
PH
COMP
Frequency
Shift
DRV
REG
Maximum
Clamp
ZX
detect
Oscillator
with PLL
GND
THERMAL PAD
RT/CLK
Copyright © 2013, Texas Instruments Incorporated
3
TPS54061-Q1
ZHCSAY7 –MARCH 2013
www.ti.com.cn
ABSOLUTE MAXIMUM RATINGS(1)
over operating free-air temperature range (unless otherwise noted)
VALUE
MIN
UNIT
MAX
62
8
VIN
EN(2)
–0.3
–0.3
V
V
BOOT-PH
BOOT
8
V
70
6
V
Voltage
VSENSE
–0.3
V
COMP
–0.3
3
V
PH
–0.6
62
62
6
V
PH, 10-ns transient
–2
V
RT/CLK
VIN
–0.3
V
Internally limited
A
Current
BOOT
PH
100
mA
A
Internally limited
Human Body Model (HBM) QSS 009-105 (JESD22-
A114A) and AEC-Q100 Classification Level H2
2
kV
Electrostatic discharge
Charged Device Model (CDM) QSS 009-147 (JESD22-
C101B.01) and AEC-Q100 500V Classification Level
C3B
750
V
Operating junction temperature
Storage temperature
–40
–65
150
150
ºC
ºC
(1) The absolute maximum ratings specified in this section apply to all specifications of this document unless otherwise noted. These
specifications will be interpreted as the conditions which may damage the device with a single occurrence.
(2) See Enable and Adjusting Undervoltage Lockout section
THERMAL INFORMATION
TPS54061-Q1
THERMAL METRIC(1)
UNIT
VSON-8
42.9
46
θJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
θJCtop
θJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
18.1
0.5
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ψJB
18.3
3
θJCbot
(1) 有关传统和新的热 度量的更多信息，请参阅IC 封装热度量应用报告， SPRA953。
4
Copyright © 2013, Texas Instruments Incorporated
TPS54061-Q1
www.ti.com.cn
ZHCSAY7 –MARCH 2013
ELECTRICAL CHARACTERISTICS(1)
TEST CONDITIONS: TJ = –40°C to 150°C, VIN = 4.7 To 60 V ( (unless otherwise noted)
PARAMETER
SUPPLY VOLTAGE (VIN PIN)
Operating input voltage
CONDITIONS
MIN
TYP
MAX
60
UNIT
VIN
4.7
V
Shutdown supply current
EN = 0 V
1.4
90
µA
µA
Iq Operating – Non switching
ENABLE AND UVLO (EN PIN)
VSENSE = 0.9 V, VIN = 12 V
110
1.4
Rising
1.23
1.18
–4.7
–1.2
–3.5
450
V
Enable threshold
Input current
Falling
1
V
Enable threshold 50 mV
Enable threshold –50 mV
µA
µA
µA
µs
Hysteresis
Enable high to start switching time
VIN
VIN start voltage
VOLTAGE REFERENCE
VIN rising
4.5
V
V
TJ = 25°C, VIN = 12 V
0.792
0.784
0.8 0.808
0.8 0.816
Voltage reference
1 mA < IOUT < Minimum current limit
HIGH-SIDE MOSFET
Switch resistance
BOOT-PH = 5.7 V
VIN = 12 V
1.5
0.8
3.0
1.5
Ω
Ω
LOW-SIDE MOSFET
Switch resistance
ERROR AMPLIFIER
Input current
VSENSE pin
20
108
27
nA
µMhos
µMhos
V/V
Error-amplifier gm
–2 µA < I(COMP) < 2 µA, V(COMP) = 1 V
–2 µA < I(COMP) < 2 µA, V(COMP) = 1 V, VSENSE = 0.4 V
VSENSE = 0.8 V
EA gm during slow start
Error amplifier dc gain
Minimum unity-gain bandwidth
Error amplifier source and sink
Start-switching threshold
COMP to Iswitch gm
CURRENT LIMIT
1000
0.5
MHz
µA
V(COMP) = 1 V, 100 mV overdrive
±8
0.57
1.0
V
A/V
High-side sourcing current-limit
threshold
BOOT-PH = 5.7 V
250
350
500
mA
mA
Zero-cross detect current
THERMAL SHUTDOWN
Thermal shutdown
–1.1
176
C
RT/CLK
Operating frequency using RT mode
Switching frequency
50
1100
520
kHz
kHz
ns
V
R(RT/CLK) = 120 kΩ
R(RT/CLK) = 120 kΩ
425
472
40
Minimum CLK pulse duration
RT/CLK voltage
0.53
RT/CLK high threshold
RT/CLK low threshold
1.8
V
0.5
V
RT/CLK falling-edge to PH rising-
edge delay
Measure at 500 kHz with RT resistor
Measure at 500 kHz
67
ns
µs
PLL lock-in time
100
(1) The electrical ratings specified in this section apply to all specifications in this document unless otherwise noted. These specifications
will be interpreted as conditions that will not degrade the device’s parametric or functional specifications for the life of the product
containing it.
Copyright © 2013, Texas Instruments Incorporated
5
TPS54061-Q1
ZHCSAY7 –MARCH 2013
www.ti.com.cn
ELECTRICAL CHARACTERISTICS(1) (continued)
TEST CONDITIONS: TJ = –40°C to 150°C, VIN = 4.7 To 60 V ( (unless otherwise noted)
PARAMETER
PLL frequency range
CONDITIONS
MIN
TYP
MAX
1100
UNIT
300
kHz
PH
Minimum on-time
Dead time
Measured at 50% to 50%, IOUT = 200 mA
VIN = 12 V, IOUT = 200 mA, one transition
120
30
ns
ns
BOOT
BOOT-to-PH regulation voltage
BOOT-PH UVLO
INTERNAL SLOW START TIME
Slow-start time
VIN = 12 V
6
V
V
2.9
fSW = 472 kHz, RT = 120 kΩ, 10% to 90%
2.36
ms
6
Copyright © 2013, Texas Instruments Incorporated
TPS54061-Q1
www.ti.com.cn
ZHCSAY7 –MARCH 2013
TYPICAL CHARACTERISTICS
SPACER
3
1.4
VIN = 12 V
VIN = 12 V
1.2
1
2.5
2
0.8
0.6
0.4
1.5
1
0.5
0
0.2
0
-50
-25
0
25
50
75
100
125
150
-50
-25
0
25
50
75
100
125
150
T
- Junction Temperature - °C
J
T
- Junction Temperature - °C
J
Figure 1. High-Side rDS(on) versus Temperature
Figure 2. Low-Side rDS(on) versus Temperature
120
0.803
V
= 12 V,
= 120 kW
= 25°C
IN
R
T
T
0.801
0.799
0.797
100
80
60
40
20
0
J
Rising
0.795
0.793
Falling
0.791
0.789
0.787
0
100
200
300
400
500
- Feedback Voltage - mV
600
700
800
–50
–25
0
25
50
75
100
125
150
V
SENSE
T
– Junction Temperature – Deg
J
Figure 3. VREF Voltage versus Temperature
Figure 4. Frequency versus VSENSE Voltage
540
520
500
480
460
440
420
1100
1000
900
800
700
600
500
400
300
200
100
0
V
= 12 V,
VIN = 12 V
TJ = 25°C
IN
R
= 120 kW
T
25
100
Timing Resistance (kΩ)
1000
2500
G001
400
-50
-25
0
25
50
75
100
125
150
T
- Junction Temperature - °C
J
Figure 5. Frequency versus Temperature
Figure 6. Frequency versus RT/CLK Resistance
Copyright © 2013, Texas Instruments Incorporated
7
TPS54061-Q1
ZHCSAY7 –MARCH 2013
www.ti.com.cn
TYPICAL CHARACTERISTICS (continued)
1.26
140
120
100
80
V
= 12 V
V
Rising
IN
EN
V
= 12 V
IN
1.24
1.22
1.20
1.18
1.16
1.14
V
Falling
EN
60
40
20
0
1.12
1.10
-50
-25
0
25
50
75
100
125
150
-50
-25
0
25
50
75
100
125
150
T
- Junction Temperature - °C
T
- Junction Temperature - °C
J
J
Figure 7. Error Amplifier Transconductance versuis
Temperature
Figure 8. Enable-Pin Voltage versus Temperature
4.6
4.55
4.5
-3.35
V
= 12 V
IN
-3.40
-3.45
-3.50
-3.55
-3.60
-3.65
-3.70
-3.75
4.45
4.4
UVLO Start
UVLO Stop
4.35
4.3
4.25
4.2
4.15
4.1
4.05
4
-50
-25
0
25
50
75
100
125
150
-50
-25
0
25
T - Junction Temperature - °C
J
50
75
100
125
150
T
- Junction Temperature - °C
J
Figure 9. Enable-Pin Hysteresis Current
versus Temperature
Figure 10. Input Voltage (UVLO) versus Temperature
-1
-1.05
-1.1
3
V
= 12 V
IN
= 25°C
EN = 0 V
T
J
2.5
2
-1.15
-1.2
1.5
1
-1.25
-1.3
TJ = 150°C
TJ = −40°C
TJ = 25°C
-1.35
-1.4
0.5
0
-1.45
-1.5
0
5
10 15 20 25 30 35 40 45 50 55 60
VI - Input Voltage (V)
G002
0
5
10
15
20
25
30 35
40
45
50
55
60
V - Input Voltage - V
I
Figure 11. Enable-Pin Pullup Current versus Input Voltage
Figure 12. Shutdown Supply Current (VIN) versus Input
Voltage
8
Copyright © 2013, Texas Instruments Incorporated
TPS54061-Q1
www.ti.com.cn
ZHCSAY7 –MARCH 2013
TYPICAL CHARACTERISTICS (continued)
98
96
94
92
90
88
86
84
82
2
EN = Open
VSENSE = 0.83 V
EN = 0 V
1.75
TJ = 150°C
TJ = −40°C
TJ = 25°C
1.5
1.25
1
0.75
TJ = 150°C
TJ = −40°C
0.5
TJ = 25°C
0.25
0
80
0
5
10 15 20 25 30 35 40 45 50 55 60
Input Voltage (V)
0
1
2
3
4
5
Input Voltage (V)
G003
G004
Figure 13. Supply Current (VIN Pin) versus Input Voltage
Figure 14. Supply Current (VIN Pin)
versus Input Voltage (0 V to VSTART), EN Pin Low
2.48
2.46
2.44
2.42
2.40
2.38
2.36
160
EN = Open
V
f
= 12 V,
IN
T
= 150°C
= 472 kHz
J
140
120
100
80
sw
T
= -40°C
J
T
= 25°C
J
60
40
20
0
2.34
2.32
-50
-25
0
25
50
75
100
125
150
0
1
2
3
V - Input Voltage - V
4
5
T
- Junction Temperature - °C
I
J
Figure 15. Supply Current (VIN pin) versus
Input Voltage (0 V to VSTART), EN Pin Open
Figure 16. Slow-Start Time versus Temperature
0.45
T
= -40°C
J
T
= 25°C
J
0.4
0.35
T
= 150°C
0.3
0.25
0.2
J
0
5
10
15
20
25
30
35
40
45
50
55 60
V - Input Voltage - V
I
Figure 17. Current Limit versus Input Voltage
Copyright © 2013, Texas Instruments Incorporated
9
TPS54061-Q1
ZHCSAY7 –MARCH 2013
www.ti.com.cn
OVERVIEW
The TPS54061-Q1 device is a 60 V, 200 mA, step-down (buck) regulator with integrated high-side and low-side
n-channel MOSFETs. To improve performance during line and load transients, the device implements a
constant-frequency, current-mode control which reduces output capacitance and simplifies external frequency-
compensation design.
The switching frequency of 50 kHz to 1100 kHz allows for efficiency and size optimization when selecting the
output filter components. Adjustment of the switching frequency is by use of a resistor to ground on the RT/CLK
pin. The device has an internal phase-lock loop (PLL) on the RT/CLK pin that synchronizes the power-switch
turnon to a falling edge of an external system clock.
The TPS54061-Q1 has a default start-up voltage of approximately 4.5 V. The EN pin has an internal pullup
current source, a possible use of which is to adjust the input voltage undervoltage lockout (UVLO) threshold with
two external resistors. In addition, the pullup current provides a default condition. When the EN pin is floating, the
device operates. The operating current is 90 µA when not switching and under no load. When the device is
disabled, the supply current is 1.4 µA.
The integrated 1.5-Ω high-side MOSFET and 0.8-Ω low-side MOSFET allow for high-efficiency power-supply
designs capable of delivering 200 milliamperes of continuous current to a load.
The TPS54061-Q1 reduces the external component count by integrating the boot recharge diode. A capacitor
between the BOOT and PH pins supplies the bias voltage for the integrated high-side MOSFET. The boot
capacitor voltage is monitored by an UVLO circuit and will turn the high side MOSFET off when the boot voltage
falls below a preset threshold. The TPS54061-Q1 can operate at high duty cycles because of the boot UVLO.
The output voltage can be adjusted down to as low as the 0.8 V reference.
The TPS54061-Q1 has an internal output OV protection that disables the high side MOSFET if the output voltage
is 109% of the nominal output voltage.
The TPS54061-Q1 reduces external component count by integrating the slow start time using a reference DAC
system.
The TPS54061-Q1 resets the slow start times during overload conditions with an overload recovery circuit. The
overload recovery circuit will slow start the output from the fault voltage to the nominal regulation voltage once a
fault condition is removed. A frequency foldback circuit reduces the switching frequency during startup and
overcurrent fault conditions to help control the inductor current.
10
Copyright © 2013, Texas Instruments Incorporated
TPS54061-Q1
www.ti.com.cn
ZHCSAY7 –MARCH 2013
DETAILED DESCRIPTION
Fixed Frequency PWM Control
The TPS54061-Q1 uses adjustable fixed frequency, peak current mode control. The output voltage is sensed
through external resistors on the VSENSE pin and compared to an internal voltage reference by an error
amplifier which drives the COMP pin. An internal oscillator initiates the turn on of the high side power switch. The
error amplifier output is compared to the high side power switch current. When the power switch current reaches
the level set by the COMP voltage, the power switch is turned off. The COMP pin voltage will increase and
decrease as the output current increases and decreases. The device implements current limiting by clamping the
COMP pin voltage to a maximum level.
Slope Compensation Output Current
The TPS54061-Q1 adds a compensating ramp to the switch current signal. This slope compensation prevents
sub-harmonic oscillations.
Error Amplifier
The TPS54061-Q1 uses a transconductance amplifier for the error amplifier. The error amplifier compares the
VSENSE voltage to the lower of the internal slow start voltage or the internal 0.8 V voltage reference. The
transconductance (gm) of the error amplifier is 108 µA/V during normal operation. During the slow start
operation, the transconductance is a fraction of the normal operating gm. The frequency compensation
components (capacitor, series resistor and capacitor) are added to the COMP pin to ground.
Voltage Reference
The voltage reference system produces a precise voltage reference over temperature by scaling the output of a
temperature stable band-gap circuit
Adjusting the Output Voltage
The output voltage is set with a resistor divider from the output node to the VSENSE pin. It is recommended to
use 1% tolerance or better divider resistors. Start with a 10kΩ for the RLS resistor and use the Equation 1 to
calculate RHS
.
V
- 0.8 V
æ
ö
OUT
R
= R ´
LS
ç
÷
HS
ç
÷
0.8 V
è
ø
(1)
Enable and Adjusting Undervoltage Lockout
The TPS54061-Q1 is enabled when the VIN pin voltage rises above 4.5 V and the EN pin voltage exceeds the
EN rising threshold of 1.23V. The EN pin has an internal pull-up current source, I1, of 1.2 µA that provides the
default enabled condition when the EN pin floats.
If an application requires a higher input undervoltage lockout (UVLO) threshold, use the circuit shown in
Figure 18 to adjust the input voltage UVLO with two external resistors. When the EN pin voltage exceeds 1.23 V,
an additional 3.5 µA of hysteresis current, Ihys, is sourced out of the EN pin. When the EN pin is pulled below
1.18 V, the 3.5 µA Ihys current is removed. This additional current facilitates adjustable input voltage hysteresis.
Use Equation 2 to calculate RUVLO1 for the desired input start and stop voltages . Use Equation 3 to similarly
calculate RUVLO2
.
In applications designed to start at relatively low input voltages (e.g., from 4.7 V to 10 V) and withstand high input
voltages (e.g., from 40 V to 60 V), the EN pin may experience a voltage greater than the absolute maximum
voltage of 8 V during the high input voltage condition. It is recommended to use a zener diode to clamp the pin
voltage below the absolute maximum rating.
Copyright © 2013, Texas Instruments Incorporated
11
TPS54061-Q1
ZHCSAY7 –MARCH 2013
www.ti.com.cn
VIN
TPS54061
i1 ihys
Ruvlo1
EN
Optional
VEN
Ruvlo2
Figure 18. Adjustable Undervoltage Lock Out
æ
ö
÷
ø
VENAFALLING
V
- V
START ç
STOP
VENARISING
è
RUVLO1 =
æ
ö
VENAFALLING
I1 × 1-
+ I
HYS
ç
÷
VENARISING
è
ø
(2)
(3)
RUVLO1 ´ VENAFALLING
VSTOP - VENAFALLING + RUVLO1 ´ I + I
RUVLO 2 =
(
)
1
HYS
Internal Slow Start
The TPS54061-Q1 has an internal digital slow start that ramps the reference voltage from zero volts to its final
value in 1114 switching cycles. The internal slow start time is calculated by the following expression:
1114
tss(ms) =
fSW (kHz)
(4)
If the EN pin is pulled below the stop threshold of 1.18 V, switching stops and the internal slow start resets. The
slow start also resets in thermal shutdown.
Constant Switching Frequency and Timing Resistor (RT/CLK Pin)
The switching frequency of the TPS54061-Q1 is adjustable over a wide range from 50 kHz to 1100 kHz by
varying the resistor on the RT/CLK pin. The RT/CLK pin voltage is typically 0.53 V and must have a resistor to
ground to set the switching frequency. To determine the timing resistance for a given switching frequency, use
Equation 5. To reduce the solution size, one would typically set the switching frequency as high as possible, but
tradeoffs of the supply efficiency, maximum input voltage and minimum controllable on time should be
considered. The minimum controllable on time is typically 120ns and limits the operating frequency for high input
voltages. The maximum switching frequency is also limited by the frequency shift circuit. More discussion on the
details of the maximum switching frequency is located below.
71657
fSW (kHz)1.039
RT (kW) =
(5)
Selecting the Switching Frequency
The TPS54061-Q1 implements current mode control which uses the COMP pin voltage to turn off the high side
MOSFET on a cycle-by-cycle basis. Each cycle the switch current and COMP pin voltage are compared, when
the peak switch current intersects the COMP voltage, the high side switch is turned off. During overcurrent
conditions that pull the output voltage low, the error amplifier will respond by driving the COMP pin high,
increasing the switch current. The error amplifier output is clamped internally, which functions as a switch current
limit.
12
Copyright © 2013, Texas Instruments Incorporated
TPS54061-Q1
www.ti.com.cn
ZHCSAY7 –MARCH 2013
To enable higher switching frequency at high input voltages, the TPS54061-Q1 implements a frequency shift.
The switching frequency is divided by 8, 4, 2, and 1 as the voltage ramps from 0 to 0.8 volts on VSENSE pin.
The device implements a digital frequency shift to enable synchronizing to an external clock during normal
startup and fault conditions. Since the device can only divide the switching frequency by 8, there is a maximum
input voltage limit in which the device operates and still have frequency shift protection. During short-circuit
events (particularly with high input voltage applications), the control loop has a finite minimum controllable on
time and the output has a low voltage. During the switch on time, the inductor current ramps to the peak current
limit because of the high input voltage and minimum on time. During the switch off time, the inductor would
normally not have enough off time and output voltage for the inductor to ramp down by the ramp up amount. The
frequency shift effectively increases the off time allowing the current to ramp down.
æ
ç
è
ö
÷
ø
æ
ç
è
ö
÷
ø
V OUT + RLS ´ IO + RDC ´ IO
VIN - IO ´ RHS + IO ´ RLS
1
fSW (maxskip) =
´
tON
(6)
(7)
æ
ç
ö
æ
ç
è
ö
÷
ø
V OUTSC + RLS × ICL + RDC ´ ICL
VIN - ICL ´ RHS + ICL ´ RLS
f div
f
SW (shift) =
×
÷
tON
è
ø
Where:
IO = Output current
ICL = Current Limit
VIN = Input Voltage
VOUT = Output Voltage
VOUTSC Output Voltage during short
RDC = Inductor resistance
RHS = High side MOSFET resistance
RLS = Low side MOSFET resistance
ton = Controllable on time
fdiv = Frequency divide (equals 1, 2, 4, or 8)
Synchronization to RT/CLK Pin
The RT/CLK pin can be used to synchronize the regulator to an external system clock. To implement the
synchronization feature connect a square wave to the RT/CLK pin through one of the circuit networks shown in
Figure 19. The square wave amplitude must extend lower than 0.5 V and higher than 1.8V on the RT/CLK pin
and have high and low states greater than 40ns. The synchronization frequency range is 300 kHz to 1100 kHz.
The rising edge of the PH will be synchronized to the falling edge of RT/CLK pin signal. The external
synchronization circuit should be designed in such a way that the device will have the default frequency set
resistor connected from the RT/CLK pin to ground should the synchronization signal turn off. It is recommended
to use a frequency set resistor connected as shown in Figure 19 through another resistor (e.g., 50Ω) to ground
for clock signal that are not Hi-Z or tristate during the off state. The sum of the resistance should set the
switching frequency close to the external CLK frequency. It is recommended to ac couple the synchronization
signal through a 10pF ceramic capacitor to RT/CLK pin. The first time the CLK is pulled above the CLK threshold
the device switches from the RT resistor frequency to PLL mode. The internal 0.5 V voltage source is removed
and the CLK pin becomes high impedance as the PLL starts to lock onto the external signal. The switching
frequency can be higher or lower than the frequency set with the RT/CLK resistor. The device transitions from
the resistor mode to the PLL mode and lock onto the CLK frequency within 100 microseconds. When the device
transitions from the PLL mode to the resistor mode, the switching frequency will reduce from the external CLK
frequency to 150 kHz, then reapply the 0.5V voltage source and the resistor will then set the switching frequency.
The switching frequency is divided by 8, 4, 2, and 1 as the voltage ramps from 0 to 0.8 volts on VSENSE pin.
The device implements a digital frequency shift to enable synchronizing to an external clock during normal
startup and fault conditions.
Copyright © 2013, Texas Instruments Incorporated
13
TPS54061-Q1
ZHCSAY7 –MARCH 2013
www.ti.com.cn
TPS54061
PLL
TPS54061
PLL
RT/CLK
RT
RT/CLK
RT
Hi-Z
Clock
Source
Clock
Source
Figure 19. Synchronizing to a System Clock
Overvoltage Protection
The TPS54061-Q1 incorporates an output over-voltage transient protection (OVP) circuit to minimize voltage
overshoot when recovering from output fault conditions or strong unload transients on power supply designs with
low value output capacitance. For example, when the power supply output is overloaded the error amplifier
compares the actual output voltage to the internal reference voltage. If the VSENSE pin voltage is lower than the
internal reference voltage for a considerable time, the output of the error amplifier will respond by clamping the
error amplifier output to a high voltage. Thus, requesting the maximum output current. Once the condition is
removed, the regulator output rises and the error amplifier output transitions to the steady state duty cycle. In
some applications, the power supply output voltage can respond faster than the error amplifier output can
respond, this actuality leads to the possibility of an output overshoot.
The OVP feature minimizes the output overshoot when using a low value output capacitor by comparing the
VSENSE pin voltage to OVP threshold which is 109% of the internal voltage reference. If the VSENSE pin
voltage is greater than the OVP threshold, the high side MOSFET is disabled to minimize output overshoot.
When the VSENSE voltage drops lower than the OVP threshold, the high side MOSFET resumes normal
operation.
Thermal Shutdown
The device implements an internal thermal shutdown until the junction temperature exceeds 176°C. The thermal
shutdown forces the device to stop switching until the junction temperature falls below the thermal trip threshold.
Once the die temperature decreases below 176°C, the device reinitiates the power up sequence by restarting the
internal slow start.
14
Copyright © 2013, Texas Instruments Incorporated
TPS54061-Q1
www.ti.com.cn
ZHCSAY7 –MARCH 2013
DESIGN GUIDE – STEP-BY-STEP DESIGN PROCEDURE No.1
CBOOT
0.01 μF
LO
U1
TPS54061
100 μH
3.3 V 200 mA
2
1
1
2
8
7
8 V to 60 V
RCOMP
3
4
RHS
6
5
RUVLO1
196 kΩ
CO
31.6 kΩ
26.1 kΩ
CIN
CCOMP
CPOLE
33 pF
10 μF
RT
RUVLO2
2.2 μF
*
4700 pF
RLS
143 kΩ
36.5 kΩ
10 kΩ
* See Enable and Adjusting Undervoltage Lockout section
Figure 20. CCM Application Schematic
This example details the design of a continuous conduction mode (CCM) switching regulator design using
ceramic output capacitors. If a low output current design is see design procedure Number 2. A few parameters
must be known in order to start the design process. These parameters are typically determined at the system
level. For this example, we will start with the following known parameters:
Output Voltage
5.0V
Transient Response 50 to 150mA load step
Maximum Output Current
Input Voltage
ΔVOUT = 4%
200mA
24 V nom. 8V to 60V
0.5% of VOUT
7.50V
Output Voltage Ripple
Start Input Voltage (rising VIN)
Stop Input Voltage (falling VIN)
6.50V
Selecting the Switching Frequency
The first step is to decide on a switching frequency for the regulator. Typically, the user will want to choose the
highest switching frequency possible since this will produce the smallest solution size. The high switching
frequency allows for lower valued inductors and smaller output capacitors compared to a power supply that
switches at a lower frequency. The switching frequency is limited by the minimum on-time of the internal power
switch, the maximum input voltage, the output voltage and the frequency shift limitation.
Equation 6 and Equation 7 must be used to find the maximum switching frequency for the regulator, choose the
lower value of the two results. Switching frequencies higher than these values will result in pulse skipping or a
lack of overcurrent protection during short circuit conditions. The typical minimum on time, tonmin, is 120ns for the
TPS54061-Q1. To ensure overcurrent runaway does not occur during short circuits in your design, use
Equation 7 to determine the maximum switching frequency. With a maximum input voltage of 60V, inductor
resistance of 0.77 Ω, high side switch resistance of 3.0 Ω, low side switch resistance of 1.5Ω, a current limit
value of 350 mA and a short circuit output voltage of 0.1 V, the maximum switching frequency is 524 kHz and
1003 kHz in each case respectively. A switching frequency of 400 kHz is used. To determine the timing
resistance for a given switching frequency, use Equation 5. The switching frequency is set by resistor RT shown
in Figure 20. RT is calculated to be 142 kΩ. A standard value of 143 kΩ is used.
Copyright © 2013, Texas Instruments Incorporated
15
TPS54061-Q1
ZHCSAY7 –MARCH 2013
www.ti.com.cn
Output Inductor Selection (LO)
To calculate the minimum value of the output inductor, use Equation 8. KIND is a coefficient that represents the
amount of inductor ripple current relative to the maximum output current. The inductor ripple current will be
filtered by the output capacitor. Therefore, choosing high inductor ripple currents will impact the selection of the
output capacitor since the output capacitor must have a ripple current rating equal to or greater than the inductor
ripple current. In general, the inductor ripple value is at the discretion of the designer; however, the following
guidelines may be used. Typically it is recommended to use KIND values in the range of 0.2 to 0.4; however, for
designs using low ESR output capacitors such as ceramics and low output currents, a KIND value as high as 1
may be used. In a wide input voltage regulator, it is best to choose an inductor ripple current on the larger side.
This allows the inductor to still have a measurable ripple current with the input voltage at its minimum. For this
design example, use KIND of 0.4 and the minimum inductor value is calculated to be 97 µH. For this design, a
standard 100µH value was chosen. It is important that the RMS current and saturation current ratings of the
inductor not be exceeded. The RMS and peak inductor current can be found from Equation 10 and Equation 11.
For this design, the RMS inductor current is 200 mA and the peak inductor current is 239 mA. The chosen
inductor is a Würth 74408943101. It has a saturation current rating of 680 mA and an RMS current rating of 520
mA. As the equation set demonstrates, lower ripple currents will reduce the output voltage ripple of the regulator
but will require a larger value of inductance. Selecting higher ripple currents will increase the output voltage ripple
of the regulator but allow for a lower inductance value. The current flowing through the inductor is the inductor
ripple current plus the average output current. During power up, faults or transient load conditions, the inductor
current can increase above the peak inductor current level calculated above. In transient conditions, the inductor
current can increase up to the switch current limit of the device. For this reason, the most conservative approach
is to specify an inductor with a saturation current rating equal to or greater than the switch current limit rather
than the calculated peak inductor current.
V max - VOUT
VOUT
IN
L
min ³
´
O
Kind ´ I
V max ´ ¦sw
IN
O
(8)
(9)
VOUT
´
V max - V
IN OUT
(
V max ´ LO ´ fSW
)
IRIPPLE
³
IN
æ
ö2
VOUT
´
V max - V
(
)
1
IN
OUT
2
ILrms = IO
+
´
ç
ç
÷
÷
12
V max ´ LO ´ fSW
IN
è
ø
(10)
(11)
IRIPPLE
ILpeak = IOUT
+
2
Output Capacitor
There are three primary considerations for selecting the value of the output capacitor. The output capacitor will
determine the modulator pole, the output voltage ripple, and how the regulator responds to a large change in
load current. The output capacitance needs to be selected based on the most stringent of these three criteria.
The desired response to a large change in the load current is the first criteria. The output capacitor needs to
supply the load with current until the regulator increases the inductor current. This situation would occur if there
are desired hold-up times for the regulator where the output capacitor must hold the output voltage above a
certain level for a specified amount of time after the input power is removed. The regulator also will temporarily
not be able to supply sufficient output current if there is a large, fast increase in the current needs of the load
such as transitioning from no load to a full load. The regulator usually needs two or more clock cycles for the
control loop to see the change in load current and output voltage and adjust the duty cycle to react to the
change. The output capacitor must be sized to supply the extra current to the load until the control loop responds
to the load change. The output capacitance must be large enough to supply the difference in current for 2 clock
cycles while only allowing a tolerable amount of droop in the output voltage. Equation 15 shows the minimum
output capacitance necessary to accomplish this, where ΔIout is the change in output current, ƒsw is the
regulators switching frequency and ΔVout is the allowable change in the output voltage.
For this example, the transient load response is specified as a 4% change in Vout for a load step from 50 mA to
150 mA. For this example, ΔIOUT = 0.150 –0.05 = 0.10 and ΔVOUT = 0.04 × 3.3 = 0.132.
16
Copyright © 2013, Texas Instruments Incorporated
TPS54061-Q1
www.ti.com.cn
ZHCSAY7 –MARCH 2013
Using these values gives a minimum capacitance of 3.79 µF. This does not take the ESR of the output capacitor
into account in the output voltage change. For ceramic capacitors, the ESR is usually small enough to ignore in
this calculation. Aluminum electrolytic and tantalum capacitors have higher ESR that should be taken into
account.
The low side FET of the regulator emulates a diode so it can not sink current so any stored energy in the
inductor will produce an output voltage overshoot when the load current rapidly decreases, as in Figure 28. The
output capacitor must also be sized to absorb energy stored in the inductor when transitioning from a high load
current to a lower load current. The excess energy that gets stored in the output capacitor will increase the
voltage on the capacitor. The capacitor must be sized to maintain the desired output voltage during these
transient periods. Equation 14 is used to calculate the minimum capacitance input the output voltage overshoot
to a desired value, where
is the value of the inductor, IOH is the output current under heavy load, IOL is the
LO
output under light load, VO+ΔVO is the final peak output voltage, and Vi is the initial capacitor voltage. For this
example, the worst case load step will be from 150 mA to 50 mA. The output voltage will increase during this
load transition and must be limited to 4% of the output voltage to satisy the design goal. This will make VO+ΔVO
= 1.04 × 3.3 = 3.432 V. VO is the initial capacitor voltage which is the nominal output voltage of 3.3 V. Using
these numbers in Equation 14 yields a minimum capacitance of 2.25 µF.
Equation 13 calculates the minimum output capacitance needed to meet the output voltage ripple specification,
where fSW is the switching frequency, Vripple is the maximum allowable output voltage ripple, and Iripple is the
inductor ripple current. Equation 13 yields 1.48 µF. Equation 16 calculates the maximum ESR an output
capacitor can have to meet the output voltage ripple specification. Equation 16 indicates the ESR should be less
than 0.160 Ω.
The most stringent criteria for the output capacitor is 3.79 µF of capacitance to maintain the output voltage
regulation during an load transient.
Additional capacitance de-ratings for aging, temperature and dc bias will increase this minimum value. For this
example, 10 µF, 10V X5R ceramic capacitor with 0.003 Ω of ESR in a 1206 package is used.
Capacitors generally have limits to the amount of ripple current they can handle without failing or producing
excess heat. An output capacitor that can support the inductor ripple current must be specified. Some capacitor
data sheets specify the Root Mean Square (RMS) value of the maximum ripple current.
Equation 12 can be used to calculate the RMS ripple current the output capacitor needs to support. For this
example, Equation 12 yields 10.23 mA.
æ
ö
VOUT
´
V max - V
(
)
1
IN
OUT
ICOrms =
´
ç
ç
÷
÷
V max ´ LO ´ fSW
12
IN
è
ø
(12)
(13)
æ
ç
è
ö
IRIPPLE
1
CO1 ³
´
÷
VRIPPLE
8 ´ fSW
ø
2
IOH - IOL
2
CO 2 ³ LO
´
2
2
V
(
+ DVOUT
- VOUT
)
OUT
(14)
(15)
(16)
DIOUT
2
CO 3 ³
´
DVOUT f sw
VRIPPLE
RC
£
IRIPPLE
Input capacitor
The TPS54061-Q1 requires a high quality ceramic, type X5R or X7R, input decoupling capacitor of at least 1µF
of effective capacitance. The effective capacitance includes any deration for dc bias effects. The voltage rating of
the input capacitor must be greater than the maximum input voltage. The capacitor must also have an rms
current rating greater than the maximum rms input current. The input rms current can be calculated using
Equation 17. The value of a ceramic capacitor varies significantly over temperature and the dc bias applied to the
capacitor. The capacitance variations with temperature can be minimized by selecting a dielectric material that is
stable over temperature. X5R and X7R ceramic dielectrics are usually selected for power regulator capacitors
Copyright © 2013, Texas Instruments Incorporated
17
TPS54061-Q1
ZHCSAY7 –MARCH 2013
www.ti.com.cn
because they have a high capacitance to volume ratio and are fairly stable over temperature. The effective value
of a capacitor decreases as the dc bias across a capacitor increases. For this example design, a ceramic
capacitor with at least a 60 V voltage rating is required to support the maximum input voltage. The input
capacitance value determines the input ripple voltage of the regulator. The input voltage ripple can be calculated
by rearranging Equation 18.
Using the design example values, Ioutmax = 200 mA, CIN = 2.2 µF, ƒSW = 400 kHz, yields an input voltage ripple
of 56.8 mV and an rms input ripple current of 98.5 mA.
V
- VOUT
(
)
VOUT
INmin
ICINrms = IOUT
´
´
V
V
INmin
INmin
(17)
(18)
æ
ç
è
ö
IO
0.25
CIN
³
´
÷
V ripple
fSW
IN
ø
Bootstrap Capacitor Selection
A 0.01-µF ceramic capacitor must be connected between the BOOT and PH pins for proper operation. It is
recommended to use a ceramic capacitor with X5R or better grade dielectric. The capacitor should have 10V or
higher voltage rating.
Under Voltage Lock Out Set Point
The Under Voltage Lock Out (UVLO) can be adjusted using an external voltage divider on the EN pin of the
TPS54061-Q1. The UVLO has two thresholds, one for power up when the input voltage is rising and one for
power down or brown outs when the input voltage is falling. For the example design, the supply should turn on
and start switching once the input voltage increases above 7.50 V (enabled). After the regulator starts switching,
it should continue to do so until the input voltage falls below 6.50 V (UVLO stop). The programmable UVLO and
enable voltages are set by connecting resistor divider between Vin and ground to the EN pin. Equation 2 and
Equation 3 can be used to calculate the resistance values necessary. For example, a 196 kΩ resistor between
Vin and EN and a 36.5 kΩ resistor between EN and ground are required to produce the 7.50 and 6.50 volt start
and stop voltages. See the Enable and Adjusting Undervoltage Lockout section for additional considerations in
high input voltage applications.
Output Voltage and Feedback Resistors Selection
For the example design, 10 kΩ was selected for RLS. Using Equation 1, RHS is calculated as 31.46 kΩ. The
nearest standard 1% resistor is 31.6 kΩ.
Closing the Loop
There are several methods used to compensate DC/DC regulators. The method presented here is easy to
calculate and ignores the effects of the slope compensation that is internal to the device. Since the slope
compensation is ignored, the actual cross over frequency will usually be lower than the cross over frequency
used in the calculations. This method assume the crossover frequency is between the modulator pole and the
ESR zero and the ESR zero is at least 10 times greater the modulator pole.
To get started, the modulator pole, fpole, and the ESR zero, fzero must be calculated using Equation 19 and
Equation 20. For Cout, use a derated value of 6.0 µF. Use Equation 21 and Equation 22, to estimate a starting
point for the crossover frequency, fco, to design the compensation. For the example design, fpole is 1015 Hz and
fzero is 5584 kHz.
Equation 21 is the geometric mean of the modulator pole and the ESR zero and Equation 22 is the mean of
modulator pole and the switching frequency. Equation 21 yields 119.2 kHz and Equation 22 gives 17.9 kHz. Use
a frequency near the lower value of Equation 21 or Equation 22 for an initial crossover frequency.
For this example, fco of 17.9 kHz is used. Next, the compensation components are calculated. A resistor in
series with a capacitor is used to create a compensating zero. A capacitor in parallel to these two components
forms the compensating pole.
To determine the compensation resistor, RCOMP, use Equation 23. Assume the power stage transconductance,
gmps, is 1.00 A/V. The output voltage, Vo, reference voltage, VREF, and amplifier transconductance, gmea, are
3.3 V, 0.8 V and 108 µA/V, respectively.
18
Copyright © 2013, Texas Instruments Incorporated
TPS54061-Q1
www.ti.com.cn
ZHCSAY7 –MARCH 2013
RCOMP is calculated to be 25.9 kΩ, use the nearest standard value of 26.1 kΩ. Use Equation 24 to set the
compensation zero equal to the modulator pole frequency. Equation 24 yields a 3790 pF for capacitor CCOMP and
a 4700 pF is chosen. Use the larger value of Equation 25 and Equation 26 to calculate the CPOLE value, to set
the compensation pole. Equation 26 yields 30.5 pF so the nearest standard of 33 pF is selected.
1
f pole(Hz) =
Vout
´ Co ´ 2 ´ p
Io
(19)
1
f zero(Hz) =
RC ´ CO ´ 2 ´ p
(20)
(21)
0.5
)
fco1(Hz) = f zero ´ f pole
(
ö0.5
f sw
æ
f co2(Hz) =
´ f pole
ç
÷
2
è
ø
(22)
(23)
2 ´ p ´ ¦CO ´ CO
VOUT
RCOMP
=
´
gmps
VREF ´ gmea
1
C5 =
2 ´ p ´ R4 ´ fPOLE
(24)
(25)
RC ´ CO
C6 =
R4
1
C6 =
R4 ´ fSW ´ p
(26)
Copyright © 2013, Texas Instruments Incorporated
19
TPS54061-Q1
ZHCSAY7 –MARCH 2013
www.ti.com.cn
Characteristics
SPACER
100
90
80
70
60
50
40
30
20
10
0
100
90
V
F
= 3.3 V,
OUT
= 400 kHz
SW
80
70
60
50
40
30
20
V
V
V
V
V
= 8 V
V
V
V
V
V
= 8 V
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
= 12 V
= 24 V
= 36 V
= 60 V
= 12 V
= 24 V
= 36 V
= 60 V
V
F
= 3.3 V,
OUT
10
0
= 400 kHz
SW
0
0.025
0.05
0.075
0.1
0.125
0.15
0.175
0.2
0.001
0.01
0.1
1
Load Current (A)
Load Current (A)
Figure 21. Efficiency vs Output Current
spacer
Figure 22. Efficiency vs Output Current
spacer
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
V
F
= 5 V,
OUT
= 400 kHz
SW
V
V
V
V
V
= 8 V
V
V
V
V
V
= 8 V
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
= 12 V
= 24 V
= 36 V
= 60 V
= 12 V
= 24 V
= 36 V
= 60 V
V
F
= 5 V,
OUT
= 400 kHz
SW
0.001
0.01
0.1
1
0
0.025
0.05
0.075
0.1
0.125
0.15
0.175
0.2
Load Current (A)
Load Current (A)
Figure 23. Efficiency vs Output Current
spacer
Figure 24. Efficiency vs Output Current
spacer
0.25
60
40
180
120
60
I
= 200 mA,
= 400 kHz
OUT
0.2
0.15
0.1
F
SW
20
0.05
0
0
0
–0.05
–0.1
–0.15
–0.2
–0.25
–20
–40
–60
–60
–120
–180
Gain
Phase
0
10
20
30
40
50
60
10
100
1K
10K
100K
Input Voltage (V)
Frequency (Hz)
Figure 25. Gain vs Phase
Figure 26. Output Voltage vs Input Voltage
20
Copyright © 2013, Texas Instruments Incorporated
TPS54061-Q1
www.ti.com.cn
ZHCSAY7 –MARCH 2013
Characteristics (continued)
SPACER
0.50
V
V
F
= 24 V,
IN
0.40
0.30
= 3.3 V,
= 400 kHz
OUT
IOUT = 100 mA /div
SW
0.20
0.10
0
–0.10
–0.20
–0.30
–0.40
–0.50
V
OUT = 50 mV /div ac coupled
0
0.025
0.05
0.075
0.1
0.125
0.15
0.175
0.2
500 μs /div
Load Current (A)
Figure 27. Output Voltage vs Output Current
spacer
Figure 28. Load Transient
spacer
VIN = 10 V /div
VIN = 10 V /div
V
EN = 5 V /div
VOUT = 20 mV /div ac coupled
V
OUT = 2 V /div
5 ms /div
1 ms /div
Figure 29. Line Transient
spacer
Figure 30. Startup with ENA
spacer
PH = 20 V /div
V
IN = 10 V /div
Inductor Current = 200 mA /div
V
EN = 2 V /div
V
OUT = 2 V /div
V
IN = 10 mV /div ac coupled
2 ms /div
2 μs /div
Figure 31. Startup with VIN
Figure 32. Input Ripple in DCM
Copyright © 2013, Texas Instruments Incorporated
21
TPS54061-Q1
ZHCSAY7 –MARCH 2013
www.ti.com.cn
Characteristics (continued)
SPACER
PH = 20 V /div
PH = 20 V /div
Inductor Current = 200 mA /div
Inductor Current = 200 mA /div
V
IN = 50 mV /div ac coupled
V
IN = 10 mV /div ac coupled
2 μs /div
2 μs /div
Figure 33. Input Ripple in CCM
spacer
Figure 34. Input Ripple Skip
spacer
PH = 20 V /div
PH = 20 V /div
Inductor Current = 200 mA /div
Inductor Current = 200 mA /div
V
OUT = 10 mV /div
V
OUT = 10 mV /div ac coupled
2 μs /div
2 μs /div
Figure 35. Output Ripple in DCM
spacer
Figure 36. Output Ripple in CCM
spacer
PH = 20 V /div
Inductor Current = 200 mA /div ac coupled
V
OUT = 20 mV /div ac coupled
2 μs /div
Figure 37. Output Ripple Skip
22
Copyright © 2013, Texas Instruments Incorporated
TPS54061-Q1
www.ti.com.cn
ZHCSAY7 –MARCH 2013
DESIGN GUIDE – STEP-BY-STEP PROCEDURE Number 2
CBOOT
0.01 µF
LO
U1
TPS54061
220 µH
5.0 V
1
2
8
7
1
2
8 V to 40 V
744 053 221
RCOMP
3
4
6
5
RHS
RUVLO1
CO
52.3 kΩ
35.7 kΩ
255 kΩ
CIN
CCOMP
CPOLE
22 µF
RLS
RT
RUVLO2
2.2 µF
220 pF
0.33 µF
1240 kΩ
45.3 kΩ
10 kΩ
Figure 38. DCM Application Schematic
It is most desirable to have a power supply that is efficient and has a fixed switching frequency at low output
currents. A fixed frequency power supply will have a predictable output voltage ripple and noise. Using a
traditional continuous conduction mode (CCM) design method to calculate the output inductor will yield a large
inductance for a low output current supply. Using a CCM inductor will result in a large sized supply or will affect
efficiency from the large dc resistance an alternative is to operate in discontinuous conduction mode (DCM). Use
the procedure below to calculate the components values for designing a power supply operating in discontinuous
conduction mode. The advantage of operating a power supply in DCM for low output current is the fixed
switching frequency, lower output inductance, and lower dc resistance on the inductor. Use the frequency shift
and skip equations to estimate the maximum switching frequency.
For Designing an Efficient, Low Output Current Power Supply at a Fixed Switching Frequency
This example details the design of a low output current, fixed switching regulator design using ceramic output
capacitors. A few parameters must be known in order to start the design process. These parameters are typically
determined at the system level. For this example, we will start with the following known parameters:
Output Voltage
5.0 V
Transient Response 37.5 to 75 mA load step ΔVOUT = 4%
Maximum Output Current
Minimum Output Currert
Input Voltage
75 mA
1 mA
24 V nom. 8 V to 40 V
Output Voltage Ripple
Switching Frequency
1 % of VOUT
50 kHz
8 V
Start Input Voltage (rising VIN)
Stop Input Voltage (falling VIN)
6.8 V
The TPS54061-Q1 is designed for applications which require a fixed operating frequency and low output voltage
ripple at low output currents, thus, the TPS54061-Q1 does not have a pulse skip mode at light loads. Since the
device has a minimum controllable on time, there is an output current at which the power supply will pulse skip.
To ensure that the supply does not pulse skip at output current of the application the inductor value will be need
to be selected greater than a minimum value. The minimum inductance needed to maintain a fixed switching
frequency at the minimum load is calculated to be 227 µH using Equation 27. Since the equation is ideal and
was derived without losses, assume the minimum controllable light load on time, tonminll, is 180 ns. To maintain
DCM operation the inductor value and output current need to stay below a maximum value. The maximum
inductance is calculated to be 250 µH using Equation 28. A 744053221 inductor from Würth Elektronik is
selected. If CCM operation is necessary, use the previous design procedure.
Copyright © 2013, Texas Instruments Incorporated
23
TPS54061-Q1
ZHCSAY7 –MARCH 2013
www.ti.com.cn
Use Equation 29, to make sure the minimum current limit on the high side power switch is not exceeded at the
maximum output current. The peak current is calculated as 244 mA and is lower than the 350 mA current limit.
To determine the rms current for the inductor and output capacitor, it is necessary to calculate the duty cycle.
The duty cycle, D1, for a step down regulator in DCM is calculated in Equation 30. D1 is the portion of the
switching cycle the high side power switch is on, and is calculated to be 0.1345. D2 is the portion of the switching
cycle the low side power switch is on, and is calculated to be 0.5111.
Using the Equation 32 and Equation 33, the rms current of the inductor and output capacitor are calculated, to be
0.1078 A and 0.0774 A respectively. Select components that ratings exceed the calculated rms values. Calculate
the output capacitance using the Equation 34 to Equation 36 and use the largest value, Vripple is the steady
state voltage ripple and deltaV is voltage change during a transient. A minimum of 7.5 µF capacitance is
calculated. Additional capacitance de-ratings for aging, temperature and dc bias should be factored in which
increases this minimum value. For this example, a 22 µF 10 V X7R ceramic capacitor with 5mΩ ESR is used. To
have a low output ripple power supply use a low esr capacitor. Use Equation 37 to estimate the maximum esr for
the output capacitor. Equation 38 and Equation 39 estimate the rms current and capacitance for the input
capacitor. An rms current of 38.7 mA and capacitance of 1.56 µF is calculated. A 2.2 µF 100V/X7R ceramic is
used for this example.
tOnmin2
æ
ç
è
ö
÷
ø
V max - VOUT
V max
æ
ö
IN
IN
Lomin ³
´
´
x f sw
ç
÷
VOUT
2
IOmin
è
ø
(27)
(28)
æ
ö
V min - V
VOUT
1
æ
ö
IN
OUT
LOmax £
´
÷
´
÷
ç
ç
2
V min
fsw ´ IO
è
ø
IN
è
ø
æ
ö0.5
2 ´ VOUT ´ Iomax ´ V max - V
(
)
IN
OUT
ILpeak =
ç
ç
÷
÷
V max ´ LO ´ fsw
IN
è
ø
(29)
æ
ö0.5
2 ´ VOUT ´ IO ´ LO ´ fsw
D1 =
ç
ç
÷
÷
V
´
V
- VOUT
(
)
IN
IN
è
ø
(30)
(31)
(32)
æ
ç
è
ö
V
- VOUT
IN
D2 =
´ D1
÷
VOUT
ø
0.5
D1 + D2
3
æ
ö
ILrms = ILpeak ´
ç
÷
è
ø
æ
ç
ç
è
2 ö0.5
÷
÷
ø
D1 + D2
3
D1 + D2
4
æ
ö
æ
ö
ICOrms = ILpeak ´
-
ç
ç
÷
÷
è
ø
è
ø
(33)
(34)
æ
ç
è
ö
÷
ø
ILpeak
D1 + D2
CO1 £
´
VRIPPLE
CO 2 ³ LO
IOUT
8 ´ fSW
Io2 - 02
´
2
2
V
+ DV
- VOUT
(
)
OUT
(35)
(36)
(37)
1
Co3 ³
´
DVOUT fco
VRIPPLE
£
RC
ILpeak
æ
ç
ç
è
2 ö0.5
÷
÷
ø
D1
3
D1
4
æ
ö
æ
ö
ICINrms = ILpeak ´
-
ç
÷
ç
÷
è
ø
è
ø
(38)
æ
ö
IO
0.25
CIN
³
´
ç
÷
V RIPPLE
fSW
IN
è
ø
(39)
24
Copyright © 2013, Texas Instruments Incorporated
TPS54061-Q1
www.ti.com.cn
ZHCSAY7 –MARCH 2013
Closing the Feedback Loop
The method presented here is easy to calculate and includes the effect of the slope compensation that is internal
to the TPS54061-Q1. This method assumes the crossover frequency is between the modulator pole and the ESR
zero and the ESR zero is at least 10 times greater than the modulator pole. Once the output components are
determined, use the equations below to close the feedback loop. A current mode controlled power supply
operating in DCM has a transfer function which includes an ESR zero and pole as shown in Equation 40. To
calculate the current mode power stage gain, first calculate, Kdcm, the DCM gain, and Fm, the modulator gain,
using Equation 41 and Equation 42. Kdcm and Fm are 32.4 and 0.475 respectively. The location of the pole and
ESR zero are calculated using Equation 43 and Equation 44 . The pole and zero are 491 Hz and 2.8 MHz,
respectively. Use the lower value of Equation 45 and Equation 46 as a starting point for the crossover frequency.
Equation 45 is the geometric mean of the power stage pole and the esr zero and Equation 46 is the mean of
power stage pole and the switching frequency. The crossover frequency is chosen as 5 kHz from Equation 46.
To determine the compensation resistor, RCOMP, use Equation 47. Assume the power stage transconductance,
gmps, is 1.0 A/V. The output voltage, VO, reference voltage, VREF, and amplifier transconductance, gmea, are
5.0 V, 0.8 V and 108 µA/V, respectively. RCOMP is calculated to be 38.3 kΩ; use the nearest standard value of
35.7 kΩ. Use Equation 48 to set the compensation zero to equalthe modulator pole frequency. Equation 48
yields 290 nF for compensating capacitor CCOMP, and a 330 nF is used. Use the larger value of Equation 49 or
Equation 50 to calculate the CPOLE, which sets the compensation pole. Equation 50 yields 178 pF standard value
of 220 pF is selected.
s
1 +
2 ´ p ´ fZERO
Gdcm(s) » Fm ´ Kdcm ´
s
1 +
2 ´ p ´ fPOLE
(40)
VOUT
´
V
- VOUT
(
)
2
IN
Kdcm =
´
D1
æ
ç
ö
÷
Rdc
ç
ç
÷
÷
V
´
2 +
- VOUT
IN
VOUT
ç
÷
IO
è
ø
(41)
(42)
gmps
Fm =
æ
ç
è
ö
÷
ø
V
- VOUT
IN
+ 0.380
LO ´ fsw
VOUT
æ
ö
÷
÷
÷
2 -
ç
V
1
IN
ç
ç
fPOLE(Hz) =
´
VOUT
VOUT
´ CO ´ 2 ´ p
1 -
ç
÷
IO
V
IN
è
ø
(43)
1
fZERO(Hz) =
fCO1(Hz) =
RC ´ CO ´ 2 ´ p
(44)
(45)
(46)
0.5
f
´ fPOLE
(
)
0.5
ZERO
fCO2(Hz) =
f
´ fPOLE
SW
(
)
¦
VOUT
VREF ´ gmea
co
Kdcm´Fm´ ¦POLE
RCOMP
CCOMP
CPOLE1
CPOLE2
=
x
(47)
(48)
(49)
1
=
2 ´ p ´ RCOMP ´ Kdcm ´ Fm
RC ´ CO
=
RCOMP
1
=
RCOMP ´ fSW ´ p
(50)
25
Copyright © 2013, Texas Instruments Incorporated
TPS54061-Q1
ZHCSAY7 –MARCH 2013
www.ti.com.cn
Characteristics
SPACER
100
90
100
90
V
F
= 5 V,
OUT
= 50 kHz
SW
80
70
60
50
40
30
80
70
60
50
40
30
20
V
V
V
V
= 8 V
V
V
V
V
= 8 V
IN
IN
IN
IN
IN
IN
IN
IN
= 12 V
= 24 V
= 36 V
20
= 12 V
= 24 V
= 36 V
V
F
= 5 V,
OUT
10
0
10
0
= 50 kHz
SW
0
0.025
0.05
0.075
0.1
0.001
0.01
0.1
Load Current (A)
Load Current (A)
Figure 39. Efficiency vs Load Current
Figure 40. Efficiency vs Load Current
100
90
100
90
V
F
= 3.3 V,
OUT
= 50 kHz
SW
80
70
60
50
40
30
80
70
60
50
40
30
20
10
0
V
V
V
V
= 8 V
V
V
V
V
= 8 V
IN
IN
IN
IN
IN
IN
IN
IN
= 12 V
= 24 V
= 36 V
20
= 12 V
= 24 V
= 36 V
V
F
= 3.3 V,
OUT
10
0
= 50 kHz
SW
0
0.025
0.05
0.075
0.1
0.001
0.01
0.1
Load Current (A)
Load Current (A)
Figure 41. Efficiency vs Load Current
Figure 42. Efficiency vs Load Current
0.50
0.40
40
180
135
90
Gain
V
V
F
= 24 V,
= 5 V,
IN
30
20
Phase
OUT
0.30
= 50 kHz
SW
0.20
10
45
0.10
0.00
0
0
–0.10
–0.20
–0.30
–0.40
–0.50
–10
–20
–30
–40
–45
–90
–135
–180
0
0.025
0.05
0.075
0.1
10
100
1K
10K
100K
Load Current (A)
Frequency (Hz)
Figure 43. Frequency Response
Figure 44. Output Voltage Normalized vs Load
Current
26
Copyright © 2013, Texas Instruments Incorporated
TPS54061-Q1
www.ti.com.cn
ZHCSAY7 –MARCH 2013
Characteristics (continued)
SPACER
0.25
V
OUT = 100 mV /div ac coupled
I
= 37.5 mA,
= 50 kHz
0.2
0.15
0.1
OUT
F
SW
0.05
0
–0.05
–0.1
–0.15
–0.2
–0.25
IOUT = 20 mA/div
2 ms /div
0
10
20
30
40
50
60
Input Voltage (V)
Figure 45. Output Voltage Normalized vs Input
Voltage
Figure 46. Load Transient
V
OUT = 100 mV /div ac coupled
V
IN = 10 V /div
V
OUT = 2 V /div
EN = 5 V /div
IOUT = 20 mA/div
IOUT = 50 mA/div
10 ms /div
4 ms /div
Figure 47. Unload Transient
Figure 48. Startup With ENA
V
IN = 10 V /div
V
IN = 10 V /div
V
OUT = 2 V /div
V
OUT = 2 V /div
EN = 5 V /div
EN = 5 V /div
IOUT = 50 mA/div
IOUT = 50 mA/div
10 ms /div
10 ms /div
Figure 49. Startup With VIN
Figure 50. Prebias Startup With ENA
Copyright © 2013, Texas Instruments Incorporated
27
TPS54061-Q1
ZHCSAY7 –MARCH 2013
www.ti.com.cn
Characteristics (continued)
SPACER
PH = 20 V /div
V
IN = 10 V /div
V
IN = 100 nV /div ac coupled
V
OUT = 2 V /div
V
OUT = 50 mV /div ac coupled
EN = 5 V /div
IOUT = 50 mA/div
Inductor current = 100 mA/div
4 µs /div
10 ms /div
Figure 51. Prebias Startup With VIN
spacer
Figure 52. Input and Output Ripple in DCM
spacer
PH = 20 V /div
V
IN = 20 mV /div ac coupled
VOUT = 20 mV /div ac coupled
Inductor current = 20 mA/div
4 µs /div
Figure 53. Input and Output Ripple in PSM
28
Copyright © 2013, Texas Instruments Incorporated
TPS54061-Q1
www.ti.com.cn
ZHCSAY7 –MARCH 2013
Layout
Layout is a critical portion of good power supply design. There are several signals paths that conduct fast
changing currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise
or degrade the power supplies performance. To help eliminate these problems, the VIN pin should be bypassed
to ground with a low ESR ceramic bypass capacitor with X5R or X7R dielectric. Care should be taken to
minimize the loop area formed by the bypass capacitor connections, the VIN pin, and the GND pin. See
Figure 54 for a PCB layout example. Since the PH connection is the switching node and output inductor should
be located close to the PH pins, and the area of the PCB conductor minimized to prevent excessive capacitive
coupling. The RT/CLK pin is sensitive to noise. so the RT resistor should be located as close as possible to the
IC and routed with minimal lengths of trace. The additional external components can be placed approximately as
shown. It may be possible to obtain acceptable performance with alternate PCB layouts; however; this layout has
been shown to produce good results and is meant as a guideline.
VOUT
Output
Capacitor
Output
Inductor
Route Boot Capacitor
Trace on another layer to
provide wide path for
topside ground
GND
Input
Capacitor
Boot
Capacitor
PH
GND
BOOT
VIN
Compensation
Network
VIN
Feedback
Resistors
COMP
EN
UVLO
Adjust
Resistor
RT/CLK
VSENSE
Signal VIA
Frequency Set
Resistor
Figure 54. PCB Layout Example
Copyright © 2013, Texas Instruments Incorporated
29
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS54061QDRBRQ1
TPS54061QDRBTQ1
ACTIVE
ACTIVE
SON
SON
DRB
DRB
8
8
2500 RoHS & Green
250 RoHS & Green
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 150
-40 to 150
61Q1
61Q1
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE OUTLINE
DRB0008B
VSON - 1 mm max height
SCALE 4.000
PLASTIC SMALL OUTLINE - NO LEAD
3.1
2.9
B
A
PIN 1 INDEX AREA
3.1
2.9
C
1 MAX
SEATING PLANE
0.08 C
0.05
0.00
EXPOSED
THERMAL PAD
1.65 0.05
(0.2) TYP
4
5
2X
1.95
2.4 0.05
8
1
6X 0.65
0.35
0.25
8X
PIN 1 ID
0.1
C A B
C
0.5
0.3
8X
(OPTIONAL)
0.05
4218876/A 12/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
DRB0008B
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(1.65)
SYMM
8X (0.6)
1
8
8X (0.3)
(2.4)
(0.95)
6X (0.65)
4
5
(R0.05) TYP
(0.575)
(2.8)
(
0.2) VIA
TYP
LAND PATTERN EXAMPLE
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4218876/A 12/2017
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
DRB0008B
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
SYMM
METAL
TYP
8X (0.6)
8X (0.3)
1
8
(0.63)
SYMM
(1.06)
6X (0.65)
5
4
(R0.05) TYP
(1.47)
(2.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
81% PRINTED SOLDER COVERAGE BY AREA
SCALE:25X
4218876/A 12/2017
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
重要声明和免责声明
TI 均以“原样”提供技术性及可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资
源，不保证其中不含任何瑕疵，且不做任何明示或暗示的担保，包括但不限于对适销性、适合某特定用途或不侵犯任何第三方知识产权的暗示
担保。
所述资源可供专业开发人员应用TI 产品进行设计使用。您将对以下行为独自承担全部责任：(1) 针对您的应用选择合适的TI 产品；(2) 设计、
验证并测试您的应用；(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。所述资源如有变更，恕不另行通知。TI 对您使用
所述资源的授权仅限于开发资源所涉及TI 产品的相关应用。除此之外不得复制或展示所述资源，也不提供其它TI或任何第三方的知识产权授权
许可。如因使用所述资源而产生任何索赔、赔偿、成本、损失及债务等，TI对此概不负责，并且您须赔偿由此对TI 及其代表造成的损害。
TI 所提供产品均受TI 的销售条款 (http://www.ti.com.cn/zh-cn/legal/termsofsale.html) 以及ti.com.cn上或随附TI产品提供的其他可适用条款的约
束。TI提供所述资源并不扩展或以其他方式更改TI 针对TI 产品所发布的可适用的担保范围或担保免责声明。IMPORTANT NOTICE
邮寄地址：上海市浦东新区世纪大道 1568 号中建大厦 32 楼，邮政编码：200122
Copyright © 2020 德州仪器半导体技术（上海）有限公司
相关型号：
TPS54073PWPRG4
3V to 4V Input, 14A Synchronous Step-Down SWIFT™ Converter for Pre-biased Outputs 28-HTSSOP -40 to 85
TI
©2020 ICPDF网 联系我们和版权申明