TPS54116-Q1 [TI]

采用 4A 2MHZ VDDQ 直流/直流转换器、1A VTT LDO 和 VTTREF 的汽车类 DDR 电源解决方案;


型号：	TPS54116-Q1
厂家：	TEXAS INSTRUMENTS
描述：	采用 4A 2MHZ VDDQ 直流/直流转换器、1A VTT LDO 和 VTTREF 的汽车类 DDR 电源解决方案双倍数据速率转换器
文件：	总41页 (文件大小：1180K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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TPS54116-Q1

ZHCSFG9A –AUGUST 2016–REVISED AUGUST 2016

TPS54116-Q1 2.95V 至 6V 输入、4A 降压转换器和 1A 拉/灌电流 DDR 终

端稳压器

1 特性

TPS54116-Q1 降压稳压器通过集成 MOSFET 和减小

电感尺寸来最大限度减小解决方案尺寸，开关频率最高

达 2.5MHz。开关频率可设置在中波频段以上以满足噪

声敏感型应用的需求，而且能够与外部时钟同步。同

步整流使频率在整个输出负载范围内保持为固定值。效

率通过集成 25mΩ 低侧 MOSFET 和 33mΩ 高侧

MOSFET 得到了最大限度的提升。逐周期峰值电流限

制在过流状态下保护器件，并且可通过 ILIM 引脚上的

电阻进行调整，从而针对小尺寸电感进行优化。

•

具有符合 AEC-Q100 标准的下列结果：

–

器件温度 1 级：-40℃ 至 +125℃ 的环境运行温

度范围

器件人体模型 (HBM) 静电放电 (ESD) 分类等级

器件组件充电模式 (CDM) ESD 分类等级 C6

•

单片 DDR2、DDR3 和 DDR3L 存储器电源解决方

案

4A 同步降压转换器

VTT 终端稳压器仅利用 2 × 10µF 的陶瓷输出电容即可

保持快速瞬态响应，从而减少外部组件数量。

TPS54116-Q1 使用 VTT 进行远程感测，从而实现最

佳的稳压效果。

–

集成了 33mΩ 高侧和 25mΩ 低侧金属氧化物半

导体场效应晶体管 (MOSFET)

–

固定频率电流模式控制

可调频率范围：100kHz 至 2.5MHz

与一个外部时钟同步

该器件可利用使能引脚进入关断模式，从而使电源电流

降至 1µA。欠压闭锁阈值可通过任一使能引脚上的电

阻网络进行设置。VTT 和 VTTREF 输出被 ENLDO 禁

用时会进行放电。

整个温度范围内的电压基准为 0.6V ± 1%

可调逐周期峰值电流限制

针对预偏置输出的单调性启动

•

直流精度为 ±20mV 的 1A 拉/灌电流终端低压降

(LDO) 稳压器

该器件具备全集成特性，并且采用小尺寸的 4mm ×

4mm 耐热增强型 WQFN 封装，最大限度地减小了 IC

尺寸。

–

与 2 × 10µF 多层陶瓷电容 (MLCC) 电容一起工

作时保持稳定

–

10mA 拉/灌电流缓冲参考输出稳定在 VDDQ 的

49% 至 51% 之间

器件信息⁽¹⁾

器件型号

封装

WQFN (24)

封装尺寸（标称值）

•

独立使能引脚，欠压闭锁 (UVLO) 和迟滞均可调

热关断

TPS54116-Q1

4.00mm x 4.00mm

(1) 如需了解所有可用封装，请见数据表末尾的可订购产品附录。

运行温度 (T_{J) 范围：-40°C 至 150°C}

简化电路原理图

24 引脚 4mm x 4mm 超薄四方扁平无引线

(WSON) 封装

TPS54116-Q1 _BOOT

V_IN

AVIN

2 应用

ENSW

ENLDO

PGOOD

ILIM

•

嵌入式计算系统中的 DDR2、DDR3、DDR3L 和

V_IN

PVIN

PGND

DDR4 存储器电源

•

SSTL_18、SSTL_15、SSTL_135、SSTL_12 和

HSTL 终端

VDDQSNS

LDOIN

SS/TRK

V_DDQ

•

信息娱乐和仪表板

COMP

VTT

先进的驾驶员辅助系统 (ADAS)

VTTSNS

VTTGND

VTTREF

V_TT

3 说明

AGND

RT/SYNC

TPS54116-Q1 器件是一款功能全面的 6V、4A 同步降

压转换器，其配有两个集成型 MOSFET 以及带

VTTREF 缓冲参考输出的 1A 拉/灌电流双倍数据速率

(DDR) VTT 终端稳压器。

V_TTREF

PAD

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

English Data Sheet: SLVSCO3

TPS54116-Q1

ZHCSFG9A –AUGUST 2016–REVISED AUGUST 2016

www.ti.com.cn

7.4 Device Functional Modes........................................ 23

Application and Implementation ........................ 24

8.1 Application Information............................................ 24

8.2 Typical Application ................................................. 25

Power Supply Recommendations...................... 34

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Pin Configuration and Functions......................... 3

Specifications......................................................... 4

6.1 Absolute Maximum Ratings ...................................... 4

6.2 ESD Ratings ............................................................ 4

6.3 Recommended Operating Conditions....................... 5

6.4 Thermal Information.................................................. 5

6.5 Electrical Characteristics........................................... 5

6.6 Typical Characteristics.............................................. 8

Detailed Description ............................................ 15

7.1 Overview ................................................................. 15

7.2 Functional Block Diagram ....................................... 16

7.3 Feature Description................................................. 17

10 Layout................................................................... 34

10.1 Layout Guidelines ................................................. 34

10.2 Layout Example .................................................... 35

11 器件和文档支持 ..................................................... 36

11.1 接收文档更新通知 ................................................. 36

11.2 社区资源................................................................ 36

11.3 商标....................................................................... 36

11.4 静电放电警告......................................................... 36

11.5 Glossary................................................................ 36

12 机械、封装和可订购信息....................................... 36

4 修订历史记录

Changes from Original (August 2016) to Revision A

Page

•

Changed pin 18 From: RT/CLK To: RT/SYNC in the Pin Functions table............................................................................. 4

Changed R_(RT/CLK)To: R_(RT/SYNC)in 图 16 and 图 17............................................................................................................... 9

Changed "The RT/CLK is typically 0.5 V.." To: "The RT/SYNC is typically 0.5 V.." in Constant Switching Frequency

and Timing Resistor (RT/SYNC) .......................................................................................................................................... 20

TPS54116-Q1

www.ti.com.cn

ZHCSFG9A –AUGUST 2016–REVISED AUGUST 2016

5 Pin Configuration and Functions

RTW Package

WQFN 24 Pins

Top View

RT/SYNC

SS/TRK

COMP

BOOT

AVIN

PAD

ENSW

ENLDO

AGND

ILIM

PGOOD

Pin Functions

I/O

DESCRIPTION

NAME

NO.

1, 23, 24

Switching node of the buck converter.

Bootstrap capacitor node for high-side MOSFET gate driver of the buck converter. Connect

the bootstrap capacitor from this pin to the SW pin.

BOOT

AVIN

The input supply pin to the IC, powering the control circuits of both the buck converter and

DDR termination regulator. Connect AVIN to a supply voltage between 2.95 V and 6 V.

Buck converter enable pin with internal pull-up current source. Floating this pin will enable

the IC. Pull below 1.17 V to enter low current standby mode. Pull below 0.4 V to enter

shutdown mode. The ENSW pin can be used to implement adjustable under-voltage lockout

(UVLO) using two resistors.

ENSW

VTT LDO enable pin with internal pull-up current source. Floating this pin will enable the IC.

Pull below 1.17 V to enter low current standby mode. Pull below 0.4 V to enter shutdown

mode. The ENLDO pin can be used to implement adjustable under-voltage lockout (UVLO)

using two resistors.

ENLDO

Power good indicator for the buck regulator. This pin is an open-drain output. A 10-kΩ pull-

up resistor is recommended between PGOOD and AVIN or an external logic supply pin.

PGOOD

VDDQSNS

VDDQ sense input to generate VDDQ/2 reference for VTTREF.

Power supply input for VTT LDO. Connected VDDQ in typical application. Alternatively this

pin can be used for split-rail configuration to reduce power dissipation when sourcing current

to the VTT output by powering the VTT LDO with a lower voltage.

LDOIN

VTT

1-A LDO output. Connect 2 x 10-µF ceramic capacitors to VTTGND for stability.

Power ground for VTT LDO.

VTTGND

VTTSNS

VTT LDO voltage feedback.

Buffered low-noise VTT reference output. Connect to a 0.22 µF or larger ceramic capacitor to

AGND for stability.

VTTREF

Programmable current limit pin. An internal amplifier holds this pin at a fixed voltage then

sets the high-side MOSFET peak current limit based on the value of an external resistor to

AGND.

ILIM

Analog signal ground of the IC. AGND should be connected to PGND via a single point on

the PCB, typically to the thermal pad.

AGND

TPS54116-Q1

ZHCSFG9A –AUGUST 2016–REVISED AUGUST 2016

www.ti.com.cn

Pin Functions (continued)

I/O

DESCRIPTION

NAME

NO.

Error amplifier inverting input and feedback pin for voltage regulation of the buck converter.

Connect this pin to the center of a resistor divider to set the output voltage of the buck

converter. The resistor divider should go from the regulated output voltage to AGND.

Output of the internal transconductance error amplifier for the buck converter. The feedback

loop compensation network is connected from this pin to AGND.

COMP

Soft-start programming pin. A capacitor between the SS/TRK pin and AGND pin sets soft-

start time. The voltage on this pin overrides the internal reference allowing it to be used for

tracking and sequencing.

SS/TRK

Resistor Timing and External Clock. An internal amplifier holds this pin at a fixed voltage

when using an external resistor to AGND to set the switching frequency. If the pin is pulled

above the upper threshold, a mode change occurs and the pin becomes a synchronization

input. The internal amplifier is disabled and the pin is a high impedance clock input. If

clocking edges stop, the internal amplifier is re-enabled and the operating mode returns to

resistor frequency programming.

RT/SYNC

Power ground of the buck regulator. PGND should be connected to AGND via a single point

on PCB board, typically to the thermal pad.

PGND

PVIN

19, 20

21, 22

The input supply pin for power MOSFETs. Connect PVIN to a supply voltage between 2.95 V

and 6 V.

The exposed thermal pad must be electrically connected to AGND and PGND on the printed

circuit board for proper operation. Connect to the largest possible copper area for best

thermal performance.

PAD

–

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)

(1)

MIN

-0.3

-0.6

-4

MAX

UNIT

PVIN, AVIN, ENSW, ENLDO, PGOOD

FB, COMP, SS/TRK, ILIM

RT/SYNC

BOOT with respect to SW

Voltage Range

LDOIN, VTTSNS, VDDQSNS

3.6

SW, 10-ns transient

VTT, VTTREF

3.6

100

-0.3

-100

-5

RT/SYNC

Current Range

µA

°C

PGOOD

Operating junction temperature

Storage temperature, T_stg

-40

150

-65

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE

UNIT

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins⁽¹⁾

±2000

V_(ESD)

Electrostatic discharge

Charged device model (CDM), per JEDEC specification JESD22-C101,

all pins⁽²⁾

±1000

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

TPS54116-Q1

www.ti.com.cn

ZHCSFG9A –AUGUST 2016–REVISED AUGUST 2016

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

MAX

UNIT

V_(AVIN), V_(PVIN)

V_OUT

Input voltage

2.95

Buck output voltage

Buck output current

0.6

4.5

I_OUT

V_(VDDQSNS)

V_(LDOIN)

VDDQSNS input voltage

LDOIN input voltage

VTT and VTTREF output voltage

VTT + VDO

0.5

3.5

V_(VTT), V_(VTTREF)

6.4 Thermal Information

TPS54116-Q1

THERMAL METRIC⁽¹⁾

RTW (WQFN)

24 PINS

36.2

UNIT

R_θJA

Junction-to-ambient thermal resistance

R_θJC(top)

R_θJB

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

35.0

14.3

°C/W

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.4

ψ_JB

14.4

R_θJC(bot)

4.6

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report.

6.5 Electrical Characteristics

TJ = -40°C to 150°C, AVIN = PVIN = 2.95 V to 6 V, VLDOIN = VDDQSNS (unless otherwise noted)

PARAMETER

SUPPLY VOLTAGE (AVIN and PVIN PINS)

AVIN and PVIN operating

TEST CONDITIONS

MIN

TYP

MAX

UNIT

2.95

2.8

AVIN internal UVLO threshold

AVIN rising

2.7

AVIN internal UVLO hysteresis

0.05

0.12

V_(ENSW)= V_(ENLDO)= 0 V, V_(VDDQSNS)= 1.8

V, TJ = 25°C

Iq shutdown

650

190

3.5

800

300

µA

V_(ENSW)= V_(ENLDO)= V_(AVIN)= 5 V, V_(FB)

0.7 V, V_(VDDQSNS)= 1.8 V, TJ = 25°C

Iq operating — LDO and buck enabled

Iq operating — LDO enabled, buck

disabled

V_(ENLDO)= V_(AVIN)= 5 V, V_(ENSW)= 0 V,

V_(VDDQSNS)= 1.8 V, TJ = 25°C

V_(ENSW)= V_(AVIN)= 5 V, V_(ENLDO)= 0 V,

V_(FB)= 0.7 V, V_(VDDQSNS)= 1.8 V, TJ =

25°C

Iq operating — LDO disabled, buck

enabled

570

700

µA

ENABLE (ENSW and ENLDO PINS)

V_ENRISING

ENLDO rising threshold

ENLDO falling threshold

ENLDO voltage ramping up

1.20

1.17

V_ENFALLING

ENLDO voltage ramping down

ENLDO input current above voltage

threshold

V_(ENLDO)= Enable threshold + 50 mV

V_(ENLDO)= Enable threshold - 50 mV

-4.4

-1.7

ENLDO input current below voltage

threshold

µA

I_p

I_h

ENLDO hysteresis current

ENSW rising threshold

ENSW falling threshold

-2.7

1.20

1.17

V_ENRISING

V_ENFALLING

ENSW voltage ramping up

ENSW voltage ramping down

ENSW input current above voltage

threshold

V_(ENSW)= Enable threshold + 50 mV

V_(ENSW)= Enable threshold - 50 mV

-4.4

ENSW input current below voltage

threshold

µA

I_p

I_h

-1.7

-2.7

-8.5

ENSW hysteresis current

Input current above voltage threshold with V_(ENLDO)= V_(ENSW)= Enable threshold +

ENLDO and ENSW connected 50 mV

TPS54116-Q1

ZHCSFG9A –AUGUST 2016–REVISED AUGUST 2016

www.ti.com.cn

Electrical Characteristics (continued)

TJ = -40°C to 150°C, AVIN = PVIN = 2.95 V to 6 V, VLDOIN = VDDQSNS (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Input current below voltage threshold with V_(ENLDO)= V_(ENSW)= Enable threshold -

-3.4

µA

ENLDO and ENSW connected

50 mV

Hysteresis current with ENLDO and

ENSW connected

-5.1

µA

VOLTAGE REFERENCE AND ERROR AMPLIFIER (FB AND COMP PINS)

V_REF

Voltage Reference

0.594

0.6

0.606

360

FB pin input current

µS

µA

gm_EA

Error Amp transconductance (gm)

Error Amp source/sink

-2 µA < I_(COMP)< 2 µA, V_(COMP)= 1 V

V_(COMP)= 1 V, V_(FB)= 100 mV overdrive

260

MOSFETS AND POWER STAGE (SW AND BOOT PINS)

V_(BOOT-SW)= 5 V

2.2

6.6

High side switch resistance

mΩ

V_(BOOT-SW)= 3.3 V

V_(PVIN)= 5 V

Low side switch resistance

V_(PVIN)= 3.3 V

BOOT-SW UVLO

V_(PVIN)= 2.95 V

High-side FET current limit

Low-side FET reverse current limit

V_(PVIN)= 6V, R_(ILIM)= 100k

V_(PVIN)= 6V, R_(ILIM)= 200k

5.2

1.5

8.2

3.8

4.5

gm_PS

V_(COMP)to I_(SW)peak transconductance

Minimum pulse width

R_(ILIM)= 100k

A/V

Measured at 50% points on V_(SW), I_OUT

2 A

Measured at 50% points V_(SW), V_(PVIN)= 5

V, I_OUT= 0 A, TJ = -40°C to 125°C

Minimum pulse width

Minimum off-time

100

125

Prior to skipping off pulses, I_OUT= 2 A

TIMING RESISTOR AND EXTERNAL CLOCK (RT/SYNC PIN)

Switching frequency range using RT

mode

100

2500

kHz

R_(RT/SYNC)= 150 kΩ

370

1910

340

400

2070

420

430

2230

480

kHz

Switching frequency

R_(RT/SYNC)= 27 kΩ

V_(RT/SYNC)> 2.2 V or V_(RT/SYNC)< 0.35 V

Switching frequency range using SYNC

mode

100

2500

kHz

Minimum SYNC input pulse width

RT/SYNC high threshold

1.5

0.4

2.2

RT/SYNC low threshold

0.35

RT/SYNC rising edge to SW rising edge

delay

f_SW= 500 kHz

RT to SYNC lock in time

SYNC to RT lock in time

R_(RT/SYNC)= 150 kΩ

µs

Logic high or logic low at RT/SYNC to

SYNC signal

Internal RT to SYNC lock in time

µs

SYNC signal to logic high or logic low at

RT/SYNC

SYNC to internal RT lock in time

SOFT START AND TRACKING (SS/TRK PIN)

V_SSTHR

SS voltage threshold

0.15

V_(SS/TRK)< V_SSTHR

V_(SS/TRK)> V_SSTHR

V_(SS/TRK)= 0.3 V

98% normal

µA

I_SS

Charge Current

1.5

2.4

3.2

SS/TRK to FB matching

SS/TRK to reference crossover

SS/TRK discharge voltage (overload)

SS/TRK discharge voltage (fault)

SS/TRK discharge current (overload)

0.85

120

V_(FB)= 0 V

µA

V_(FB)= 0 V

V_(FB)= 0 V, V_(SS/TRK)= 0.4 V

160

TPS54116-Q1

www.ti.com.cn

ZHCSFG9A –AUGUST 2016–REVISED AUGUST 2016

Electrical Characteristics (continued)

TJ = -40°C to 150°C, AVIN = PVIN = 2.95 V to 6 V, VLDOIN = VDDQSNS (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

SS/TRK discharge current (AVIN UVLO,

ENSW low, thermal fault)

V_(AVIN)= 5 V, V_(SS/TRK)= 0.4 V

760

µA

POWER GOOD (PGOOD PIN)

V_(FB)falling (fault)

109

106

V_(FB)rising (good)

Threshold

V_(FB)rising (fault)

105

% V_REF

V_(FB)falling (good)

Hysteresis

V_(FB)falling and rising

V_(FB)= V_REF, V_(PGOOD)= 5.5 V

V_(AVIN)= 2.95 V

Output high leakage

On resistance

125

170

1.7

1.3

Minimum V_(AVIN)for valid output

V_(PGOOD)< 0.5 V, I_(PGOOD)= 100 µA

TERMINATION REGULATOR INPUTS (VLDOIN AND VDDQSNS PINS)

V_(LDOIN)Operating

3.5

1.2 V < V_(VDDQSNS)< 2.5 V, I_(VTT)= 0.5 A,

V_(VTT)= V_(VTTREF)- 40 mV

V_DO

DC V_(LDOIN)– V_(VTT)dropout

0.15

1.2 V < V_(VDDQSNS)< 2.5 V, I_(VTT)= 1.5 A,

V_(VTT)= V_(VTTREF)- 40 mV

0.45

VLDOIN supply current

VDDQSNS input current

V_(LDOIN)= 1.8 V, TJ = 25°C

V_(VDDQSNS)= 1.8 V

µA

VTTREF OUTPUT (VTTREF PIN)

V_(VTTREF)

VTTREF output voltage

V_(VDDQSNS)/2

|I_(VTTREF)| < 10 mA, V_(VDDQSNS)= 1.8 V

|I_(VTTREF)| < 10 mA, V_(VDDQSNS)= 1.5 V

|I_(VTTREF)| < 10 mA, V_(VDDQSNS)= 1.2 V

|I_(VTTREF)| < 5 mA, V_(VDDQSNS)= 1.2 V

V_(VDDQSNS)= 1.8 V, V_(VTTREF)= 0 V

V_(VDDQSNS)= 0 V, V_(VTTREF)= 1.8 V

-18

-15

-12

VTTREF output voltage difference from

V_(VDDQSNS)/2

V_(VTTREF)TOL

I_(VTTREF)SRC

I_(VTTREF)SNK

VTTREF source current limit

VTTREF sink current limit

TJ = 25°C, V_(VTTREF)= 0.5V, V_(ENLDO)= 0

I_(VTTREF)DIS

VTTREF discharge current

0.9

1.1

VTT OUTPUT (VTT PIN)

V_(VTT)

VTT output voltage

V_(VTTREF)

|I_(VTT)|≤ 10 mA, 1.2 V ≤ V_(VDDQSNS)≤ 1.8 V

VTT output voltage tolerance to VTTREF |I_(VTT)|≤ 1 A, 1.2 V ≤ V_(VDDQSNS)≤ 1.8 V

|I_(VTT)|≤ 1.5 A, 1.2 V ≤ V_(VDDQSNS)≤ 1.8 V

-20

-30

-40

V_(VTT)TOL

V_(VDDQSNS)= 1.8 V, V_(VTT)= V_(VTTSNS)

0.7 V

I_(VTT)SRC

I_(VTT)SNK

VTT source current limit

VTT sink current limit

1.5

2.5

V_(VDDQSNS)= 1.8 V, V_(VTT)= V_(VTTSNS)

1.1 V

I_(VTTSNS)BIASVTTSNS input bias current

I_(VTT)DISVTT discharge current

THERMAL SHUTDOWN

Thermal shutdown temperature

-0.1

4.8

0.1

µA

TJ = 25°C, V_(VTT)= 0.5 V, V_(ENLDO)= 0 V

175

℃

Thermal shutdown hysteresis

TPS54116-Q1

ZHCSFG9A –AUGUST 2016–REVISED AUGUST 2016

www.ti.com.cn

6.6 Typical Characteristics

800

775

750

725

700

675

650

625

600

V_IN= 3.3 V

V_IN= 5 V

V_IN= 3.3 V

V_IN= 5 V

-50

-25

100

125

150

-50

-25

100

125

150

Junction Temperature (èC)

D001

D002

图 1. Shutdown Supply Current vs Temperature

图 2. Non-switching Supply Current - LDO and Buck

Enabled vs Temperature

325

300

275

250

225

200

175

150

125

610

605

600

595

590

585

580

575

570

565

560

555

V_IN= 3.3 V

V_IN= 5 V

V_IN= 3.3 V

V_IN= 5 V

-50

-25

100

125

150

-50

-25

100

125

150

Junction Temperature (èC)

D003

D004

图 3. Non-switching Supply Current - LDO Enabled and

图 4. Non-switching Supply Current - LDO Disabled and

Buck Disabled vs Temperature

Buck Enabled vs Temperature

1.21

-1

EN Rising

EN Falling

1.205

1.2

-1.5

-2

-2.5

-3

1.195

1.19

1.185

1.18

V_(EN)= Threshold - 50 mV

V_(EN)= Threshold + 50 mV

-3.5

-4

1.175

1.17

1.165

1.16

-4.5

-5

-50

-25

100

125

150

-50

-25

100

125

150

Junction Temperature (èC)

D005

Junction Temperature (èC)

D006

图 5. ENSW and ENLDO Voltage Threshold vs Temperature

图 6. ENSW and ENLDO Individual Input Current vs

Temperature

TPS54116-Q1

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ZHCSFG9A –AUGUST 2016–REVISED AUGUST 2016

Typical Characteristics (接下页)

0.606

0.605

0.604

0.603

0.602

0.601

0.6

-2

-3

-4

-5

V_(EN)= Threshold - 50 mV

V_(EN)= Threshold + 50 mV

-6

0.599

0.598

0.597

0.596

0.595

0.594

-7

-8

-9

-10

-50

-25

100

125

150

-50

-25

100

125

150

Junction Temperature (èC)

D008

D007

图 8. Voltage Reference vs Temperature

图 7. ENSW and ENLDO Parallel Input Current vs

Temperature

320

300

280

260

240

220

200

High-side, V_(BOOT-SW)= 3.3 V

High-side, V_(BOOT-SW)= 5 V

Low-side, V_(PVIN)= 3.3 V

Low-side, V_(PVIN)= 5 V

-50

-25

100

125

150

-50

-25

100

125

150

Junction Temperature (èC)

D009

D010

图 9. Error Amplifier Transconductance vs Temperature

图 10. MOSFET R_ds(on)vs Temperature

6.5

5.5

R_(ILIM)= 100 k

R_(ILIM)= 200 k

4.5

3.5

2.5

-50

-25

100

125

150

100 110 120 130 140 150 160 170 180 190 200

R(ILIM)

Junction Temperature (èC)

D011

D012

V_(PVIN)= 5 V

图 11. High-side Current Limit vs Temperature

V_(PVIN)= 5 V

T_A= 25°C

图 12. High-side Current Limit vs R_ILIM

TPS54116-Q1

ZHCSFG9A –AUGUST 2016–REVISED AUGUST 2016

www.ti.com.cn

Typical Characteristics (接下页)

140

130

120

110

100

V_IN= 3.3 V, I_OUT= 0 A

V_IN= 5 V, I_OUT= 0 A

V_IN= 3.3 V, I_OUT= 2 A

V_IN= 5 V, I_OUT= 2 A

V_IN= 3.3 V

V_IN= 5 V

-50

-25

100

125

150

-50

-25

100

125

Ambient Temperature (èC)

D013

D014

图 13. V_(COMP)to I_(SW)Transconductance vs Temperature

图 14. Minimum Pulse-width vs Temperature

100

650

600

550

500

450

400

350

300

250

200

150

100

V_IN= 3.3 V

V_IN= 5 V

0.5

1.5

2.5

3.5

100 150 200 250 300 350 400 450 500 550 600 650

IOUT (A)

R_(RT/SYNC)(kW)

D015

D016

T_A= 25°C

图 15. Minimum pulse-width vs Load Current

图 16. Switching Frequency vs R_(RT/SYNC)Low Range

2800

2600

2400

2200

2000

1800

1600

1400

1200

1000

800

410

408

406

404

402

400

398

396

394

392

390

600

100

-50

-25

100

125

150

R_(RT/SYNC)(kW)

Junction Temperature (èC)

D017

D018

T_A= 25°C

R_(RT/SYNC)= 150 kΩ

图 18. Switching Frequency vs Temperature

图 17. Switching Frequency vs R_(RT/SYNC)High Range

TPS54116-Q1

www.ti.com.cn

ZHCSFG9A –AUGUST 2016–REVISED AUGUST 2016

Typical Characteristics (接下页)

2080

2078

2076

2074

2072

2070

2068

2066

2064

2062

2060

430

425

420

415

410

405

400

-50

-25

100

125

150

-50

-25

100

125

150

Junction Temperature (èC)

D019

D020

R_(RT/SYNC)= 27 kΩ

图 19. Switching Frequency vs Temperature

Internal RT

图 20. Switching Frequency vs Temperature

54.5

2.5

2.48

2.46

2.44

2.42

2.4

53.5

52.5

2.38

2.36

2.34

51.5

-50

-25

100

125

150

-50

-25

100

125

150

Junction Temperature (èC)

D021

D022

V_(SS/TRK)< V_SS(THR)

V_(SS/TRK)> V_SS(THR)

图 21. I_(SS/TRK)vs Temperature

图 22. I_(SS/TRK)vs Temperature

110

108

106

104

102

100

0.65

0.6

0.55

0.5

0.45

0.4

V_(FB)falling (fault)

V_(FB)rising (good)

V_(FB)rising (fault)

0.35

0.3

V_(FB)falling (good)

0.25

0.2

0.15

0.1

0.05

0.2

0.4

0.6

0.8

1.2

1.4

1.6

1.8

-50

-25

100

125

150

V_(SS/TRK)(V)

Junction Temperature (èC)

D023

D024

T_A= 25°C

图 23. V_(FB)vs V_(SS/TRK)

图 24. PGOOD Thresholds vs Temperature

TPS54116-Q1

ZHCSFG9A –AUGUST 2016–REVISED AUGUST 2016

www.ti.com.cn

Typical Characteristics (接下页)

T_A= -40 C

T_A= 25 C

T_A= 125 C

T_A= -40 C

T_A= 25 C

T_A= 125 C

-2

-4

-6

-8

-10

-2

-4

-6

-8

-10

-8

-6

-4

-2

-10

-8

-6

-4

-2

VTTREF Current (mA)

D026

VDDQSNS = 1.8 V

V_IN= 5 V

VDDQSNS = 1.5 V

V_IN= 5 V

图 25. VTTREF Regulation to VDDQSNS/2 vs I_(VTTREF)

图 26. VTTREF Regulation to VDDQSNS/2 vs I_(VTTREF)

T_A= -40 C

T_A= 25 C

T_A= 125 C

T_A= -40 C

T_A= 25 C

T_A= 125 C

-2

-4

-6

-8

-10

-2

-4

-6

-8

-10

-8

-6

-4

-2

-10

-8

-6

-4

-2

VTTREF Current (mA)

D026

VDDQSNS = 1.35

V_IN= 5 V

VDDQSNS = 1.2 V

V_IN= 5 V

图 28. VTTREF Regulation to VDDQSNS/2 vs I_(VTTREF)

图 27. VTTREF Regulation to VDDQSNS/2 vs I_(VTTREF)

T_A= -40 C

T_A= 25 C

T_A= 125 C

T_A= -40 C

T_A= 25 C

T_A= 125 C

-5

-10

-15

-20

-25

-10

-15

-20

-25

-1.5 -1.2 -0.9 -0.6 -0.3

0.3 0.6 0.9 1.2 1.5

-1.5 -1.2 -0.9 -0.6 -0.3

0.3 0.6 0.9 1.2 1.5

VTT Current (A)

D030

VDDQSNS = 1.8 V

V_IN= 5 V

VDDQSNS = 1.5 V

V_IN= 5 V

图 29. VTT Regulation to VTTREF vs I_(VTT)

图 30. VTT Regulation to VTTREF vs I_(VTT)

TPS54116-Q1

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ZHCSFG9A –AUGUST 2016–REVISED AUGUST 2016

Typical Characteristics (接下页)

T_A= -40 C

T_A= 25 C

T_A= 125 C

T_A= -40 C

T_A= 25 C

T_A= 125 C

-5

-10

-15

-20

-25

-10

-15

-20

-25

-1.5 -1.2 -0.9 -0.6 -0.3

0.3 0.6 0.9 1.2 1.5

-1.5 -1.2 -0.9 -0.6 -0.3

0.3 0.6 0.9 1.2 1.5

VTT Current (A)

D030

VDDQSNS = 1.35

V_IN= 5 V

VDDQSNS = 1.2 V

V_IN= 5 V

图 32. VTT Regulation to VTTREF vs I_(VTT)

图 31. VTT Regulation to VTTREF vs I_(VTT)

0.6

0.55

0.5

200

T_A= -40 C

T_A= 25 C

T_A= 125 C

Gain

Phase

150

100

0.45

0.4

0.35

0.3

0.25

0.2

0.15

0.1

-10

-50

0.05

-20

-100

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

IVTT Sourcing Transient (A)

10000

100000

1000000

1E+7

Frequency (Hz)

D034

D035

VDDQSNS = 1.5 V

V_IN= 5 V

V_(VTT)= 1.5 V

T_A= 25°C

V_IN= 5 V

I_(VTT)= +1 A

图 33. VTT Dropout

图 34. VTT Sourcing Frequency Response

100

200

Gain

Phase

150

100

V_DDQ= 1.8 V

V_DDQ= 1.5 V

V_DDQ= 1.35 V

V_DDQ= 1.2 V

-10

-50

-20

-100

10000

100000

1000000

1E+7

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

Frequency (Hz)

Output Current (A)

D036

D044

V_(VTT)= 1.5 V

T_A= 25°C

V_IN= 5 V

I_(VTT)= –1 A

f_SYNC= 2.1 MHz

T_A= 25°C

V_IN= 3.3 V

L = 744373240068

图 35. VTT Sinking Frequency Response

图 36. Efficiency

TPS54116-Q1

ZHCSFG9A –AUGUST 2016–REVISED AUGUST 2016

www.ti.com.cn

Typical Characteristics (接下页)

100

V_DDQ= 1.8 V

V_DDQ= 1.5 V

V_DDQ= 1.35 V

V_DDQ= 1.2 V

V_DDQ= 1.8 V

V_DDQ= 1.5 V

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

Output Current (A)

D045

D046

f_SYNC= 2.1 MHz

T_A= 25°C

V_IN= 5 V

L = 744373240068

f_SYNC= 400 kHz

T_A= 25°C

V_IN= 3.3 V

L = 744310200

图 37. Efficiency

图 38. Efficiency

100

V_DDQ= 1.8 V

V_DDQ= 1.5 V

V_DDQ= 1.35 V

V_DDQ= 1.2 V

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

Output Current (A)

D047

f_SYNC= 400 kHz

T_A= 25°C

V_IN= 5 V

L = 744310200

图 39. Efficiency

TPS54116-Q1

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ZHCSFG9A –AUGUST 2016–REVISED AUGUST 2016

7 Detailed Description

7.1 Overview

The TPS54116-Q1 is a 6-V, 4-A, synchronous step-down (buck) converter with two integrated N-channel

MOSFETs and integrated 1-A sink/source double data rate (DDR) VTT termination regulator with a VTTREF

buffed reference output.

To improve the performance during line and load transients the buck converter implements a constant frequency,

peak current mode control which reduces output capacitance and simplifies external frequency compensation

design. The wide switching frequency range of 100 kHz to 2500 kHz allows for efficiency and size optimization

when selecting the output filter components. The switching frequency is adjusted using a resistor to ground on

the RT/SYNC pin. The RT/SYNC pin can also be used to synchronize the power switch turn on to the rising edge

of an external clock. The switching frequency can be set using an internal resistor by pulling the RT/SYNC below

the low threshold or above the high threshold.

The TPS54116-Q1 has a typical default start-up voltage of 2.7 V. The ENSW pin can be used to enable the buck

converter and the ENLDO pin can be used to enable VTT and VTTREF. The ENSW and ENLDO pins have

internal pullup current sources that can be used to adjust the input voltage under voltage lockout (UVLO) with

two external resistors. In addition, the pullup current provides a default condition when the ENSW or ENLDO pin

is floating for the device to operate. The total operating current for the TPS54116-Q1 is typically 650 µA when

not switching and under no load. When the device is disabled, the supply current is less than 3.5 µA.

The integrated 33-mΩ and 25-mΩ MOSFETs allow for high-efficiency power supply designs with continuous

output currents up to 4 amperes. The TPS54116-Q1 reduces the external component count by integrating the

boot recharge diode. The bias voltage for the integrated high-side MOSFET is supplied by a capacitor between

the BOOT and SW pins. The boot capacitor voltage is monitored by an UVLO circuit and turns off the high-side

MOSFET when the voltage falls below the BOOT-SW UVLO threshold. This BOOT circuit allows the TPS54116-

Q1 to operate approaching 100% duty cycle. The output voltage can be stepped down to as low as the 0.60-V

reference.

The TPS54116-Q1 features monotonic start-up under prebias conditions. The low-side FET turns on for a short

time period every cycle before the output voltage reaches the prebiased voltage. This ensures the boot capacitor

has enough charge to turn on the top FET when the output voltage reaches the prebiased voltage.

The TPS54116-Q1 has a power good comparator (PGOOD) with 3% hysteresis. Excessive output overvoltage

transients are minimized by taking advantage of the overvoltage power good comparator. When the regulated

output voltage (as sensed by the FB voltage) is greater than 109% of the nominal voltage, the overvoltage

comparator is activated, and the high-side MOSFET is turned off and masked from turning on until the output

voltage is lower than 106%.

The SS/TRK (soft-start or tracking) pin is used to minimize inrush currents or provide power supply sequencing

during power up. A small value capacitor should be coupled to the pin for soft-start. The SS/TRK pin is

discharged before the output power up to ensure a repeatable restart after an over temperature fault, UVLO fault

or disabled condition. To optimize the output startup waveform, two levels of SS/TRK output current are

implemented.

The TPS54116-Q1 limits the peak inductor current by sensing the current through the high-side MOSFET with

cycle-by-cycle protection. The peak current limit is adjusted using a resistor to ground on the ILIM pin. The

reverse current through the low-side MOSFET is also limited.

The 10-mA VTTREF buffered reference uses an internal resistor divider to regulate its output within 49% to 51%

of VDDQSNS. The 1-A VTT termination regulates to VTTREF and maintains fast transient response with only 2 ×

10-µF ceramic output capacitance. Remote sensing of VTT is used for best regulation. The VTT and VTTREF

outputs are discharged when disabled with the AVIN UVLO or with ENLDO.

TPS54116-Q1

ZHCSFG9A –AUGUST 2016–REVISED AUGUST 2016

www.ti.com.cn

7.2 Functional Block Diagram

PGOOD

AVIN

PVIN

UVLO

Comparator

AGND

Vref_UV

BOOT

Charge

Voltage

Reference

Vref_OV

BOOT

UVLO

Current

Sense

OVLO

Comparator

Error

Amplifier

BOOT

PWM

Comparator

PWM Latch

SS/TRK

Logic

Enable

Switcher

ENSW

COMP

Slope

Compensation

Current

Sense

Maximum

Clamp

Current

Limit

ILIM

Reference

ILIM

Current

Limit

Oscillator

with

PGND

RT/SYNC

SYNC

VLDOIN

VDDQSNS

VTTREF

Shutdown

VTT

VTTSNS

ENLDO

Shutdown

Enable LDO

VTTGND

PAD

TPS54116-Q1

www.ti.com.cn

ZHCSFG9A –AUGUST 2016–REVISED AUGUST 2016

7.3 Feature Description

7.3.1 Fixed Frequency PWM Control

The TPS54116-Q1 uses an adjustable fixed frequency, peak current mode control. The output voltage is

compared through external resistors on the FB pin to an internal voltage reference by an error amplifier which

drives the COMP pin. An internal oscillator initiates the turn on of the high-side power switch. The error amplifier

output is compared to the high-side power switch current. When the power switch current reaches the COMP

signal level the high-side power switch is turned off and the low-side power switch is turned on. The COMP pin

voltage will increase and decrease as the output current increases and decreases. The device implements a

current limit by clamping the internal COMP signal.

An internal ramp is used to provide slope compensation to prevent sub-harmonic oscillations. The peak inductor

current limit is constant over the full duty cycle range.

7.3.2 Bootstrap Voltage (BOOT) and Low Dropout Operation

The TPS54116-Q1 has an integrated boot regulator and requires a small ceramic capacitor between the BOOT

and SW pins to provide the gate drive voltage for the high-side MOSFET. The value of the ceramic capacitor

should be 0.1 µF. A ceramic capacitor with an X7R or X5R grade dielectric is recommended because of the

stable characteristics over temperature and voltage.

To improve dropout, the TPS54116-Q1 is designed to operate at 100% duty cycle as long as the BOOT-SW

voltage is greater than 2.2 V. The high-side MOSFET is turned off using an UVLO circuit, allowing for the low-

side MOSFET to conduct, when the BOOT-SW voltage drops below 2.2 V. Because the supply current sourced

from the BOOT pin is low, the high-side MOSFET can remain on for more switching cycles than are required to

refresh the capacitor, thus the effective duty of the switching regulator is high.

7.3.3 Error Amplifier

The TPS54116-Q1 has a transconductance amplifier for the error amplifier. The error amplifier compares the FB

voltage to the lower of the SS/TRK pin voltage or the internal 0.6-V voltage reference. The transconductance

(gm_EA) of the error amplifier is 260 µA/V during normal operation. During soft-start, the gm_EAis reduced to 90

µA/V. The frequency compensation components are added to the COMP pin to ground.

When operating at current limit the COMP pin voltage is clamped to a maximum level to improve response when

the load current decreases. When FB is greater than the internal voltage reference or SS/TRK the COMP pin

voltage is clamped to a minimum level and the devices enters a high-side skip mode.

7.3.4 Voltage Reference and Adjusting the Output Voltage

The voltage reference system produces a precise ±1% voltage reference over temperature by scaling the output

of a temperature stable bandgap circuit. The FB voltage is regulated to the voltage reference. The output voltage

is set with a resistor divider from the output node to the FB pin. It is recommended to use divider resistors with

1% tolerance or better. Start with a 10.0 kΩ for the bottom resistor R_FBBand use the 公式 1 to calculate R_FBT

The maximum recommend resistance value for the bottom resistor is 100 kΩ.

vertical spacer

≈

∆

’

V_OUT

V_REF

R_FBT= R_FBB

-1

◊

(1)

TPS54116-Q1

ZHCSFG9A –AUGUST 2016–REVISED AUGUST 2016

www.ti.com.cn

Feature Description (接下页)

TPS54116-Q1

V_OUT

R_FBT

0.6 V

R_FBB

图 40. Voltage Divider Circuit

7.3.5 Enable and Adjusting Undervoltage Lockout

The TPS54116-Q1 is enabled when the AVIN pin voltage exceeds 2.7 V and is disabled when it falls below 2.65

V. If an application requires a higher under-voltage lockout (UVLO) or more hysteresis, use the ENSW or ENLDO

pins as shown in 图 41 to adjust the input voltage UVLO by using two external resistors. The EN pin has an

internal pull-up current source (I_p) of 1.7 µA that provides the default condition of the TPS54116-Q1 operating

when the EN pin floats. Once the EN pin voltage exceeds 1.2 V, an additional 2.7 μA hysteresis current (I_h) is

added. When the EN pin is pulled below 1.17 V, the 2.7 μA is removed. This additional current facilitates input

voltage hysteresis. It is recommended to use the EN resistors to set the UVLO falling threshold (V_STOP) at 2.65V

or higher. The rising threshold (V_START) should be set to provide enough hysteresis to allow for any input supply

variations. 公式 2 can be used to calculate the top resistor in the EN divider and 公式 3 is used to calculate the

bottom resistor.

The ENSW and ENLDO can also be tied in parallel. Calculations can be done the same but with the increased

EN current of I_p= 3.4 µA and I_h= 5.1 µA.

TPS54116-Q1

AVIN

I_p

I_h

R_ENT

ENLDO

R_ENB

ENSW

图 41. Adjustable Under Voltage Lock Out

TPS54116-Q1

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ZHCSFG9A –AUGUST 2016–REVISED AUGUST 2016

Feature Description (接下页)

≈

∆

’

V_ENFALLING

V_START

- V

STOP

V_{ENRISING ◊}

R_ENT

≈

’

V_ENFALLING

I ì 1-

∆

V_{ENRISING ◊}

(2)

(3)

vertical spacer

R_ENB

R_ENTì V_ENFALLING

V_STOP- V_ENFALLING+ R_ENTì I +I

(

)

Where:

•

I_h= 2.7 µA

I_p= 1.7 µA

V_ENRISING= 1.2 V

V_ENFALLING= 1.17 V

7.3.6 Soft Start and Tracking

The TPS54116-Q1 regulates to the lower of the SS/TRK pin and the internal reference voltage. A capacitor on

the SS/TRK pin to ground implements a soft start time. Before the SS pin reaches the voltage threshold V_SSTHR

of 0.15 V, the charge current is about 47 μA. The TPS54116-Q1 internal pull-up current source of 2.4 μA charges

the external soft start capacitor after the SS pin voltage exceeds V_SSTHR. 公式 4 calculates the required soft start

capacitor value where t_SSis the desired soft start time for the output voltage to reach 90% its final value in ms

and C_SSis the required capacitance in nF.

vertical spacer

C_SSnF = 5.3ì t

(

)

(

)

(4)

If during normal operation, AVIN goes below the UVLO, ENSW pin pulled below 1.17 V, or a thermal shutdown

event occurs, the TPS54116-Q1 stops switching. When the AVIN goes above UVLO, ENSW is released or pulled

high, or a thermal shutdown is exited, then SS/TRK is discharged to below 5 mV before reinitiating a powering up

sequence. The FB voltage will follow the SS/TRK pin voltage with a 60 mV offset up to 90% of the internal

voltage reference. When the SS/TRK voltage is greater than 90% of the internal reference voltage the offset

increases as the effective system reference transitions from the SS/TRK voltage to the internal voltage reference.

When the COMP pin voltage is clamped by the maximum COMP clamp in an overload condition the soft-start pin

is discharged to near the FB voltage. When the overload condition is removed, the soft-start circuit controls the

recovery from the fault output level to the nominal regulation voltage. At the beginning of recovery a spike in the

output voltage may occur as the COMP voltage transitions to the value determined by the loop.

7.3.7 Start-up into Pre-Biased Output

The TPS54116-Q1 features monotonic startup into pre-biased output. The low-side MOSFET turns on for a very

short time period every cycle before the output voltage reaches the pre-biased voltage. This ensures the BOOT-

SW cap has enough charge to turn on the high-side MOSFET when the output voltage reaches the pre-biased

voltage. The low-side MOSFET reverse current protection provides another layer of protection but it should not

be reached due to the implemented prebias function.

7.3.8 Power Good

The PGOOD pin is an open-drain output requiring an external pullup resistor to output a high signal. Once the FB

pin is between 94% and 106% of the internal voltage reference, the PGOOD pin is de-asserted and the pin

floats. A pull up resistor between the values of 10 kΩ and 100 kΩ to a voltage source that is 6 V or less is

recommended. The PGOOD is in a defined state once the AVIN input voltage is greater than 1.3 V but with

reduced current sinking capability.

The PGOOD pin is pulled low when the FB is lower than 91% or greater than 109% of the nominal internal

reference voltage. The PGOOD is also pulled low if AVIN falls below its UVLO, ENSW pin is pulled low or the

TPS54116-Q1 enters thermal shutdown.

TPS54116-Q1

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www.ti.com.cn

Feature Description (接下页)

7.3.9 Sequencing

Many of the common power supply sequencing methods can be implemented using the SS/TRK, ENSW and

PGOOD pins. The sequential method can be implemented using an open-drain or collector output of a power on

reset pin of another device. An example sequential method is shown in 图 42. PGOOD is connected to the EN

pin on the next power supply, which will enable the second power supply once the first supply reaches

regulation.

TPS54116-Q1

PGOOD

2nd DC/DC

ENSW

PGOOD

SS/TRK

C_SS

图 42. Sequential Startup Example

7.3.10 Constant Switching Frequency and Timing Resistor (RT/SYNC)

The switching frequency of the TPS54116-Q1 is adjustable over a wide range from 100 kHz to 2500 kHz by

placing a maximum of 620 kΩ and minimum of 22 kΩ, respectively, on the RT/SYNC pin. Alternatively the

RT/SYNC pin can be tied above the high threshold or below the low threshold to use an internal RT resistor to

set the switching frequency to 420 kHz. The RT/SYNC is typically 0.5 V and the current through the resistor sets

the switching frequency. To determine the timing resistance for a given switching frequency, refer to the curve in

图 16 and 图 17 or use 公式 5. For a given RT resistor the nominal switching frequency can be calculated with 公

式 6. To reduce the solution size one would typically set the switching frequency as high as possible, but

tradeoffs of the supply efficiency, maximum input voltage and minimum controllable on time should be

considered. The minimum controllable on time is typically 60 ns at 2-A load current and 100 ns at no load, and

will limit the maximum operating input voltage or minimum output voltage.

72540

R_TkW =

(

)

1.033

f_SWkHz

(

)

(5)

50740

f_SWkHz =

(

)

0.968

)

R_TkW

(

(6)

The RT/SYNC pin can also be used to synchronize the converter to an external system clock. When using the

internal RT resistor, the TPS54116-Q1 cannot be synchronized to an external clock. The synchronization

frequency range is 100 kHz to 2500 kHz. The rising edge of SW will be synchronized to the rising edge of

RT/SYNC. To implement the synchronization feature in a system connect a square wave to the RT/SYNC pin

with on-time at least 10 ns. The square wave amplitude at this pin must transition lower than 0.35 V and higher

than 2.2 V.

See 图 43 for synchronizing to a high impedance system clock. See 图 44 and 图 45 for synchronizing to a low

impedance system clock. A tri-state buffer with its output directly connected to the RT/SYNC pin is the

recommended method to accomodate a wide range of external clock frequencies and duty cycles. Alternatively

an AC blocking capacitor circuit can be used when synchronizing to frequencies greater than 800 kHz and with

clock signals with duty cycle near 50%. When using an AC coupling capacitor to interface with an external clock,

RT/SYNC is not actively pulled low by the external clock. As a result the TPS54116-Q1 begins its transition back

to RT mode while the external clock is low. When connecting the RT/SYNC pin to the external clock source, it is

important to minimize routing connected to the RT/SYNC pin as much as possible to minimize noise sensitivity

when operating in RT mode.

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Feature Description (接下页)

TPS54116-Q1

RT/SYNC

R_RT

Oscillator

图 43. Synchronizing to a High Impedance System Clock

TPS54116-Q1

RT/SYNC

R_RT

Oscillator

图 44. Interfacing to the RT/SYNC Pin with Buffer

TPS54116-Q1

RT/SYNC

Oscillator

1 kꢀ

22 pF

R_RT

图 45. Interfacing to the RT/SYNC Pin with RC

TPS54116-Q1

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Feature Description (接下页)

7.3.11 Buck Overcurrent Protection

The TPS54116-Q1 implements current mode control which uses the COMP pin voltage to turn off the high-side

MOSFET and turn on the low-side MOSFET on a cycle-by-cycle basis. Each cycle the switch current and the

COMP pin voltage are compared, when the peak switch current intersects the COMP voltage the high-side

switch is turned off. During overcurrent conditions that pull the output voltage low, the error amplifier will respond

by driving the COMP pin high, increasing the switch current. The error amplifier output is clamped internally. This

clamp functions as a high-side switch current limit.

A resistor placed from ILIM to AGND sets the peak current limit of the buck converter in the TPS54116-Q1. A

100 kΩ resistor sets it to the maximum value and a 200 kΩ resistor sets it to the minimum value. Any resistor

within this range can be used. 图 12 shows the relationship between peak current limit and ILIM resistor. To

determine the resistor value for a target current limit use 公式 7.

vertical spacer

-0.75

R_ILIM= 420ìI

limit

(7)

The TPS54116-Q1 also implements low-side current protection by detecting the voltage over the low-side

MOSFET. When the converter sinks current through the low-side MOSFET is more than 4.5 A, the control circuit

will turn the low-side MOSFET off immediately for the rest of the clock cycle. Under this condition, both the high-

side and low-side are off until the start of the next cycle.

7.3.12 Overvoltage Transient Protection

The TPS54116-Q1 incorporates an overvoltage transient protection (OVTP) circuit to minimize voltage overshoot

when recovering from output fault conditions or strong unload transients. The OVTP feature minimizes the output

overshoot by implementing a circuit to compare the FB pin voltage to OVTP threshold which is 109% of the

internal voltage reference. If the FB pin voltage is greater than the OVTP threshold, the high-side MOSFET is

disabled preventing current from flowing to the output and minimizing output overshoot. The output voltage can

overshoot the 109% threshold as the current in the inductor discharges to 0 A. When the FB voltage drops lower

than the OVTP threshold the high-side MOSFET is allowed to turn on the next clock cycle.

7.3.13 VTT Sink and Source Regulator

The TPS54116-Q1 integrates a high-performance, low-dropout (LDO) linear regulator (VTT) that has ultimate fast

response to track ½ VDDQSNS within 40 mV at all conditions, and its current capability is 1.5 A peak current for

both sink and source directions. Two 10-µF (or greater) ceramic capacitor(s) need to be attached close to the

VTT pin for stable operation. X5R grade or better is recommended. To achieve tight regulation with minimum

effect of trace resistance, the remote sensing terminal, VTTSNS, should be connected to the positive terminal of

the output capacitor(s) as a separate trace from the high current path from the VTT pin.

The device has a dedicated pin, VLDOIN, for VTT power supply to minimize the LDO power dissipation on user

application. The minimum VLDOIN voltage is 0.45 V above the ½ VDDQSNS voltage.

7.3.14 VTTREF

The VTTREF pin has a 10 mA sink and source current capability, and regulates to within 49% to 51% of

VDDQSNS. A 0.22-µF ceramic capacitor needs to be attached close to the VTTREF terminal for stable

operation. X5R grade or better is recommended.

7.3.15 Thermal Shutdown

The device implements an internal thermal shutdown to protect itself if the junction temperature exceeds 175°C.

The thermal shutdown has a hysteresis of 16°C. When the junction temperature exceeds thermal trip threshold,

thermal shutdown forces the device to stop switching and discharges both VTT and VTTREF. When the die

temperature decreases below 159°C, the device reinitiates the power-up sequence by discharging the SS/TRK

pin.

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7.4 Device Functional Modes

The enable pins and an AVIN UVLO are used to control turn on and turn off of the TPS54116-Q1. The device

becomes active when V_(AVIN)exceeds the 2.7 V typical UVLO and when either V_(ENSW)or V_(ENLDO)exceeds 1.20

V typical. The ENSW pin is used to control the turn on and turn off of the buck converter. The ENLDO pin is used

to control the turn on and turn off of the VTTREF and VTT outputs of the termination regulator. The ENSW and

ENLDO pins both have an internal current source to enable their respective outputs when left floating. Both

ENSW and ENLDO need to be pulled low to put the device into a low quiescent current state.

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8 Application and Implementation

注

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

The TPS54116-Q1 is a fully integrated power solution for DDR2, DDR3 and DDR3L memory supplying VDDQ,

VTTREF and VTT as shown in 图 46. It can also be used to power LPDDR2, LPDDR3 and DDR4 memory but an

additional power supply is required for VDD1 or VPP as shown in 图 47. The TPS54116-Q1 can supply 4 A for

VDDQ and 1 A for VTT. The sourcing current for VTT comes from VDDQ and must be included as part of the

total VDDQ load current. Use the following design procedure to select component values for the TPS54116-Q1.

This procedure illustrates the design of a high-frequency switching regulator using ceramic output capacitors.

Alternatively the WEBENCH® software can be used to generate a complete design. The WEBENCH® software

uses an interactive design procedure and accesses a comprehensive database of components when generating

a design. This section presents a simplified discussion of the design process.

VDDQ

5.0 V or 3.3 V

TPS54116-Q1

VTTREF

VTT

图 46. DDR2, DDR3 and DDR3L Application Block Diagram

VDDQ

5.0 V or 3.3 V

TPS54116-Q1

VTTREF

VTT

TPS57112-Q1

or other DC/DC

VPP or

VDD1

图 47. LPDDR2, LPDDR3 and DDR4 Application Block Diagram

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8.2 Typical Application

VIN

VDDQ

L1 680nH

R14

15.0k

C17

180pF

47µF

0.1µF

10µF

1µF

10µF

C12

47µF

C13

47µF

C14

47µF

45.3k

C10

0.1µF

R15

10.0k

TPS54116QRTWRQ1

AVIN

BOOT

PVIN

30.1k

LDOIN

ENSW

ENLDO

PGOOD

ILIM

VDDQSNS

VTT

VTTSNS

VTTREF

AGND

C15

10µF

C16

10µF

100k

VTTREF

C11

0.22µF

SS/TRK

COMP

PGND

100k

3300pF

VTTGND

PAD

20.5k

NT1

RT/SYNC

Net-Tie

180pF

1800pF

OSC IN

AGND

PGND

1.00k

26.7k

22pF

图 48. 3.3-V or 5-V Input, 2.1 MHz fsw, DDR3 Schematic

8.2.1 Design Requirements

表 1. Design Parameters

DESIGN PARAMETERS

EXAMPLE VALUES

Input Voltage

5 V nominal, 2.95 V to 5.25 V

Output Voltage

1.5 V

4 A

Maximum Output Current (VDDQ)

Maximum Output Current (VTT)

Output Voltage Ripple (VDDQ)

Transient Response 1 A to 3 A load step

Start Input Voltage (rising VIN)

Stop Input Voltage (falling VIN)

1 A

0.5% of V_OUT

ΔV_OUT= 4 %

2.9 V

2.6 V

8.2.2 Detailed Design Procedure

8.2.2.1 Switching Frequency

The first step is to decide on a switching frequency for the regulator. The buck converter is capable of running

from 100 kHz to 2.5 MHz. Typically the highest switching frequency possible is desired because it will produce

the smallest solution size. A high switching frequency allows for lower valued inductors and smaller output

capacitors compared to a power supply that switches at a lower frequency. Additionally in applications with EMI

requirements, such as automotive, choosing a switching frequency of 2.1 MHz is desired to keep the switching

noise above the medium wave band or AM band. They main trade off made with selecting a higher switching

frequency is extra switching power loss, which hurt the converter’s efficiency.

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The maximum switching frequency for a given application is limited by the minimum on-time of the converter and

is estimated with 公式 8. For this application with the maximum minimum on-time of 125 ns at no load and 5.25 V

maximum input voltage the maximum switching frequency is 2.28 MHz. A switching frequency of 2.1 MHz is

selected to stay above the AM band. 公式 9 calculates R14 to be 26.8 kΩ. A standard 1% 26.7 kΩ value was

chosen in the design.

V_OUT

V max

f_SWmax =

(

)

tonmin

(

)

(8)

(9)

72540

R_TkW =

(

)

1.033

f_SWkHz

(

)

8.2.2.2 Output Inductor Selection

To calculate the value of the output inductor, use 公式 10. K_INDis a ratio that represents the amount of inductor

ripple current relative to the maximum output current. The inductor ripple current is filtered by the output

capacitor. Therefore, choosing high inductor ripple currents impacts the selection of the output capacitor since

the output capacitor must have a ripple current rating equal to or greater than the inductor ripple current.

Additionally the inductor current ripple is used as part of the PWM control system. Choosing small inductor ripple

currents can degrade the transient response performance or introduce jitter in the duty cycle. In general, the

inductor ripple value is at the discretion of the designer; however, K_INDis normally from 0.1 to 0.3 for the majority

of applications giving a peak to peak ripple current range of 0.4 A to 1.2 A. It is recommended to always keep the

peak to peak ripple current above 0.4 A because with a current mode control the inductor current ramp is used in

the PWM control system.

For this design example, K_IND= 0.3 is used and the inductor value is calculated to be 0.43 μH. The next standard

value 0.68 µH is selected. It is important that the RMS current and saturation current ratings of the inductor not

be exceeded. The RMS and peak inductor current can be found from 公式 12 and 公式 13. For this design, the

RMS inductor current is 4.0 A and the peak inductor current is 4.4 A. The chosen inductor is a WE

744373240068. It has a saturation current rating of 10.0 A (20% inductance loss) and a RMS current rating of 5.5

A (40 °C. temperature rise). The series resistance is 16.0 mΩ typical.

The current flowing through the inductor is the inductor ripple current plus the output current. During power up,

faults or transient load conditions, the inductor current can increase above the calculated peak inductor current

level calculated above. In transient conditions, the inductor current can increase up to the switch current limit of

the device. For this reason, the most conservative approach is to specify an inductor with a saturation current

rating equal to or greater than the switch current limit rather than the steady-state peak inductor current.

Additionally if a hard short on the output occurs in a fault condition the peak inductor current can exceed the

current limit and may reach up to 10 A. The peak current limit in this scenario is only limited by the minimum on-

time of the TPS54116-Q1 and the parasitic DC voltage drops in the circuit. The peak current during a hard short

will vary with the switching frequency and only exceeds the current limit when using the TPS54116-Q1 with

higher switching frequencies like 2.1 MHz. To protect the inductor in a hard output short the inductor should be

rated for this current.

Vinmax - Vout

Vout

L1 =

Io ´ Kind

Vinmax ´ ¦sw

(10)

vertical spacer

Vinmax - Vout

Vout

Iripple =

Vinmax ´ ¦sw

(11)

vertical spacer

ö²

Vo ´ (Vinmax - Vo)

Vinmax ´ L1 ´ ¦sw

ILrms = Io²

(12)

vertical spacer

ILpeak = Iout +

Iripple

(13)

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8.2.2.3 Output Capacitor

There are three primary considerations for selecting the value of the output capacitor. The output capacitor

determines the modulator pole, the output voltage ripple, and how the regulator responds to a large change in

load current. The output capacitance needs to be selected based on the more stringent of these three criteria.

The desired response to a large change in the load current is the first criteria and is often the most stringent. The

output capacitor needs to supply the increased load current until the regulator responds to the load step. The

regulator does not respond immediately to a large, fast increase in the load current such as transitioning from no

load to a full load. The regulator usually needs two or more clock cycles for the control loop to sense the change

in output voltage and adjust the peak switch current in response to the higher load. The output capacitance must

be large enough to supply the difference in current for 2 clock cycles to maintain the output voltage within the

specified range. At higher switching frequencies the fastest response time is about 4 µs. 公式 14 shows the

minimum output capacitance necessary, where ΔI_OUTis the change in output current, tresponse is the regulators

response time and ΔV_OUTis the allowable change in the output voltage. The minimum of 2/fsw or 4 µs should be

used for the response time in the output capacitance calculation. It is important to realize the response to a

transient load also depends on the loop compensation and slew rate of the transient load. This calculation

assumes the loop compensation is designed for the output filter with the equations later on in this procedure.

For this example, the transient load response is specified as a 4% change in VOUT for a load step of 2 A.

Therefore, ΔI_OUTis 2 A and ΔV_OUT= 0.04 × 1.5 = 60 mV. Using these numbers with a 4 µs response time gives a

minimum capacitance of 133 μF. This value does not take the ESR of the output capacitor into account in the

output voltage change. For ceramic capacitors, the ESR is usually small enough to be ignored. Aluminum

electrolytic and tantalum capacitors have higher ESR that must be considered for load step response.

公式 15 calculates the minimum output capacitance needed to meet the output voltage ripple specification.

Where fsw is the switching frequency, Vripple is the maximum allowable output voltage ripple, and Iripple is the

inductor ripple current. In this case, the maximum output voltage ripple is 7.5 mV. Under this requirement, 公式

15 yields 6.3 µF.

vertical spacer

DIout

DVout

Co > t_response

(14)

vertical spacer

Co >

Voripple

Iripple

8 ´ ¦sw

Where:

•

ΔI_OUTis the change in output current

fsw is the regulators switching frequency

ΔV_OUTis the allowable change in the output voltage

(15)

vertical spacer

公式 16 calculates the maximum combined ESR the output capacitors can have to meet the output voltage ripple

specification and this shows the ESR should be less than 10 mΩ. In this case ceramic capacitors will be used

and the combined ESR of the ceramic capacitors in parallel is much less than 10 mΩ. Capacitors also generally

have limits to the amount of ripple current they can handle without failing or producing excess heat. An output

capacitor that can support the inductor ripple current must be specified. Some capacitor data sheets specify the

RMS (Root Mean Square) value of the maximum ripple current. 公式 17 can be used to calculate the RMS ripple

current the output capacitor needs to support. For this application, 公式 17 yields 220 mA. Ceramic capacitors

used in this design will have a ripple current rating much higher than 220 mA.

Voripple

Resr <

Iripple

(16)

vertical spacer

Vout ´ (Vinmax - Vout)

Icorms =

12 ´ Vinmax ´ L1 ´ ¦sw

(17)

TPS54116-Q1

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www.ti.com.cn

The value of a ceramic capacitor varies significantly over temperature and the amount of DC bias applied to the

capacitor. The capacitance variations due to temperature can be minimized by selecting a dielectric material that

is stable over temperature. X5R and X7R ceramic dielectrics are usually selected for power regulator capacitors

because they have a high capacitance to volume ratio and are fairly stable over temperature. The output

capacitor must also be selected with the DC bias taken into account. The capacitance value of a capacitor

decreases as the DC bias across a capacitor increases. For this application example, three 47 μF 10 V 1210

X7R ceramic capacitors each with 8 mΩ of ESR at the fsw are used. The estimated capacitance after derating

shown on the capcaitor manufacturer's website with 1.5 V DC bias is 51.4 µF each. With 3 parallel capacitors the

total output capacitance is 154 µF and the ESR is 2.7 mΩ.

8.2.2.4 Input Capacitor

The TPS54116-Q1 requires a high quality ceramic, type X5R or X7R, input decoupling capacitor of at least 10 μF

of effective capacitance placed across the PVIN and PGND pins and in some applications a bulk capacitance.

The effective capacitance includes any DC bias effects. The voltage rating of the input capacitor must be greater

than the maximum input voltage. The capacitor must also have a ripple current rating greater than the maximum

RMS input current of the TPS54116-Q1. The RMS input current can be calculated using 公式 18. An input

decoupling capacitor of 1 µF must also be placed at the AVIN pin to ensure a stable input voltage to the internal

control circuits.

For this example design, a ceramic capacitor with at least a 10 V voltage rating is required to support the

maximum input voltage. For this example, one 47 µF 1210 X7R, one 10 µF 0603 X7R and one 0.1 μF 0603 X7R

10 V capacitors in parallel have been selected for the PVIN to PGND pins. Additionally one 1 µF 0603 X5R 10 V

capacitor is selected for the AVIN pin. The 0.1 µF at the PVIN pin is used to better bypass the higher frequency

content when the high-side MOSFET switches on and off. Based on the capacitor manufacturer's website, the

total input capacitance derates to 34 µF at the nominal input voltage of 5 V. The input capacitance value

determines the input ripple voltage of the regulator. The input voltage ripple can be calculated using 公式 19.

Using the design example values, Ioutmax = 4 A, Cin = 34 μF, f_SW= 2.1 MHz, yields an input voltage ripple of 14

mV and a rms input ripple current of 1.9 A.

Vinmin - Vout

(

)

Vout

Icirms = Iout ´

Vinmin

(18)

(19)

vertical spacer

Ioutmax ´ 0.25

Cin ´ ¦sw

DVin =

8.2.2.5 Soft Start Capacitor

The soft-start capacitor determines the minimum amount of time it takes for the output voltage to reach its

nominal programmed value during power up. This is useful if a load requires a controlled voltage slew rate. This

is also used if the output capacitance is very large and would require large amounts of current to quickly charge

the capacitor to the output voltage level. The large currents necessary to charge the capacitor may make the

TPS54116-Q1 reach the current limit or excessive current draw from the input power supply may cause the input

voltage rail to sag. Limiting the output voltage slew rate solves both of these problems.

The soft-start capacitor value can be calculated using 公式 20. For the example circuit, the soft-start time is not

too critical since the output capacitor value of 3 x 47 µF does not require much current to charge to 1.5 V. With

the higher switching frequency used in this example a faster start-up time improves the start up behavior. Near

the beginning of the start up time when the output voltage is low the minimum on-time of the converter is too

large to regulate the output causing additional ripple on the output. A faster start-up time will reduce the time the

converter spends in this region. The example circuit is designed for a soft-start time of 0.6 ms which requires a

3300 pF capacitor.

C_SSnF = 5.3ì t

(

)

(

)

(20)

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8.2.2.6 Undervoltage Lock Out Set Point

The Undervoltage Lock Out (UVLO) can be adjusted using an external voltage divider on the ENSW and ENLDO

pin of the TPS54116. Each pin can have its own resistor divider if different thresholds are needed for the VTT

LDO and the buck converter. If only one threshold is needed only one resistor divider is needed and the pins can

be connected in parallel. If connected in parallel the pull up current and hysteresis current should be increased to

3.4 µA and 5.1 µA respectively as shown in the electrical specifications. The UVLO has two thresholds, one for

power-up when the input voltage is rising, and one for power-down or brown outs when the input voltage is

falling.

For the example design, the supply should turn on and start switching once the input voltage increases above

2.9 V (enabled). After the regulator starts switching, it should continue to do so until the input voltage falls below

2.6 V (UVLO stop). The EN pins are also connected in parallel so the higher pull up current and hysteresis

current is used. 公式 2 through 公式 3 can be used to calculate the resistance values necessary. A 45.3 kΩ

between PVIN and the EN pins (R1) and a 30.1 kΩ between the EN pins and ground (R2) are used producing a

start voltage of 2.85 V and stop voltage of 2.47 V. The 2.47 V stop voltage is below the 2.65 V AVIN UVLO so

with this application example the TPS54116-Q1 will turn off due to the AVIN UVLO.

8.2.2.7 Bootstrap Capacitor

A 0.1 μF ceramic capacitor must be connected between the BOOT and SW pins for proper operation. It is

recommended to use a ceramic capacitor with X5R or better grade dielectric. The capacitor should have 10 V or

higher voltage rating.

8.2.2.8 Power Good Pullup

A 100 kΩ resistor is used to pull up the power good signal to VIN when FB conditions are met.

8.2.2.9 ILIM Resistor

The recommended peak current limit is calculated with 公式 21 using ILpeak from 公式 13. This calculation

includes 10% margin for load transients and an additional 1.5 A for the tolerance of the peak current limit. In this

application a 100 kΩ resistor is placed from ILIM to AGND to set the peak current limit to its maximum value. For

applications requiring a different peak current limit 公式 7 is used to calculate the ILIM resistor.

vertical spacer

= ILpeak ì1.1+1.5A

limit

(21)

8.2.2.10 Output Voltage and Feedback Resistors Selection

For the example design, 10.0 kΩ was selected for R7. Using 公式 22, R5 is calculated as 15.0 kΩ which is a

standard 1% resistor.

vertical spacer

≈

∆

’

V_OUT

V_REF

R_FBT= R_FBB

-1

◊

(22)

8.2.2.11 Compensation

There are several methods used to compensate DC - DC regulators. The method presented here is easy to

calculate and ignores the effects of the slope compensation that is internal to the device. Because the slope

compensation is ignored, the actual cross-over frequency will usually be lower than the cross-over frequency

used in the calculations. This method assumes the cross-over frequency is between the modulator pole and the

ESR zero and the ESR zero is at least 10 times greater the modulator pole. This is the case when using low

ESR output capacitors. Use the WEBENCH software for more accurate loop compensation. These tools include

a more comprehensive model of the control loop.

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To get started, the modulator pole, fpmod, and the ESR zero, fz1 must be calculated using 公式 23 and 公式 24.

For Cout, use a derated value of 154 μF. Use equations 公式 25 and 公式 26, to estimate a starting point for the

crossover frequency, fco, to design the compensation. For the example design, fpmod is 2.8 kHz and fzmod is

388 kHz. 公式 25 is the geometric mean of the modulator pole and the esr zero and 公式 26 is the mean of

modulator pole and one half the switching frequency or 250 kHz, whichever is larger. For the 2.1 MHz switching

frequency application 250 kHz is used so 公式 25 yields 33 kHz and 公式 26 gives 52 kHz. Use the lower value

of 公式 25 or 公式 26 for an initial crossover frequency. Next, the compensation components are calculated. A

resistor-in-series with a capacitor is used to create a compensating zero. A capacitor in parallel to these two

components forms the compensating pole.

Ioutmax

¦p mod =

2 × p × Vout × Cout

(23)

¦z mod =

2 ´ p ´ Resr × Cout

(24)

(25)

f_co

f_pmod´ f_zmod

f_sw

f_pmod´

f_co

(26)

To determine the compensation resistor, R6, use 公式 27. Assume the power stage transconductance, gmps, is

16 A/V. The output voltage, Vo, reference voltage, VREF, and amplifier transconductance, gmea, are 1.5 V, 0.6

V and 260 μA/V, respectively. R6 is calculated to be 19 kΩ and the closest standard value 19.1 kΩ. Use 公式 28

to set the compensation zero to the modulator pole frequency. 公式 28 yields 3020 pF for compensating

capacitor C6 and the closest standard value is 3300 pF.

≈

∆

’ ≈

’

2ì pì f_COìC_OUT

V_OUT

R_COMP

÷ ∆

gm_PS

V_REFì gm_{EA ◊}

◊ «

(27)

C_COMP

2ì pìR_COMPì f_PMOD

(28)

A compensation pole is implemented using an additional capacitor C7 in parallel with the series combination of

R6 and C6. This capacitor is recommended to help filter any noise that may couple to the COMP voltage signal.

Use the larger value of 公式 29 and 公式 30 to calculate the C7, to set the compensation pole. C7 is calculated

to 21 pF or 8 pF and the closest standard value is 22 pF.

C_OUTìR_ESR

C_HF

R_COMP

(29)

C_HF

pìR_COMPì f_SW

(30)

Type III compensation is used by adding the feed forward capacitor (C17) in parallel with the upper feedback

resistor. This increases the crossover and adds phase boost above what is normally possible from Type II

compensation. It places an additional zero/pole pair. This zero and pole pair is not independent. Once the zero

location is chosen, the pole is fixed as well. The zero is placed at the intended crossover frequency by

calculating the value of C17 with 公式 31. The calculated value is 216 pF and the closest standard value is 220

pF.

C_FF

3ì pìR_FBTì f_CO

(31)

The initial compensation based on these calculations is R6 = 19.1 kΩ, C6 = 3300 pF, C7 = 22 pF and C17 = 220

pF. These values yield a stable design but after testing the real circuit these values were changed to optimize

performance. The final values used in the schematic are R6 = 20.5 kΩ, C6 = 1800 pF, C7 = 180 pF and C17 =

180 pF.

8.2.2.12 LDOIN Capacitor

Depending on the trace impedance between the LDOIN bulk power supply to the device, a transient increase of

source current is supplied mostly by the charge from the LDOIN input capacitor. Use a 10-µF (or greater) and

X5R grade (or better) ceramic capacitor to supply this transient charge.

TPS54116-Q1

www.ti.com.cn

ZHCSFG9A –AUGUST 2016–REVISED AUGUST 2016

8.2.2.13 VTTREF Capacitor

Add a ceramic capacitor, with a value 0.22 µF and X5R grade (or better), placed close to the VTTREF terminal

for stable operation.

8.2.2.14 VTT Capacitor

For stable operation, two 10-µF (or greater) and X5R (or better) grade ceramic capacitor(s) need to be attached

close to the VTT terminal. This capacitor is recommended to minimize any additional equivalent series resistance

(ESR) and/or equivalent series inductance (ESL) of ground trace between the PGND terminal and the VTT

capacitor(s).

8.2.3 Application Curves

100

0.30

0.25

0.20

0.15

0.10

0.05

0.00

-0.05

-0.10

-0.15

-0.20

-0.25

-0.30

V_IN= 5V

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

Output Current (A)

D037

D039

图 49. V_DDOutput Efficiency

图 50. V_DDOutput Load Regulation, V_IN= 5 V

180

0.25

0.20

0.15

0.10

0.05

0.00

-0.05

-0.10

-0.15

-0.20

-0.25

150

120

-10

-20

-30

-40

-50

-60

-30

-60

-90

-120

-150

-180

Gain (dB)

Phase (Deg)

100 200 500 1000

10000

Frequency (Hz)

100000

500000

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

Input Voltage (V)

D043

D041

图 52. V_DDOutput Loop Response

图 51. V_DDOutput Line Regulation, I_OUT= 2 A

TPS54116-Q1

ZHCSFG9A –AUGUST 2016–REVISED AUGUST 2016

www.ti.com.cn

EN = 2 V / div

SS= 1 V / div

EN = 2 V / div

V_TT= 1 V / div

V_DD= 1 V / div

PGOOD = 5 V / div

Time = 1 msec / div

图 53. V_DDStart-Up Relative to Enable

图 54. V_TTand V_DDStart-Up Relative to Enable

EN = 2 V / div

SS= 1 V / div

V_IN= 5 V / div

SS= 1 V / div

V_DD= 1 V / div

PGOOD = 5 V / div

Time = 1 msec / div

图 55. V_DDStart-Up Relative to V_IN

图 56. V_DDShutdown Relative to Enable

V_IN= 5 V / div

SS= 1 V / div

EN = 2 V / div

V_TT= 1 V / div

V_DD= 1 V / div

PGOOD = 5 V / div

Time = 1 msec / div

图 57. V_TTand V_DDShutdown Relative to Enable

图 58. V_DDShutdown Relative to V_IN

TPS54116-Q1

www.ti.com.cn

ZHCSFG9A –AUGUST 2016–REVISED AUGUST 2016

V_TT= 20 mV / div (ac coupled)

V_DD= 10 mV / div (ac coupled)

SW = 2 V / div

Time = 500 nsec / div

图 59. V_DDOutput Ripple

图 60. V_TTOutput Ripple

V_IN= 100 mV / div (ac coupled)

V_DD= 50 mV / div (ac coupled)

I_OUT= 1A / div

SW = 2 V / div

Load step 1 A to 3 A, slew rate 500 mA / µsec

Time = 200 µsec / div

Time = 500 nsec / div

图 61. Input Ripple

图 62. V_DDOutput Transient Response

V_TT= 20 mV / div (ac coupled)

CLK = 2 V / div

Time = 100 µsec / div

图 63. V_TTOutput Transient Response

TPS54116-Q1

ZHCSFG9A –AUGUST 2016–REVISED AUGUST 2016

www.ti.com.cn

9 Power Supply Recommendations

The TPS54116-Q1 is designed to be powered by a well regulated dc voltage between 2.95 and 6 V. The

TPS54116-Q1 is a buck converter so the input supply voltage must be greater than the desired output voltage to

regulate the output voltage to the desired value. If the input supply voltage is not high enough the output voltage

will begin to drop. Input supply current must be appropriate for the desired output current.

10 Layout

10.1 Layout Guidelines

Layout is a critical portion of good power supply design. There are several signal paths that conduct fast

changing currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise

or degrade the power supplies performance. Guidelines are as follows. See 图 64 for a PCB layout example.

•

The input bypass capacitor for PVIN to PGND should be placed as close as possible to the TPS54116-Q1

with short and wide connections to minimize parasitic inductance.

•

The input bypass capacitor for AVIN should be placed as close as possible to the TPS54116-Q1 with a short

return to the AGND pin. This capacitor and pin should also be tied to the input voltage before the PVIN

bypass capacitors to limit the switching noise from PVIN.

•

The output capacitor for VTT to VTTGND should be placed as close as possible to the TPS54116-Q1 with

short and wide connections to minimize parasitic inductance and resistance. Too much parasitic inductance

and resistance can affect the stability of the high performance VTT LDO.

The VTTSNS pin should be connected tothe VTT output capacitors as a seperate trace from the high current

VTT power trace. If sensing the voltage at the pont of the load is required, it is recommended to also attach

the output capacitors at that point while still minimizing parasitic inductance and resistance.

The input bypass capacitor for LDOIN to VTTGND should be placed as close as possible to the TPS54116-

Q1 with short and wide connections to minimize parasitic inductance. This capacitor is used to supply the

transient current to the VTT output.

•

The VDDQSNS pin should be routed as a separate trace from the high current VDDQ trace and connect near

the point of regulation for VDDQ.

The top of the FB resistor divider should be routed as a separate trace from the high current VDDQ trace and

connect near the the point of regulation for VDDQ.

The analog control circuits should have a return path to the quiet AGND and not overlap with the noisey

PGND. Sensitive pins containing analog control circuits are RT/SYNC, SS/TRK, COMP, FB, ILIM, and

VTTREF. It is important to minimize the length of the traces connected to the RT/SYNC, COMP, FB and ILIM

pins.

•

The PGND pins, AGND and VTTGND pin should be tied directly to the power pad under the IC to provide a

low impedance connection between the pins.

•

The BOOT capacitor should connect directly between the BOOT and SW pins.

The SW pin should be routed to the output inductor with a short and wide trace to minimize capacitive

coupling.

•

The thermal pad should be connected to any internal PCB ground planes using multiple vias directly under

the IC. For operation at full rated load, the top side ground area and bottom side ground area along with any

additional internal ground planes must provide adequate heat dissipating area. For best thermal performance

minimize cuts in the bottom side ground copper.

•

Additional vias can be used to connect the top side ground area to the internal planes near the input and

output capacitors for the buck converter and VTT LDO.

The additional external components can be placed approximately as shown. It may be possible to obtain

acceptable performance with alternate PCB layouts, however this layout has been shown to produce good

results and is meant as a guideline.

TPS54116-Q1

www.ti.com.cn

ZHCSFG9A –AUGUST 2016–REVISED AUGUST 2016

10.2 Layout Example

GND

VTT

LDOIN

VREF

FBT

ILIM

AGND

PGOOD

ENLDO

ENSW

AVIN

ENT

THERMAL PAD

COMP

SS/TRK

RT/ SYNC

BOOT

VOUT

COUT

GND

VIN

图 64. PCB Layout Example

TPS54116-Q1

ZHCSFG9A –AUGUST 2016–REVISED AUGUST 2016

www.ti.com.cn

11 器件和文档支持

11.1 接收文档更新通知

如需接收文档更新通知，请访问 www.ti.com.cn 网站上的器件产品文件夹。点击右上角的提醒我 (Alert me) 注册

后，即可每周定期收到已更改的产品信息。有关更改的详细信息，请查阅已修订文档中包含的修订历史记录。

11.2 社区资源

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective

contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of

Use.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help

solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and

contact information for technical support.

11.3 商标

E2E is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

11.4 静电放电警告

这些装置包含有限的内置 ESD 保护。存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损

伤。

11.5 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

12 机械、封装和可订购信息

以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对

本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏

PACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

TPS54116QRTWRQ1

TPS54116QRTWTQ1

ACTIVE

WQFN

RTW

3000 RoHS & Green

250 RoHS & Green

NIPDAU

Level-2-260C-1 YEAR

-40 to 125

54116Q

ACTIVE

RTW

NIPDAU

54116Q

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

20-Apr-2023

TAPE AND REEL INFORMATION

REEL DIMENSIONS

TAPE DIMENSIONS

Reel

Diameter

Cavity

A0 Dimension designed to accommodate the component width

B0 Dimension designed to accommodate the component length

K0 Dimension designed to accommodate the component thickness

Overall width of the carrier tape

P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2

Q3 Q4

Q1 Q2

Q3 Q4

User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TPS54116QRTWRQ1

TPS54116QRTWTQ1

WQFN

RTW

3000

250

330.0

180.0

12.4

4.25

1.15

8.0

12.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

20-Apr-2023

TAPE AND REEL BOX DIMENSIONS

Width (mm)

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

TPS54116QRTWRQ1

TPS54116QRTWTQ1

WQFN

RTW

3000

250

346.0

210.0

346.0

185.0

33.0

35.0

Pack Materials-Page 2

重要声明和免责声明

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这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验

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邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

TPS54116-Q1 [TI]

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