TPS54290_技术文档

TPS54290, TPS54291, TPS54292

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SLUS973 –OCTOBER 2009

1.5-A/2.5-A Dual, Fully-Synchronous Buck Converter With Integrated MOSFET

Check for Samples :TPS54290 TPS54291 TPS54292

1

FEATURES

APPLICATIONS

•

Set Top Box

Digital TV

Power for DSP

Consumer Electronics

2

•

4.5 V to 18 V Input Range

•

Output Voltage Range 0.8 V to D_MAX× V_IN

Fully Integrated Dual Buck, 1.5 A/2.5 A

Three Fixed Switching Frequency Versions:

–

TPS54290 – 300 kHz

TPS54291 – 600 kHz

TPS54292 – 1.2 MHz

DESCRIPTION

TPS54290/1/2 is a dual output fully synchronous buck

converter capable of supporting applications with a

minimal number of external components. It operates

from a 4.5 V to 18 V input supply voltage, and

supports output voltages as low as 0.8 V and as high

as 90% of the input voltage.

•

Integrated UVLO

0.8 V_REFWith 1% Accuracy (0°C to 85°C)

Internal Soft-Start

–

TPS54290 – 5.2 ms

TPS54291 – 2.6 ms

TPS54292 – 1.3 ms

Both high-side and low-side MOSFETs are integrated

to provide fully synchronous conversion with higher

efficiency. Channel1 can provide up to 1.5 A of

continuous current, meanwhile, Channel2 supports

up to 2.5 A.

•

Dual PWM Outputs 180° Out-of-Phase

Dedicated Enable for Each Channel

Current mode control simplifies the compensation.

The external compensation adds flexibility for the

user to choose different type of output capacitors.

Current Mode Control for Simplified

Compensation

•

External Compensation

180° out-of-phase operation reduces the ripple

current through the input capacitor, providing the

benefit of reducing input capacitance, alleviating EMI

and increasing capacitor life.

Pulse-by-Pulse Overcurrent Protection,

2.2 A/3.8 A Overcurrent Limit

•

Integrated Bootstrap Switch

Thermal Shutdown Protection at 145°C

16-Pin PowerPAD™ HTSSOP Package

V

IN

TPS54290

1

2

3

4

5

6

7

8

PVDD1 PVDD2 16

BOOT1 BOOT2 15

V

OUT2

OUT1

SW1

SW2 14

PGND1 PGND2 13

EN1

EN2

FB1

BP 12

GND 11

FB2 10

COMP1 COMP2

GND

9

UDG-09130

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2

PowerPAD is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

TPS54290, TPS54291, TPS54292

SLUS973 –OCTOBER 2009

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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

ORDERING INFORMATION

ORDERABLE

DEVICE

NUMBER

OPERATING

FREQUENCY

(kHz)

PACKING

MEDIA

PACKING

QUANTITY

T_J

PACKAGE

TPS54290PWP

TPS54290PWPR

TPS54291PWP

TPS54291PWPR

TPS54292PWP

TPS54292PWPR

Tube

Tape and Reel

Tube

90

2500

90

300

600

16-Pin

HTTSOP

–40°C to 145°C

Tape and Reel

Tube

2500

90

1200

Tape and Reel

2500

ABSOLUTE MAXIMUM RATINGS (operating in a typical application circuit)

over operating free-air temperature range, all voltages are with respect to GND (unless otherwise noted)

VALUE

UNIT

PVDD1, PVDD2, EN1, EN2

–0.3 to 20

–1 to 20

–0.3 to SW+7

–3 to 20

7

SW1, SW2

BOOT1, BOOT2

V

SW1, SW2 transient (< 50 ns)

BP

FB1, FB2

–0.3 to 3

–40 to 145

–55 to 155

260

Operating junction temperature

Storage junction temperature

°C

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds

PACKAGE DISSIPATION RATINGS^{(1) (2) (3)}

THERMAL IMPEDANCE

T_A= 25°C

POWER RATING

T_A= 85°C

POWER RATING

PACKAGE

JUNCTION TO THERMAL PAD

16 Pin HTSSOP (PWP)

2.07°/W

1.6 W

1.0 W

(1) For more information on the PWP package, refer to TI technical brief (SLMA002A)

(2) TI device packages are modeled and tested for thermal performance using PWB designs outlined in JEDEC standards JESD 51-3 and

JESD 51-7.

(3) For Application information see Power Derating section

RECOMMENDED OPERATING CONDITIONS

MIN

4.5

MAX

18

UNIT

V

V_DD

T_J

Input voltage

Junction temperature

–40

125

°C

ELECTROSTATIC DISCHARGE (ESD) PROTECTION

PARAMETER

MIN

2k

UNIT

V

Human Body Model

CDM

1.5k

V

2

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SLUS973 –OCTOBER 2009

ELECTRICAL CHARACTERISTICS

T_J= –40°C to 125°C, PVDD1 and 2 = 12V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

INPUT SUPPLY

PVDD1, PVDD2 Input voltage range

4.5

18

160

V

IDD_SDN

IDD_Q

Shutdown current

EN1=EN2 = PVDD2 (4.5-18V)

FB1 = FB2 = 1 V, Outputs Off

FB1 = FB2 = 0.75V, measured at BP

PVDD2 only

80

1.65

10

µA

mA

V

Quiescent, non-switching

Quiescent, while switching

Minimum turn-on voltage

Hysteresis

3.00

IDD_SW

UVLO

3.8

0.9

4.1

4.4

UVLO_HYS

460

600

mV

Time from startup to soft start

begin

CBP=10µF, EN1 and EN2 go low

simultaneously

(1) (2)

t_start

1.5

ms

ENABLE (ACTIVE LOW)

Enable threshold voltage

1.2

70

1.5

10

V

V _ENx

Hysteresis

mV

µA

I _ENx

Enable pull-up current

Time from enable to soft-start

begin

(1)

t _ENx

Other enable pin = GND

10

µs

BP REGULATOR

BP

Regulator voltage

Dropout voltage

8 V ≤ V_PVDD2≤ 18 V

V_PVDD2= 4.5 V

5.0

5.2

400

25

5.6

V

BP_LDO

mV

mA

I_BPS

Regulator short current

4.5 V ≤ V_PVDD2≤ 18 V

OSCILLATOR

TPS54290

260

520

300

600

360

720

kHz

f_SW

Oscillator frequency

Clock dead time

TPS54291

TPS54292

1040

1200

140

1440

kHz

ns

(1)

t_DEAD

g_MTRANSCONDUCTANCE AMPLIFIER AND VOLTAGE REFERENCE (Applies to both channels)

0°C < T_J< 85°C

792

786

800

5

808

812

50

mV

nA

µS

µA

V_FB

I_FB

Feedback input voltage

–40ºC < T_J< 125°C

V_FB=0.8 V

Feedback Input bias current

Transconductance

(1)

g_M

200

15

325

30

450

40

Error amplifier source current

capability

I_SOURCE

V_FB1=V_FB2=0.7 V, V_COMP=0 V

V_FB1=V_FB2=0.9 V, V_COMP=2 V

Error amplifier sink current

capability

I_SINK

15

30

40

µA

ms

SOFT-START (Applies to both channels)

TPS54290 0 V ≤ V_FB≤ 0.8 V

4.0

2.0

1.0

5.2

2.6

1.3

6.0

3.0

1.6

t_SS

Soft-start time

TPS54291

TPS54292

OVERCURRENT PROTECTION

I_CL1

I_CL2

Current limit CH1

Current limit CH2

1.8

3.2

2.2

3.8

30

2.6

4.6

A

TPS54290

TPS54291

TPS54292

ms

(1)

T_HICCUP

Hiccup timeout

16

8

(1)

t_ONOC

Minimum overcurrent pulse

150

200

ns

(1) Specified by design. Not tested in production.

(2) When both outputs are started simultaneously, a 20-mA current source charges the BP capacitor. Faster times are possible with a lower

BP capacitor value. See Input UVLO and Startup.

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ELECTRICAL CHARACTERISTICS (continued)

T_J= –40°C to 125°C, PVDD1 and 2 = 12V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

BOOTSTRAP (Applied to both channels)

R_BOOT

PGOOD

V_UV

Bootstrap switch resistance

R(BP to BOOT), I external = 10 mA

33

Ω

Feedback voltage limit for PGOOD

PGOOD hysteresis voltage on FB

660

40

730

mV

(3)

V_PG-HYST

OUTPUT STAGE (Applied to both channels)

On resistance of high-side FET

R_DS(on1)(HS)⁽³⁾

170

120

265

190

150

mΩ

and bondwire on CH1

On resistance of high-side FET

R_DS(on2)(HS)⁽³⁾

mΩ

and bondwire on CH2

On resistance of low-side FET and

R_DS(on1)(LS)⁽³⁾

bondwire on CH1

On resistance of low-side FET and

R_DS(on2)(LS)⁽³⁾

90

mΩ

bondwire on CH2

(3)

t_{ON_MIN}

Miimum controllable pulse width

Output driver dead time

150

ns

Minimum duty

cycle

V_FB= 0.9 V

0%

HDRV off to LDRV on

LDRV off to HDRV on

20

ns

(3)

t_DEAD

TPS54290

90%

85%

78%

96%

91%

82%

D_MAX

Maximum duty cycle

TPS54291

TPS54292

THERMAL SHUTDOWN

(3)

T_SD

Shutdown temperature

Hysteresis

145

20

°C

(3)

T_{SD_HYS}

(3) Specified by design. Not tested in production.

4

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TYPICAL PERFORMANCE CHARACTERISTICS

QUIESCENT CURRENT

vs

SHUTDOWN CURRENT

vs

TEMPERATURE

1.75

140

120

100

Non-Switching

1.70

1.65

V

= 18 V

IN

80

60

V

= 12 V

IN

1.60

1.55

40

20

0

V

= 4.5 V

IN

1.50

–40 –25 –10

5 20 35 50 65 80 95 110 125

– Junction Temperature – °C

–40 –25 –10

5 20 35 50 65 80 95 110 125

– Junction Temperature – °C

T

J

Figure 1.

Figure 2.

UVLO TURN-ON AND TURN-OFF THRESHOLDS

ENx TURN ON AND OFF THRESHOLD

vs

TEMPERATURE

4.2

4.1

1.26

1.24

UVLO ON

1.22

4.0

3.9

Enable OFF

1.20

1.18

Enable ON

3.8

3.7

3.6

1.16

1.14

UVLO OFF

1.12

–40 –25 –10

5 20 35 50 65 80 95 110 125

– Junction Temperature – °C

–40 –25 –10

5 20 35 50 65 80 95 110 125

– Junction Temperature – °C

T

J

Figure 3.

Figure 4.

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TYPICAL PERFORMANCE CHARACTERISTICS (continued)

SOFT START TIME

vs

OSCILLATOR FREQUENCY

vs

TEMPERATURE

1.4

1.2

6

5

4

1.0

0.8

f

= 1.2 MHz

SW

f

= 300 kHz

SW

f

= 600 kHz

SW

f

= 600 kHz

SW

3

2

0.6

0.4

1

0

0.2

f

= 300 kHz

f

= 1.2 MHz

SW

0

–40 –25 –10

5 20 35 50 65 80 95 110 125

– Junction Temperature – °C

–40 –25 –10

5 20 35 50 65 80 95 110 125

– Junction Temperature – °C

T

J

Figure 5.

Figure 6.

FEEDBACK VOLTAGE

vs

CURRENT LIMIT

vs

TEMPERATURE

4.50

4.25

4.00

808

Channel2

806

804

802

800

798

3.75

3.50

3.25

3.00

2.75

796

794

792

790

Channel1

2.50

2.25

2.00

788

–40 –25 –10

5 20 35 50 65 80 95 110 125

– Junction Temperature – °C

–40 –25 –10

5 20 35 50 65 80 95 110 125

– Junction Temperature – °C

T

J

Figure 7.

Figure 8.

6

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SLUS973 –OCTOBER 2009

TYPICAL PERFORMANCE CHARACTERISTICS (continued)

BP VOLTAGE

vs

SW NODE LEAKAGE CURRENT

vs

TEMPERARURE

TEMPERATURE

5.20

5.15

5.10

9

8

7

6

5

4

3

2

5.05

5.00

1

0

V

= 12 V

VDD

-1

–40 –25 –10

5 20 35 50 65 80 95 110 125

– Junction Temperature – °C

–40 –25 –10

5 20 35 50 65 80 95 110 125

– Junction Temperature – °C

T

J

Figure 9.

Figure 10.

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DEVICE INFORMATION

HTSSOP (PWP)

(Top View)

PVDD1

1

2

3

4

5

6

7

8

16 PVDD2

BOOT1

SW1

15 BOOT2

14 SW2

13 PGND2

12 BP

PGND1

EN1

EN2

11 GND

10 FB2

FB1

Thermal Pad

(bottom side)

COMP1

9 COMP2

PIN FUNCTIONS

I/O

DESCRIPTION

NAME

NO.

Input supply to the high-side gate driver for Output1. Connect a 22 nF to 68 nF capacitor from this pin to

SW1. This capacitor is charged from the BP pin voltage through an internal switch. The switch is turned ON

during the off time of the converter. To slow down the turn ON of the internal FET, a small resistor (2 Ω to 5

Ω) may be placed in series with the bootstrap capacitor.

BOOT1

2

I

Input supply to the high-side gate driver for Output2. Connect a 22 nF to 68 nF capacitor from this pin to

SW2. This capacitor is charged from the BP pin voltage through an internal switch. The switch is turned ON

during the off time of the converter. To slow down the turn ON of the internal FET, a small resistor (2 Ω to 5

Ω) may be placed in series with the bootstrap capacitor.

BOOT2

BP

15

12

5

I

–

I

Regulated voltage to charge the bootstrap capacitors. Bypass this pin to GND with a low-ESR 4.7-µF (10-µF

preferred) ceramic capacitor.

Active-low enable input for Output1. If the voltage on this pin is greater than 1.5 V, Output1 is disabled

(high-side switch is OFF). A voltage of less than 0.9 V enables Output1 and allow soft start of Output1 to

begin. An internal current source drives this pin to PVDD2 if left floating. Connect this pin to GND to bypass

the enable function.

EN1

Active-low enable input for Output2. If the voltage on this pin is greater than 1.5 V, Output2 is disabled

(high-side switch is OFF). A voltage of less than 0.9 V enables Output2 and allow soft-start of Output2 to

begin. An internal current source drives this pin to PVDD2 if left floating. Connect this pin to GND to bypass

the enable function.

EN2

6

I

FB1

FB2

7

I

Voltage feedback pin for Outputx. The internal transconductance error amplifier adjusts the PWM for Outputx

to regulate the voltage at this pin to the internal 0.8 V reference. A series resistor divider from Outputx to

ground, with the center connection tied to this pin, determines the value of the regulated output voltage.

10

COMP1

COMP2

PGND1

PGND2

GND

8

9

O

–

Output of the transconductance (g_M) amplifier. A R-C compensation network is connected from COMPx to

GND.

4

Power ground for Outputx. It is separated from GND to prevent the switching noise coupled to the internal

logic circuits.

13

11

–

Analog ground pin for the device.

Power input to the Output1 high-side MOSFET only. This pin should be locally bypassed to PGND1 with a

low ESR ceramic capacitor of 10 µF or greater. PVDD1 and PVDD2 could be tied externally together.

PVDD1

1

I

The PVDD2 pin provides power to the device control circuitry, provides the pull-up for the EN1 and EN2 pins

and provides power to the Output2 high-side MOSFET. This pin should be locally bypassed to PGND2 with

a low ESR ceramic capacitor of 10 µF or greater. The UVLO function monitors PVDD2 and enables the

device when PVDD2 is greater than 4.2 V.

PVDD2

16

SW1

SW2

3

O

–

Source (switching) output for Output1 PWM.

Source (switching) output for Output2 PWM.

This pad must be tied externally to a ground plane.

14

Thermal Pad

8

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BLOCK DIAGRAM

BP

2

1

BOOT1

PVDD1

f(I

) + DC(ofst)

DRAIN1

Current

Comparator

FET

Switch

CLK1

I

DRAIN1

S

R

Q

+

COMP1

FB1

8

7

3

SW1

f(I

)

DRAIN1

+

BP

Overcurrent Comp

)

+

0.8 V

REF

f(I

)

f(I

SLOPE1

MAX1

CLK1

Anti-Cross

Conduction

Soft Start

1

4

PGND1

SD1

TSD

10 mA

(max)

10 mA

(max)

EN1

EN2

5

6

SD1

f(I

)

SLOPE1

Internal

Control

Ramp

Gen 1

SD2

UVLO

CLK1

2.4 MHz

Oscilator

Divide by

2/4/8

f(I

)

SLOPE2

Ramp

Gen 2

FB1

FB2

Output

Undervoltage

Detect

CLK2

PVDD2

5.25-V

Regulator

BP 12

References

BP

15 BOOT2

16 PVDD2

GND 11

f(I

) + DC(ofst)

Current

DRAIN2

FET

Switch

Comparator

CLK2

I

DRAIN2

S

Q

+

R

COMP2

9

14 SW2

f(I

)

DRAIN2

+

FB2 10

BP

Overcurrent Comp

)

+

0.8 V

REF

f(I

)

f(I

SLOPE2

MAX2

CLK2

Anti-Cross

Conduction

Soft Start

2

13 PGND2

SD2

FET

Switch

UDG-09124

Figure 11. Block Diagram

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APPLICATION INFORMATION

FUNCTIONAL DESCRIPTION

The TPS54290/1/2 is a dual output fully synchronous buck converter. Each PWM channel contains an error

amplifier, current mode pulse width modulator (PWM), switching and rectifying MOSFETs, enable, and fault

protection circuitry. Common to the two channels are the internal voltage regulator, voltage reference, and clock

oscillator.

VOLTAGE REFERENCE

The band gap cell common to both outputs, trimmed to 800 mV. The reference voltage is 1% accurate in the

temperature range from 0°C to 85°C.

OSCILLATOR

The oscillator frequency is internally fixed at 2.4 MHz which is divided by 8/4/2 to generate the ramps for

TPS54290/1/2 respectively. The two outputs are internally configured to operate on alternating switch cycles (i.e.,

180° out-of-phase).

INPUT UVLO AND STARTUP

When the voltage at the PVDD2 pin is less than 4.4 V, a portion of the internal bias circuitry is operational, and

all other functions are held OFF. All of the internal MOSFETs are also held OFF. When the PVDD2 voltage rises

above the UVLO turn on threshold, the state of the enable pins determines the remainder of the internal startup

sequence. If either output is enabled (ENx pulled low), the BP regulator turns on, charging the BP capacitor with

a 20 mA current. When the BP pin is greater than 4 V, PWM is enabled and soft-start commences.

Note that the internal regulator and control circuitry are powered from PVDD2. The voltage on PVDD1 may be

higher or lower than PVDD2.

ENABLE AND TIMED TURN ON OF THE OUTPUTS

Each output has a dedicated (active low) enable pin. If left floating, an internal current source pulls the pin to

PVDD2. By grounding, or by pulling the ENx pin to below approximately 1.25 V with an external circuit, the

associated output is enabled and soft-start is initiated.

If both enable pins are left in the “high” state, the device operates in a shutdown mode, where the BP regulator is

shut down and minimal house keeping functions are active. The total standby current from both PVDD pins is

80 µA at 12 V input supply.

An R-C connect to an ENx pin may be used to delay the turn on of the associated output after power is applied

to PVDDx (see Figure 12). After power is applied to PVDD2, the voltage on the ENx pin slowly decays towards

ground. Once the voltage decays to approximately 1.25 V, then the output is enabled and the startup sequence

begins. If it is desired to enable the outputs of the device immediately upon the application of power to the

PVDD2 pin, then omit these two components and tie the ENx pin to GND directly.

If an R-C circuit is used to delay the turn on of the output, the resistor value must be an order of magnitude less

than 1.25 V/10 µA or 120 kΩ. A suggested value is 51 kΩ. This allows the ENx voltage to decay below the 1.25

V threshold while the 10-µA bias current flows.

The time to start (after the application of PVDD2) is

æ

ç

è

ö

÷

ø

V

_TH-I

´R

(

)

ENx

t_START= -R´ C´ln

s

( )

uuuuur

V_IN- 2´I_ENx´R

(1)

where

•

R and C are the timing components

V_THis the 1.25 V enable threshold voltage

I_ENis the 10-µA maximum enable pin biasing current

Figure 12 and Figure 13 illustrate startup delay with an R-C filter on the enable pin(s).

10

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PVDD2

10 mA (max)

C

ENx

PVDDx

+

PVDDx

1.25 V

1.25-V

R

Threshold

TPS5429x

UDG-09125

ENxB

V

OUTx

Time

0

t

+ t

DELAY

DELAY SS

Figure 12. Startup Delay Schematic

Figure 13. Startup Delay Timing Diagram

NOTE

If delayed output voltage startup is not necessary, simply connect EN1 and EN2 to

GND. This allows the outputs to “start” immediately on the valid application of PVDD2.

If ENx is allowed to go “high” after the outputx has been in regulation, the upper and

lower MOSFETs shut off, and the output decays at a rate determined by the output

capacitor and the load.

SOFT START

Each output has a dedicated soft start circuit. The soft start voltage is an internal digital reference ramp to one of

the two non-inverting inputs of the error amplifier. The other input is the internal precise 0.8-V reference. The

total ramp time for the FB voltage to charge from 0 V to 0.8 V is about 5.2 ms, 2.6 ms and 1.3 ms for

TPS54190/1/2 respectively. During a soft start interval, the TPS5429x output slowly increases the voltage to the

non-inverting input of the error amplifier. In this way, the output voltage slowly ramps up until the voltage on the

non-inverting input to the error amplifier reaches the internal 0.8V reference voltage. At that time, the voltage at

the non-inverting input to the error amplifier remains at the reference voltage.

During the soft-start interval, pulse-by-pulse current limiting is in effect. If an over-current pulse is detected, six

PWM pulses is skipped to allow the inductor current to decay before another PWM pulse is applied (See Output

Overload Protection). There is no pulse skipping if a current limit pulse is not detected.

If the rate of rise of the input voltage (PVDDx) is such that the input voltage is too low to support the desired

regulation voltage by the time soft-start has completed, then the output UV circuit may trip and cause a hiccup in

the output voltage. In this case, use a timed delay startup from the ENx pin to delay the startup of the output until

the PVDDx voltage has the capability of supporting the desired regulation voltage.

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OUTPUT VOLTAGE REGULATION

The regulation output voltage is determined by a resistor divider connecting the output node, the FBx pin, and

GND (Figure 14). The value of the output voltage is shown in Equation 2.

R1

æ

ö

V_OUT= V_REF´ 1+

V

( )

ç

÷

R2

è

ø

(2)

where

•

V_REFis the internal 0.8-V reference voltage

TPS54290

1

2

3

4

5

6

7

8

PVDD1 PVDD2 16

BOOT1 BOOT2 15

V

OUT1

SW1

SW2 14

PGND1 PGND2 13

R1

EN1

EN2

FB1

BP 12

GND 11

FB2 10

COMP1 COMP2

9

R2

UDG-09131

Figure 14. Feedback Network for Channel1

INDUCTOR SELECTION

Equation 3 calculates the inductance value so that the output ripple current falls from 20% to 40% of the full load

current.

V

- V

IN

OUT

L =

DI

OUT

(3)

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MAXIMUM OUTPUT CAPACITANCE

With internal pulse-by-pulse current limiting and a fixed soft-start time, there is a maximum output capacitance

which may be used before startup problems begin to occur. If the output capacitance is large enough so that the

device enters a current-limit protection mode during startup, then there is a possibility that the output never

reaches regulation. Instead, the TPS5429x simply shuts down and attempts a restart as if the output were

short-circuited to ground. The maximum output capacitance (including bypass capacitance distributed at the

load) is given by

æ

ö

÷

ø

t

I

RIPPLE

æ

ö

SS

C

=

´ ILIM - I

-

ç

OUT(max)

LOAD

ç

÷

V

2

è

ø

OUT

è

(4)

where

•

t_SSis the soft start time

ILIM is the current limit level

FEEDBACK LOOP COMPENSATION

In the feedback signal path, the output voltage setting divider is followed by an internal g_M-type error amplifier

with a typical transconductance of 325 µS. An external series connected R-C circuit from the g_Mamplifier output

(COMPx pin) to ground serves as the compensation network for the converter. The signal from the error amplifier

output is then buffered and combined with a slope compensation signal before it is mirrored to be referenced to

the SW node. Here, it is compared with the current feedback signal to create a pulse-width-modulated (PWM)

signal-fed to drive the upper MOSFET switch. A simplified equivalent circuit of the signal control path is depicted

in Figure 15.

NOTE

Noise coupling from the SWx node to internal circuitry of BOOTx may impact narrow

pulse width operation, especially at load currents less than 1 A.

BP

I

– I

SLOPE

COMP

PWM to

Switch

x 2

Error

Amplifier

I

SLOPE

FB

I

+

COMP

Offset

+

f(I

)

DRAIN

0.8 V

REF

COMP

GND

11.5 kW

R

COMP

C

COMP

UDG-09128

Figure 15. Feedback Loop Equivalent Circuit

A more conventional small-signal equivalent block diagram is shown in Figure 16. Here, the full closed-loop

signal path is shown. Because the TPS5429x contains internal slope compensation, the external L-C filter must

be selected appropriately so that the resulting control loop meets criteria for stability.

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V

IN

V_C

V

OUT

+

Modulator

V

REF

_

Filter

Current

Feedback

Network

Compensation

Network

Figure 16. Small Signal Equivalent Block Diagram

To determine the components necessary for compensating the feedback loop, the controller frequency response

characteristics must be understood and the desired crossover frequency selected. The best results are obtained

if 10% of the switching frequency is used as this closed loop crossover frequency. In some cases, up to 20% of

the switching frequency is also possible.

With the output filter components selected, the next step is to calculate the DC gain of the modulator. For

TPS5429x:

f

SW

FM

=

TPS5429x

æ

ç

è

ö

÷

ø

æ

ç

è

ö

÷

ø

V

- V

OUT

(

)

K´t

(

)

IN

-6

ON

19.7 ´ e

+ 95 ´10

´

L

(5)

where

•

K = 5.6 ×10⁵for TPS54290

K = 1.5 × 10⁶for TPS54291

K = 3.6 × 10⁶for TPS54292

The overall DC gain of the converter control-to-output transfer function is approximated Equation 6.

-4

V

´FM´ 2´10

IN

f

=

C

æ

ç

-6

ö

÷

æ

ç

è

ö

V

´FM´ 95´10

(

)

IN

÷

1+

÷

ø

2´R

LOAD

ç

è

÷

ø

(6)

The next step is to find the desired gain of the error amplifier at the desired crossover frequency. Assuming a

single-pole roll-off, us Equation 6 to evaluate the following expression at the desired crossover frequency.

æ

ç

ö

÷

f_C

K_EA= -20´log

ç

÷

1+ 2´ p´ f ´ 2´R

´ C

)

OUT

(

)

CO

LOAD

è

ø

(7)

where

•

ƒ_COis the desired crossover frequency

14

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TPS54290

1

2

3

4

5

6

7

8

PVDD1 PVDD2 16

BOOT1 BOOT2 15

V

Z

UPPER

OUT1

SW1

SW2 14

PGND1 PGND2 13

R1

C1

(Optional)

EN1

EN2

FB1

BP 12

GND 11

FB2 10

COMP1 COMP2

9

R2

C2

(Optional)

R

COMP

C

COMP

Z

LOWER

UDG-09129

Figure 17. Loop Compensation Network

If operating at wide duty cycles (over 50%), a capacitor may be necessary across the upper resistor of the

voltage setting divider. If duty cycles are less than 50%, this capacitor may be omitted.

L ´ C

OUT

C1 =

R1

(8)

If a high ESR capacitor is used in the output filter, a zero appears in the loop response that could lead to

instability. To compensate, a small capacitor is placed in parallel with the lower voltage setting divider resistor.

The value of the capacitor is determined such that a pole is placed at the same frequency as the ESR zero. If

low ESR capacitors are used, this capacitor may be omitted.

ESR ´ R1+ R2

(

R1´R2

)

C2 = C

´

OUT

(

)

(9)

Next, calculate the value of the error amplifier gain setting resistor and capacitor using Equation 10.

KEA

20

10

´ Z

+ Z

(

g ´ Z

)

LOWER UPPER

R

=

COMP

M

LOWER

(10)

(11)

1

C

=

COMP

2´ p´ f

´R

COMP

POLE

where

•

1

f_POLE

=

2´ p´ 2´R

(

´ C

)

OUT

LOAD

NOTE

Once the filter and compensation component values have been established,

laboratory measurements of the physical design should be performed to confirm

converter stability.

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BOOTSTRAP FOR N-CHANNEL MOSFET

A bootstrap circuit provides a voltage source higher than the input voltage and of sufficient energy to fully

enhance the switching MOSFET each switching cycle. The PWM duty cycle is limited to maximum, i.e., 90% for

TPS54291, allowing an external bootstrap capacitor to charge through an internal synchronous switch (between

BP and BOOTx) during every cycle. When the PWM switch is commanded to turn ON, the energy used to drive

the MOSFET gate is derived from the voltage on this capacitor.

Because this is a charge transfer circuit, care must be taken in selecting the value of the bootstrap capacitor. It

must be sized such that the energy stored in the capacitor on a per cycle basis is greater than the gate charge

requirement of the MOSFET being used. Typically a ceramic capacitor with a value between 22nF and 68nF is

selected for the bootstrap capacitor.

OUTPUT OVERLOAD PROTECTION

In the event of an overcurrent on either output after the output reaches regulation, pulse-by-pulse current limit is

in effect for that output. In addition, an output under-voltage (UV) comparator monitors the FBx voltage (which

follows the output voltage) to declare a fault if the output drops below 85% of regulation. During this fault

condition, both PWM outputs are disabled. This ensures that both outputs discharge to GND, in the event that

over-current is on one output while the other is not loaded. The converter enters a hiccup mode timeout before

attempting to restart.

If an over-current condition exists during soft start, pulse-by-pulse current limiting reduces the pulse width of the

affected output’s PWM. In addition, if an overcurrent pulse is detected, six clock cycles are skipped before a next

PWM pulse is enabled, effectively dividing the PWM frequency by six and preventing excessive current build up

in the indictor. At the end of the soft start time, a UV fault is declared and the operation is the same as described

above.

The overcurrent threshold for Output1 and Output2 are set nominally 2.2 A and 3.8 A respectively.

DESIGN HINT: The OCP Threshold refers to the peak current in the internal switch. Be sure to add the 1/2

of the peak inductor ripple current to the DC load current in determining how close the actual operating point

is to the OCP Threshold.

OPERATING NEAR MAXIMUM DUTY CYCLE

If the TPS5429x is operated at maximum duty cycle, and if the input voltage is insufficient to support the output

voltage (at full load or during a load current transient) then there is a possibility that the output voltage falls from

regulation and trip the output UV comparator. If this should occur, the TPS5429x protection circuitry declares a

fault and enter hiccup mode.

DESIGN HINT: Ensure that under ALL conditions of line and load regulation that there is sufficient duty cycle

to maintain output voltage regulation.

DUAL SUPPLY OPERATION

It is possible to operate a TPS5429x from two supply voltages. If this application is desired, then the sequencing

of the supplies must be such that PVDD2 is above the UVLO voltage before PVDD1 begins to rise. This is to

ensure the internal regulator and the control circuitry is in operation before PVDD1 supplies energy to the output.

In addition, Output1 must be held in the disabled state (EN1 high) until there is sufficient voltage on PVDD1 to

support Output1 in regulation. (See Operating near Maximum Duty Cycle)

The preferred sequence of events follows:

1. PVDD2 rises above the input UVLO voltage

2. PVDD1 rises with Output1 disabled until PVDD1 rises above level to support Output1 regulation

With the two conditions above satisfied, there is no restriction on PVDD2 to be greater than, or less than PVDD1.

DESIGN HINT: An R-C delay on EN1 may be used to delay the startup of Output1 for a long enough period

of time to ensure PVDD1 can support Output1 load.

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OVER-TEMPERATURE PROTECTION AND JUNCTION TEMPERATURE RISE

The over temperature thermal protection limits the maximum power to be dissipated at a given operating ambient

temperature. In other words, at a given device power dissipation, the maximum ambient operating temperature is

limited by the maximum allowable junction operating temperature. The device junction temperature is a function

of power dissipation, and the thermal impedance from the junction to the ambient. If the internal die temperature

should reach the thermal shutdown level, the TPS5429x shuts off both PWMs and remain in this state until the

die temperature drops below 125°C, at which time the device restarts.

The first step in determining the device junction temperature is to calculate the power dissipation. The power

dissipation is dominated by the two switching MOSFETs and the BP internal regulator. The power dissipated by

each MOSFET is composed of conduction losses and switching losses. The total conduction loss in the high side

and low side MOSFETs for each channel is given by Equation 12.

2

æ

ö

÷

ø

DI

2

O

ç

P

= R

(

´D + R

´ 1- D ´ I

+

(

)

D(cond)

DS(on)LS

)

O

DS on HS

( )

ç

12

è

(12)

where

•

I_Ois the DC output current,

ΔI_Ois the peak-to-peak ripple current in the inductor

Notice the impact of operating duty cycle on the result.

The switching loss for each channal is approximated by Equation 13.

2

V

´ C

(

HS + C

LS ´ f

OSS S

_OSS( )

2

( )

)

IN

P

=

D(SW )

(13)

where

•

C_OSS(HS)is the output capacitance of the high-side MOSFET

C_OSS(LS)is the output capacitance of the low-side MOSFET

ƒ_Sis the switching frequency

The total power dissipation is found by summing the power loss for both MOSFETs plus the loss in the internal

regulator.

P = P

+ P

+ V ´Iq

D

D(cond)output1

D(SW)output1

D(cond)output2

D(SW)output2 IN

(14)

The temperature rise of the device junction is dependent on the thermal impedance from junction to the mounting

pad (See Package Dissipation Ratings), plus the thermal impedance from the thermal pad to ambient. The

thermal impedance from the thermal pad to ambient is dependent on the PCB layout (PowerPAD interface to the

PCB, the exposed pad area) and airflow (if any). See PCB Layout Guidelines, Additional References.

The operating junction temperature is shown in Equation 15.

T = T + P ´ q

(

+ q_TH(pad-amb)

)

J

A

D

TH(pkg)

(15)

where

•

θth is the thermal impedance

BYPASSING AND FILTERING

As with any integrated circuit, supply bypassing is important for jitter free operation. To improve the noise

immunity of the converter, ceramic bypass capacitors must be placed as close to the package as possible.

•

PVDD1 to GND – Use a 10 µF ceramic capacitor

PVDD2 to GND – Use a 10 µF ceramic capacitor

BP to GND – Use a 4.7 µF Ceramic capacitor

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POWER DERATING

The TPS5429x delivers full current at wide duty cycles at ambient temperatures up to 85°C if the thermal

impedance from the thermal pad is sufficient to maintain the junction temperature below the thermal shut down

level. At higher ambient temperatures, the device power dissipation must be reduced to maintain the junction

temperature at or below the thermal shutdown level. Figure 18 illustrates the power derating for elevated ambient

temperature under various air flow conditions. Note that these curves assume the PowerPAD is soldered to the

recommended thermal pad. See References for further information.

1.8

LFM = 250

LFM = 500

1.6

1.4

LFM = 0

1.2

LFM = 150

1.0

0.8

0.6

LFM

0.4

0.2

0

150

250

500

0

20

40

60

80

100

– Ambient Temperature – °C

120

140

T

A

Figure 18. Power Derating Curves

PowerPAD PACKAGE

The PowerPAD package provides low thermal impedance for heat removal from the device. The PowerPAD

derives its name and low thermal impedance from the large bonding pad on the bottom of the device. The circuit

board must have an area of solder-tinned-copper underneath the package. The dimensions of this area depend

on the size of the PowerPAD package. Thermal vias connect this area to internal or external copper planes and

should have a drill diameter sufficiently small so that the via hole is effectively plugged when the barrel of the via

is plated with copper. This plug is needed to prevent wicking the solder away from the interface between the

package body and the solder-tinned area under the device during solder reflow. Drill diameters of 0.33 mm (13

mils) works well when 1-oz copper is plated at the surface of the board while simultaneously plating the barrel of

the via. If the thermal vias are not plugged when the copper plating is performed, then a solder mask material

should be used to cap the vias with a diameter equal to the via diameter of 0.1 mm minimum. This capping

prevents the solder from being wicked through the thermal vias and potentially creating a solder void under the

package. (See Additional References)

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LAYOUT RECOMMENDATIONS

•

The PowerPad must be connected to the low-current ground with available surface copper to dissipate heat.

Extending ground land beyond the device package area between PVDD1 (pin 1) and PVDD2 (pin 16) and

between COMP1 (pin 8) and COMP2( pin 9) is recommended..

•

Connect PGND1 and PGND2 to the PowerPad through a 10-mil wide trace.

Place the ceramic input capacitors near PVDD1 and PVDD2 and bypass to PGND1 and PGND2 respectively.

Locate the inductor near the SW1 or SW2 pin.

Connect the output capacitor grounds to PGND1 or PGND2 with wide, tight loops.

Use a wide ground connection from input capacitor PGND1 or PGND2 as close to power path as possible. It

is recommend they be placed directly underneath.

•

Locate the bootstrap capacitor near the BOOT pin to minimize gate drive loop.

Locate the feedback and compensation components far from switch node and input capacitor ground

connection.

•

Locate the snubber components from SW1 or SW2 to PGND1 or PGND2 close to the device, minimizing the

loop area.

Locate the BP bypass capacitor very close to device and bypass to PowerPad. Locate output ceramic

capacitor close to inductor output terminal and between inductor and electrolytic capacitors if used.

Figure 19. Top Layer

Figure 20. Bottom Layer

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DESIGN EXAMPLES

Design Example 1

The following example illustrates the design process and component selection for a 12-V to 5-V and 3.3-V dual

non-synchronous buck regulator using the TPS54291 converter. A definition of symbols used can be found in

Table 1 of the appendix

Table 1. Design Example Electrical Characteristics

PARAMETER

INPUT CHARACTERSTICS

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V_IN

I_IN

Input voltage

8

12

14

V

A

Input current

V_IN= Nom, I_OUT= Max

No load input current

Input UVLO

V_IN= Nom, I_OUT= 0 A

I_OUT= Min to Max

12

20

mA

V

V_IN(UVLO)

4

4.2

4.4

OUTPUT CHARACTERSTICS

V_OUT1

V_OUT2

Output voltage 1

V_IN= Nom, I_OUT= Nom

VIN = Min to Max

3.2

3.3

3.4

1.25

1%

50

V

Output voltage 2

1.15

1.20

Line regulation

Load regulation

I_OUT= Min to Max

V_OUT1(ripple)

V_OUT2(ripple)

I_OUT1

Output1 voltage Ripple

Output2 voltage Ripple

Output current 1

V_IN= Nom, I_OUT1= Max

V_IN= Nom, I_OUT2= Max

V_IN= Min to Max

mV_PP

24

mV_PP

0

1.5

2.5

2.6

4.6

A

I_OUT2

Output current 2

V_IN= Min to Max

I_OCP1

Output overcurrent Channel 1

Output overcurrent Channel 2

V_IN= Nom, V_OUT= (V_OUT1– 5%)

V_IN= Nom, V_OUT= (V_OUT2– 5%)

1.8

3.2

2.2

3.8

I_OCP2

TRANSIENT RESPONSE

ΔV_OUTChange from load transient

Settling time

SYSTEMS CHARACTERSTICS

ΔI_OUT= 1 A @ 3 µA/s

200

1

mV

ms

to 1% of V_OUT

f _SW

η_PEAK

η

Switching frequency

500

0

600

90%

80%

25

700

60

kHz

°C

Peak efficiency

V_IN= Nom

Full load efficiency

V_IN= Nom, I_OUT= Max

V_IN= Min to Max, I_OUT= Min to Max

T_OP

Operating temperature range

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The list of materials for this application is shown below in Table 2. The efficiency, line regulation and load

regulation from printed circuit boards built using this design are shown in Figure 23 and Figure 24.

Figure 21. TPS54291 Design Example 1 Schematic

Step by Step Design Procedure

Duty Cycle Estimation

The duty cycle of the main switching FET is estimated by Equation 16 and Equation 17.

V

OUT

3.3

1.2

OUT

D

»

=

= 0.413 ¾¾®D

»

=

= 0.15

MAX1

MAX2

V

8.0

V

8.0

IN min

(

IN min

(

)

(16)

(17)

V_OUT

3.3

14

1.2

14

D_MIN1

»

=

= 0.236 ¾¾®D_MIN2

»

=

= 0.086

V

IN max

(

)

(

)

Inductor Selection

The peak to peak ripple should be limited to between 20% and 30% of the maximum output current.

I_{Lrip1 max}= 0.30´I_{OUT max}= 0.3´1.5A = 0.450A

(

)

(

)

(18)

(19)

I_{Lrip2 max}= 0.30´I_{OUT max}= 0.3´ 2.5A = 0.750A

(

)

(

)

The minimum inductor size can be estimated by Equation 20 and Equation 21.

V

- V_OUT

IN max

(

)

1

14 - 3.3

1

L_MIN1

»

´D_MIN

´

=

´ 0.236´

= 9.35mH

I_{LRIP max}

f_SW

0.45A

600kHz

(

)

(20)

(21)

V

- V_OUT

IN max

(

)

1

14 - 1.2

1

L_MIN2

»

´ D_MIN

´

=

´ 0.086 ´

= 2.45mH

I_{LRIP max}

f_SW

0.75 A

600kHz

(

)

The standard inductor values of 8.2 µH and 3.3 µH are selected for Channel 1 and Channel 2 respectively. The

actual ripple currents are estimated by Equation 22 and Equation 23.

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V

- V_OUT

IN max

(

)

1

14 - 3.3

8.2mH

1

I_RIPPLE1

»

´D_MIN

´

=

´ 0.236´

´ 0.086´

= 0.513A

= 0.556A

L1

- V_OUT

f_SW

600kHz

(22)

(23)

V

IN max

(

)

1

14 -1.2

3.3mH

1

I_RIPPLE2

»

´D_MIN

´

=

L2

f_SW

600kHz

The RMS current through the inductor is approximated by Equation 24 and Equation 25.

2

I_{L rms}

=

I_{L avg}

+

₁₂I_RIPPLE

»

I_{OUT max}

+

₁₂I_RIPPLE

=

1.5

( )

+

0.513 ²A = 1.51A

2

)

2

)

2

1

12

(

)

(

)

(

(24)

(25)

2

0.556 ²A = 2.51A

2

)

2

)

2

1

12

I_{L rms}

=

I_{L avg}

+

₁₂I_RIPPLE

»

I_{OUT max}

+

₁₂I_RIPPLE

=

2.5

( )

+

(

)

(

)

(

A DC current with 30% peak-to-peak ripple has an RMS current approximately 0.4% above the average current.

The peak inductor current is estimated by Equation 26 and Equation 27.

1

I

» I

+

I

= 1.5A +

0.513A = 1.76A

0.556A = 2.78A

2

RIPPLE

L peak

(

OUT max

(

2

)

(26)

(27)

1

I

» I

+

I

RIPPLE

= 2.5A +

L peak

(

OUT max

(

2

)

A 8.2-µH inductor with a minimum RMS current rating of 1.51 A and minimum saturation current rating of 3.7 A

must be selected. A Coilcraft MSS1048-822ML 8.2-µH, 4.38-A inductor is chosen for Channel 1 and a Coilcraft

MSS1048-332 3.3-µH inductor is chosen for Channel 2.

Output Capacitor Selection

Output capacitors are selected to support load transients and output ripple current. The minimum output

capacitance to meet the transient specification is given by Equation 28 and Equation 29.

I_{TRAN max}²´L

(

)

1A²´ 8.2mH

3.3V ´0.2V

C_{OUT1 min}

=

= 12.4mF

= 13.7mF

(

)

V

´ V

)

OVER

(

OUT

(28)

(29)

2

1A ´ 3.3mH

I

´ L

TRAN max

(

)

C

=

OUT2 min

(

)

V

(

´ V

1.2 V ´ 0.2 V

)

OUT

OVER

The maximum ESR to meet the ripple specification is given by Equation 30 and Equation 31.

æ

ç

è

ö

÷

ø

I

æ

ç

è

ö

÷

ø

0.513A

8´12.4mF´ 600kHz

0.513A

RIPPLE

V

-

0.050V -

RIPPLE(total)

8´ C

´ f

SW

OUT

ESR

=

= 0.081W

MAX

I

RIPPLE

(30)

(31)

æ

ö

÷

ø

I

æ

ç

è

ö

÷

ø

0.556A

8´13.7mF´ 600kHz

0.556A

RIPPLE

V

-

ç

0.024V -

RIPPLE(total)

8´ C

´ f

SW

OUT

è

ESR

=

= 0.028W

MAX

I

RIPPLE

A single 22-µF ceramic capacitor with approximately 2.5 mΩ of ESR is selected to provide sufficient margin for

capacitance loss due to DC voltage bias.

Input Capacitor Selection

A minimum 10-µF ceramic input capacitor on each PVDD pin is recommended. The ceramic capacitor must

handle the RMS ripple current in the input capacitor.

The RMS current in the input capacitors is estimated by Equation 32 and Equation 33.

22

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I

= I

´ D ´ 1- D = 1.5A ´ 0.413´ 1- 0.413 = 0.74A

(

OUT1 1 1

)

RMS CIN1

(

)

(32)

(33)

I

= I

´ D ´ 1- D = 2.5A ´ 0.15´ 1- 0.15 = 0.89A

(

OUT1 2 2

)

RMS CIN2

(

)

One 1210 10-µF, 25-V, X5R, ceramic capacitor with 2-mΩ ESR and a 2-A RMS current rating are selected for

each PVDD input. Higher voltage capacitors are selected to minimize capacitance loss at the DC bias voltage to

ensure the capacitors will have sufficient capacitance at the working voltage.

Feedback

The primary feedback divider resistor (R_FB) from VOUT to FB should be selected between 10-kΩ and 100-kΩ to

maintain a balance between power dissipation and noise sensitivity. For a 3.3-V and 5-V output, 20.5 kΩ is

selected and the lower resistor is given by Equation 34.

V

´R

FB

R

=

BIAS

V

- V

FB

OUT

(34)

For R_FB= 20.5kΩ and V_FB= 0.80 V, R_BIAS= 6.56 kΩ and 41.0 kΩ (6.49 kΩ and 40.2 kΩ selected) for 3.3 V and

1.2 V respectively. It is common to select the next lower available resistor value for the bias resistor. This biases

the nominal output voltage slightly higher, allowing additional tolerance for load regulation.

Compensation Components

The TPS54291 controller uses a transconductance error amplifier, which is compensated with a series capacitor

and resistor to ground plus a high-frequency capacitor to reduce the gain at high frequency. To select the

component, the following equations define the control loop and power stage gain and transfer function:

f_SW

600kHz

FM_TPS5429x

=

= 3762

é

ù

ú

û

é

ù

ú

V

_IN- V_OUT

æ

ç

è

ö

÷

ø

1.5´10⁶´393ns

K´t

(

æ

ç

è

ö

÷

)

(

)

14 - 3.3

8.2mH

ON

+ 95´10^-6

´

19.7´ e

+ 95´10^-6

´

19.7´ e

ê

L

ë

ê

ë

øú

û

(35)

where

•

K = 5.6 × 10⁵for TPS54290

K = 1.5 × 10⁶for TPS54291

K = 3.6 × 10⁶for TPS54292

The overall DC gain of the converter control-to-output transfer function is approximated by Equation 36.

-4

V

´FM´ 2´10

14V ´3762´ 2´10

IN

f

=

= 4.293

C

-6

é

ù

ú

é

ù

ú

æ

ö

÷

ø

æ

ç

è

ö

÷

ø

V

´FM´ 95´10

14V ´3762´95´10

4.4W

IN

ê

1+

1+ ç

ç

2´R

ê

ú

ê

ú

LOAD

è

ë

û

ë

û

(36)

With the power stage DC gain, it is possible to estimate the required mid-band gain to program a desired

cross-over frequency.

æ

ç

è

ö

÷

ø

f_C

æ

ç

è

ö

÷

ø

3.22

K_EA= -20´log

= -20´log

= 11.83dB

1+ 2´ p´ f_CO´ 2´R

´ C

)

1+ 2´ p´ 30kHz ´ 4.4W ´ 22mF

(

LOAD

OUT

(37)

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Compensation Gain Setting Resistor

R_COMPprograms the mid-band error amplifier gain to set the desired cross-over frequency in Equation 38.

KEA

11.83dB

20

10

´ Z

+ Z

(

g ´ Z

)

10

´(6.49kW + 20.5kW)

325mS´ 6.49kW

LOWER UPPER

R

=

= 50.42kW » 53.6kW

COMP

M

LOWER

(38)

Compensation Integrator Capacitor

An integrator capacitor provides maximum DC gain for the best possible DC regulation while programming the

compensation zero to match the natural pole of the output filter. C_COMPis selected by Equation 40.

1

f

=

= 1.644kHz

POLE

2´ p´R

´ C

2´ p´ 4.4W ´ 22mF

LOAD

OUT

(39)

(40)

1

C

=

= 1.80nF

COMP

2´ p´ f

´R

2´ p´1.644kHz ´53.6kW

POLE

COMP

Bootstap Capacitor

To ensure proper charging of the high-side FET gate and limit the ripple voltage on the boost capacitor, a 47-nF

boot strap capacitor is recommended.

Power Dissipation

The power dissipation in the TPS54291 is made from FET conduction losses, switching losses and regulator

losses.

Conduction losses are estimated by Equation 41 and Equation 42.

æ

ö²

ø

P_CON1= R_{DS on HS}´D₁+ R_{DS on LS}´ 1- D ´ I

= 150mW ´0.413 +100mW ´0.587 ´ 1.51 ²= 0.275W

(

)

(

) (

)

ç

÷

(

1

( )

è ^{SW1 RMS}

(

)

(41)

æ

ö²

÷

P_CON2= R_{DS on HS}´D₁+ R_{DS on LS}´ 1- D ´ I

= 105mW ´0.15 + 75mW ´0.85 ´ 2.51 ²= 0.501W

(

)

(

) (

)

ç

(

1

( )

è ^{SW1 RMS}

ø

(

)

(42)

The switching losses are estimated by Equation 43 and Equation 44.

14²´(140pF + 200pF)´ 600kHz

V

²´(C_OSS(HS)+ C_OSS(LS))´ f_SW

IN max

(

)

P_SW1

»

=

= 20mW

= 28mW

2

(43)

(44)

V

²´(C_{OSS HS}+ C_{OSS LS})´ f_SW

IN max

(

)

( )

14²´(200pF + 280pF)´ 600kHz

P_SW2

»

=

2

The regulator losses are estimated by Equation 45.

P_REG» I_DD´ V + I_BP´ V - V_BP= 10mA ´14V = 140mW

)

(

IN max

(

IN max

(

)

(45)

Total power dissipation in the device is the sum of conduction losses and switching losses for both channels plus

regulator losses, which is estimated to be 1.01 W.

24

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Design Example Test Results

Figure 22. TPS54291 Design Example Switching Waveforms

90

85

100

95

V

= 8 V

IN

V

= 8 V

IN

90

85

80

75

70

65

60

55

50

V

= 12 V

V

= 14 V

IN

80

75

V

= 14 V

V

= 12 V

IN

70

65

60

55

50

V

= 1.2 V

V

= 3.3 V

OUT

2.0

OUT

1.2

0

0.5

1.0 1.5

– Load Current – A

2.5

0

0.3

0.6 0.9

– Load Current – A

1.5

I

LOAD

Figure 23. Design Efficiency for 1.2-V Output

Figure 24. Design Efficiency for 3.3-V Output

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MFR

Table 2. Design Example List of Materials

REFERENCE

DESIGNATOR

QTY

VALUE

4.7 µF

DESCRIPTION

SIZE

PART NUMBER

C12

1

2

Capacitor, Ceramic, 10 V, X5R, 20%

Capacitor, Ceramic, 6.3 V, X5R, 20%

Capacitor, Ceramic, 25 V, X7R, 20%

0805

Std

C2, C14

C3, C13

C4, C11

22 µF

1206

0603

C3216X5R0J226M TDK

470 pF

0.047 µF

Std

C3225X5R1E106

M

C5, C10

2

10 µF

Capacitor, Ceramic, 25 V, X5R, 20%

1210

TDK

C6

C7

C8

C9

2

1

1.8 nF

15 pF

47 pF

1.2 nF

Capacitor, Ceramic, 25 V, X7R, 20%

0603

Std

0.402 x

0.394 inch

L1

L2

1

8.2 µH

3.3 µH

Inductor, SMT, 4.38 A, 20 mΩ

Inductor, SMT, 5.04 A, 10 mΩ

MSS1048-822L

MSS1048-332L

Coilcraft

0.402 x

0.394 inch

R10

1

2

1

40.2 kΩ

10 Ω

Resistor, Chip, 1/16W, 1%

Resistor, Chip, 1/16W, 5%

Resistor, Chip, 1/16W, 1%

0603

Std

R2, R11

R3, R12

R4

20.5 kΩ

6.49 kΩ

7.87 kΩ

4.64 kΩ

R6

R7

2.5 A/1.5 A, Dual Output Fully Synchronous Buck

600 Hz Converter w/Integrated FET

U1

1

CSP

TPS54291PWP

TI

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Design Example 2 (Cascading Operation)

TPS5429x can be configured as cascaded operation as shown in Figure 25. The 12-V input supply is applied to

PVDD2 and the the channel 2 output is tied to PVDD1. The channel 2 output is 3.3 V and capable of supporting

1.5 A to the load while generating power for the 1.2-V input for channel 1.

+

3.3V@1.5A

1.2V@1.5A

+

Figure 25. Cascading Operation

Design Example 2 Test Results

For Figure 26, Ch1: 12-V supply; Ch2: V_OUT1(1.2 V); Ch3: V_OUT2(3.3 V). For Figure 27, Ch1: Channel 1 SW

node; Ch2: Channel 1 output ripple Ch3: Channel 2 output ripple; Ch2: Channel 2 SW node.

Figure 26. Start-Up Waveforms

Figure 27. Output Ripple and SW Nodes

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ADDITIONAL REFERENCES

RELATED DEVICES

The following devices have characteristics similar to the TPS54290/1/2 and may be of interest.

DEVICE

TPS40222

DESCRIPTION

5-V input, 1.5-A, Non-Synchronous Buck Converter

TPS54283/TPS54286

TPS55383/TPS55386

2-A DUAL NON-SYNCHRONOUS CONVERTER WITH INTEGRATED HIGH-SIDE FET

3-A DUAL NON-SYNCHRONOUS CONVERTER WITH INTEGRATED HIGH-SIDE FET

REFERENCES

These references, design tools and links to additional references, including design software, may be found at

www.power.ti.com.

1. Additional PowerPAD™ information may be found in Applications Briefs (SLMA002A) and (SLMA004).

2. Under The Hood Of Low Voltage DC/DC Converters – SEM1500 Topic 5 – 2002 Seminar Series

3. Understanding Buck Power Stages in Switchmode Power Supplies, (SLVA057), March 1999

4. Designing Stable Control Loops – SEM 1400 – 2001 Seminar Series

Package Outline and Recommended PCB Footprint

The following pages outline the mechanical dimensions of the 16-pin PWP package and provide

recommendations for PCB layout.

28

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PACKAGE OPTION ADDENDUM

www.ti.com

20-Nov-2009

PACKAGING INFORMATION

Orderable Device

TPS54290PWP

TPS54290PWPR

TPS54291PWP

TPS54291PWPR

TPS54292PWP

TPS54292PWPR

Status ⁽¹⁾

ACTIVE

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

Drawing

HTSSOP

PWP

16

90 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

HTSSOP

PWP

2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

90 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

90 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

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information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

Addendum-Page 1

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型号：	TPS54290
厂家：	TEXAS INSTRUMENTS
描述：	1.5-A/2.5-A Dual, Fully-Synchronous Buck Converter With Integrated MOSFET 1.5 A / 2.5 -A双通道，全同步降压转换器，集成MOSFET 转换器
文件：	总33页 (文件大小：1335K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TPS54290 [TI]

相关型号：

TPS54290PWP

TPS54290PWPR

TPS54290_1

TPS54290_12

TPS54291

TPS54291PWP

TPS54291PWPR

TPS54292

TPS54292PWP

TPS54292PWPR

TPS54294

TPS542941