TPS5430_技术文档

TPS54377

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SLVS779–SEPTEMBER 2007

1.6 MHz, 3-V TO 6-V INPUT, 3-A SYNCHRONOUS STEP-DOWN SWIFT™ CONVERTER

WITH DISABLED SINKING DURING START-UP

1

FEATURES

DESCRIPTION

2

•

60-mΩ MOSFET Switches for High Efficiency

at 3-A Continuous Output Current

As a member of the SWIFT™ family of dc/dc

regulators, the TPS54377 low-input-voltage

high-output-current synchronous-buck PWM

•

Adjustable Output Voltage Down to 0.9 V With

1% Accuracy

converter integrates all required active components.

Included on the substrate with the listed features are

a true, high performance, voltage error amplifier that

provides high performance under transient conditions;

an undervoltage-lockout circuit to prevent start-up

until the input voltage reaches 3 V; an internally and

externally set slow-start circuit to limit in-rush

Switching Frequency: Adjustable From

280 kHz to 1600 kHz

•

Disabled Current Sinking During Start-Up

Fast Transient Response

Load Protected by Peak Current Limit and

Thermal Shutdown

currents; and

a power good output useful for

•

Integrated Solution Reduces Board Area and

Total Cost

processor/logic reset, fault signaling, and supply

sequencing.

•

Spacing Saving 4mm x 5mm QFN Packaging

For reliable power up in output precharge

applications, the TPS54377 is designed to only

source current during start-up.

For SWIFT Documentation, Application Notes,

and Design Software, see the TI website at

www.ti.com/swift

The TPS54377 device is available in a thermally

enhanced 24-pin QFN (RHF) PowerPAD™ package,

which eliminates bulky heatsinks. TI provides

evaluation modules and the SWIFT designer software

tool to aid in achieving high-performance power

supply designs to meet aggressive equipment

development cycles.

APPLICATIONS

•

Low-Voltage, High-Density Systems With

Power Distributed at 5 V or 3.3 V

Point of Load Regulation for High

Performance DSPs, FPGAs, ASICs, and

Microprocessors

•

Broadband, Networking and Optical

Communications Infrastructure

START-UP WAVEFORM

Simplified Schematic

*

R

L

= 1 Ω

Input

Output

TPS54377

VIN

PH

PWRGD

SS/ENA

SYNC

RT

BOOT

PGND

V = 3.3 V

I

VSENSE

VBIAS

AGND COMP

V

= 1.8 V

O

5.0 ms/div

* Optional

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2

SWIFT, PowerPAD are trademarks of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

TPS54377

www.ti.com

SLVS779–SEPTEMBER 2007

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

ORDERING INFORMATION

T_J

OUTPUT VOLTAGE

PACKAGE

PART NUMBER

–40°C to 125°C

Adjustable Down to 0.9 V

QFN (RHF)⁽¹⁾⁽²⁾

TPS54377RHF

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

website at www.ti.com.

(2) The RHF package is available in two different tape and reel quantities. Add an R suffix to the device type (i.e. TPS54377RHFR) for a

3000 piece reel and add a T suffix (TPS54377RHFT) for a 250 piece reel.

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

VALUE

–0.3 to 7

–0.3 to 6

–0.3 to 4

–0.3 to 17

–0.3 to 7

–0.6 to 10

–2 to 10

UNIT

V

VIN, SS/ENA, SYNC

RT

V

V_I

Input voltage range

VSENSE

V

BOOT

V

VBIAS, PWRGD, COMP

PH (steady state)

PH (transient < 20 ns)

PH

V

V_O

Output voltage range

Output current range

Sink current

V

Internally Limited

I_O

COMP, VBIAS

PH

6

mA

A

COMP

6

mA

V

SS/ENA, PWRGD

AGND to PGND

10

±0.3

Voltage differential

Continuous power dissipation

See Power Dissipation Rating Table

T_J

Operating virtual junction temperature range

Storage temperature

–40 to 150

–65 to 150

°C

T_stg

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

RECOMMENDED OPERATING CONDITIONS

MIN

3

NOM

MAX

6

UNIT

V

V_I

Input voltage range

T_J

Operating junction temperature

–40

125

°C

2

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SLVS779–SEPTEMBER 2007

PACKAGE DISSIPATION RATINGS^{(1) (2)}

PACKAGE

THERMAL IMPEDANCE

JUNCTION-TO-AMBIENT

THERMAL IMPEDANCE

JUNCTION-TO-CASE

24-Pin RHF with solder

19.7°C/W

1.7°C/W

(1) Maximum power dissipation may be limited by overcurrent protection.

(2) Test board conditions:

a. 3 inch x 3 inch, 4 layers, thickness: 0.062 inch

b. 2 oz. copper traces located on the top of the PCB

c. 2 oz. copper ground plane on the bottom of the PCB

d. 2 oz. copper ground planes on the 2 internal layers

e. 6 thermal vias (see the Recommended land pattern, Figure 12)

ELECTRICAL CHARACTERISTICS

T_J= –40°C to 125°C, V_I= 3 V to 6 V (unless otherwise noted)

PARAMETER

SUPPLY VOLTAGE, VIN

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V_I

Input voltage range, VIN

3

6

V

f_s= 350 kHz, SYNC = 0.8 V, RT open

6.2

8.4

1

9.6

f_s= 550 kHz, SYNC ≥ 2.5 V, RT open,

phase pin open

Quiescent current

12.8

1.4

mA

Shutdown, SS/ENA = 0 V

UNDERVOLTAGE LOCK OUT

Start threshold voltage, UVLO

2.95

2.8

3

V

Stop threshold voltage, UVLO

Hysteresis voltage, UVLO

2.7

0.14

0.16

V

Rising and falling edge deglitch,

UVLO⁽¹⁾

2.5

µs

BIAS VOLTAGE

Output voltage, VBIAS

Output current, VBIAS

I_(VBIAS)= 0

2.7

2.8

2.9

V

V_O

(2)

100

µA

CUMULATIVE REFERENCE

V_refAccuracy

REGULATION

Line regulation^{(1) (3)}

Load regulation^{(1) (3)}

OSCILLATOR

0.882

0.891 0.900

V

I_L= 1.5 A, f_s= 1.1 MHz, T_J= 25°C

0.04

0.09

%/V

%/A

I_L= 0 A to 3 A, f_s= 1.1 MHz, T_J= 25°C

SYNC ≤ 0.8 V, RT open

280

440

460

995

2.5

350

550

420

660

Internally set free-running frequency

range

kHz

SYNC ≥ 2.5 V, RT open

RT = 100 kΩ (1% resistor to AGND)

RT = 43 kΩ (1% resistor to AGND)

500

540

Externally set free-running frequency

range

1075

1155

High-level threshold voltage, SYNC

Low-level threshold voltage, SYNC

Pulse duration, SYNC⁽¹⁾

V

0.8

50

ns

kHz

V

Frequency range, SYNC

Ramp valley⁽¹⁾

Ramp amplitude (peak-to-peak)⁽¹⁾

Minimum controllable on time

Maximum duty cycle

330

1600

0.75

1

V

150

ns

90%

(1) Specified by design

(2) Static resistive loads only

(3) Specified by the circuit used in Figure 10.

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SLVS779–SEPTEMBER 2007

ELECTRICAL CHARACTERISTICS (continued)

T_J= –40°C to 125°C, V_I= 3 V to 6 V (unless otherwise noted)

PARAMETER

ERROR AMPLIFIER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Error amplifier open loop voltage gain

Error amplifier unity gain bandwidth

1 kΩ COMP to AGND⁽⁴⁾

Parallel 10 kΩ, 160 pF COMP to AGND⁽⁴⁾

90

3

110

5

dB

MHz

Error amplifier common-mode input

voltage range

Powered by internal LDO⁽⁴⁾

VSENSE = V_ref

0

VBIAS

250

V

I_IB

Input bias current, VSENSE

60

nA

Output voltage slew rate (symmetric),

COMP

V_O

1

1.4

V/µs

PWM COMPARATOR

PWM comparator propagation delay

time, PWM comparator input to PH pin

(excluding dead time)

10 mV overdrive⁽⁴⁾

70

85

ns

SLOW-START/ENABLE

Enable threshold voltage, SS/ENA

Enable hysteresis voltage, SS/ENA

0.82

1.2

0.03

2.5

3.35

5

1.4

V

(4)

Falling edge deglitch, SS/ENA

µs

ms

µA

mA

Internal slow-start time

Charge current, SS/ENA

Discharge current, SS/ENA

2.6

3

4.1

8

SS/ENA = 0 V

SS/ENA = 0.2 V, V_I= 2.7 V

1.3

2.3

4

POWER GOOD

Power good threshold voltage

Power good hysteresis voltage

VSENSE falling

90

3

%V_ref

µs

(4)

Power good falling edge deglitch

35

Output saturation voltage, PWRGD

Leakage current, PWRGD

I_(sink)= 2.5 mA

V_I= 5.5 V

0.18

0.3

1

V

µA

CURRENT LIMIT

(4)

V_I= 3 V, output shorted

4

6.5

7.5

Current limit trip point

A

(4)

V_I= 6 V, output shorted

4.5

Current limit leading edge blanking

time⁽⁴⁾

100

200

ns

(4)

Current limit total response time

THERMAL SHUTDOWN

Thermal shutdown trip point

Thermal shutdown hysteresis

OUTPUT POWER MOSFETS

(4)

135

150

10

165

°C

V_I= 6 V

V_I= 3 V

59

85

88

mΩ

r_DS(on)

Power MOSFET switches

136

(4) Specified by design

4

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SLVS779–SEPTEMBER 2007

PIN ASSIGNMENTS

RHF PACKAGE

(BOTTOM VIEW)

6

1

2

3

4

5

7

24

23

22

21

20

8

PH

VSNS

AGND

9

PH

NC

Exposed

Thermal Pad

(Pin 25)

10

RT

NC

11

12

PGND

SYNC

19 18

17 16 15 14

13

TERMINAL FUNCTIONS

TERMINAL

DESCRIPTION

NAME

NO.

COMP

1

Error amplifier output. Connect compensation network from COMP to VSENSE.

Power good open drain output. High when VSENSE ≥ 90% V_ref, otherwise PWRGD is low. Note that output is low

when SS/ENA is low or internal shutdown signal active.

PWRGD

2

Bootstrap input. 0.022-μF to 0.1-μF low-ESR capacitor connected from BOOT to PH generates floating drive for the

high-side FET driver.

BOOT

PH

3

4-9

Phase input/output. Junction of the internal high and low-side power MOSFETs, and output inductor.

Power ground. High current return for the low-side driver and power MOSFET. Connect PGND with large copper

areas to the input and output supply returns, and negative terminals of the input and output capacitors.

PGND

11-14

Input supply for the power MOSFET switches and internal bias regulator. Bypass VIN pins to PGND pins close to

device package with a high quality, low ESR 1-μF to 10-μF ceramic capacitor.

VIN

15-17

18

Internal bias regulator output. Supplies regulated voltage to internal circuitry. Bypass VBIAS pin to AGND pin with a

high quality, low ESR 0.1-μF to 1.0-μF ceramic capacitor.

VBIAS

SS/ENA

Slow-start/enable input/output. Dual function pin which provides logic input to enable/disable device operation and

capacitor input to externally set the start-up time.

19

Synchronization input. Dual function pin which provides logic input to synchronize to an external oscillator or pin

select between two internally set switching frequencies. When used to synchronize to an external signal, a resistor

must be connected to the RT pin.

SYNC

20

RT

22

23, 25

24

Frequency setting resistor input. Connect a resistor from RT to AGND to set the switching frequency, f_s.

Analog ground. Return for compensation network/output divider, slow-start capacitor, VBIAS capacitor, RT resistor

and SYNC pin. Make PowerPAD connection to AGND.

AGND

VSNS

NC

Error amplifier inverting input.

10, 21 Not connected internally.

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SLVS779–SEPTEMBER 2007

FUNCTIONAL BLOCK DIAGRAM

VBIAS

AGND

VIN

Enable

Comparator

SS/ENA

REG

VBIAS

ILIM

Falling

Edge

Deglitch

SHUTDOWN

1.2 V

VIN

Comparator

Thermal

Shutdown

150°C

Hysteresis: 0.03 V

Leading

Edge

2.5 µs

Blanking

VIN UVLO

Comparator

Falling

and

100 ns

SHUTDOWN

VIN

BOOT

Rising

Edge

2.95 V

Deglitch

Hysteresis: 0.16

V

60 mΩ

Start-Up

Driver

Suppression

2.5 µs

SS_DIS

L

OUT

V

O

PH

Internal/External

Slow-start

(Internal Slow-Start Time = 3.35 ms)

+

−

C

O

Adaptive Dead-Time

and

Control Logic

R

S

Q

Error

Amplifier

PWM

Comparator

Reference

VIN

VREF = 0.891 V

60 mΩ

PGND

OSC

Powergood

Comparator

PWRGD

VSENSE

0.90 V

Falling

Edge

ref

Deglitch

TPS54373

Hysteresis: 0.03 Vref

SHUTDOWN

35 µs

SYNC

VSENSE

COMP

RT

ADDITIONAL 3-A SWIFT DEVICES

DEVICE

OUTPUT VOLTAGE

DEVICE

TPS54350

TPS54372

TPS54373

OUTPUT VOLTAGE

TPS5430/1

TPS54310 & TPS54317

TPS54380

Wide Vin/Adjustable

Adjustable

Low Side Gate Drive/Adjustable

DDR/Adjustable

Sequencing/Adjustable

Prebias/Adjustable

6

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SLVS779–SEPTEMBER 2007

TYPICAL CHARACTERISTICS

DRAIN-SOURCE ON-STATE

INTERNALLY SET OSCILLATOR

FREQUENCY

RESISTANCE

vs

RESISTANCE

vs

JUNCTION TEMPERATURE

100

vs

JUNCTION TEMPERATURE

120

100

80

750

650

550

450

V

= 5 V

V

= 3.3 V

I

80

60

40

20

0

SYNC ≥ 2.5 V

60

SYNC ≤ 0.8 V

40

350

250

20

0

−40

0

25

85

125

−40

0

25

85

125

−40

0

25

85

125

T − Junction Temperature − °C

J

T

J

− Junction Temperature − °C

T

J

− Junction Temperature − °C

Figure 1.

Figure 2.

Figure 3.

EXTERNALLY SET OSCILLATOR

FREQUENCY

EXTERNALLY SET OSCILLATOR

FREQUENCY

VOLTAGE REFERENCE

vs

JUNCTION TEMPERATURE

vs

JUNCTION TEMPERATURE

0.895

1200

1150

600

550

500

450

400

RT = 43 kW

RT = 100 kW

0.893

0.891

1100

1050

1000

0.889

0.887

0.885

−40

0

25

85

125

−40

0

25

85

125

−40

0

25

85

125

− Junction Temperature − ^o

C

T

− Junction Temperature − ^o

C

T

J

− Junction Temperature − °C

T

J

Figure 4.

Figure 5.

Figure 6.

INTERNAL SLOW-START TIME

vs

DEVICE POWER LOSSES

vs

ERROR AMPLIFIER

OPEN LOOP RESPONSE

JUNCTION TEMPERATURE

LOAD CURRENT

1.2

1

0

3.80

3.65

3.50

3.35

3.20

3.05

140

120

100

80

T

f

= 25^oC,

R = 10 kΩ,

A

L

−20

−40

−60

−80

= 700 kHz,

C

T

= 160 pF,

= 25°C

L

s

V = 5 V,

A

I

V

= 3.3 V

O

0.8

0.6

Phase

−100

−120

60

40

20

Gain

0.4

0.2

0

−140

−160

0

2.90

2.75

−180

−200

−20

0

10

100 1 k 10 k 100 k 1 M 10 M

0

0.5

1

1.5

2

2.5

3

−40

0

25

85

125

f − Frequency − Hz

I

− Output Current − A

T

J

− Junction Temperature − °C

O

Figure 7.

Figure 8.

Figure 9.

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SLVS779–SEPTEMBER 2007

APPLICATION INFORMATION

Figure 10 shows the schematic diagram for a typical TPS54377 application. The TPS54377 (U1) provides up to

3 A of output current at a nominal output voltage of 1.8 V. For proper thermal performance, the power pad

underneath the TPS54377 integrated circuit needs to be soldered well to the printed circuit board. The

TPS54377 can be evaluated by replacing the TPS54317 on the TPS54317 EVM.

C8

2200 pF

R1

10 kW

R5

442 W

1

2

+

C1

150 mF

R3

6.81 kW

C7

150 pF

R2

9.76 kW

C6

3300 pF

U1

TPS54377

R6

10 kW

1

24

23

22

21

20

19

18

17

16

15

14

13

VSNS

COMP

2

AGND

PWRGD

R4

3

C3

0.047 mF

RT

BOOT

PH

4

41.2 kW

NC

5

SYNC

SS/EN

VBIAS

VIN

PH

L1

1.5 mH

6

PH

7

PH

VOUT

8

PH

C5

C4

0.1 mF

9

VIN

PH

C2

100 mF

C10

100 mF

C11

1000 pF

10

11

12

VIN

NC

PGND

C9

10 mF

PwPd

Open

Figure 10. TPS54377 Schematic

51 k

- 4.7 k

R(W) =

ƒ (MHz)

(1)

INPUT VOLTAGE

The input to the circuit is a nominal 3.3 VDC, applied

at J1. The optional input filter (C1) is a 150-µF

capacitor, with a maximum allowable ripple current of

3 A. C9 is the decoupling capacitor for the TPS54377

and must be located as close to the device as

possible.

OUTPUT FILTER

The output filter is composed of a 1.5-µH inductor

and two capacitors. The inductor is a low dc

resistance (0.017 Ω) type, Coilcraft DO1813P-122HC.

The feedback loop is compensated so that the unity

gain frequency is approximately 75 kHz.

FEEDBACK CIRCUIT

PCB LAYOUT

The resistor divider network of R1 and R2 sets the

output voltage for the circuit at 1.8 V. R1, along with

R5, R3, C5, C7, and C8 forms the loop compensation

network for the circuit. For this design, a Type 3

topology is used.

Figure 11 shows a generalized PCB layout guide for

the TPS54377.

The VIN pins should be connected together on the

printed circuit board (PCB) and bypassed with a low

ESR ceramic bypass capacitor. Care should be taken

to minimize the loop area formed by the bypass

capacitor connections, the VIN pins, and the

TPS54377 ground pins. The minimum recommended

bypass capacitance is 10-µF ceramic with a X5R or

X7R dielectric and the optimum placement is closest

to the VIN pins and the PGND pins.

OPERATING FREQUENCY

In the application circuit, the 1.1-MHz operation is

selected. Connecting a 41.2-kΩ between RT (pin 22)

and analog ground can be used to set the switching

frequency from 280 kHz to 1.6 MHz. To calculate the

RT resistor, use the Equation 1:

8

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SLVS779–SEPTEMBER 2007

The TPS54377 has two internal grounds (analog and

power). Inside the TPS54377, the analog ground ties

to all of the noise sensitive signals, while the power

ground ties to the noisier power signals. Noise

injected between the two grounds can degrade the

performance of the TPS54377, particularly at higher

output currents. Ground noise on an analog ground

plane can also cause problems with some of the

control and bias signals. For these reasons, separate

analog and power ground traces are recommended.

There should be an area of ground on the top layer

directly under the IC, with an exposed area for

connection to the PowerPAD. Use vias to connect

this ground area to any internal ground planes. Use

additional vias at the ground side of the input and

output filter capacitors as well. The AGND and PGND

pins should be tied to the PCB ground by connecting

them to the ground area under the device as shown.

The only components that should tie directly to the

power ground plane are the input capacitors, the

output capacitors, the input voltage decoupling

capacitor, and the PGND pins of the TPS54377. Use

a separate wide trace for the analog ground signal

path. This analog ground should be used for the

voltage set point divider, timing resistor RT, slow start

capacitor and bias capacitor grounds. Connect this

trace directly to AGND (pin 1).

The PH pins should be tied together and routed to

the output inductor. Since the PH connection is the

switching node, inductor should be located very close

to the PH pins and the area of the PCB conductor

minimized to prevent excessive capacitive coupling.

Connect the boot capacitor between the phase node

and the BOOT pin as shown. Keep the boot capacitor

close to the IC and minimize the conductor trace

lengths.

Connect the output filter capacitor(s) as shown

between the VOUT trace and PGND. It is important to

keep the loop formed by the PH pins, L_O, C_Oand

PGND as small as practical.

Place the compensation components from the VOUT

trace to the VSENSE and COMP pins. Do not place

these components too close to the PH trace. Due to

the size of the IC package and the device pinout,

they must be routed close, but maintain as much

separation as possible while still keeping the layout

compact.

Connect the bias capacitor from the VBIAS pin to

analog ground using the isolated analog ground

trace. The bias capacitor should be as close as

possible to the VBIAS pin and analog ground . If a

slow-start capacitor or RT resistor is used, or if the

SYNC pin is used to select 350-kHz operating

frequency, connect them to this trace.

TOPSIDE GROUND AREA

INPUT

PH

BYPASS

OUTPUT

BULK

CAPACITOR

FILTER

OUTPUT INDUCTOR

FILTER

CAPACITOR

VOUT

PGND

VIN

PH

BOOT

CAPACITOR

EXPOSED

PowerPAD

AREA

PH

Vin

VIN

PH

VIN

BOOT

PWRGD

COMP

VBIAS

SS/ENA

COMPENSATION

NETWORK

BIAS CAPACITOR

SLOW START

CAPACITOR

FREQUENCY SET RESISTOR

ANALOG GROUND TRACE

VIA to Ground Plane

Figure 11. TPS54377 PCB Layout

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SLVS779–SEPTEMBER 2007

LAYOUT CONSIDERATIONS FOR THERMAL PERFORMANCE

For operation at full rated load current, the analog ground plane must provide adequate heat dissipating area. A

3 inch by 3 inch plane of 1 ounce copper is recommended, though not mandatory, depending on ambient

temperature and airflow. Most applications have larger areas of internal ground plane available, and the

PowerPAD should be connected to the largest area available. Additional areas on the top or bottom layers also

help dissipate heat, and any area available should be used when 3 A or greater operation is desired. Connection

from the exposed area of the PowerPAD to the analog ground plane layer should be made using 0.013 inch

diameter vias to avoid solder wicking through the vias. Six vias should be in the PowerPAD area additional vias

located under the device package may be added to enhance thermal performance. The vias under the package,

but not in the exposed thermal pad area, can be increased in size to 0.018.

0.1250

EXPOSED

POWERPAD

AREA

0.0400 0.0400

6 x 0.013 DIA

PIN 1

24 x 0.0320

0.0197

24 x 0.0120

0.1182

0.1620

Figure 12. Recommended Land Pattern for 24-Pin QFN PowerPAD

10

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SLVS779–SEPTEMBER 2007

PERFORMANCE GRAPHS

T_A= 25°C, f_s= 1.1 MHz, V_I= 3.3 V, V_O= 1.8 V (unless otherwise specified)

EFFICIENCY

vs

OUTPUT CURRENT

OUTPUT VOLTAGE

vs

OUTPUT CURRENT

LOOP RESPONSE

180

100

95

0.3

0.2

60

50

40

Phase

120

V = 3 V

I

30

V = 4 V

I

60

20

10

0.1

90

85

GAIN

0

−10

−60

−20

−30

-0.1

V = 5 V

I

80

75

−40

−50

−60

−120

−180

-0.2

-0.3

V = 6 V

I

10

100

1 k

10 k

100 k

1 M

0

0.5

1

1.5

2

2.5

3

3.5

0

0.5

1

1.5

2

2.5

3

f − Frequency − Hz

I

− Output Current − A

I

− Output Current − A

O

Figure 13.

Figure 14.

Figure 15.

OUTPUT RIPPLE VOLTAGE

LOAD TRANSIENT RESPONSE

SLOW-START TIMING

V

= 20 mV/div

O

V

= 10 mV/div

O

V = 1 V/div

I

(AC Coupled)

V

= 1 V/div

O

PH = 2 V/div

I

= 1 A/div

O

0.75 A to 2.25 A / step

1 ms / div

500 ms / div

500 ns / div

Figure 16.

Figure 17.

Figure 18.

Submit Documentation Feedback

11

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TPS54377

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SLVS779–SEPTEMBER 2007

T_A= 25°C, f_s= 1.1 MHz, V_I= 3.3 V, V_O= 1.8 V (unless otherwise specified)

AMBIENT TEMPERATURE

vs

LINE REGULATION

vs

LOAD CURRENT

INPUT RIPPLE VOLTAGE

INPUT VOLTAGE

130

120

110

0.3

0.2

V = 50 mV/div

I

(AC Coupled)

I

= 1.5 A

O

100

90

I

= 3 A

O

0.1

I

= 0 A

O

80

70

60

50

40

30

Safe Operating Area †

0

PH = 2 V/div

f

= 700 kHz

= 5 V

s

-0.1

V

T

I

= 3.3 V

= 125^oC

O

20

-0.2

-0.3

J

10

0

0.5

1

1.5

2

2.5

3

4

5

6

− Load Current − A

I

L

500 ns / div

V − Input Voltage − V

I

† Safe operating area is applicable to the test

board conditions listed in the dissipation

rating table section of this data sheet.

Figure 19.

Figure 20.

Figure 21.

the error amplifier is linearly ramped up from 0 V to

0.891 V in 3.35 ms. Similarly, the converter output

voltage reaches regulation in approximately 3.35 ms.

Voltage hysteresis and a 2.5-μs falling edge deglitch

circuit reduce the likelihood of triggering the enable

due to noise.

DETAILED DESCRIPTION

Disabled Sinking During Start-Up (DSDS)

The DSDS feature enables minimal voltage drooping

of output precharge capacitors at start-up. The

TPS54373 is designed to disable the low-side

MOSFET to prevent sinking current from a precharge

output capacitor during start-up. Once the high-side

MOSFET has been turned on to the maximum duty

cycle limit, the low-side MOSFET is allowed to switch.

Once the maximum duty cycle condition is met, the

converter functions as a sourcing converter until the

SS/ENA is pulled low.

The second function of the SS/ENA pin provides an

external means of extending the slow-start time with

a low-value capacitor connected between SS/ENA

and AGND. Adding a capacitor to the SS/ENA pin

has two effects on start-up. First, a delay occurs

between release of the SS/ENA pin and start up of

the output. The delay is proportional to the slow-start

capacitor value and lasts until the SS/ENA pin

reaches the enable threshold. The start-up delay is

approximately:

Undervoltage Lock Out (UVLO)

1.2 V

5 mA

The TPS54377 incorporates an undervoltage lockout

circuit to keep the device disabled when the input

voltage (VIN) is insufficient. During power up, internal

circuits are held inactive until VIN exceeds the

nominal UVLO threshold voltage of 2.95 V. Once the

UVLO start threshold is reached, device start-up

begins. The device operates until VIN falls below the

nominal UVLO stop threshold of 2.8 V. Hysteresis in

the UVLO comparator, and a 2.5-µs rising and falling

edge deglitch circuit reduce the likelihood of shutting

the device down due to noise on VIN.

t

+ C

d

(SS)

(2)

Second, as the output becomes active, a brief

ramp-up at the internal slow-start rate may be

observed before the externally set slow-start rate

takes control and the output rises at

proportional to the slow-start capacitor. The slow-start

time set by the capacitor is approximately:

a rate

0.7 V

t

+ C

(SS)

5 mA

(3)

The actual slow-start is likely to be less than the

above approximation due to the brief ramp-up at the

internal rate.

Slow-Start/Enable (SS/ENA)

The slow-start/enable pin provides two functions; first,

the pin acts as an enable (shutdown) control by

keeping the device turned off until the voltage

exceeds the start threshold voltage of approximately

1.2 V. When SS/ENA exceeds the enable threshold,

device start up begins. The reference voltage fed to

12

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TPS54377

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SLVS779–SEPTEMBER 2007

VBIAS Regulator (VBIAS)

Oscillator and PWM Ramp

The VBIAS regulator provides internal analog and

digital blocks with a stable supply voltage over

variations in junction temperature and input voltage. A

high quality, low-ESR, ceramic bypass capacitor is

required on the VBIAS pin. X7R or X5R grade

dielectrics are recommended because their values

are more stable over temperature. The bypass

capacitor should be placed close to the VBIAS pin

and returned to AGND. External loading on VBIAS is

allowed, with the caution that internal circuits require

a minimum VBIAS of 2.70 V, and external loads on

VBIAS with ac or digital switching noise may degrade

performance. The VBIAS pin may be useful as a

reference voltage for external circuits.

The oscillator frequency can be set to internally fixed

values of 350 kHz or 550 kHz using the SYNC pin as

a static digital input. If a different frequency of

operation is required for the application, the oscillator

frequency can be externally adjusted from 280 kHz to

1600 kHz by connecting a resistor to the RT pin to

ground and floating the SYNC pin. The switching

frequency is approximated by the following equation,

where R is the resistance from RT to AGND:

51 k

R(W) + 4.7 k

SWITCHING FREQUENCY (MHz) =

(4)

External synchronization of the PWM ramp is

possible over the frequency range of 330 kHz to 1600

kHz by driving a synchronization signal into SYNC

and connecting a resistor from RT to AGND. Choose

an RT resistor that sets the free-running frequency to

Voltage Reference

The voltage reference system produces a precise V_ref

signal by scaling the output of a temperature stable

bandgap circuit. During manufacture, the bandgap

and scaling circuits are trimmed to produce 0.891 V

at the output of the error amplifier, with the amplifier

connected as a voltage follower. The trim procedure

adds to the high precision regulation of the

TPS54377, since it cancels offset errors in the scale

and error amplifier circuits.

80% of the synchronization signal. Table

summarizes the frequency selection configurations.

1

Table 1. Summary of the Frequency Selection Configurations

SWITCHING FREQUENCY

350 kHz, internally set

SYNC PIN

Float or AGND

RT PIN

Float

550 kHz, internally set

≥ 2.5 V

Float

Externally set 280 kHz to 1600 kHz

Externally synchronized frequency

Float

R = 27.4 k to 180 k

Synchronization signal

R = RT value for 80% of external synchronization frequency

Error Amplifier

The high performance, wide bandwidth, voltage error

amplifier sets the TPS54377 apart from most dc/dc

converters. The user is given the flexibility to use a

wide range of output L and C filter components to suit

the particular application needs. Type 2 or type 3

compensation can be employed using external

compensation components.

to its valley voltage. When the ramp begins to charge

back up, the low-side FET turns off and high-side

FET turns on. As the PWM ramp voltage exceeds the

error amplifier output voltage, the PWM comparator

resets the latch, thus turning off the high-side FET

and turning on the low-side FET. The low-side FET

remains on until the next oscillator pulse discharges

the PWM ramp.

PWM Control

During transient conditions, the error amplifier output

could be below the PWM ramp valley voltage or

above the PWM peak voltage. If the error amplifier is

high, the PWM latch is never reset and the high-side

FET remains on until the oscillator pulse signals the

control logic to turn off the high-side FET and turns

on the low-side FET. The device operates at its

maximum duty cycle until the output voltage rises to

the regulation set-point, setting VSENSE to

approximately the same voltage as V_ref. If the error

amplifier output is low, the pwm latch is continually

reset and the high-side FET does not turn on. The

Signals from the error amplifier output, oscillator, and

current limit circuit are processed by the PWM control

logic. Referring to the internal block diagram, the

control logic includes the PWM comparator, OR gate,

PWM latch, and portions of the adaptive dead-time

and control logic block. During steady-state operation

below the current limit threshold, the PWM

comparator output and oscillator pulse train

alternately reset and set the PWM latch. Once the

PWM latch is set, the low-side FET remains on for a

minimum duration set by the oscillator pulse duration.

During this period, the PWM ramp discharges rapidly

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TPS54377

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SLVS779–SEPTEMBER 2007

low-side FET remains on until the VSENSE voltage

several milliseconds. With a persistent fault condition,

the device cycles continuously; starting up by control

of the soft-start circuit, heating up due to the fault,

and then shutting down upon reaching the thermal

shutdown point.

decreases to

a

range that allows the PWM

comparator to change states. The TPS54377 is

capable of sinking current continuously until the C_O

reaches the regulation set-point.

If the current limit comparator trips for longer than

100 ns, the PWM latch resets before the PWM ramp

exceeds the error amplifier output. The high-side FET

turns off and low-side FET turns on to decrease the

energy in the output inductor, and consequently, the

output current. This process is repeated each cycle in

which the current limit comparator is tripped.

Power Good (PWRGD)

The power good circuit monitors for undervoltage

conditions on VSENSE. If the voltage on VSENSE is

10% below the reference voltage, the open-drain

PWRGD output is pulled low. PWRGD is also pulled

low if VIN is less than the UVLO threshold, or

SS/ENA is low, or thermal shutdown is asserted.

When VIN = UVLO threshold, SS/ENA = enable

threshold, and VSENSE > 90% of V_ref, the open drain

output of the PWRGD pin is high. A hysteresis

voltage equal to 3% of V_refand a 35-μs falling edge

deglitch circuit prevent tripping of the power good

comparator due to high frequency noise.

Dead-Time Control and MOSFET Drivers

Adaptive dead-time control prevents shoot-through

current from flowing in both N-channel power

MOSFETs during the switching transitions by actively

controlling the turn-on times of the MOSFET drivers.

The high-side driver does not turn on until the gate

drive voltage to the low-side FET is below 2 V. The

low-side driver does not turn on until the voltage at

the gate of the high-side MOSFETs is below 2 V. The

high-side and low-side drivers are designed with a

300-mA source and sink capability to drive the power

MOSFETs gates. The low-side driver is supplied from

VIN, while the high-side drive is supplied from the

BOOT pin. A bootstrap circuit uses an external BOOT

capacitor and an internal 2.5-Ω bootstrap switch

connected between the VIN and BOOT pins. The

integrated bootstrap switch improves drive efficiency

and reduces external component count.

OUTPUT VOLTAGE LIMITATIONS

Due to the internal design of the TPS54377, there are

both upper and lower output voltage limits for any

given input voltage. Additionally, the lower boundary

of the output voltage set point range is also

dependent on operating frequency. The upper limit of

the output voltage set point is constrained by the

maximum duty cycle of 90% and is given by

Equation 5:

V max = 0.9 x V min - I max [ (-0.016 x V min + 0.184) + RL]

O

I

O

I

(5)

Where:

Overcurrent Protection

V_Imin = minimum input voltage

I_Omax = maximum load current

RL = series resistance of the output inductor

The cycle by cycle current limiting is achieved by

sensing the current flowing through the high-side

MOSFET and differential amplifier, and comparing it

to the preset overcurrent threshold. The high-side

MOSFET is turned off within 200 ns of reaching the

Equation 5 assumes maximum on resistance for the

internal high-side and low-side FETs.

current limit threshold.

A 100-ns leading edge

The lower limit is constrained by the minimum

controllable on time which may be as high as 150 ns.

The approximate minimum output voltage for a given

input voltage, operating frequency, and minimum load

current is given in Equation 6:

blanking circuit prevents false tripping of the current

limit. Current limit detection occurs only when current

flows from VIN to PH when sourcing current to the

output filter. Load protection during current sink

operation is provided by thermal shutdown.

V min = (150E-9 x V max x Fs x 1.08) - I min x

O

I

o

Thermal Shutdown

-0.026

3

The device uses the thermal shutdown to turn off the

power MOSFETs and disable the controller if the

junction temperature exceeds 150°C. The device is

released from shutdown when the junction

temperature decreases to 10°C below the thermal

shutdown trip point and starts up under control of the

slow-start circuit. Thermal shutdown provides

protection when an overload condition is sustained for

X V max

+ 0.111 + RL

)

(

[

]

i

(6)

Where:

V_I= maximum input voltage

Fs = programmed operating frequency

I_O= minimum load current

RL = series resistance of the output inductor

14

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TPS54377

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SLVS779–SEPTEMBER 2007

Equation 6 assumes nominal on resistance for the

high-side and low-side FETs, and has an eight

percent factor for variation of operating frequency set

point. Any design operating near the operational limits

of the device should be carefully checked to assure

proper functionality.

Submit Documentation Feedback

15

Product Folder Link(s): TPS54377

PACKAGE OPTION ADDENDUM

www.ti.com

8-Oct-2007

PACKAGING INFORMATION

Orderable Device

TPS54377RHFR

TPS54377RHFRG4

TPS54377RHFT

Status ⁽¹⁾

ACTIVE

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

Drawing

QFN

RHF

24

3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

QFN

RHF

3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

TPS54377RHFTG4

250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

Addendum-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

5-Oct-2007

TAPE AND REEL BOX INFORMATION

Device

Package Pins

Site

Reel

A0 (mm)

B0 (mm)

K0 (mm)

P1

W

Pin1

Diameter Width

(mm) (mm) Quadrant

(mm)

330

(mm)

12

TPS54377RHFR

TPS54377RHFT

RHF

24

SITE 41

4.3

5.3

1.3

8

12

Q1

180

12

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

5-Oct-2007

Device

Package

Pins

Site

Length (mm) Width (mm) Height (mm)

TPS54377RHFR

TPS54377RHFT

RHF

24

SITE 41

346.0

190.0

346.0

212.7

29.0

31.75

Pack Materials-Page 2

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型号：	TPS5430
厂家：	TEXAS INSTRUMENTS
描述：	1.6 MHz, 3-V TO 6-V INPUT, 3-A SYNCHRONOUS STEP-DOWN SWIFT⑩ CONVERTER WITH DISABLED SINKING DURING START-UP 1.6兆赫， 3 V至6 V的输入， 3 -A同步降压型转换器SWIFT⑩禁用塌陷启动时转换器输入元件
文件：	总21页 (文件大小：691K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TPS5430 [TI]

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