TPS54315MPWPREP [TI]
3-V TO 6-V INPUT, 3-A OUTPUT SYNCHRONOUS-BUCK PWM SWITCHER WITH INTEGRATED FETs (SWIFTâ¢); 3 V至6 V的输入， 3 -A具有集成FET输出同步降压PWM切换器（ SWIFTâ ?? ¢ ）
| 型号： | TPS54315MPWPREP |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 3-V TO 6-V INPUT, 3-A OUTPUT SYNCHRONOUS-BUCK PWM SWITCHER WITH INTEGRATED FETs (SWIFTâ¢) |
| 文件： | 总21页 (文件大小：731K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
T
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e
TPS54311-EP, TPS54312-EP,
TPS54313-EP, TPS54314-EP,
(
6
,
3
m
m
x
6
,
4
m
m
)
TPS54315-EP, TPS54316-EP
www.ti.com
SGLS376A–FEBRUARY 2007–REVISED MARCH 2007
3-V TO 6-V INPUT, 3-A OUTPUT SYNCHRONOUS-BUCK PWM
SWITCHER WITH INTEGRATED FETs (SWIFT™)
FEATURES
•
Controlled Baseline
APPLICATIONS
•
Low-Voltage, High-Density Systems With
Power Distributed at 5 V or 3.3 V
–
One Assembly/Test Site, One Fabrication
Site
•
Point of Load Regulation for High
Performance DSPs, FPGAs, ASICs, and
Microprocessors
Broadband, Networking and Optical
Communications Infrastructure
•
•
Extended Temperature Performance of –55°C
to 125°C
Enhanced Diminishing Manufacturing Sources
(DMS) Support
•
•
•
•
•
Enhanced Product-Change Notification
Automotive Telematics
(1)
Qualification Pedigree
PWP PACKAGE
(TOP VIEW)
60-mΩ MOSFET Switches for High Efficiency
at 3-A Continuous Output Source or Sink
Current
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
AGND
VSENSE
NC
PWRGD
BOOT
PH
RT
•
0.9 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V and 3.3 V Fixed
Output Voltage Device With 1% Initial
Accuracy
FSEL
SS/ENA
VBIAS
VIN
VIN
VIN
PGND
PGND
PGND
•
•
•
Internally Compensated for Low Parts Count
Fast Transient Response
PH
PH
PH
PH
Wide PWM Frequency: Fixed 350 kHz, 550
kHz, or Adjustable 280 kHz to 700 kHz
•
•
Load Protected by Peak Current Limit and
Thermal Shutdown
NC − No internal connection
Integrated Solution Reduces Board Area and
Total Cost
(1) Component qualification in accordance with JEDEC and
industry standards to ensure reliable operation over an
extended temperature range. This includes, but is not limited
to, Highly Accelerated Stress Test (HAST) or biased 85/85,
temperature cycle, autoclave or unbiased HAST,
electromigration, bond intermetallic life, and mold compound
life. Such qualification testing should not be viewed as
justifying use of this component beyond specified
performance and environmental limits.
DESCRIPTION/ORDERING INFORMATION
As A member of the SWIFT family of dc/dc regulators, the TPS54311, TPS54312, TPS54313, TPS54314,
TPS54315 and TPS54316 low-input-voltage high-output current synchronous-buck PWM converter integrates all
required active components. Included on the substrate with the listed features are a true, high performance,
voltage error amplifier that provides high performance under transient conditions; an undervoltage-lockout circuit
to prevent start-up until the input voltage reaches 3 V; an internally and externally set slow-start circuit to limit
in-rush currents; and a power good output useful for processor/logic reset, fault signaling, and supply
sequencing.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SWIFT, PowerPAD are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 2007, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TPS54311-EP, TPS54312-EP,
TPS54313-EP, TPS54314-EP,
TPS54315-EP, TPS54316-EP
www.ti.com
SGLS376A–FEBRUARY 2007–REVISED MARCH 2007
The TPS54311, TPS54312, TPS54313, TPS54314, TPS54315 and TPS54316 devices are available in a
thermally enhanced 20-pin TSSOP (PWP) PowerPAD™ package, which eliminates bulky heatsinks. Texas
Instruments provides evaluation modules and the SWIFT designer software tool to aid in quickly achieving
high-performance power supply designs to meet aggressive equipment development cycles.
ORDERING INFORMATION(1)
TJ
OUTPUT VOLTAGE
PACKAGED DEVICES PLASTIC HTSSOP
(PWP)(2)
TOP SIDE MARKING
TPS54311
0.9 V
1.2 V
1.5 V
1.8 V
2.5 V
3.3 V
TPS54311MPWPREP
TPS54312MPWPREP
TPS54313MPWPREP
TPS54314MPWPREP
TPS54315MPWPREP
TPS54316MPWPREP
TPS54312
TPS54313
TPS54314
TPS54315
TPS54316
–55°C to 125°C
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
Web site at www.ti.com.
(2) The PWP package is taped and reeled as indicated by the R suffix. See application section of data sheet for PowerPAD drawing and
layout information
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
TERMINAL FUNCTIONS
TERMINAL
DESCRIPTION
NAME
NO.
Analog ground. Return for compensation network/output divider, slow-start capacitor, VBIAS capacitor, RT
resistor and FSEL pin. Make PowerPAD connection to AGND.
AGND
1
Bootstrap input. 0.022-µF to 0.1-µF low-ESR capacitor connected from BOOT to PH generates floating drive for
the high-side FET driver.
BOOT
5
FSEL
NC
19
3
Frequency select input. Provides logic input to select between two internally set switching frequencies.
No connection
Power ground. High current return for the low-side driver and power MOSFET. Connect PGND with large copper
areas to the input and output supply returns, and negative terminals of the input and output capacitors.
PGND
PH
11–13
6–10
4
Phase input/output. Junction of the internal high and low-side power MOSFETs, and output inductor.
Power good open drain output. Hi-Z when VSENSE ≥ 90% Vref, otherwise PWRGD is low. Note that output is low
when SS/ENA is low or internal shutdown signal active.
PWRGD
RT
20
Frequency setting resistor input. Connect a resistor from RT to AGND to set the switching frequency, fs.
Slow-start/enable input/output. Dual function pin which provides logic input to enable/disable device operation and
capacitor input to externally set the start-up time.
SS/ENA
18
Internal bias regulator output. Supplies regulated voltage to internal circuitry. Bypass VBIAS pin to AGND pin with
a high quality, low ESR 0.1-µF to 1-µF ceramic capacitor.
VBIAS
17
Input supply for the power MOSFET switches and internal bias regulator. Bypass VIN pins to PGND pins close to
device package with a high quality, low ESR 1-µF to 10-µF ceramic capacitor.
VIN
14–16
2
VSENSE
Error amplifier inverting input. Connect directly to output voltage sense point.
2
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TPS54311-EP, TPS54312-EP,
TPS54313-EP, TPS54314-EP,
TPS54315-EP, TPS54316-EP
www.ti.com
SGLS376A–FEBRUARY 2007–REVISED MARCH 2007
FUNCTIONAL BLOCK DIAGRAM
VBIAS
AGND
VIN
Enable
Comparator
5 µA
SS/ENA
REG
VBIAS
ILIM
Falling
Edge
Deglitch
SHUTDOWN
VIN
1.2 V
VIN
Comparator
Thermal
Shutdown
145°C
Hysteresis: 0.03 V
Leading
Edge
2.5 µs
Blanking
VIN UVLO
Comparator
Falling
and
100 ns
VIN
BOOT
Rising
Edge
2.95 V
Deglitch
Hysteresis: 0.16 V
2.5 µs
SS_DIS
SHUTDOWN
L
OUT
V
O
PH
Internal/External
Slow-Start
(Internal Slow-Start Time =
3.3 ms to 6.6 ms)
+
−
C
O
Adaptive Dead-Time
and
Control Logic
R
S
Q
2 kΩ
PWM
Comparator
40 kΩ
Error
Amplifier
VIN
25 ns Adaptive
Deadtime
V
I
Feed-Forward
Compensation
V
I
OSC
PGND
Power good
Comparator
Reference/
DAC
Falling
Edge
PWRGD
VSENSE
0.90 V
ref
Deglitch
TPS5431x
Hysteresis: 0.03 Vref
SHUTDOWN
35 µs
FSEL
VSENSE
RT
EFFICIENCY
vs
LOAD CURRENT
Simplified Schematic
96
94
92
90
88
86
84
82
Input
Output
VIN
PH
BOOT
PGND
VBIAS
VSENSE
GND
T
= 25°C
V = 5 V
A
I
V
= 3.3 V
O
80
0
0.5
1
1.5
2
2.5
3
Load Current − A
3
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TPS54311-EP, TPS54312-EP,
TPS54313-EP, TPS54314-EP,
TPS54315-EP, TPS54316-EP
www.ti.com
SGLS376A–FEBRUARY 2007–REVISED MARCH 2007
Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
MIN
–0.3
–0.3
–0.3
–0.3
–0.3
–0.6
MAX UNIT
VIN, SS/ENA, FSEL
RT
7
6
V
4
VI
Input voltage range
VSENSE
BOOT
17
VBIAS, PWRGD, COMP
7
V
VO
Output voltage range
Source current
PH
10
PH
Internally Limited
IO
COMP, VBIAS
PH
6
6
mA
A
Sink current
COMP
6
mA
mA
V
SS/ENA,PWRGD
AGND to PGND
10
±0.3
Voltage differential
TJ
Operating virtual junction temperature range
Storage temperature
–55
–65
150
150
300
°C
°C
°C
Tstg
Lead temperature 1,6 mm (1/16 in) from case for 10 s
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Recommended Operating Conditions
MIN NOM
MAX
6
UNIT
V
VI
Input voltage range
3
TJ
Operating junction temperature
–55
125
°C
Package Dissipation Ratings(1)(2)
THERMAL IMPEDANCE
JUNCTION-TO-AMBIENT
TA = 25°C
POWER RATING
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
PACKAGE
20-Pin PWP with solder
26°C/W
3.85 W(3)
2.12 W
1.54 W
0.69 W
20-Pin PWP without solder
57.5°C/W
1.73 W
0.96 W
(1) For more information on the PWP package, see the Texas Instruments technical brief (SLMA002).
(2) Test board conditions:
a. 3 in × 3 in, 2 layers, Thickness: 0.062 in
b. 1.5 oz copper traces located on the top of the PCB
c. 1.5 oz copper ground plane on the bottom of PCB
d. Ten thermal vias (see the recommended land pattern in the Applications section of this data sheet)
(3) Maximum power dissipation may be limited by overcurrent protection.
4
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TPS54311-EP, TPS54312-EP,
TPS54313-EP, TPS54314-EP,
TPS54315-EP, TPS54316-EP
www.ti.com
SGLS376A–FEBRUARY 2007–REVISED MARCH 2007
Electrical Characteristics
TJ = –55°C to 125°C, VIN = 3 V to 6 V (unless otherwise noted)
PARAMETER
SUPPLY VOLTAGE, VIN
TEST CONDITIONS
MIN
TYP MAX UNIT
VIN
Input voltage range
3
6
V
fs = 350 kHz,
RT open
FSEL ≤ 0.8 V,
xxx
6.2
9.6
Quiescent current
fs = 550 kHz,
Phase pin open,
FSEL ≥ 2.5 V,
RT open
mA
8.4 12.8
Shutdown,
SS/ENA = 0 V
1
1.4
3
UNDER VOLTAGE LOCK OUT
Start threshold voltage, UVLO
Stop threshold voltage, UVLO
Hysteresis voltage, UVLO
2.95
2.8
V
2.7
2.7
0.14
V
Rising and falling edge deglitch,
UVLO(1)
2.5
µs
BIAS VOLTAGE
Output voltage, VBIAS
Output current, VBIAS(2)
OUTPUT VOLTAGE
I(VBIAS) = 0
2.8 2.95
100
V
µA
TJ = 25°C
VIN = 5.0 V
0 ≤ IL ≤ 3A
VIN = 5.0 V
0 ≤ IL ≤ 3A
VIN = 5.0 V
0 ≤ IL ≤ 3A
VIN = 5.0 V
0 ≤ IL ≤ 3A
VIN = 5.0 V
0 ≤ IL ≤ 3A
VIN = 5.0 V
0 ≤ IL ≤ 3A
0.9
V
V
V
V
V
V
TPS54311
3 ≤ VIN ≤ 6V
TJ = 25°C
–55°C ≤ TJ ≤ 125°C
–55°C ≤ TJ ≤ 125°C
–55°C ≤ TJ ≤ 125°C
–55°C ≤ TJ ≤ 125°C
–55°C ≤ TJ ≤ 125°C
–55°C ≤ TJ ≤ 125°C
–3.0%
–3.0%
–3.0%
–3.0%
–3.0%
–3.0%
3.0%
1.2
TPS54312
TPS54313
TPS54314
TPS54315
TPS54316
3 ≤ VIN ≤ 6V
TJ = 25°C
3.0%
1.5
3 ≤ VIN ≤ 6V
TJ = 25°C
3.0%
1.8
VOOutput Voltage
3 ≤ VIN ≤ 6V
TJ = 25°C
3.0%
2.5
3 ≤ VIN ≤ 6V
TJ = 25°C
3.0%
3.3
3 ≤ VIN ≤ 6V
3.0%
REGULATION
Line regulation(1)(3)
Load regulation(1)(3)
OSCILLATOR
IL = 1.5 A,
350 ≤ fs ≤ 550 kHz,
350 ≤ fs ≤ 550 kHz,
0.21
%/V
%/A
IL = 0 A to 3 A,
0.21
FSEL ≤ 0.8 V,
FSEL ≥ 2.5 V,
RT = 180 kΩ (1% resistor to AGND)(1)
RT = 160 kΩ (1% resistor to AGND)
RT = 68 kΩ (1% resistor to AGND)(1)
RT open
RT open
255
400
252
290
663
2.5
350 450
550 700
280 308
312 350
700 762
Internally set free-running frequency
range
kHz
kHz
Externally set free-running frequency
range
High-level threshold voltage at FSEL
Low-level threshold voltage at FSEL
Pulse duration, FSEL(1)
Frequency range, FSEL(1)(4)
Ramp valley(1)
V
V
0.8
50
ns
kHz
V
330
700
0.75
(1) Specified by design
(2) Static resistive loads only
(3) Specified by the circuit used in Figure 10.
(4) To ensure proper operation when RC filter is used between external clock and FSEL pin, the recommended values are R ≤ 1 kΩ and C
≤ 68 pF.
5
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TPS54311-EP, TPS54312-EP,
TPS54313-EP, TPS54314-EP,
TPS54315-EP, TPS54316-EP
www.ti.com
SGLS376A–FEBRUARY 2007–REVISED MARCH 2007
Electrical Characteristics (continued)
TJ = –55°C to 125°C, VIN = 3 V to 6 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX UNIT
Ramp amplitude (peak-to-peak)(1)
Minimum controllable on time(1)
Maximum duty cycle(1)
1
V
200
ns
90%
ERROR AMPLIFIER
Error amplifier open loop voltage
gain(1)
Error amplifier unity gain bandwidth(1)
26
5
dB
3
MHz
PWM COMPARATOR
PWM comparator propagation delay
time, PWM comparator input to PH
pin (excluding dead time)
10-mV overdrive(1)
70
85
ns
SLOW-START/ENABLE
Enable threshold voltage, SS/ENA
Enable hysteresis voltage, SS/ENA(5)
Falling edge deglitch, SS/ENA(5)
Internal slow-start time(5)
0.82
1.2
0.03
2.5
4.5
5
1.4
V
V
µs
ms
µA
mA
3.5
2.5
1.2
5.4
8
Charge current, SS/ENA
SS/ENA = 0 V
Discharge current, SS/ENA
SS/ENA = 0.2 V, VI = 2.7 V
2.3
4
POWER GOOD
Power good threshold voltage
Power good hysteresis voltage(5)
Power good falling edge deglitch(5)
Output saturation voltage, PWRGD
Leakage current, PWRGD
VSENSE falling
90
3
%Vref
%Vref
µs
35
I(sink) = 2.5 mA
VI = 6.0 V
0.18
0.3
1
V
µA
CURRENT LIMIT
Current limit trip point
VI = 3 V, output shorted
4
6.5
100
200
A
Current limit leading edge blanking
time(5)
Current limit total response time(5)
ns
ns
THERMAL SHUTDOWN
Thermal shutdown trip point(5)
Thermal shutdown hysteresis(5)
OUTPUT POWER MOSFETS
135
150 165
10
°C
°C
VI = 6 V(6)
VI = 3 V(6)
59
85
88
rDS(o
Power MOSFET switches
mΩ
n)
136
(5) Specified by design
(6) Matched MOSFETs, low side rDS(on) production tested, high side rDS(on) specified by design.
6
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TPS54311-EP, TPS54312-EP,
TPS54313-EP, TPS54314-EP,
TPS54315-EP, TPS54316-EP
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SGLS376A–FEBRUARY 2007–REVISED MARCH 2007
TYPICAL CHARACTERISTICS
DRAIN-SOURCE ON-STATE RESISTANCE
vs
DRAIN-SOURCE ON-STATE RESISTANCE
vs
INTERNALLY SET OSCILLATOR
FREQUENCY
JUNCTION TEMPERATURE
JUNCTION TEMPERATURE
vs
120
100
JUNCTION TEMPERATURE
V
= 3.3 V
V = 5 V
I
750
650
550
450
I
100
80
I
= 3 A
O
I
= 3 A
O
80
60
40
20
0
FSEL ≥ 2.5 V
60
40
FSEL ≤ 0.8 V
20
0
350
250
−40
0
25
85
125
−40
0
25
85
125
T
J
− Junction Temperature − °C
T
J
− Junction Temperature − °C
−40
0
25
85
125
T
J
− Junction Temperature − °C
Figure 1.
Figure 2.
Figure 3.
EXTERNALLY SET OSCILLATOR
FREQUENCY
VOLTAGE REFERENCE
vs
OUTPUT VOLTAGE REGULATION
vs
vs
JUNCTION TEMPERATURE
INPUT VOLTAGE
0.8950
0.8930
0.8910
0.8890
0.895
JUNCTION TEMPERATURE
T
A
= 85°C
800
RT = 68 k
0.893
0.891
700
600
500
400
RT = 100 k
f = 350 kHz
0.889
0.8870
0.8850
0.887
0.885
RT = 180 k
300
200
−40
0
25
85
125
3
4
5
6
V − Input Voltage − V
I
−40
0
25
85
125
T
J
− Junction Temperature − °C
T
J
− Junction Temperature − °C
Figure 4.
Figure 5.
Figure 6.
ERROR AMPLIFIER
OPEN LOOP RESPONSE
INTERNAL SLOW-START TIME
vs
JUNCTION TEMPERATURE
DEVICE POWER LOSSES
vs
0
140
120
100
80
LOAD CURRENT
R = 10 kΩ,
L
−20
−40
−60
−80
2.25
2
3.80
3.65
3.50
3.35
3.20
3.05
C
T
= 160 pF,
= 25°C
L
T
f
− 125°C,
J
A
= 700 kHz
s
1.75
1.5
Phase
V = 3.3 V
I
−100
−120
60
1.25
40
20
Gain
−140
−160
1
V = 5 V
I
0.75
0
−180
−200
0.5
0.25
0
−20
2.90
2.75
0
10
100 1 k 10 k 100 k 1 M 10 M
f − Frequency − Hz
0
1
2
3
4
−40
0
25
85
125
I
− Load Current − A
T
J
− Junction Temperature − °C
L
Figure 7.
Figure 8.
Figure 9.
7
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TPS54311-EP, TPS54312-EP,
TPS54313-EP, TPS54314-EP,
TPS54315-EP, TPS54316-EP
www.ti.com
SGLS376A–FEBRUARY 2007–REVISED MARCH 2007
APPLICATION INFORMATION
Figure 10 shows the schematic diagram for a typical TPS54314 application. The TPS54314 (U1) can provide up
to 3 A of output current at a nominal output voltage of 1.8 V. For proper thermal performance, the PowerPAD
underneath the TPS54314 integrated circuit needs to be soldered to the printed circuit board.
J1
2
V
I
+
U1
1
C2
1
GND
R1
10 kΩ
TPS54312PWP
R7
1
20
19
18
AGND
RT
2
3
4
5
6
7
8
71.5 kΩ
VSENSE
FSEL
NC
SS/ENA
VBIAS
VIN
17
16
15
PWRGD
BOOT
PWRGD
L1
C7
0.047 µF
C8
10 µF
C3
0.1 µF
PH
PH
PH
VIN
14
13
12
11
5.2 µH
J3
VIN
1
2
V
O
PGND
PGND
PGND
9
GND
PH
PH
+
C9
470 µF
4 V
10
C11
1000 pF
PwrPAD
1
Optional
Figure 10. TPS54314 Schematic
INPUT VOLTAGE
The input to the circuit is a nominal 5 VDC, applied at J1. The optional input filter (C2) is a 220-µF POSCAP
capacitor, with a maximum allowable ripple current of 3 A. C8 is the decoupling capacitor for the TPS54314 and
must be located as close to the device as possible.
FEEDBACK CIRCUIT
The output voltage of the converter is fed directly into the VSENSE pin of the TPS54314. The TPS54314 is
internally compensated to provide stability of the output under varying line and load conditions.
OPERATING FREQUENCY
In the application circuit, a 700 kHz operating frequency is selected by leaving FSEL open and connecting a
71.5 kΩ resistor between the RT pin and AGND. Different operating frequencies may be selected by varying the
value of R3 using equation 1:
500 kHz
Switching Frequency
R +
100 kW
(1)
Alternately, preset operating frequencies of 350 kHz or 550 kHz my be selected by leaving RT open and
connecting the FSEL pin to AGND or VIN, respectively.
OUTPUT FILTER
The output filter is composed of a 5.2-µH inductor and 470-µF capacitor. The inductor is a low dc resistance
(16-mΩ) type, Sumida CDRH104R-5R2. The capacitor used is a 4-V POSCAP with a maximum ESR of 40 mΩ.
The output filter components work with the internal compensation network to provide a stable closed loop
response for the converter.
8
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TPS54311-EP, TPS54312-EP,
TPS54313-EP, TPS54314-EP,
TPS54315-EP, TPS54316-EP
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SGLS376A–FEBRUARY 2007–REVISED MARCH 2007
APPLICATION INFORMATION (continued)
GROUNDING AND PowerPAD LAYOUT
The TPS54311-16 has two internal grounds (analog and power). Inside the TPS54311-16, the analog ground
ties to all of the noise sensitive signals, while the power ground ties to the noisier power signals. The PowerPAD
must be connected directly to AGND. Noise injected between the two grounds can degrade the performance of
the TPS54311-16, particularly at higher output currents. However, ground noise on an analog ground plane can
also cause problems with some of the control and bias signals. For these reasons, separate analog and power
ground planes are recommended. These two planes should tie together directly at the IC to reduce noise
between the two grounds. The only components that should tie directly to the power ground plane are the input
capacitor, the output capacitor, the input voltage decoupling capacitor, and the PGND pins of the TPS54311-16.
The layout of the TPS54311-16 evaluation module is representative of a recommended layout for a 4-layer
board. Documentation for the TPS54311-16 evaluation module can be found on the Texas Instruments web site
under the TPS54311-16 product folder and in the application note, Texas Instruments literature number
SLVA111.
LAYOUT CONSIDERATIONS FOR THERMAL PERFORMANCE
For operation at full rated load current, the analog ground plane must provide adequate heat dissipating area. A
3 inch by 3 inch plane of 1 ounce copper is recommended, though not mandatory, depending on ambient
temperature and airflow. Most applications have larger areas of internal ground plane available, and the
PowerPAD should be connected to the largest area available. Additional areas on the top or bottom layers also
help dissipate heat, and any area available should be used when 3 A or greater operation is desired. Connection
from the exposed area of the PowerPAD to the analog ground plane layer should be made using 0.013 inch
diameter vias to avoid solder wicking through the vias. Six vias should be in the PowerPAD area with four
additional vias located under the device package. The size of the vias under the package, but not in the exposed
thermal pad area, can be increased to 0.018. Additional vias beyond the ten recommended that enhance
thermal performance should be included in areas not under the device package.
6 PL
4 PL
0.0130
0.0180
Minimum Recommended Thermal Vias: 6 × .013 dia.
Inside Powerpad Area 4 × .018 dia. Under Device as Shown.
Additional .018 dia. Vias May be Used if Top Side Analog
Ground Area is Extended.
Connect Pin 1 to Analog Ground Plane
in This Area for Optimum Performance
0.0150
0.06
0.0227
0.0600
0.0400
0.2560
0.2454
0.1010
0.0400
0.0600
0.0256
0.1700
0.1340
0.0620
0.0400
Minimum Recommended Exposed
Copper Area For Powerpad. 5mm
Stencils may Require 10 Percent
Larger Area
Minimum Recommended Top
Side Analog Ground Area
Figure 11. Recommended Land Pattern for 20-Pin PWP PowerPAD
9
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TPS54313-EP, TPS54314-EP,
TPS54315-EP, TPS54316-EP
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SGLS376A–FEBRUARY 2007–REVISED MARCH 2007
PERFORMANCE GRAPHS
EFFICIENCY
vs
LOAD CURRENT
OUTPUT VOLTAGE
LOOP RESPONSE
60
45
180
vs
LOAD CURRENT
1.9
135
100
Phase
Efficiency at 700 kHz
90
45
30
15
90
80
70
5 V
I
1.85
Gain
3.3 V
I
0
0
3.3 V
1.8
I
−45
−90
−15
−30
5 V
I
1.75
1.7
60
50
100
1 k
10 k
100 k
1 M
f − Frequency − Hz
0
1
2
3
4
5
0
1
2
3
4
5
Load Current − A
I
− Load Current − A
L
Figure 12.
Figure 13.
Figure 14.
OUTPUT RIPPLE VOLTAGE
LOAD TRANSIENT RESPONSE
START-UP WAVEFORMS
V 2 V/div
I
V
50 mV/div
O
V
(AC)
O
10 mV/div
V
2 V/div
O
I
2 A/div
O
V = 5 V
I
I
= 3 A
O
V
5 V/div
PWRGD
400 ns/div
Time − 100 µs/div
Time − 2 ms/div
Time − 10 µs/div
Figure 15.
Figure 16.
Figure 17.
AMBIENT TEMPERATURE
vs
LOAD CURRENT
125
115
105
95
†
Safe operating area is applicable to the test
board conditions listed in the Dissipation Rating
Table section of this data sheet.
85
75
65
55
†
Safe Operating Area
45
35
25
0
1
2
3
4
I
− Load Current − A
L
Figure 18.
DETAILED DESCRIPTION
Under Voltage Lock Out (UVLO)
The TPS54311-16 incorporates an under voltage lockout circuit to keep the device disabled when the input
voltage (VIN) is insufficient. During power up, internal circuits are held inactive until VIN exceeds the nominal
UVLO threshold voltage of 2.95 V. Once the UVLO start threshold is reached, device start-up begins. The
device operates until VIN falls below the nominal UVLO stop threshold of 2.8 V. Hysteresis in the UVLO
comparator, and a 2.5-µs rising and falling edge deglitch circuit reduce the likelihood of shutting the device down
due to noise on VIN.
10
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TPS54313-EP, TPS54314-EP,
TPS54315-EP, TPS54316-EP
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SGLS376A–FEBRUARY 2007–REVISED MARCH 2007
PERFORMANCE GRAPHS (continued)
Slow-Start/Enable (SS/ENA)
The slow-start/enable pin provides two functions; first, the pin acts as an enable (shutdown) control by keeping
the device turned off until the voltage exceeds the start threshold voltage of approximately 1.2 V. When SS/ENA
exceeds the enable threshold, device start up begins. The reference voltage fed to the error amplifier is linearly
ramped up from 0 V to 0.891 V in 3.35 ms. Similarly, the converter output voltage reaches regulation in
approximately 3.35 ms. Voltage hysteresis and a 2.5-µs falling edge deglitch circuit reduce the likelihood of
triggering the enable due to noise.
DEVICE
OUTPUT VOLTAGE
SLOW START
3.3 ms
TPS54311
TPS54312
TPS54313
TPS54314
TPS54315
TPS54316
0.9 V
1.2 V
1.5 V
1.8 V
2.5 V
3.3 V
4.5 ms
5.6 ms
3.3 ms
4.7 ms
6.1 ms
The second function of the SS/ENA pin provides an external means of extending the slow-start time with a
low-value capacitor connected between SS/ENA and AGND. Adding a capacitor to the SS/ENA pin has two
effects on start-up. First, a delay occurs between release of the SS/ENA pin and start up of the output. The
delay is proportional to the slow-start capacitor value and lasts until the SS/ENA pin reaches the enable
threshold. The start-up delay is approximately:
1.2 V
5 mA
t
+ C
d
(SS)
(2)
Second, as the output becomes active, a brief ramp-up at the internal slow-start rate may be observed before
the externally set slow-start rate takes control and the output rises at a rate proportional to the slow-start
capacitor. The slow-start time set by the capacitor is approximately:
0.7 V
5 mA
t
+ C
(SS)
(SS)
(3)
The actual slow-start is likely to be less than the above approximation due to the brief ramp-up at the internal
rate.
VBIAS Regulator (VBIAS)
The VBIAS regulator provides internal analog and digital blocks with a stable supply voltage over variations in
junction temperature and input voltage. A high quality, low-ESR, ceramic bypass capacitor is required on the
VBIAS pin. X7R or X5R grade dielectrics are recommended because their values are more stable over
temperature. The bypass capacitor should be placed close to the VBIAS pin and returned to AGND. External
loading on VBIAS is allowed, with the caution that internal circuits require a minimum VBIAS of 2.7 V and
external loads on VBIAS with ac or digital switching noise may degrade performance. The VBIAS pin may be
useful as a reference voltage for external circuits.
Voltage Reference
The voltage reference system produces a precise Vref signal by scaling the output of a temperature stable
bandgap circuit. During manufacture, the bandgap and scaling circuits are trimmed to produce 0.891 V at the
output of the error amplifier, with the amplifier connected as a voltage follower. The trim procedure adds to the
high precision regulation of the TPS54311-16, since it cancels offset errors in the scale and error amplifier
circuits.
11
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SGLS376A–FEBRUARY 2007–REVISED MARCH 2007
Oscillator and PWM Ramp
The oscillator frequency can be set to internally fixed values of 350 kHz or 550 kHz using the FSEL pin as a
static digital input. If a different frequency of operation is required for the application, the oscillator frequency can
be externally adjusted from 280 kHz to 700 kHz by connecting a resistor to the RT pin to ground and floating the
FSEL pin. The switching frequency is approximated by the following equation, where R is the resistance from RT
to AGND:
100 kW
SWITCHING FREQUENCY +
500 kHz
R
(4)
External synchronization of the PWM ramp is possible over the frequency range of 330 kHz to 700 kHz by
driving a synchronization signal into FSEL and connecting a resistor from RT to AGND. Choose an RT resistor
that sets the free-running frequency to 80% of the synchronization signal. Table 1 summarizes the frequency
selection configurations.
Table 1. Summary of the Frequency Selection Configurations
SWITCHING FREQUENCY
350 kHz, internally set
FSEL PIN
Float or AGND
RT PIN
Float
550 kHz, internally set
≥2.5 V
Float
Externally set 280 kHz to 700 kHz
Externally synchronized frequency(1)
Float
R = 68 k to 180 k
Synchronization signal
R = RT value for 80% of external synchronization frequency
(1) To ensure proper operation when RC filter is used between external clock and FSEL pin, the recommended values are R ≤ 1 kΩ and C
≤ 68 pF.
Error Amplifier
The high performance, wide bandwidth, voltage error amplifier is gain limited to provide internal compensation of
the control loop. The user is given limited flexibility in choosing output L and C filter components. Inductance
values of 4.7 µH to 10 µH are typical and available from several vendors. The resulting designs exhibit good
noise and ripple characteristics, along with exceptional transient response. Transient recovery times are typically
in the range of 10 µs to 20 µs.
PWM Control
Signals from the error amplifier output, oscillator, and current limit circuit are processed by the PWM control
logic. Referring to the internal block diagram, the control logic includes the PWM comparator, OR gate, PWM
latch, and portions of the adaptive dead-time and control logic block. During steady-state operation below the
current limit threshold, the PWM comparator output and oscillator pulse train alternately reset and set the PWM
latch. Once the PWM latch is set, the low-side FET remains on for a minimum duration set by the oscillator
pulse duration. During this period, the PWM ramp discharges rapidly to its valley voltage. When the ramp begins
to charge back up, the low-side FET turns off and high-side FET turns on. As the PWM ramp voltage exceeds
the error amplifier output voltage, the PWM comparator resets the latch, thus turning off the high-side FET and
turning on the low-side FET. The low-side FET remains on until the next oscillator pulse discharges the PWM
ramp.
During transient conditions, the error amplifier output could be below the PWM ramp valley voltage or above the
PWM peak voltage. If the error amplifier is high, the PWM latch is never reset and the high-side FET remains on
until the oscillator pulse signals the control logic to turn the high-side FET off and the low-side FET on. The
device operates at its maximum duty cycle until the output voltage rises to the regulation set-point, setting
VSENSE to approximately the same voltage as Vref. If the error amplifier output is low, the PWM latch is
continually reset and the high-side FET does not turn on. The low-side FET remains on until the VSENSE
voltage decreases to a range that allows the PWM comparator to change states. The TPS54311-16 is capable
of sinking current continuously until the output reaches the regulation set-point.
If the current limit comparator trips for longer than 100 ns, the PWM latch resets before the PWM ramp exceeds
the error amplifier output. The high-side FET turns off and low-side FET turns on to decrease the energy in the
output inductor and consequently the output current. This process is repeated each cycle in which the current
limit comparator is tripped.
12
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TPS54313-EP, TPS54314-EP,
TPS54315-EP, TPS54316-EP
www.ti.com
SGLS376A–FEBRUARY 2007–REVISED MARCH 2007
Dead-Time Control and MOSFET Drivers
Adaptive dead-time control prevents shoot-through current from flowing in both N-channel power MOSFETs
during the switching transitions by actively controlling the turn-on times of the MOSFET drivers. The high-side
driver does not turn on until the gate drive voltage to the low-side FET is below 2 V. The low-side driver does not
turn on until the voltage at the gate of the high-side MOSFETs is below 2 V. The high-side and low-side drivers
are designed with 300-mA source and sink capability to quickly drive the power MOSFETs gates. The low-side
driver is supplied from VIN, while the high-side drive is supplied from the BOOT pin. A bootstrap circuit uses an
external BOOT capacitor and an internal 2.5-Ω bootstrap switch connected between the VIN and BOOT pins.
The integrated bootstrap switch improves drive efficiency and reduces external component count.
Overcurrent Protection
The cycle by cycle current limiting is achieved by sensing the current flowing through the high-side MOSFET
and differential amplifier and comparing it to the preset overcurrent threshold. The high-side MOSFET is turned
off within 200 ns of reaching the current limit threshold. A 100-ns leading edge blanking circuit prevents false
tripping of the current limit. Current limit detection occurs only when current flows from VIN to PH when sourcing
current to the output filter. Load protection during current sink operation is provided by thermal shutdown.
Thermal Shutdown
The device uses the thermal shutdown to turn off the power MOSFETs and disable the controller if the junction
temperature exceeds 150°C. The device is released from shutdown when the junction temperature decreases to
10°C below the thermal shutdown trip point and starts up under control of the slow-start circuit. Thermal
shutdown provides protection when an overload condition is sustained for several milliseconds. With a persistent
fault condition, the device cycles continuously; starting up by control of the soft-start circuit, heating up due to
the fault, and then shutting down upon reaching the thermal shutdown point.
Power Good (PWRGD)
The power good circuit monitors for under voltage conditions on VSENSE. If the voltage on VSENSE is 10%
below the reference voltage, the open-drain PWRGD output is pulled low. PWRGD is also pulled low if VIN is
less than the UVLO threshold, or SS/ENA is low, or thermal shutdown is asserted. When VIN = UVLO threshold,
SS/ENA = enable threshold, and VSENSE > 90% of Vref, the open drain output of the PWRGD pin is high. A
hysteresis voltage equal to 3% of Vref and a 35-µs falling edge deglitch circuit prevent tripping of the power good
comparator due to high frequency noise.
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PACKAGE OPTION ADDENDUM
www.ti.com
11-May-2011
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
TPS54311MPWPREP
TPS54312MPWPREP
TPS54313MPWPREP
TPS54314MPWPREP
TPS54315MPWPREP
TPS54316MPWPREP
V62/06657-01XE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
HTSSOP
HTSSOP
HTSSOP
HTSSOP
HTSSOP
HTSSOP
HTSSOP
HTSSOP
HTSSOP
HTSSOP
HTSSOP
HTSSOP
PWP
PWP
PWP
PWP
PWP
PWP
PWP
PWP
PWP
PWP
PWP
PWP
20
20
20
20
20
20
20
20
20
20
20
20
2000
2000
2000
2000
2000
2000
2000
2000
2000
2000
2000
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
V62/06657-02XE
Green (RoHS
& no Sb/Br)
V62/06657-03XE
Green (RoHS
& no Sb/Br)
V62/06657-04XE
Green (RoHS
& no Sb/Br)
V62/06657-05XE
Green (RoHS
& no Sb/Br)
V62/06657-06XE
Green (RoHS
& no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
11-May-2011
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TPS54311-EP, TPS54312-EP, TPS54313-EP, TPS54314-EP, TPS54315-EP, TPS54316-EP :
Catalog: TPS54311, TPS54312, TPS54313, TPS54314, TPS54315, TPS54316
•
Automotive: TPS54312-Q1, TPS54314-Q1, TPS54315-Q1, TPS54316-Q1
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS54311MPWPREP HTSSOP PWP
TPS54312MPWPREP HTSSOP PWP
TPS54313MPWPREP HTSSOP PWP
TPS54314MPWPREP HTSSOP PWP
TPS54315MPWPREP HTSSOP PWP
TPS54316MPWPREP HTSSOP PWP
20
20
20
20
20
20
2000
2000
2000
2000
2000
2000
330.0
330.0
330.0
330.0
330.0
330.0
16.4
16.4
16.4
16.4
16.4
16.4
6.95
6.95
6.95
6.95
6.95
6.95
7.1
7.1
7.1
7.1
7.1
7.1
1.6
1.6
1.6
1.6
1.6
1.6
8.0
8.0
8.0
8.0
8.0
8.0
16.0
16.0
16.0
16.0
16.0
16.0
Q1
Q1
Q1
Q1
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS54311MPWPREP
TPS54312MPWPREP
TPS54313MPWPREP
TPS54314MPWPREP
TPS54315MPWPREP
TPS54316MPWPREP
HTSSOP
HTSSOP
HTSSOP
HTSSOP
HTSSOP
HTSSOP
PWP
PWP
PWP
PWP
PWP
PWP
20
20
20
20
20
20
2000
2000
2000
2000
2000
2000
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
38.0
38.0
38.0
38.0
38.0
38.0
Pack Materials-Page 2
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TI
TPS54315PWPR
3-V TO 6-V INPUT, 3-A OUTPUT SYNCHRONOUS-BUCK PWM SWITCHER WITH INTEGRATED FETs (SWIFT)Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TI
TPS54315PWPRG4
3-V TO 6-V INPUT, 3-A OUTPUT SYNCHRONOUS-BUCK PWM SWITCHER WITH INTEGRATED FETs (SWIFT)Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TI
TPS54315QPWPRQ1
3-V TO 6-V INPUT, 3-A OUTPUT SYNCHRONOUS-BUCK PWM SWITCHER WITH INTEGRATED FETs (SWIFT)Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TI
TPS54316
3-V TO 6-V INPUT, 3-A OUTPUT SYNCHRONOUS-BUCK PWM SWITCHER WITH INTEGRATED FETsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TI
TPS54316-EP
具有集成 Fet 的增强型产品 3V 至 6V 输入 3A 输出的同步降压 Pwm 转换开关Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TI
TPS54316MPWPREP
3-V TO 6-V INPUT, 3-A OUTPUT SYNCHRONOUS-BUCK PWM SWITCHER WITH INTEGRATED FETs (SWIFTâ¢)Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TI
TPS54316PWP
3-V TO 6-V INPUT, 3-A OUTPUT SYNCHRONOUS-BUCK PWM SWITCHER WITH INTEGRATED FETsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TI
TPS54316PWPG4
3-V TO 6-V INPUT, 3-A OUTPUT SYNCHRONOUS-BUCK PWM SWITCHER WITH INTEGRATED FETs (SWIFT)Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TI
TPS54316PWPR
3-V TO 6-V INPUT, 3-A OUTPUT SYNCHRONOUS-BUCK PWM SWITCHER WITH INTEGRATED FETs (SWIFT)Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TI
TPS54316PWPRG4
3-V TO 6-V INPUT, 3-A OUTPUT SYNCHRONOUS-BUCK PWM SWITCHER WITH INTEGRATED FETs (SWIFT)Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TI
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